Step-down power converter with pre-differential pressure control

Abstract

A buck power converter with pre-differential pressure control is presented. The buck converter includes: a power stage having at least one phase, each phase including an inductor; a driver; and a clock source. The driver drives the power stages in a synchronous mode or an asynchronous mode of operation using a minimum turn-off time. When the output voltage of the converter approaches the input voltage, the duty cycle of the converter is increased to a value limited by the minimum turn-off time. The clock source generates a first clock signal having a predefined pulse width. The driver generates a first stretchable clock signal having an adjustable pulse width and an adjustable period. Upon transitioning from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 533,691, filed Aug. 6, 2019, the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a step-down converter; in particular, to a step-down converter that can operate in a synchronous mode and an asynchronous mode. The asynchronous mode can be referred to as a pre-drop out (PDO) mode. Background

[0005] Buck converters commonly used in chargers often face situations where the required output voltage is very close to the input voltage. This requires a duty cycle that exceeds what is easily achievable based on a fixed period and a fixed defined minimum off time.

[0006] The duty cycle of a step-down converter is determined by the ratio of the output voltage to the input voltage. When the duty cycle approaches 1, the step-down converter (whether multi-level or single-level) typically transitions from a synchronous operation mode to an asynchronous operation mode. In the synchronous operation mode, the cyclic conduction of the power switch is synchronized with the system clock signal. However, after the on-time of the switch state is the minimum off-time of that switch state. During low-dropout operation where the input voltage is only slightly higher than the output voltage, synchronous operation is limited by the minimum off-time that pushes the duty cycle towards 100%. The maximum on-time of the switch state established by the system clock signal minus the minimum off-time limits the achievable duty cycle during synchronous operation.

[0007] To increase the duty cycle for low-dropout operation, the step-down converter typically transitions to an asynchronous operation mode, in which the switch states are switched on without being synchronized with the system clock signal. Therefore, the on-time of the switch states can be increased because it is no longer associated with the system clock signal period. Thus, the achievable duty cycle can be increased through asynchronous operation.

[0008] Although asynchronous operation is thus advantageous, as the duty cycle decreases, the step-down converter must transition back to synchronous operation.

[0009] A fixed frequency can be selected to optimize efficiency within the expected operating condition range (including input and output voltage requirements and the expected dynamic load range). This is true for both simple buck converters and hybrid converters. Multilevel converters are a subset of hybrid converters. Early methods to achieve this included reducing the switching frequency in a step - by - step manner when needed. For longer periods, even with a minimum off - time limit, a higher duty cycle may be possible. In US10998818B2, a method was proposed that allows for a smooth transition into and out of asynchronous mode, such that the period is naturally extended to maintain the duty cycle required for arbitrarily long periods, which allows the duty cycle to approach 1 (unity).

[0010] However, to maintain regulation of the output voltage during the transition, the circuit proposed in US10998818B2 uses a cyclic timer. This increases the complexity and footprint of the system. The object of the present disclosure is to address one or more of the above limitations.

[0011] Overview

[0012] According to a first aspect of the present disclosure, there is provided a buck converter configured to receive an input voltage and provide an output voltage, the buck converter comprising: a power stage having at least one phase, each phase including an inductor; a driver configured to drive the power stage in a synchronous mode or an asynchronous operation mode using a minimum off - time; wherein when the output voltage approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off - time; a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; wherein, when transitioning from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal.

[0013] Optionally, the driver includes a first state machine configured to generate the first stretchable clock signal and adjust the pulse width and period of the first stretchable clock signal.

[0014] Optionally, the first clock signal and the first stretchable clock signal are in - phase.

[0015] Optionally, the buck converter includes: a first ramp generator configured to generate a first ramp signal in response to the first clock signal; and an error comparator configured to generate an error signal by comparing the output voltage with a reference voltage; wherein the pulse width of the first stretchable clock signal increases as the error signal increases to a limit value.

[0016] For example, the limit value can be set by the threshold of the first ramp signal. The threshold of the first ramp signal is an upper limit value indicating how far the ramp signal is allowed to increase.

[0017] Optionally, the buck converter includes a first comparator configured to compare the first ramp signal with an error signal, and wherein when the first ramp signal increases to equal the error signal, the comparator trips and the comparator output goes high.

[0018] Optionally, if the first clock signal occurs before the comparator trip event, the converter transitions to asynchronous mode; otherwise, the converter remains in synchronous mode.

[0019] Optionally, the first state machine is configured to generate: a first ramp reset signal to reset the first ramp signal; a first asynchronous mode signal indicating that the converter has transitioned to asynchronous mode; a first minimum off-time trigger signal configured to trigger the start of a timer; and a first magnetization request signal configured to start inductor magnetization after the timer has completed.

[0020] Optionally, the buck converter includes a first logic circuit coupled to the first state machine.

[0021] Optionally, the first logic circuit includes a plurality of persistent latches. For example, the persistent latches can include one or more wait cells and / or one or more arbitrators.

[0022] Optionally, the buck converter includes a second state machine coupled to a second logic circuit; the second state machine is configured to generate a second stretchable clock signal having an adjustable pulse width and an adjustable period.

[0023] Optionally, the first logic circuit and the second logic circuit are configured to receive a logic signal for setting the state machine as a master or a slave, such that when the first state machine is the master, the second state machine is the slave, and conversely, when the first state machine is the slave, the second state machine is the master.

[0024] Optionally, the buck converter includes a second ramp generator; wherein the second state machine is configured to generate a second ramp reset signal to reset the second ramp signal.

[0025] Optionally, the second state machine is configured to generate the following signals: a second asynchronous mode signal indicating that the converter has transitioned to the asynchronous mode; a second minimum off-time trigger signal configured to trigger the start of a timer; and a second magnetization request signal configured to start inductor magnetization after the timer is completed.

[0026] Optionally, the buck converter includes a minimum off-time timer configured to start upon receipt of a trigger signal.

[0027] For example, the minimum off-time timer may include a capacitor timer based on a constant current.

[0028] According to a second aspect of the present disclosure, a method of controlling a buck converter configured to receive an input voltage and provide an output voltage is provided. The method includes:

[0029] Providing a driver configured to drive a power stage of the converter in a synchronous mode or an asynchronous operating mode using a minimum off-time; wherein when the output voltage approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off-time;

[0030] Generating a first clock signal having a predefined pulse width;

[0031] Generating a first stretchable clock signal having an adjustable pulse width and an adjustable period; and

[0032] When transitioning from the synchronous mode to the asynchronous mode, increasing the adjustable pulse width and the adjustable period of the first stretchable clock signal.

[0033] Optionally, the method includes: generating a first ramp signal in response to the first clock signal; generating an error signal by comparing the output voltage with a reference voltage; wherein the pulse width of the first stretchable clock signal increases as the error signal increases to a limit value.

[0034] Optionally, the method includes generating an enable signal to effect a transition between the synchronous operating mode and the asynchronous operating mode.

[0035] Optionally, the method includes generating a magnetization request signal to magnetize the inductor.

[0036] Optionally, the magnetization of the inductor is caused by the expiration of the minimum off-time timer.

[0037] According to a third aspect of the present disclosure, there is provided a controller for use with a buck converter, the controller comprising: a driver configured to drive a power stage of the converter in a synchronous mode or an asynchronous operation mode using a minimum off-time; wherein when the output voltage approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off-time; a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; wherein, when transitioning from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present disclosure will be described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0039] Figure 1 is a schematic diagram of a power converter as described in US10998818B2;

[0040] Figure 2 is a flowchart of a method for controlling a buck converter according to the present disclosure;

[0041] Figure 3A is for implementing Figure 2 a schematic diagram of a power converter of the method;

[0042] Figure 3B is Figure 3A a schematic diagram of a driver circuit used in a power converter of

[0043] Figure 3C is Figure 3B a schematic diagram of the PDO controller shown in

[0044] Figure 4 is a schematic diagram showing Figure 3A the operation of a power converter system of

[0045] Figure 5 is a waveform diagram showing the interaction of two ramp signals with a magnetization request signal, a PWM peak detection signal, and a buckclock;

[0046] Figure 6 is a timing diagram showing the steady-state operation of the PDO control in a normal (non-PDO) mode;

[0047] Figure 7A is a schematic diagram of a waiting unit;

[0048] Figure 7B is a schematic diagram showing Figure 7A the operation of the waiting unit of

[0049] Figure 8 is an example implementation of a MUTEX element or a MUTEX unit;

[0050] Figure 9A , Figure 9B and Figure 9C show a signal transition diagram that defines the order of causality of signals in an asynchronous finite state machine;

[0051] Figure 10 is an exemplary implementation of a bidirectional arbiter;

[0052] Figure 11 is a waveform diagram showing the operation of a PDO controller as shown in Figure 3C ;

[0053] Figure 12A and Figure 12B show a more detailed transition from PWM to PDO operation;

[0054] Figure 13A and Figure 13B show a more detailed transition from PDO to PWM operation;

[0055] Figure 14A and Figure 14B show an exemplary implementation of a sub-PDO controller used in the Figure 3C PDO controller;

[0056] Figure 15 is an example implementation of a minimum off-time timer;

[0057] Figure 16A and Figure 16B show the operation of a PDO controller with two synchronous ramps; and

[0058] Figure 17 is a schematic diagram of a PDO controller implemented as a master controller.

[0059] Describe

[0060] The power converter can operate in different modes - including pulse width modulation (PWM) mode and asynchronous pre-dropout mode or simply pre-dropout (PDO) mode. In PWM mode, the switching activity of the power switch is controlled by a synchronous clock. In PDO mode, the on-time of the power switch is regulated by a loop, and the off-time is a fixed value, allowing arbitrarily long periods, which allows the duty cycle to approach 1. Therefore, the switching activity is no longer controlled by a synchronous clock.

[0061] Figure 1It is a schematic diagram of a multilevel buck converter configured to transition between a synchronous mode and an asynchronous mode during low dropout operation, as described in US10998818B2.

[0062] The multilevel buck converter 100 regulates the output power during the transition between the synchronous operation mode and the asynchronous operation mode.

[0063] The multilevel buck converter 100 includes switching transistors A, B, C, and D arranged in a conventional manner. In particular, switching transistor A has a first terminal and a second terminal, the first terminal being connected to a node for the input voltage V_IN, and the second terminal being connected to the first terminal of the flying capacitor CF. Additionally, the second terminal of switching transistor A is connected to the first terminal of switching transistor B. As used herein, a transistor "terminal" refers to, for example, the drain terminal or the source terminal of a MOS field effect transistor. The second terminal of switching transistor B is connected to the switch (SW) terminal of inductor L1, and this switch terminal of inductor L1 is connected to the output capacitor C1 for smoothing the output voltage V_OUT. Switching transistor C has a first terminal connected to the SW node (the input node of inductor L1) and a second terminal connected to the remaining terminal of the flying capacitor CF. Additionally, the second terminal of switching transistor C is connected to the first terminal of switching transistor D, and switching transistor D in turn has a second terminal connected to ground.

[0064] The error amplifier 130 generates an error signal voltage (ERV_OUT) in response to the difference between the output voltage and the reference voltage (REF V_OUT )). The error signal is compared with two ramp signals that are 180° out of phase with each other (note that other phase relationships may be used in alternative embodiments). The first ramp generator 105 generates a first ramp signal in response to a clock signal (CLK) from the clock source 110. The second ramp generator 115 generates a second ramp signal in response to the inverted clock signal (CKL_B) from the clock source 110. Thus, the second ramp signal is 180° out of phase with the first ramp signal. The first comparator 120 compares the first ramp signal with the error signal to generate a first control signal 121. Similarly, the second comparator 125 compares the second ramp signal with the error signal to generate a second control signal 126.

[0065] During the synchronization operation when the error signal is not too large, the rising edge of the clock signal CLK sets the reset-set (RS) latch 135 to assert the first magnetization signal (Mag 1). The rising edge of the clock signal CLK also triggers the first ramp generator 105 to start ramping the first ramp signal. Once the first ramp signal rises to equal the error voltage, the first control signal 121 resets the RS latch 135 to reset the first magnetization signal (discharge the first magnetization signal). In the synchronization operation, the rising edge of the complementary clock signal CLK_B sets the RS latch 140 to assert the second magnetization signal (Mag 2). The rising edge of the complementary clock signal also triggers the second ramp generator 115 to start ramping the second ramp signal. Once the second ramp signal rises to equal the error voltage, the second control signal 126 resets the RS latch 140 to reset the second magnetization signal (discharge the second magnetization signal).

[0066] The switch controller and drive circuit 150 processes the first magnetization signal and the second magnetization signal to determine the switch state during the synchronization operation. For the sake of brevity, in the following discussion, the switch controller and drive circuit 150 is simply referred to as the switch controller 150. The switching transistors A, B, C, and D can be configured into one of four switch states, which are designated as the D1 switch state, the D2 switch state, the DV switch state, and the DP switch state in this article (see Figure 1 Illustration). In the switch state D1, the switching transistors A and C are turned on, and the switching transistors B and D are turned off. In the switch state DV, only the switching transistors C and D are turned on. In the switch state D2, only the switching transistors B and D are turned on. Finally, in the switch state DP, only the switching transistors A and B are turned on.

[0067] The switch controller and drive circuit 150 interprets the Mag1 and Mag2 signals and creates sequences. The high conversion rate (HCR) sequence is DP / D1 / DP / D2, where DP is for magnetization, and D1 and D2 are two different paths for demagnetization. The low conversion rate (LCR) sequence is D1 / DV / D2 / DV, where D1 and D2 are two different magnetization paths, and DV is for demagnetization. Therefore, D1 and D2 can be for magnetization (if in the LCR) or for demagnetization (if in the HCR). Inside the block 150, the choice of generating D1, D2, or DP based on the magnetization signals is determined based on the overlap situation of the two mag signals. If they overlap, they create DP. If they underlap (neither is true), then DV is created. If one is different from the other, then D1 is created for the case where Mag1 is 1, and D2 is created for the case where Mag2 is 1.

[0068] The synchronization operation depends on the duty cycle, which in turn determines whether the error signal is less than or greater than 50% of the midpoint of the peak voltages of the two ramp signals (half of the peak voltage). When the error signal rises, the on-time of the D1 switch state approaches the period of the clock signal. However, there is a minimum off-time that prevents the first magnetization signal from having an on-time equal to the clock period. If the on-time of the first control signal 121 from the comparator 120 exceeds the clock signal period minus the minimum off-time, the first control signal 121 is reset even if the first ramp signal has not risen to equal the error signal. The minimum off-time timer 122 times the minimum off-time period. For example, the minimum off-time timer 122 can be formed by offsetting the clock signal by the minimum off-time period. In such an embodiment, the minimum off-time timer 122 will assert the offset clock signal at the start of the minimum off-time period before the assertion of the clock signal.

[0069] The switch controller 150 monitors whether the first magnetization signal must be reset due to the minimum off-time requirement to determine whether to transition from the synchronous operation to the asynchronous operation mode, in which there is a relatively small voltage difference between the input voltage and the output voltage. In one embodiment, the switch controller 150 counts the number of consecutive cycles of the clock signal in which the first magnetization signal is reset due to the minimum off-time requirement. For example, when the count equals 4, the switch controller 150 can transition to the asynchronous operation mode.

[0070] Regardless of how the transition to the asynchronous mode is triggered, the start of the on-time of the magnetization signal is no longer synchronized with the clock signal. During asynchronous operation, the switch controller 150 asserts the asynchronous trigger signal to trigger the first ramp generator to start ramping the first ramp signal and sets the RS latch 135 to set the first magnetization signal. During the asynchronous mode, the first magnetization signal is reset only when the first ramp signal has risen to equal the error signal, even if the final on-time of the first magnetization signal may exceed the clock signal period. Once the first magnetization signal is reset, it remains off for the minimum off-time, and then the first ramp signal is triggered by the asynchronous trigger signal to start ramping again while the first magnetization signal is set. Thus, during asynchronous operation, neither the first ramp signal nor the first magnetization signal is associated with the clock signal. The assertion and de-assertion of the second magnetization signal are similar during the asynchronous mode, as will be further explained herein.

[0071] Accordingly, the asynchronous operation allows the first magnetization signal to have a sufficiently long on-time such that the output voltage can be maintained at a desired level despite a relatively small voltage differential between the output voltage and the input voltage. However, once the duty cycle starts to decrease, the switch controller 150 must transition back to synchronous operation. A conventional transition from asynchronous operation to synchronous operation typically results in a significant perturbation of the output voltage. To prevent such perturbation during the transition and maintain regulation of the output voltage, the switch controller 150 uses a cycle timer 165 that times a cycle timer period that is shorter than the clock signal period.

[0072] Figure 2 is a flowchart of a method for controlling a buck converter according to the present disclosure. The buck converter may include one or more phases, each phase including an inductor. Each phase may include a high-side power switch coupled to a low-side power switch at a switch node. It should be understood that each phase may have more than two switches. For example, each inductor phase may have four switches (see Figure 1 and Figure 3A ).

[0073] In step 210, a driver is provided. The driver is configured to drive the power stage of the converter in a synchronous mode or an asynchronous operation mode using a minimum off-time. When the output voltage of the converter approaches the input voltage received by the converter, the duty cycle of the converter increases to a value limited by the minimum off-time.

[0074] In step 220, a first clock signal having a predefined pulse width is generated. The first clock may be referred to as a first buck clock. In step 230, a first stretchable clock signal having an adjustable pulse width and an adjustable period is generated.

[0075] In step 240, when transitioning from the synchronous mode to the asynchronous mode, the adjustable pulse width and the adjustable period of the stretchable clock signal increase. When the on-time is stretched beyond the normal period boundary defined by the buck clock, the cycle period can be stretched as needed.

[0076] An error signal can be generated by comparing the output voltage with a reference voltage. The pulse width of the stretchable clock signal increases as the error signal increases to a limit value. For example, the limit value can be set by a threshold of a ramp signal. The threshold of the ramp signal is an upper limit value indicating how high the ramp signal is allowed to increase. This also sets the minimum frequency (longest period) allowed to obtain a desired duty cycle. When this limit is reached, the converter changes from PDO to DO; that is, the signal starts to decrease; that is, it drops below regulation.

[0077] Figure 3A is a diagram of a power converter for implementing Figure 2 method. The power converter 300 is similar toFigure 1 a power converter 100, and use Figure 1 the same reference numerals as those described in Figure 1 the converter, the cycle timer 165 has been removed, and block 150 is replaced by a driver 350 including a PDO controller 360. Therefore, the power converter can be implemented on a smaller die area.

[0078] The circuit 300 can be referred to as a hybrid multilevel converter (in this case, a three-level converter). The Mag1 signal represents the main signal, while the Mag2 signal represents the slave signal. The Mag2 signal maintains a phase relationship of 180 degrees with respect to the Mag1 signal. It should be understood that additional phases can be added at different phase angles.

[0079] The input S of the (RS) latch 135 can be driven from the clock source 110 (buck_clk1 signal) or from the driver 350 (ramp_reset_1_ph1 signal). In non-PDO operation, the latch 135 is driven from the clock source, while in PDO mode, the latch 135 is driven from the PDO controller 360 within the driver 350. The RS latch 135 is also referred to as the D1 PWM latch in the following Figure 4 text.

[0080] Figure 3B is Figure 3A a schematic diagram of the driver circuit 350 used in the power converter of

[0081] Figure 3C The driver circuit 350 includes a high-side driver 351 for driving high-side power switches A and B; and a low-side driver 352 for driving low-side power switches C and D. The driver is also provided with a PDO controller 360 and a driver finite state machine 353. The driver state machine controls the high-side driver and the low-side driver based on the magnetization signals "mag_req1" and "mag_req2" provided by the PDO controller 360.

[0082] The logic circuit receives several signals, including the main clock "buck_clk", the master / slave signal "m_sb", the enable signal "pdo_en", the pdo input signal "pdo_in", and the comparator signal "pwm_n", where pwm_n is the inverted comparator output from the PWM comparator 120 / 125.

[0083] When m_sb is true, the controller is the master device; otherwise, it is the slave device. When pdo_en is true, the system is allowed to enter the pre-dropout mode to achieve the desired duty cycle. If it is false, the system will not enter the pre-dropout mode even if the duty cycle requested by the error amplifier exceeds the possible duty cycle of the given fixed cycle time and the minimum off time. The pdo_in signal comes from the main pdo output to enable the slave pdo to know that the master device is in the pdo mode.

[0084] The FSM is configured to generate several signals, including: the stretched clock signal "clk1s"; the ramp reset signal "ramp_reset" for resetting the ramp; the trigger signal "min_toff_trig", the asynchronous mode signal "pdo" indicating that the converter has transitioned to the asynchronous mode; and the magnetization request signal "mag_req" configured to start inductor magnetization.

[0085] Figure 4 is a schematic diagram showing Figure 3A the operation of the power converter. Two regions are shown, which respectively represent the operations in the synchronous mode and the asynchronous mode. In this example, the synchronous mode is referred to as the normal PWM sequence, and the asynchronous mode is referred to as the pre-dropout sequence. For ease of description, various states are numbered from state 1 to state 15.

[0086] The synchronous mode (normal PWM sequence) includes states 1, 2, 3, 4, 5, 6, and 7. The asynchronous mode (pre-dropout sequence) includes states 10, 12, 13, 14, 15, 1, 2, and 3. So states 1, 2, and 3 are overlapping states used in both modes. State 11 is the transition state from the synchronous mode to the asynchronous mode.

[0087] The operation starts from State 1. In State 1, the system (a state machine in this example) is waiting for the rising edge of the buck clock. When the rising edge of the clock is detected, the stretched clock "clk1s" is asserted in State 2. Next in State 3, the system evaluates whether the PWM comparators 120 / 125 have triggered. The voltage ramp (from 105 / 115) starts ramping up at the point where the magnetization signals (Mag1 / Mag2) start. This is because the Mag1 signal triggers the "ramp_reset" signal. This has not happened yet. The Mag1 signal corresponds to the on-time of the buck converter. After the magnetization signal starts, the ramp starts rising. When the ramp exceeds the output of the error amplifier 130 (ERV_OUT), the PWM comparators 120 / 125 trigger (go high), thus causing the termination of the PWM on-time, which is the time to reset the D1 PWM latches 135 / 140 in the schematic.

[0088] If the D1 PWM latches 135 / 140 are not set, the system enters State 4, otherwise it enters State 10. In State 4, the min_toff timer 122 is triggered (by the min_toff_trig1 signal), and after this timer has expired, the system advances to State 5, where the PWM latches 135 / 140 are set and inductor magnetization starts. As the system progresses through State 6, this also causes the reset of the stretched clock clk1s.

[0089] Once the inductor magnetization has started, the system waits in State 7 to determine, using an asynchronous arbiter, whether the clock occurs first or the PWM comparator triggers first. If the PWM comparator triggers first, the inductor magnetization terminates and the system returns to State 1, waiting for the next rising edge of the buck clock. Then another normal operation cycle occurs.

[0090] However, if the system is in State 7, where we have just terminated the stretched clock CLK1S and started the inductor magnetization, and if the buck clock edge occurs before the PWM comparator trigger event, the system advances from State 7 to State 11 instead of State 1. This is because the duty cycle is large enough such that the system will require a longer buck clock cycle period to achieve the desired duty cycle while still maintaining the minimum off-time requirement.

[0091] State 11 sets the stretched clock CLK1s and advances to State 10. State 11 also sets the pre-dropout (PDO) signal, which allows the system to know that it has advanced into the pre-dropout mode.

[0092] In state 10, the system waits for the completion of the PWM comparator trigger. This is because the clock edge occurs before the PWM comparator trigger event. Once the PWM comparator has triggered, the minimum toff timer is triggered again in state 12, and in state 13, the stretched clock is de-asserted.

[0093] Once the minimum toff time has expired, the PWM signal is set, and a new inductor magnetization immediately starts in state 14.

[0094] Then, the system advances to state 15. In this state, a buck clock or a PWM comparator trigger may occur, and the occurrence of one or the other event will indicate whether the system continues in the pre-dropout (PDO sequence) or returns to the normal PWM sequence.

[0095] If the clock edge occurs first, the system will advance to state 2, where the system will set the clk1s stretched pulse. If the system still needs to continue the pre-dropout operation, this may be the direction to exit from state 15. However, if the PWM comparator triggers first, then the state machine enters state 1, where the state machine will wait for another buck clock and then continue to move forward. In this case, the PDO signal is reset and the system will continue in the normal PWM mode.

[0096] If the system exits state 15 via the clock edge, state 2 will set the stretched clock CLK1s signal and will advance to state 3. In this case, state 3 will see that the PWM comparator has not triggered and will advance to state 10 again to repeat the pre-dropout cycle.

[0097] In summary, the state sequence of the PWM sequence is 1, 2, 3, 4, 5, 6, 7, 1...... etc. When entering the pre-dropout, the state sequence changes from 7 to the following: states 11, 10, 12, 13, 14, 15, 2, 3, and then back to 10. When coming out of the PDO, the sequence becomes 10, 12, 13, 14, 15, 1, 2, 3, 4, 5, 6, 7, 1, 2...... etc.

[0098] The proposed buck converter provides a smooth transition into and out of the "asynchronous dropout mode" while maintaining a relatively simple design. In particular, no cycle timer is required.

[0099] Figure 5 is a waveform diagram showing the following signals:

[0100] The buck clock signals "buck_clk1" and "buck_clk2", which are generated by the high-side and low-side clocks 110 respectively.

[0101] The magnetization request signals "mag_req_1_ph1" and "mag_req_2_ph1" are respectively generated by the high-side and low-side latches 135 and 140.

[0102] The PWM peak detection signals "pwm_n_1_ph1" and "pwm_n_2_ph1" are respectively generated via the high-side and low-side PWM comparators 120 and 125.

[0103] The ramp reset signals "ramp_reset_1_ph1" and "ramp_reset_2_ph1" are respectively generated by the FSMs 361b and 362b and received by the ramp generators 105 and 115 respectively.

[0104] The minimum toff restart signals "min_toff_trig1_ph1" and "min_toff_trig2_ph1" generated by the state machines 361b and 362b; and the minimum toff return signals "min_toff_rtn1_ph1" and "min_toff_rtn2_ph1".

[0105] The "m_hpwm_n" signal is also shown, which is a signal similar to pwm_n above, but it indicates that the alternative ramp has exceeded the error amplifier input.

[0106] The ramp signals ramp_1 510 and ramp_2 520 respectively generated by the ramp generators 105 and 115 are also shown, as well as the error amplifier voltage ERV_OUT 530 from the error amplifier 130.

[0107] Figure 5 The interaction of the ramp signals 510 and 520 with the magnetization request signals "mag_req_1_ph1" and "mag_req_2_ph1", the PWM peak detection (pwm_n_1_ph1 and pwm_n_2_ph1), and the buck clock is shown. In the normal synchronous mode shown, the buck clock starts the "min_toff_trig" signal. After the minimum off-time expires, "min_toff_rtn" is asserted. This causes "mag_req" and "mag_ack" not shown. This starts the ramp. When the ramp exceeds the error amplifier voltage 530, the "pwm_n" signal goes low, which terminates the magnetization and resets the ramp. Two channels with 180-degree interleaved phases are shown in the figure. The inversion of the "ramp_reset" signal is actually the magnetization output.

[0108] Figure 6It is a timing diagram showing the steady-state operation of PDO control in the normal (non-PDO) mode. The arrows represent the causal relationships triggered by the rising or falling edges. The timing diagram shows the buck clock labeled "vco_clk", and the persistent version "vco_clk_pers" of the buck clock signal. The persistent signal "vco_clk_pers" is the clock signal "vco_clk" seen through an asynchronous wait unit controlled by the clk1_go signal.

[0109] The stretched clock "clk1s" is also shown. Its rising edge starts from the buck clock, and its falling edge is based on the completion of the minimum off-time timer "min_toff_rtn" (see Figure 4 state 4 in). At the rising edge of the clk1s stretched clock, the min_toff_trig signal is asserted, which is the start of the minimum off-time timer. When the minimum off-time is reached, the min_toff_rtn signal is sent back from the timer, and it must also be causally confirmed by the state machine before it will be de-asserted. This works in a similar way to what is done to the vco_clk_pers signal using the wait unit.

[0110] The expiration of the timer then also causes the start of inductor magnetization, which is the signal labeled PWM1. Once this signal goes true, the ramp voltage starts to rise, and when the ramp voltage exceeds the error amplifier threshold, the PWM comparator signal will be seen (see Figure 5 ), and the asynchronous state machine will see the persistent version called pwm_comp_pers of the PWM comparator signal. This will cause the termination of inductor magnetization, and we will return to state 1, where we will wait for the next buck clock again.

[0111] Figure 7A It is a schematic diagram of the wait unit. The wait unit, also known as a persistence latch, is used to detect a signal in an asynchronous circuit and present that signal as a persistent signal to another asynchronous circuit, which will be held at the other asynchronous circuit until its presence has been causally confirmed.

[0112] The wait unit includes a mutex (MUTEX) unit that has two inputs R1, R2 and two outputs G1, G2. Input R1 receives the input signal "in" via an inverter. The second input R2 is coupled to an AND gate that receives the reset signal rst_n and the go signal from an asynchronous circuit such as an asynchronous state machine. The G2 output provides the persistent signal "in_pers" to the asynchronous circuit.

[0113] Figure 7B It is shown Figure 7AA timing diagram of the operation of the wait unit. The asynchronous state machine expects all signals entering it to be causally confirmed. When it looks for the presence of a signal (called an "in" in this case), it effectively opens a window in time. It does this by asserting the go signal. The mutex will only allow grant 1 (G1) or grant 2 (G2). If requests R1 and R2 are both high, only the one that arrives first will get its corresponding R1->G1 or R2->G2 grant. After a grant is issued, it will remain true until its request is de-asserted. If the "in" signal is low before the go signal, the R1 input of the mutex is true and R2 is low, so G1 is issued and will remain true until R1 goes away. The asynchronous circuit then asserts the go signal. Even though R2 is issued, G2 will not be issued until R1 is de-asserted. When "in" becomes true, R1 is de-asserted, which will cause G1 to turn off, and R2, which is now still high, will eventually cause G2 to go high. Once this happens, it will never turn off until the go signal is deasserted. This forces the persistent version of the signal to remain present until it causes the asynchronous state machine to acknowledge its presence.

[0114] Figure 8 is an example implementation of a MUTEX element or MUTEX cell. The MUTEX cell is formed by an SR latch circuit receiving R1 and R2, coupled to a filter circuit providing G1 and G2. The MUTEX cell is designed to safely decide the order in which the two input signals change. The main purpose of the MUTEX element is to capture any metastable event within itself and not allow the event to propagate to its output pins. Therefore, if the SR latch becomes metastable because both R1 and R2 are asserted within the metastable window time of each other, since the outputs SR1 and SR2 will be at VDD / 2, both the N-channel FETs in the filter will be turned on, and both the G1 and G2 outputs will remain low until the metastability is resolved internally. Only after that time will the winner among the inputs be authorized as the output.

[0115] Figure 9A , Figure 9B and Figure 9C A signal transition diagram (STG) is shown that defines the cause-and-effect order of signals in an asynchronous finite state machine (AFSM). The signals shown in brackets are input signals to the state machine. The other signals are outputs from the state machine. The circled numbers correspond to Figure 4 The status number in .

[0116] The signals provided within square brackets are internal signals that exist within the STG and are not taken out. They have no other purpose than to make the circuit synthesizable when they are used to resolve encoding state conflicts. State variables are connections of input, output, and internal signals. Without internal signals, there would be multiple locations within the state machine where all the signals present have the same state. This problem is solved by adding state bits called internal signals, such that each token location presents a unique different state encoding.

[0117] The input has been processed through a type of persistent latch and arbiter (including a bidirectional arbiter) similar to Figure 7A a waiting cell. These devices are a special form of persistent latch that observes two input signals, "sig1" and "sig2" (instead of one); and waits for the first signal to appear and its corresponding authorization to be set until it is confirmed.

[0118] Using a tool called Workcraft, the STG is compiled into a logic gate circuit that strengthens the causal relationship of the output signal as long as the input signals (within the brackets) conform to the causal relationships described in this schematic. By using persistent latches and arbiters, the input signals are forced to comply with the causal relationship links.

[0119] Figure 10 is an exemplary implementation of a bidirectional arbiter. Arbiter 1000 includes three MUTEX units labeled g4, g4a, and g5. The first MUTEX unit g4 receives signal sig1 via inverter g1. The second MUTEX unit g4a receives signal sig2 via inverter g3. The third MUTEX unit g5 receives the G2 outputs of g4 and g4a respectively. Three AND gates labeled g0, g8, and g7 are also provided. AND gate g0 receives the control signal "ctrl" and the reset signal "rst_n". AND gate g8 receives the output G1 of g5 and the output of g0 and provides signal me1. Similarly, AND gate g7 receives the output G2 of g5 and the output of g0 and provides output me2.

[0120] The function of the bidirectional arbiter above is that when the ctrl input goes high, both MUTEX elements g4 and g4a set R2. When sig1 or sig2 occurs, the corresponding mutex will assert its G2, which will go to the R1 input and R2 input of g5 respectively. The g5 element determines the winner (which one occurred first). It will assert G1 or G2, and G1 or G2 will assert the mutually exclusive outputs me1 or me2 through g7 and g8. Whichever one is set will be guaranteed to remain set until the ctrl signal (similar to the go signal in a simple persistent latch) is de-asserted. This ensures that it is taken fromFigures 9A - 9C The signals seen by the circuit for STG synthesis will only see persistent inputs.

[0121] Figure 11 It is a waveform diagram showing the operation of the PDO controller (also known as the PDO module) as Figure 3C shown. As Figure 3A shown, for one inductor phase, but two (180-degree) ramp phases provide operation. Figure 11 The following signals are shown:

[0122] The buck clock signals "VCO_CLK1" and "VCO_CLK2" generated by the high-side and low-side clocks 110 respectively.

[0123] The stretched clock signals "CLK1S" and "CLK2S".

[0124] The PWM peak detection signals "D1_pwm" and "D2_pwm" generated by the high-side and low-side PWM comparators 120 and 125 respectively. These signals correspond to Figure 5 "pwm_n_1_ph1" and "pwm_n_2_ph1" in

[0125] The minimum toff signals "Min_TOFF D1" and "Min_TOFF D2".

[0126] The signals "PWM Comp1" and "PWM Comp2". PWM Comp1 is the original comparator output, which is inverted to generate D1_pwm (pwn_n_1_ph1).

[0127] The ramp signals ramp_1 1110 and ramp_2 1120 generated by the ramp generators 105 and 115 respectively are also shown, as well as the error amplifier voltage ERV_OUT 1130 from the error amplifier 130.

[0128] The output or load current 1140 and the inductor current 1150 are also represented.

[0129] As the error amplifier voltage ERV_OUT 1130 rises, the ramps 1110 and 1120 become higher and higher, resulting in wider cycles of the stretched clocks CLK1S and CLK2S, and the falling edges of the stretched clocks CLK1S and CLK2S define new buck cycles.

[0130] Figure 12A and Figure 12B show a more detailed transition from PWM to PDO operation.

[0131] Figure 13A and Figure 13BShows a more detailed transition from PDO to PWM operation.

[0132] Figure 14A and Figure 14B Shows an exemplary implementation of a sub-PDO controller used in the Figure 3C PDO controller. For clarity, the illustration is divided into two figures. Labels A, B,......, H indicate the Figure 14A and Figure 14B connections between the elements of.

[0133] The main block of the PDO controller 1400 labeled g0 represents a finite state machine FSM (e.g., Figure 3C 361b in Figure 3C ), while the other elements represent logic circuits (e.g., Figures 9A - 9C the logic circuit 361a in

[0134] ). Block g0 is the FSM that implements the

[0135] STG in

[0136] The remaining logic is used to connect and surround block g0 using persistent signals. The logic circuit of the PDO controller or PDO module 1400 includes 3 signal multiplexers (g9, g13, g7) and 8 persistent latches, which include 5 wait units (g5, g6, g17, g18, g21) and 3 bidirectional arbitrators (g1, g2, g8).

[0137] i) clk1s - This is the "stretched clock". In the design, this is mostly a debug signal that is output but not used by any surrounding circuits. This signal can be observed to get a good view of how the clock is modified.

[0138] ii) ramp_reset - This signal is used to reset the ramp. It is generated from the pwm output of the STG circuit. When ramp_reset is low, when PWM is true, the ramp rises. When PWM is not true, the ramp is reset to 0. For example, look at Figure 5, when ramp_reset_1_ph1 goes low, ramp 520 starts to rise. When it is re-asserted to true, the ramp drops back down to the pedestal value.

[0139] iii) min_toff_trig - This is the trigger for a constant-current-based capacitor timer (I on C) which, combined with a mutex element, will indicate via the min_toff_rtn signal (lower than the in input) that the minimum off-time has expired. The Ion C timer is as Figure 15 shown.

[0140] iv) pdo - A signal indicating that the STG has transitioned to the pre-differential pressure mode; that is, the duty cycle has risen beyond what can be tolerated without extending the cycle to maintain the required minimum off-time.

[0141] v) mag_req - A signal going to the driver state machine 353, indicating that inductor magnetization is about to start.

[0142] In addition, the inverter g12 of the logic circuit provides another output signal labeled "one_shot_trig" - a signal that drives a one-shot that generates a short pulse at the rising edge of the m_hpwm_n signal (the input to g12). This is done to make the comparator output look more like the pwm_n signal which only exists temporarily. Its width determines how far the two ramps can deviate from each other without causing problems.

[0143] The input signals include:

[0144] i) buck_clk - This is the main clock in the system and it defines the cycle boundaries when not in the pre-differential pressure mode. buck_clk is received by g9.

[0145] ii) m_sb - The master / slave bar signal. When this signal is true, the module is the master channel and has the ability to control other channels. When it is false, the module is a slave device and will then accept the input on the pdo_in signal (described below). This feature is used to ensure that all ramp phases are always in the same mode. The signal m_sb is received by g19 and g7.

[0146] iii) pdo_en - The enable signal. When it is true, the system is allowed to enter the pre-differential pressure mode to achieve the required duty cycle. If it is false, the system will not enter the pre-differential pressure mode even if the duty cycle requested by the error amplifier exceeds the achievable duty cycle given a fixed cycle time and minimum off-time. The pdo_en signal is received by g3, g15 and g7.

[0147] iv) pwm_n - This is the inverted comparator output that tells the system that the ramp has exceeded the error amplifier input. The pwm_n signal is received by g11.

[0148] v) m_hpwm_n - This is a signal similar to pwm_n above, but it indicates that the alternative ramp has exceeded the error amplifier input. It can be used in place of pwm_n when the channel is a slave channel and when in the pre - dead - time mode. The signal m_hpwm_n is received by g12, g18, and g21.

[0149] vi) pdo_in - A signal from the master PDO output that is used to let the slave PDO know that the master PDO is in PDO mode. For simplicity, even on the master device, this input should be driven by the PDO output of the same master device. The pdo_in signal is received by g22.

[0150] vii) min_toff_rtn - Used together with the output "min_toff_trig" as an indicator for the block that the time has expired since the self - trigger occurred, i.e., the minimum off - time has expired. The min_toff_rtn signal is received by g17.

[0151] viii) ss_done - Soft - start completed. If in the pre - dead - time mode, this signal is used to ensure that the slave channel terminates magnetization when its own ramp exceeds the error amplifier input; in other cases it will use the m_hwpm_n signal. When the system starts, since the load sharing is not yet balanced, the error amplifiers of some phases may not be well - matched. This signal is provided to the block so that it will tell the block when the load balancing of multiple inductor phases has occurred, which means the error amplifiers may be balanced and it is safe for the slave device to use the alternative ramp input. The signal ss_done is received by g21.

[0152] ix) mag_ack - An input used to confirm that the system has issued the inductor magnetization "mag_req" requested by the output signal. The mag_ack signal is received by g0.

[0153] x) one_shot_rtn - The return of a one - shot flip - flop triggered from the "pdo_in" signal.

[0154] The PDO controller or PDO module contains 3 signal multiplexers (g9, g13, g7) and 8 persistent latches, and these 8 persistent latches include 5 wait units (g5, g6, g17, g18, g21) and 3 bidirectional arbitrators (g1, g2, g8).

[0155] The g9 multiplexer is used to select the source of the buck clock. If the module is the master, then this is always the buck clock input. However, if it is a slave, and if pdo_en is true, and if the pdo_in signal from the master is true, then in this case, the m_hpwm_n signal will be used as the buck clock so that the slave remains in sync with the master during the pre-drop operation.

[0156] The g13 multiplexer is used to select the source of the peak detection signal that is used to terminate magnetization. If the PDO module is the master, then the source of this signal will always be pwm_n. If it is a slave, and pdo_in is true, indicating that the master is in PDO mode, and pdo_en is true, and ss_done has been seen, then the source of this signal is m_hpwm_n. Note that if m_hpwm_n is both the clock and the peak comparison, it itself defines the pre-drop magnetization, which keeps the slave aligned with the master at a certain specified phase.

[0157] The third multiplexer is g7, which is used to construct the pdo_en_y signal and the pdo_en_n signal for the g2 arbiter, which is used by the FMS g0 as a sampler to determine whether it can enter the pdo section of the FSM.

[0158] The persistence latches (or what they are sometimes called sanitization registers) are as follows:

[0159] The wait unit g18 is used as a latch to sample pdo_in. It uses the m_hpwm_n signal as its clock. The wait unit g21 does the same thing for the ss_done input. The above two wait units do not sanitize the signals of the FSM g0, but they are used as latches in the external logic. The wait unit g17 is used with the I on C timer to sanitize the min_toff_rtn signal.

[0160] Figures 9A - 9C of the STG and Figures 14A - 14B The circuit of represents a possible embodiment of the PDO controller. It should be understood that different designs can be envisioned.

[0161] For simple bucking, a single sub-PDO controller will be used. For Figure 3A the converter circuit shown, two PDO sub-controllers are used, as Figure 3C shown. Other converters with more inductor phases can be envisioned. For example, a converter with two inductor phases that are both multi-level (MLC) will require 4 sub-PDO converters; that is, 1 master and 3 slaves.

[0162] Figure 15 Shows an Figure 3A example implementation of the minimum turn-off time timer 122. In this example, the timer 122 is provided by an IonC timer constructed using a wait cell.

[0163] The FSM issues a min_toff_trig signal, which is received by the Figure 15 AND gate in and is shown as the "go signal". This enables the "trig" signal to be provided to the IonC timer 1510. In turn, this allows current to flow into the capacitor C1, resulting in a voltage ramp-up across the capacitor. When this voltage exceeds the gate threshold (a comparator can be used for accuracy), then the "rtn" signal will go to the mutex unit 1520 through an inverter and cause the "done (completed)" signal to be asserted high. This will cut off the charging of the capacitor C1 and discharge the capacitor C1. The switched constant current source I1 is used to generate a linear ramp across the capacitor C1. The rtn output signal may have glitches, but the mutex 1520 will make the "done" signal glitch-free, and it will remain true until the "go" signal disappears. The "go" signal will not be asserted until the "done" signal connected to the FSM min_toff_rtn signal has been seen; thus establishing the required causal relationship confirmation.

[0164] The two-way arbiter g2 acts as a sampler because the true and complement values of the same signal are applied to its two sig inputs. Thus, when ctrl is asserted, either me1 or me2 will be asserted, and these outputs are connected to the pdo_en_y_pers (persistence is (yes)) input and the pdo_en_n_pers (persistence no (no)) input of the FSM g0. Each time the FSM traverses the signal loop, if it wants to enter the pre-pressure difference mode, it will sample this arbiter to determine if it can go to the pre-pressure difference mode.

[0165] The two-way arbiter g8 determines whether the buck clock or the pwm comparator trigger occurs first. This corresponds to Figure 9B state 7 in the STG (and Figure 4 the flowchart of). The FSM uses this to determine if it wants to attempt to enter the pre-pressure difference mode. If the clock arrives first, it indicates that a duty cycle higher than what can be provided by the fixed cycle time under the fixed min_toff requirement is needed.

[0166] The two-way arbiter g1 again determines whether the buck clock or the pwm comparator trigger occurs first. This corresponds to Figure 9BThe state 15 of the STG. In this state, it is decided whether to stay in the pre-pressure difference mode or exit and return to the PWM mode. If the comparator triggers first, the pre-pressure difference mode will be left, but if the clock occurs first, it will stay in the pre-pressure difference mode.

[0167] The wait unit g5 observes the pwm_n signal (or its alternative signal in the slave mode). It corresponds to Figure 9C the state 10 of the STG (and Figure 4 the flowchart).

[0168] The wait unit g6 observes the buck clock (or its alternative clock in the slave mode). It corresponds to Figure 9A the state 1 of the STG (and Figure 4 the flowchart).

[0169] Figure 16A and Figure 16B shows the operation of the PDO controller with two synchronous ramps.

[0170] Figure 16A shows the logic signal "m_hwpm_n" as one of the input signals received by the Figure 14A logic circuit (see g12, g18, and g21). The falling edge of the m_hwpm_n signal causes the "one_shot_trig" signal (the output of g12). In the PDO mode, it acts as the buck clock of the slave device, enabling the slave device to maintain a 180-degree out-of-phase synchronization. The "m_hpwm_n" signal is the comparator output, and the threshold of this comparator output is 1 / 2 of the error amplifier output value. Therefore, at the midpoint of the duty cycle, this will be the start of the second-channel ramp. Essentially, this should be consistent with the time when the second ramp reaches its peak. However, there may be a limited difference in the ramp rate. The one-shot is created wide enough so that these two events will overlap. This same capability can be used for additional channels. For example, for 4 ramps, there may be 1 / 2, 1 / 4, and 3 / 4 error amplifier signals based on the ramp of channel 1 for channels 2, 3, and 4 respectively.

[0171] Figure 17 is a schematic diagram of the PDO controller 1700 implemented as the master controller. The PDO controller 1700 includes an FSM and logic 1705, an I on C timer 1710, two delay modules 1730 and 1740, and a one-shot trigger 1750. The FSM and logic 1705 can be as Figure 14A and Figure 14BThe implementation described above. The signal called pdo1_ph1 on the right side of 1705 is also fed back into the pdo_in signal on the left side of 1705. The I on C analog timer 1710 receives the "ramp_reset" signal from the FSM and the logic 1705 (which acts as the master device). The main ramp generator includes a current source I1, a capacitor C1, and a comparator U4. The comparator U4 has an inverting input that receives the output of an error amplifier labeled IEA and a non-inverting input that receives vramp1_ph1 (the output of the I on C timer). The comparator U4 compares the signal vramp1_ph1 with the signal IEA to provide the raw trigger output pwm_r1_ph1 that enters the pwm_n input of the FSM 1705.

[0172] The min_toff timer 1730 is modeled using a delay U30 and an AND gate U5. The AND gate U5 receives the "min_toff_trig" signal from the FSM at one input and a delayed version of the "min_toff_trig" signal at the other input. The output of the AND gate U5 is "min_toff_rtn" received by the FSM.

[0173] Another delay module 1740 is provided by a delay U12 and an AND gate U13. The delay module 1740 is used to model the response time based on "mag_req". The AND gate U13 receives the "mag_req" signal from the FSM at one input and a delayed version of the "mag_req" signal at the other input. The output of the AND gate U13 is "mag_ack" received by the FSM.

[0174] There is also a one-shot trigger U8 1750, which is used by the PDO module to ensure that the m_hpwm_n signal can be seen as long as the ramps are balanced within each other's limits. The m_hpwm_n signal is Figure 17 tied low in [the relevant context] because it is a master channel that does not use it. The one-shot is used to ensure that the system responds to the rising edge of the cross-phase comparator in the pre-pressure-difference mode. It should be wide enough to compensate for mismatches between the ramps. It should also be wide enough so that if one channel is within the limits but slower or faster than the other channel, it will still be captured.

[0175] As Figure 17 shown, the main difference between the main PDO controller and the slave PDO controller is that the "m_sb" signal will be set low, and "m_hpwm_n" will be connected to a comparator whose threshold is set, for example, to 1 / 2 of the error amplifier voltage, so that when in the pre-pressure-difference mode, it will trigger at 180 degrees out of phase. The slave operation defined here can also be seen in Figure 17 inFigure 17 Among them, the operation of the additional ramp comparator threshold "m_hpwm_n" signal is used to keep the ramp in proper phase synchronization with respect to the defined main ramp.

[0176] Those skilled in the art will understand that variations of the disclosed arrangements are possible without departing from the present disclosure. Therefore, the above description of specific embodiments is made by way of example only and not for the purpose of limitation. It will be clear to those skilled in the art that minor modifications can be made without significantly changing the described operations.

Claims

1. A buck converter configured to receive an input voltage and provide an output voltage, the buck converter comprising: a power stage having at least one phase, each phase including an inductor; a driver configured to drive the power stage in a synchronous mode or an asynchronous mode using a minimum off time; wherein When the output voltage approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off time; as well as a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; and Wherein, when transitioning from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal.

2. The buck converter according to claim 1, wherein: The driver includes a first state machine configured to generate the first stretchable clock signal and adjust a pulse width and a period of the first stretchable clock signal.

3. The buck converter according to claim 1, wherein: The first clock signal and the first stretchable clock signal are in phase.

4. The buck converter according to claim 2, comprising: a first ramp generator configured to generate a first ramp signal in response to the first clock signal; as well as an error comparator configured to generate an error signal by comparing the output voltage with a reference voltage, Wherein, the pulse width of the first stretchable clock signal increases as the error signal increases to a limit value.

5. The buck converter according to claim 4, comprising a first comparator, the first comparator being configured to compare the first ramp signal with the error signal, and wherein when the first ramp signal increases to become equal to the error signal, the first comparator is triggered and the output of the first comparator becomes high.

6. The buck converter according to claim 5, wherein: If the first clock signal occurs before a first comparator triggering event, the converter transitions to the asynchronous mode, otherwise the converter remains in the synchronous mode.

7. The buck converter according to claim 2, wherein: The first state machine is configured to generate: a first ramp reset signal to reset the first ramp signal; a first asynchronous mode signal indicating that the converter has transitioned to an asynchronous mode; a first minimum off-time trigger signal configured to trigger the start of a timer; and a first magnetization request signal configured to start inductor magnetization after the timer is completed.

8. The buck converter of claim 2, comprising a first logic circuit coupled to the first state machine.

9. The buck converter according to claim 8, wherein: The first logic circuit includes a plurality of persistent latches.

10. The buck converter of claim 8, comprising a second state machine coupled to the second logic circuit; the second state machine being configured to generate a second stretchable clock signal having an adjustable pulse width and an adjustable period.

11. The buck converter according to claim 10, wherein: The first logic circuit and the second logic circuit are configured to receive logic signals, and the logic signals are used to set the first state machine and the second state machine as a master device or a slave device, so that when the first state machine is a master device, the second state machine is a slave device, and conversely, when the first state machine is a slave device, the second state machine is a master device.

12. The buck converter according to claim 10, comprising a second ramp generator; wherein: The second state machine is configured to generate a second ramp reset signal to reset the second ramp signal.

13. The buck converter according to claim 10, wherein: The second state machine is configured to generate: a second asynchronous mode signal indicating that the converter has transitioned to asynchronous mode; a second minimum off-time trigger signal configured to trigger the start of a timer; and a second magnetization request signal configured to start inductor magnetization after the timer is completed. 14 . The buck converter of claim 1 , comprising a minimum off-time timer configured to start upon receiving a trigger signal.

15. A method of controlling a buck converter, the buck converter being configured to receive an input voltage and provide an output voltage, the method comprising: providing a driver configured to drive a power stage of the converter in a synchronous mode or an asynchronous mode using a minimum off time; wherein when the output voltage approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off time; generating a first clock signal having a predefined pulse width; generating a first stretchable clock signal having an adjustable pulse width and an adjustable period; as well as Upon transition from the synchronous mode to the asynchronous mode, an adjustable pulse width and an adjustable period of the first stretchable clock signal are increased.

16. The method according to claim 15, comprising: generating a first ramp signal in response to the first clock signal; as well as generating an error signal by comparing the output voltage with a reference voltage; Wherein, the pulse width of the first stretchable clock signal increases as the error signal increases to a limit value.

17. The method of claim 15, comprising generating an enable signal to effectuate a transition between the synchronous mode to the asynchronous mode.

18. The method of claim 15, comprising generating a magnetization request signal to magnetize the inductor.

19. The method according to claim 18, wherein: The magnetization of the inductor is caused by the expiration of the minimum off-time timer.

20. A controller for use with a buck converter, the controller comprising: a driver configured to drive a power stage of the converter in a synchronous mode or an asynchronous mode using a minimum off-time; wherein when the output voltage of the converter approaches the input voltage, the duty cycle of the converter increases to a value limited by the minimum off time; as well as a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; and Wherein, when transitioning from the synchronous mode to the asynchronous mode, the driver is configured to increase the adjustable pulse width and period of the first stretchable clock signal.

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