Digital adjustable grid-control power supply

Abstract

A digital adjustable grid-control power supply comprises a positive bias power supply, a negative bias power supply and a modulation circuit. The positive bias driving circuit generates two paths of pulses, an alternating current signal is formed through the positive bias switching circuit, and a positive bias voltage is obtained through the positive bias rectifying circuit. The negative bias driving circuit generates two paths of pulses, an alternating current signal is formed through the negative bias switching circuit, and negative bias voltage is obtained through the rectifying circuit; the turn-on pulse driver and the turn-off pulse driver respectively drive the modulation switch tube through the turn-on pulse isolation transformer and the turn-off pulse isolation transformer, and modulate the positive bias voltage and the negative bias voltage into pulse waveforms with required pulse width and period; the PWM control chip realizes digital adjustment of the output grid control pulse, manual adjustment is not needed, the safety risk is low, the reliability is high, the adjustment precision is high, the heat loss is small, and the pulse waveform stability is high; the modular design is adopted, adjustment is convenient, debugging and maintenance are convenient, the reverse impact influence on the load circuit during high repetition frequency work is reduced, the application range is wide, and the applicability is good.

Description

Technical Field

[0001] The present invention relates to the field of grid-controlled power supplies, and particularly to a digital adjustable grid-controlled power supply. Background Art

[0002] In the existing grid-controlled power supply control technology, an adjustable transformer is manually adjusted to achieve adjustable alternating current output, which is then transmitted to a high potential through a high-voltage isolation transformer for rectification and filtering to generate a controllable grid-controlled power supply. This grid-controlled power supply that uses an adjustable transformer to adjust the grid-controlled voltage can meet the high-voltage insulation problem. However, manually adjusting the adjustable transformer to adjust the grid-controlled power supply poses a certain risk of electric shock. At the same time, the adjustment accuracy of this method of adjusting the grid-controlled power supply is not high. In addition, the entire system is large in volume and heavy in weight, making debugging and maintenance extremely inconvenient. Summary of the Invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a digital adjustable grid-controlled power supply. The digital adjustable grid-controlled power supply uses a PWM control chip to achieve digital adjustment of the output grid-controlled pulse, without manual adjustment, with low safety risk, high reliability, high adjustment accuracy, small heat loss, and high pulse waveform stability. The present invention adopts a modular design, which is convenient for adjustment and is conducive to debugging and maintenance. The modulation pulse voltage of the present invention has steep leading and trailing edges, good pulse waveforms, and reduces the reverse impact on the load circuit during high-repetition-frequency operation. The pulse width of the present invention is adjustable from 1 to 50 μs, and the repetition frequency is adjustable from 100 Hz to 10 kHz, which can adapt to various tube types, has a wide application range, and good applicability.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions: A digital adjustable grid-controlled power supply includes a positive bias power supply, a negative bias power supply, and a modulation circuit; The positive bias power supply is composed of a positive bias drive circuit, a positive bias switch circuit, and a positive bias rectification circuit; the positive bias drive circuit generates two paths of pulses, forms an alternating current signal through the positive bias switch circuit, and obtains a positive bias voltage through the positive bias rectification circuit; The negative bias power supply is composed of a negative bias drive circuit, a negative bias switch circuit, and a negative bias rectification circuit; the negative bias drive circuit generates two paths of pulses, forms an alternating current signal through the negative bias switch circuit, and obtains a negative bias voltage through the rectification circuit; The modulation circuit is composed of a turn-on and turn-off drive pulse circuit and a modulation switch circuit; the turn-on pulse drive and the turn-off pulse drive respectively drive the modulation switch tube through the turn-on pulse isolation transformer and the turn-off isolation pulse transformer, and modulate the positive bias voltage and the negative bias voltage into a pulse waveform with the required pulse width and period.

[0005] Further, the positive bias driving circuit includes a driving chip N10 and an operational amplifier N11. The driving chip N10 is a PWM control chip. Its pin 2 is the reference input terminal, which receives an externally adjustable DC voltage of 0 - 10V to set the output voltage reference of the chip. Pin 5 is the input terminal of the filter capacitor, connected to one end of the filter capacitor C16, and the other end of the filter capacitor C16 is grounded. Pin 6 is the input terminal of the filter resistor, connected to one ends of the adjustable resistor R13 and the resistor R14. The other ends of the adjustable resistor R13 and the resistor R14 are grounded. Pin 7 is connected to the discharge resistor R15, and the discharge resistor R15 is grounded through the filter capacitor C16. Pin 8 is the soft start terminal, connected to one end of the soft start capacitor C17, and the other end of the soft start capacitor C17 is grounded. By adjusting the capacitance value of the soft start capacitor C17, the start time of the chip pulse output is changed to achieve the soft start function. Pin 16 is connected to one end of the capacitor C15, and the other end of the capacitor C15 is grounded. Pin 15 is the positive power supply terminal, connected to the power supply to provide the electrical energy required for the operation of the driving chip N10. Pin 12 is the grounding terminal, directly grounded to ensure the safe operation of the circuit. Pins 14 and 11 are the pulse output terminals, outputting control signals to drive the subsequent circuit. Pin 10 is the feedback lock control terminal, to which the signals after rectification and sampling of IP5 and IP6 are sent. The sampling filter capacitors C21, C22, the voltage dividing sampling resistor chain, the filter capacitors C19, C20, and the diode chain are connected in parallel between pin 10 and IP5, IP6. The voltage dividing sampling resistor chain is composed of the parallel voltage sampling resistors R17, R18, R19, R20, and the diode chain is composed of the parallel diodes D3, D4, D5, D6. The signals after rectification and sampling of IP5 and IP6 are sent to this pin. Pin 9 is connected to pin 1, participating in the feedback compensation process. IP5 and IP6 come from the positive bias switching circuit and are the AC feedback inputs. The operational amplifier N11 is a driver, located on the right side of the driving chip N10. Pins 10 and 12 are the pulse input terminals, respectively corresponding to and connected to pins 11 and 14 of the driving chip N10 to receive the pulse signals from the driving chip N10. Pins 3 and 9 are the positive power supply terminals connected to the power supply. Pin 2 is the grounding terminal, directly grounded. Pins 1 and 7 are the driving pulse output terminals, outputting driving signals to the subsequent circuit. Pins 11 and 13 are the low - level locking terminals, directly grounded to ensure the normal operation of the driver. A diode D2 is connected between pins 3 and 6 to suppress reverse current and protect the circuit from the impact of reverse voltage. A filter capacitor C18 is connected between pins 5 and 6. The positive bias switching circuit consists of a first - stage switching tube, two - stage two - group switching tubes and an auxiliary circuit. OUT1 and OUT2 are two control pulses sent from the positive bias driving circuit, driving the MOS tubes V2 and V3 to work, thereby forming the AC signals AC1 and AC2. This switching circuit is a half - bridge circuit. The non-inverting input terminal 3 of the voltage comparator N1 is connected to an external 0 - 10V adjustable DC signal source through a current-limiting resistor R3; the inverting input terminal 2 of the voltage comparator N1 is connected to a current-limiting resistor R4, and the other end of the current-limiting resistor R4 is connected to the common terminal of the voltage-dividing sampling resistors R7 and R8; the 8th pin of the voltage comparator N1 is externally connected to a 12V power supply, and the 4th pin is grounded; the output terminal 1 of the voltage comparator N1 is connected to the base of the transistor V4 through a resistor R6, thereby adjusting the conduction degree of the MOS transistor V1; the emitter of the transistor V4 is grounded; a capacitor C3 and a resistor R5 are connected in series between the output terminal 1 and the inverting input terminal 2 of the voltage comparator N1; The source, drain, and gate of the MOS transistor V1 are respectively connected to one end of the bus inductor L1, one end of the capacitor chain C9 - C14, and one end of the current-limiting resistor R2; the other end of the bus inductor L1 is externally connected to a 48V DC power supply; a diode D1, a resistor R1, and a capacitor C1 are connected in parallel between the source and the gate of the MOS transistor V1; the other end of the current-limiting resistor R2 is connected to the collector of the transistor V4; the drain of the MOS transistor V1 is grounded through filter capacitors C5 and C6, and is also grounded through voltage-dividing sampling resistors R7 and R8, and a sampling filter capacitor C4 is connected in parallel across both ends of the resistor R8; The drain of the MOS transistor V2 is connected to one end of the capacitor chain C9 - C14, the gate is connected to OUT1 through a current-limiting resistor R9, and the source is connected to the drain of the MOS transistor V3 and the 1st pin of the isolation feedback transformer T2; a capacitor C7 is connected between the drain and the source of the MOS transistor V2, and a resistor R10 is connected between the source and the gate of the MOS transistor V2; The source of the MOS transistor V3 is connected to the other end of the capacitor chain C9 - C14 and grounded, the gate is connected to OUT2 through a current-limiting resistor R11, and the drain is connected to the source of the MOS transistor V2 and the 1st pin of the isolation feedback transformer T2; a capacitor C8 is connected between the drain and the source of the MOS transistor V3, and a resistor R12 is connected between the source and the gate of the MOS transistor V3; One end of the capacitor chain C9 - C14 is connected to the drain of the MOS transistor V2, the other end is grounded, and the middle end is connected to AC1; the isolation feedback transformer T2 is respectively connected to the drain of the MOS transistor V3, the AC signal AC2, IP5, and IP6; The forward-biased rectification circuit includes a forward-biased high-voltage isolation transformer T1 and a voltage-doubling rectification circuit. The AC signals AC1 and AC2 generated by the forward-biased switch circuit are transmitted to a high potential through the forward-biased high-voltage isolation transformer T1, and then rectified into a DC voltage through a voltage-doubling rectification circuit composed of diodes D7, D8, capacitors C23, and C24 connected in parallel. A filter inductor L2 is provided at the positive pole of the voltage-doubling rectification circuit, and filter capacitors C25, and filter resistors R21, R22, and R23 are connected in parallel between the positive and negative poles of the voltage-doubling rectification circuit.

[0006] Further, the negative bias driving circuit includes a driving chip N3 and an operational amplifier N2. The driving chip N3 is a PWM control chip. Its pin 2 is the reference input terminal, which receives an externally adjustable DC voltage of 0 - 10V. Pin 5 is the input terminal for the filtering capacitor, connected to one end of the filtering capacitor C35, and the other end of the filtering capacitor C35 is grounded. Pin 6 is the input terminal for the filtering resistor, in parallel with the chip filtering resistor R32 and the adjustable resistor R34, and the other ends of the resistor R32 and the adjustable resistor R34 are grounded. Pin 7 is connected to the discharging resistor R31, and the discharging resistor R31 is grounded through the filtering capacitor C35. Pin 8 is the soft start terminal, connected to one end of the soft start capacitor C33, and the other end of the soft start capacitor C33 is grounded. By adjusting the capacitance value of the soft start capacitor C17, the start time of the chip pulse output is changed to achieve the soft start function. Pin 16 is connected to one end of the capacitor C34, and the other end of the capacitor C34 is grounded. Pin 15 is the positive power supply terminal, connected to the power supply to provide the electrical energy required for the operation of the driving chip N3. Pin 12 is the grounding terminal, directly grounded to ensure the safe operation of the circuit. Pins 14 and 11 are the pulse output terminals, outputting control signals to drive the subsequent circuit. Pin 10 is the feedback locking control terminal, and the signals after rectification and sampling of IP7 and IP8 are sent to this pin. The sampling filtering capacitors C30, C31, the voltage dividing sampling resistor chain, the filtering capacitors C29, C32, and the diode chain are connected in parallel between pin 10 and IP7, IP8. The voltage dividing sampling resistor chain is composed of the voltage sampling resistors R27, R28, R29, and R30 connected in parallel, and the diode chain is composed of the diodes D11, D12, D13, and D14 connected in parallel. Pin 9 is connected to pin 1 and participates in the feedback compensation process. IP7 and IP8 come from the negative bias switching circuit and are the AC feedback inputs. The operational amplifier N2 is a driver, with the model IR2113. Its position is on the right side of the driving chip N3. Pins 10 and 12 are the pulse input terminals, respectively corresponding to and connected to pins 11 and 14 of the driving chip N3 to receive the pulse signals from the driving chip N3. Pins 3 and 9 are the positive power supply terminals connected to the power supply. Pin 2 is the grounding terminal, directly grounded. Pins 1 and 7 are the driving pulse output terminals, outputting driving signals to the subsequent circuit. Pins 11 and 13 are the low - level locking terminals, directly grounded. A diode D15 is connected between pins 3 and 6 to suppress reverse current and protect the circuit from the impact of reverse voltage. A filtering capacitor C36 is connected between pins 5 and 6. The negative bias switching circuit consists of a primary switching tube, two secondary switching tubes, and an auxiliary circuit. OUT3 and OUT4 are sent by the negative bias driving circuit to drive the MOS tubes V5 and V6 to work, thereby forming the AC signal AC3 and the AC signal AC4. This switching circuit is a half - bridge circuit. The non-inverting input terminal 3 of the voltage comparator N4 is connected to an external 0 - 10V adjustable DC signal source through a current-limiting resistor R45; the inverting input terminal 2 of the voltage comparator N4 is connected to a current-limiting resistor R43, and the other end of the current-limiting resistor R43 is connected to the common terminal of the voltage-dividing sampling resistors R36 and R44; the 8th pin of the voltage comparator N4 is externally connected to a 12V power supply, and the 4th pin is grounded; the output terminal 1 of the voltage comparator N4 is connected to the base of the transistor V7 through a resistor R38, thereby adjusting the conduction degree of the MOS transistor V8; the emitter of the transistor V7 is grounded; a capacitor C47 and a resistor R46 are connected in series between the output terminal 1 and the inverting input terminal 2 of the voltage comparator N4; The source, drain, and gate of the MOS transistor V8 are respectively connected to one end of the bus inductor L4, one ends of the capacitors C41, C42, C43, C44, C49, C50, and one end of the current-limiting resistor R37; the other end of the bus inductor L4 is externally connected to a 48V DC power supply; the diode D16, the resistor R35, and the capacitor C37 are connected in parallel between the source and the gate of the MOS transistor V8; the other end of the current-limiting resistor R37 is connected to the collector of the transistor V7; the drain of the MOS transistor V8 is grounded through filter capacitors C45 and C46, and is also grounded through voltage-dividing sampling resistors R36 and R44, and a sampling filter capacitor C48 is connected in parallel across the two ends of the resistor R44; The drain of the MOS transistor V5 is connected to one ends of the capacitors C41, C42, C43, C44, C49, C50, the gate is connected to OUT3 through a current-limiting resistor R39, and the source is connected to the drain of the MOS transistor V6 and the 1st pin of the isolation feedback transformer T4; a capacitor C39 is connected between the drain and the source of the MOS transistor V5, and a resistor R40 is connected between the source and the gate of the MOS transistor V5; The source of the MOS transistor V6 is connected to the other ends of the capacitors C41, C42, C43, C44, C49, C50 and grounded, the gate is connected to OUT4 through a current-limiting resistor R42, and the drain is connected to the source of the MOS transistor V5 and the 1st pin of the isolation feedback transformer T4; a capacitor C40 is connected between the drain and the source of the MOS transistor V6, and a resistor R41 is connected between the source and the gate of the MOS transistor V6; One ends of the capacitors C41, C42, C43, C44, C49, C50 are connected to the drain of the MOS transistor V5, the other ends are grounded, and the middle ends are connected to AC3; the isolation feedback transformer T4 is respectively connected to the drain of the MOS transistor V6, the AC signal AC4, IP7, and IP8; The negative bias rectifying circuit includes a negative bias high-voltage isolation transformer T3 and a voltage-doubling rectifying circuit. The AC signals AC3 and AC4 generated by the negative bias switching circuit are transmitted to a high potential through the negative bias high-voltage isolation transformer T3, and are rectified into a DC voltage through the voltage-doubling rectifying circuit composed of diodes D9, D10, and capacitors C26, C27 in parallel. A filter inductor L3 is provided at the positive pole of the voltage-doubling rectifying circuit, and a filter capacitor C28, filter resistors R24, R25, and R26 are connected in parallel between the positive and negative poles of the voltage-doubling rectifying circuit.

[0007] Further, the on-off pulse driving circuit includes an on-pulse driving and an off-pulse driving. The 14th pin of the AND gate chip N5 is an external 5V power supply terminal, and the 7th pin is grounded; the 1st and 2nd pins of the AND gate chip N5 are connected in parallel and connected to the on TTL pulse Ton+ terminal. The on TTL pulse Ton- terminal is grounded, and an on timing filter resistor R48 and an on timing filter capacitor C52 are connected in parallel between the Ton+ terminal and the Ton- terminal; the 12th and 13th pins of the AND gate chip N5 are connected in parallel and connected to the off TTL pulse Toff+ terminal. The off TTL pulse Toff- terminal is grounded, and an off timing filter resistor R56 and an off timing filter capacitor C60 are connected in parallel between the Toff+ terminal and the Toff- terminal; the 4th, 5th, 9th, and 10th pins of the AND gate chip N5 are connected in parallel and an external 5V high-level signal is connected as an enable terminal. At the same time, the 5V high-level signal is grounded through a resistor R52 and a capacitor C56; the 6th pin of the AND gate chip N5 is an on-pulse output terminal and is connected to the 2nd pin of the driving chip N6 through a current-limiting resistor R47; the 8th pin of the AND gate chip N5 is an off-pulse output terminal and is connected to the 2nd pin of the driving chip N7 through a current-limiting resistor R57; The 1st and 8th pins of the driving chip N6 are connected to a 15V power supply. The 2nd pin is connected to one end of the current-limiting resistor R47 and one end of the filter capacitor C51. The other end of the current-limiting resistor R47 is connected to the 6th pin of the AND gate chip N5, and the other end of the filter capacitor C51 is grounded; the 4th and 5th pins of the driving chip N6 are grounded. The 6th and 7th pins are connected to the bases of transistors V10 and V11 through a series-connected current-limiting resistor R51 and a filter capacitor C53. Transistors V10 and V11 form complementary power transistors. A filter capacitor C55 and a current-limiting protection resistor R50 are connected in series between the collector of transistor V11 and the 15V power supply. The collector of transistor V10 is grounded. The emitters of transistors V10 and V11 are connected to KQ+ through a pulse output DC-blocking capacitor C54. A resistor R49 and a diode V9 are connected in series between KQ+ and KQ-; KQ+ and KQ- are on-pulse outputs; Pin 1 and pin 8 of the drive chip N7 are connected to the 15V power supply. Pin 2 is connected to one end of the current-limiting resistor R57 and one end of the filter capacitor C61. The other end of the current-limiting resistor R57 is connected to pin 8 of the AND gate chip N5. The other end of the filter capacitor C61 is grounded. Pins 4 and 5 of the drive chip N7 are grounded. Pins 6 and 7 are connected to the bases of transistors V13 and V14 through the series-connected current-limiting resistor R55 and filter capacitor C57. Transistors V13 and V14 form complementary power transistors. A filter capacitor C59 and a current-limiting protection resistor R54 are connected in series between the collector of transistor V14 and the 15V power supply. The collector of transistor V13 is grounded. The emitters of transistors V13 and V14 are connected to GD+ through the pulse output DC-blocking capacitor C58. A resistor R53 and a diode V12 are connected in series between GD+ and GD-. GD+ and GD- are the turn-off pulse outputs. The modulation switch circuit includes an on-pulse transformer T5, an off-pulse transformer T6, and a modulation switch circuit. The input terminals of the on-pulse transformer T5 are respectively connected to KQ+ and KQ-. The 1+ terminal of the on-pulse transformer T5 is connected to the gate of the switching transistor Q1 through the current-limiting resistor R59. The drain of the switching transistor Q1 is connected to the positive bias voltage MOD terminal through the current-limiting resistor R60 and grounded through the capacitor C65, that is, the output common terminal K terminal. The source of the switching transistor Q1 is connected to the 1- terminal of the on-pulse transformer T5. A capacitor C64 is connected between the drain and the source of the switching transistor Q1. A delay capacitor C67, a discharge resistor R68, and a zener diode V16 are connected between the gate and the source of the switching transistor Q1. The input terminals of the off-pulse transformer T6 are respectively connected to GD+ and GD-. The 2+ terminal of the off-pulse transformer T6 is connected to the base of the triode V18 through the current-limiting resistor R61. The 2- terminal of the off-pulse transformer T6 is connected to the emitter of the triode V18. The triode V18 is the turn-off triode of the switching transistor Q1. A discharge resistor R62 and a delay capacitor C69 are also connected between the base and the emitter of the triode V18. The collector of the triode V18 is connected to the gate of the switching transistor Q1 through the current-limiting resistor R69. A turn-off pulse current-limiting resistor R63 and a voltage-regulating diode V19 are connected in series between the 3+ terminal of the turn-off pulse transformer T6 and the gate of the switching transistor Q2; the drain of the switching transistor Q2 is connected to the source of the switching transistor Q1 and is connected to the gate output G terminal through current-limiting resistors R66 and R70; the source of the switching transistor Q2 is connected to the 3- terminal of the turn-off pulse transformer T6 and is connected to the negative bias voltage Bias terminal through a current-limiting resistor R67 and grounded through a capacitor C66, that is, the output common terminal K terminal; a capacitor C63 is connected in parallel between the drain and source of the switching transistor Q2, and resistors R65 and R71 are used to quickly discharge the output voltage after the turn-off pulse acts. R65 and R71 are connected in series and then connected in parallel between the drain and source of the switching transistor Q2; a discharge resistor R64, a delay capacitor C68, and a voltage-regulating diode V17 are connected in parallel between the gate and source of the switching transistor Q2; a capacitor C62 and a discharge tube V15 are connected in parallel between the gate output G terminal and the output common terminal K terminal.

[0008] The beneficial effects of the present invention are as follows: According to the circuit requirements, by changing the reference voltage of the drive chip N10, the duty cycle of its output pulse is changed, and then the adjustment of the positive bias power supply voltage is realized; by changing the reference voltage of the drive chip N3, the duty cycle of its output pulse is changed, and then the adjustment of the negative bias power supply voltage is realized; by changing the positive bias voltage and the negative bias voltage, the amplitude adjustment of the gate control power supply pulse is realized. By adjusting the pulse width and repetition period of the TTL turn-on pulse, the pulse width and repetition period of the gate control power supply output signal can be adjusted.

[0009] The present invention is small in size, uses a PWM control chip to realize the digital adjustment of the output gate control pulse, does not require manual adjustment, has a low safety risk, high reliability, high adjustment accuracy, small heat loss, and high pulse waveform stability; the present invention adopts a modular design, is convenient to adjust, and is convenient for debugging and maintenance; the modulation pulse voltage of the present invention has steep front and rear edges, good pulse waveform, and reduces the reverse impact on the load circuit when working at a high repetition frequency; the pulse width of the present invention is adjustable from 1 to 50 μs, and the repetition frequency is adjustable from 100 Hz to 10 kHz, which can adapt to a variety of tube types, has a wide application range and good applicability; the high-potential isolation transformer of the present invention adopts an oil-immersed type, with good insulation and heat dissipation performance; the parts not described in detail in the present invention are common existing technologies. Description of the Drawings

[0010] The present invention will be further described below with reference to the accompanying drawings: Figure 1 It is a principle block diagram; Figure 2 It is a positive bias power supply drive circuit diagram; Figure 3 It is a positive bias switch circuit diagram; Figure 4 It is a positive bias rectifier circuit diagram; Figure 5 It is a negative bias power supply drive circuit diagram; Figure 6 It is a negative bias switch circuit diagram; Figure 7 It is a negative bias rectifier circuit diagram; Figure 8 It is a turn-on and turn-off pulse drive circuit diagram; Figure 9 It is a modulation switch circuit diagram. Specific implementation manners

[0011] The present invention will be further described in detail below in conjunction with embodiments and specific implementation manners: Embodiment

[0012] As Figure 1 shown, a digital adjustable grid control power supply includes a positive bias power supply, a negative bias power supply, and a modulation circuit; the positive bias power supply is composed of a positive bias drive circuit, a positive bias switch circuit, and a positive bias rectifier circuit; the positive bias drive circuit generates two paths of pulses, forms an alternating current signal through the positive bias switch circuit, and obtains a positive bias voltage through the positive bias rectifier circuit; the negative bias power supply is composed of a negative bias drive circuit, a negative bias switch circuit, and a negative bias rectifier circuit; the negative bias drive circuit generates two paths of pulses, forms an alternating current signal through the negative bias switch circuit, and obtains a negative bias voltage through the rectifier circuit; the modulation circuit is composed of a turn-on and turn-off drive pulse circuit and a modulation switch circuit; the turn-on pulse drive and the turn-off pulse drive respectively drive a modulation switch tube through a turn-on pulse isolation transformer and a turn-off isolation pulse transformer, and modulate the positive bias voltage and the negative bias voltage into a pulse waveform with a required pulse width and period.

[0013] As Figure 2As shown in the figure, the forward bias drive circuit includes a drive chip N10 and an operational amplifier N11. The drive chip N10 is a PWM control chip. Its pin 2 is the reference input terminal, which receives an externally adjustable DC voltage of 0 - 10V to set the output voltage reference of the chip. Pin 5 is the input terminal for the filter capacitor, connected to one end of the filter capacitor C16, and the other end of the filter capacitor C16 is grounded. Pin 6 is the input terminal for the filter resistor, connected to one ends of the adjustable resistor R13 and the resistor R14, and the other ends of the adjustable resistor R13 and the resistor R14 are grounded. Pin 7 is connected to the discharge resistor R15, and the discharge resistor R15 is grounded through the filter capacitor C16. Pin 8 is the soft start terminal, connected to one end of the soft start capacitor C17, and the other end of the soft start capacitor C17 is grounded. By adjusting the capacitance value of the soft start capacitor C17, the start time of the chip pulse output is changed to achieve the soft start function. Pin 16 is connected to one end of the capacitor C15, and the other end of the capacitor C15 is grounded. Pin 15 is the positive power supply terminal, connected to the power supply to provide the electrical energy required for the operation of the drive chip N10. Pin 12 is the ground terminal, directly grounded to ensure the safe operation of the circuit. Pins 14 and 11 are the pulse output terminals, outputting control signals to drive the subsequent circuit. Pin 10 is the feedback locking control terminal, and the signals after rectification and sampling of IP5 and IP6 are sent to this pin. The sampling filter capacitors C21, C22, the voltage dividing sampling resistor chain, the filter capacitors C19, C20, and the diode chain are connected in parallel between pin 10 and IP5, IP6. The voltage dividing sampling resistor chain is composed of the parallel voltage sampling resistors R17, R18, R19, R20, and the diode chain is composed of the parallel diodes D3, D4, D5, D6. The signals after rectification and sampling of IP5 and IP6 are sent to this pin. Pin 9 is connected to pin 1 and participates in the feedback compensation process. IP5 and IP6 come from the forward bias switch circuit and are the AC feedback inputs. The operational amplifier N11 is a driver, located on the right side of the drive chip N10. Pins 10 and 12 are the pulse input terminals, respectively corresponding to and connected to pins 11 and 14 of the drive chip N10 to receive the pulse signals from the drive chip N10. Pins 3 and 9 are the positive power supply terminals connected to the power supply. Pin 2 is the ground terminal, directly grounded. Pins 1 and 7 are the drive pulse output terminals, outputting drive signals to the subsequent circuit. Pins 11 and 13 are the low - level locking terminals, directly grounded to ensure the normal operation of the driver. A diode D2 is connected between pins 3 and 6 to suppress reverse current and protect the circuit from the impact of reverse voltage. A filter capacitor C18 is connected between pins 5 and 6. As Figure 3 As shown in the figure, the forward bias switch circuit consists of a first - stage switch tube, two - stage two - group switch tubes and an auxiliary circuit. The two control pulses OUT1 and OUT2 sent by the forward bias drive circuit are respectively applied to the control terminals of the MOS tubes V2 and V3 to drive the MOS tubes V2 and V3 to work, thereby forming the AC signals AC1 and AC2. This switch circuit is a half - bridge circuit. The non-inverting input terminal 3 of the voltage comparator N1 is connected to an external 0 - 10V adjustable DC signal source through a current-limiting resistor R3; the inverting input terminal 2 of the voltage comparator N1 is connected to a current-limiting resistor R4, and the other end of the current-limiting resistor R4 is connected to the common terminal of the voltage-dividing sampling resistors R7 and R8; the 8th pin of the voltage comparator N1 is externally connected to a 12V power supply, and the 4th pin is grounded; the output terminal 1 of the voltage comparator N1 is connected to the base of the transistor V4 through a resistor R6, thereby adjusting the conduction degree of the MOS transistor V1; the emitter of the transistor V4 is grounded; a capacitor C3 and a resistor R5 are connected in series between the output terminal 1 and the inverting input terminal 2 of the voltage comparator N1; The MOS transistor V1 uses IRFP9140N. The source, drain, and gate of the MOS transistor V1 are respectively connected to one end of the bus inductor L1, one end of the capacitor chain C9 - C14, and one end of the current-limiting resistor R2; the other end of the bus inductor L1 is externally connected to a 48V DC power supply; the diode D1, the resistor R1, and the capacitor C1 are connected in parallel between the source and the gate of the MOS transistor V1; the other end of the current-limiting resistor R2 is connected to the collector of the transistor V4; the drain of the MOS transistor V1 is grounded through filter capacitors C5 and C6, and is also grounded through the voltage-dividing sampling resistors R7 and R8, and a sampling filter capacitor C4 is connected in parallel across the two ends of the resistor R8; The MOS transistor V2 uses IRL530N. The drain of the MOS transistor V2 is connected to one end of the capacitor chain C9 - C14, the gate is connected to OUT1 through a current-limiting resistor R9, and the source is connected to the drain of the MOS transistor V3 and the 1st pin of the isolation feedback transformer T2; the capacitor C7 is connected between the drain and the source of the MOS transistor V2, and the resistor R10 is connected between the gate and the source of the MOS transistor V2; The source of the MOS transistor V3 is connected to the other end of the capacitor chain C9 - C14 and grounded. The gate is connected to OUT2 through a current-limiting resistor R11, and the drain is connected to the source of the MOS transistor V2 and the 1st pin of the isolation feedback transformer T2; the capacitor C8 is connected between the drain and the source of the MOS transistor V3, and the resistor R12 is connected between the gate and the source of the MOS transistor V3; One end of the capacitor chain C9 - C14 is connected to the drain of the MOS transistor V2, the other end is grounded, and the middle terminal is connected to AC1; the isolation feedback transformer T2 is respectively connected to the drain of the MOS transistor V3, the AC signal AC2, IP5, and IP6; Such as Figure 4As shown in the figure, the forward-biased rectifier circuit includes a forward-biased high-voltage isolation transformer T1 and a voltage-doubling rectifier circuit. The AC signals AC1 and AC2 generated by the forward-biased switch circuit are transmitted to a high potential through the forward-biased high-voltage isolation transformer T1, and then pass through a voltage-doubling rectifier circuit composed of diodes D7, D8, capacitors C23, and C24 connected in parallel to rectify the AC voltage into a DC voltage. A filter inductor L2 is provided at the positive pole of the voltage-doubling rectifier circuit, and a filter capacitor C25, filter resistors R21, R22, and R23 are connected in parallel between the positive and negative poles of the voltage-doubling rectifier circuit; the forward-biased output voltage is +500V.

[0014] As Figure 5 As shown in the figure, the reverse-biased drive circuit includes a drive chip N3 and an operational amplifier N2. The drive chip N3 is a PWM control chip. Pin 2 is the reference input terminal, which receives an externally adjustable DC voltage of 0 - 10V. Pin 5 is the input terminal of the filter capacitor, connected to one end of the filter capacitor C35, and the other end of the filter capacitor C35 is grounded; Pin 6 is the input terminal of the filter resistor, in parallel with the chip filter resistor R32 and the adjustable resistor R34, and the other ends of the resistor R32 and the adjustable resistor R34 are grounded; Pin 7 is connected to the discharge resistor R31, and the discharge resistor R31 is grounded through the filter capacitor C35; Pin 8 is the soft start terminal, connected to one end of the soft start capacitor C33, and the other end of the soft start capacitor C33 is grounded. By adjusting the capacitance value of the soft start capacitor C17, the start time of the chip pulse output is changed to achieve the soft start function; Pin 16 is connected to one end of the capacitor C34, and the other end of the capacitor C34 is grounded; Pin 15 is the positive power supply terminal, connected to the power supply to provide the electrical energy required for the operation of the drive chip N3; Pin 12 is the ground terminal, directly grounded to ensure the safe operation of the circuit; Pins 14 and 11 are the pulse output terminals, outputting control signals to drive the subsequent circuit; Pin 10 is the feedback locking control terminal, and the signals after rectification and sampling of IP7 and IP8 are sent to this pin; The sampling filter capacitors C30, C31, the voltage-dividing sampling resistor chain, the filter capacitors C29, C32, and the diode chain are connected in parallel between Pin 10 and IP7, IP8. The voltage-dividing sampling resistor chain is composed of the voltage-sampling resistors R27, R28, R29, and R30 connected in parallel, and the diode chain is composed of the diodes D11, D12, D13, and D14 connected in parallel; Pin 9 is connected to Pin 1 and participates in the feedback compensation process. IP7 and IP8 come from the reverse-biased switch circuit and are AC feedback inputs. The operational amplifier N2 is a driver, with the model number IR2113. Its position is on the right side of the drive chip N3. Pins 10 and 12 are pulse input terminals, which are respectively connected to pins 11 and 14 of the drive chip N3 correspondingly to receive the pulse signals from the drive chip N3; pins 3 and 9 are connected to the positive power supply terminal to access the power supply; pin 2 is the ground terminal, directly grounded; pins 1 and 7 are drive pulse output terminals, outputting drive signals to the subsequent circuit; pins 11 and 13 are low-level locking terminals, directly grounded; a diode D15 is connected between pins 3 and 6 to suppress reverse current and protect the circuit from the impact of reverse voltage; a filter capacitor C36 is connected between pins 5 and 6.

[0015] As Figure 6 shown, the negative bias switch circuit consists of a primary switch transistor, two groups of secondary switch transistors and an auxiliary circuit. OUT3 and OUT4 are sent by the negative bias drive circuit to drive the MOS transistors V5 and V6 to work, thereby forming an AC signal AC3 and an AC signal AC4. This switch circuit is a half-bridge circuit. The non-inverting input terminal 3 of the voltage comparator N4 is connected to an external 0 - 10V adjustable DC signal source through a current-limiting resistor R45; the inverting input terminal 2 of the voltage comparator N4 is connected to the current-limiting resistor R43, and the other end of the current-limiting resistor R43 is connected to the common terminal of the voltage-dividing sampling resistors R36 and R44; the 8th pin of the voltage comparator N4 is externally connected to a 12V power supply, and the 4th pin is grounded; the output terminal 1 of the voltage comparator N4 is connected to the base of the transistor V7 through a resistor R38, thereby adjusting the conduction degree of the MOS transistor V8; the emitter of the transistor V7 is grounded; a capacitor C47 and a resistor R46 are connected in series between the output terminal 1 and the inverting input terminal 2 of the voltage comparator N4. The source, drain, and gate of the MOS transistor V8 are respectively connected to one end of the bus inductor L4, one ends of the capacitor chain C41, C42, C43, C44, C49, C50, and one end of the current-limiting resistor R37; the other end of the bus inductor L4 is externally connected to a 48V DC power supply; a diode D16, a resistor R35, and a capacitor C37 are connected in parallel between the source and the gate of the MOS transistor V8; the other end of the current-limiting resistor R37 is connected to the collector of the transistor V7; the drain of the MOS transistor V8 is grounded through filter capacitors C45 and C46, and is also grounded through the voltage-dividing sampling resistors R36 and R44. A sampling filter capacitor C48 is connected in parallel across the two ends of the voltage-dividing sampling resistor R44. The drain of the MOS transistor V5 is connected to one end of the capacitor chain C41 - C50. The gate is connected to OUT3 through a current-limiting resistor R39, and the source is connected to the drain of the MOS transistor V6 and pin 1 of the isolation feedback transformer T4; a capacitor C39 is connected between the drain and the source of the MOS transistor V5, and a resistor R40 is connected between the source and the gate of the MOS transistor V5. The source of MOS transistor V6 is connected to the other ends of capacitors C41, C42, C43, C44, C49, and C50 and grounded. The gate is connected to OUT4 through current-limiting resistor R42. The drain is connected to the source of MOS transistor V5 and pin 1 of isolation feedback transformer T4. Capacitor C40 is connected between the drain and source of MOS transistor V6. Resistor R41 is connected between the gate and source of MOS transistor V6. MOS transistors V5 / V6 are of the IRL530N type and are used for driving and amplifying the main circuit. Resistors R40 / 41 are respectively used to adjust the driving voltages of MOS transistors V5 and V6. One end of capacitors C41, C42, C43, C44, C49, and C50 is connected to the drain of MOS transistor V5, the other end is grounded, and the middle end is connected to AC3. Isolation feedback transformer T4 is respectively connected to the drain of MOS transistor V6, AC signal AC4, IP7, and IP8. Isolation transformer T4 is used for feedback sampling. AC signal AC3 and AC signal AC4 are amplified output AC signals.

[0016] As Figure 7 As shown, the negative bias rectification circuit includes a negative bias high-voltage isolation transformer T3 and a voltage-doubling rectification circuit. The AC signals AC3 and AC4 generated by the negative bias switching circuit are transmitted to a high potential through the negative bias high-voltage isolation transformer T3 and rectified into a DC voltage by the voltage-doubling rectification circuit composed of diodes D9, D10, capacitors C26, and C27 in parallel. A filter inductor L3 is provided at the positive pole of the voltage-doubling rectification circuit. Filter capacitors C28, filter resistors R24, R25, and R26 are connected in parallel between the positive and negative poles of the voltage-doubling rectification circuit. The negative bias output voltage is -500V.

[0017] As Figure 8As shown, the on-off pulse drive circuit includes an on-pulse drive and an off-pulse drive. The 14th pin of the AND gate chip N5 is an external 5V power supply terminal, and the 7th pin is grounded; the 1st and 2nd pins of the AND gate chip N5 are in parallel and connected to the on TTL pulse Ton+ terminal. The on TTL pulse Ton- terminal is grounded. An on timing filter resistor R48 and an on timing filter capacitor C52 are in parallel between the Ton+ terminal and the Ton- terminal; the 12th and 13th pins of the AND gate chip N5 are in parallel and connected to the off TTL pulse Toff+ terminal. The off TTL pulse Toff- terminal is grounded. An off timing filter resistor R56 and an off timing filter capacitor C60 are in parallel between the Toff+ terminal and the Toff- terminal; the 4th, 5th, 9th, and 10th pins of the AND gate chip N5 are in parallel and externally connected to a 5V high-level signal as an enable terminal. At the same time, the 5V high-level signal is grounded through a resistor R52 and a capacitor C56; the 6th pin of the AND gate chip N5 is an on-pulse output terminal and is connected to the 2nd pin of the drive chip N6 through a current-limiting resistor R47; the 8th pin of the AND gate chip N5 is an off-pulse output terminal and is connected to the 2nd pin of the drive chip N7 through a current-limiting resistor R57; the AND gate chip N5 uses 54LS21. When the timing signal and the enable signal are both high level, the chip outputs a high level. The drive chip N6 uses IXDN414PI to drive and amplify the on-pulse. The 1st and 8th pins of the drive chip N6 are connected to the 15V power supply. The 2nd pin is connected to one end of the current-limiting resistor R47 and one end of the filter capacitor C51. The other end of the current-limiting resistor R47 is connected to the 6th pin of the AND gate chip N5. The other end of the filter capacitor C51 is grounded; the 4th and 5th pins of the drive chip N6 are grounded. The 6th and 7th pins are connected to the bases of the transistors V10 and V11 through a series-connected current-limiting resistor R51 and a filter capacitor C53. The transistors V10 and V11 form complementary power transistors. A filter capacitor C55 and a current-limiting protection resistor R50 are in series between the collector of the transistor V11 and the 15V power supply. The collector of the transistor V10 is grounded. The emitters of the transistors V10 and V11 are connected to KQ+ through a pulse output DC-blocking capacitor C54. A resistor R49 and a diode V9 are in series between KQ+ and KQ-; KQ+ and KQ- are the on-pulse outputs. The driving chip N7 uses IXDN414PI to drive and amplify the turn-off pulse. Pin 1 and pin 8 of the driving chip N7 are connected to the 15V power supply. Pin 2 is connected to one end of the current-limiting resistor R57 and one end of the filter capacitor C61. The other end of the current-limiting resistor R57 is connected to pin 8 of the AND gate chip N5. The other end of the filter capacitor C61 is grounded. Pins 4 and 5 of the driving chip N7 are grounded. Pins 6 and 7 are connected to the bases of the transistors V13 and V14 through the series-connected current-limiting resistors R55 and filter capacitor C57. The transistors V13 and V14 form complementary power transistors. A filter capacitor C59 and a current-limiting protection resistor R54 are connected in series between the collector of the transistor V14 and the 15V power supply. The collector of the transistor V13 is grounded. The emitters of the transistors V13 and V14 are connected to GD+ through the pulse output DC-blocking capacitor C58. A resistor R53 and a diode V12 are connected in series between GD+ and GD-. GD+ and GD- are the turn-off pulse outputs.

[0018] As Figure 9 shown, the modulation switch circuit includes an on-pulse transformer T5, an off-pulse transformer T6, and a modulation switch circuit. The input terminals of the on-pulse transformer T5 are respectively connected to KQ+ and KQ-. The 1+ terminal of the on-pulse transformer T5 is connected to the gate of the switch transistor Q1 through the current-limiting resistor R59. The drain of the switch transistor Q1 is connected to the positive bias voltage MOD terminal through the current-limiting resistor R60 and grounded through the capacitor C65, that is, the output common terminal K terminal. The source of the switch transistor Q1 is connected to the 1- terminal of the on-pulse transformer T5. A capacitor C64 is connected between the drain and the source of the switch transistor Q1. A delay capacitor C67, a discharge resistor R68, and a zener diode V16 are connected between the gate and the source of the switch transistor Q1. The input terminals of the off-pulse transformer T6 are respectively connected to GD+ and GD-. The 2+ terminal of the off-pulse transformer T6 is connected to the base of the triode V18 through the current-limiting resistor R61. The 2- terminal of the off-pulse transformer T6 is connected to the emitter of the triode V18. The triode V18 is the turn-off triode of the switch transistor Q1. A discharge resistor R62 and a delay capacitor C69 are also connected between the base and the emitter of the triode V18. The collector of the triode V18 is connected to the gate of the switch transistor Q1 through the current-limiting resistor R69. A turn-off pulse current-limiting resistor R63 and a zener diode V19 are connected in series between the 3+ terminal of the turn-off pulse transformer T6 and the gate of the switching transistor Q2; the drain of the switching transistor Q2 is connected to the source of the switching transistor Q1 and is connected to the gate output G terminal through current-limiting resistors R66 and R70; the source of the switching transistor Q2 is connected to the 3- terminal of the turn-off pulse transformer T6 and is connected to the negative bias voltage Bias terminal through a current-limiting resistor R67 and grounded through a capacitor C66, that is, the output common terminal K terminal; a capacitor C63 is connected in parallel between the drain and source of the switching transistor Q2, and resistors R65 and R71 are used to quickly discharge the output voltage after the turn-off pulse acts. R65 and R71 are connected in series and then connected in parallel between the drain and source of the switching transistor Q2; a discharge resistor R64, a delay capacitor C68, and a zener diode V17 are connected in parallel between the gate and source of the switching transistor Q2; a capacitor C62 and a discharge tube V15 are connected in parallel between the gate output G terminal and the output common terminal K terminal; the switching transistor Q2 is the switching transistor for the turn-off pulse, and its model is the IXBH9N160G type MOS transistor. When the turn-off pulse is sent, Q2 conducts to output a negative turn-off pulse, which is used to improve the falling edge of the output pulse.

[0019] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A digital adjustable gate-controlled power supply, characterized in that: Including positive bias power supply, negative bias power supply and modulation circuit; The forward bias power supply is composed of a forward bias driving circuit, a forward bias switching circuit, and a forward bias rectifying circuit; the forward bias driving circuit generates two pulses, which are converted into an AC signal through the forward bias switching circuit, and a forward bias voltage is obtained through the forward bias rectifying circuit; The negative bias power supply is composed of a negative bias driving circuit, a negative bias switching circuit, and a negative bias rectifying circuit; the negative bias driving circuit generates two pulses, which are converted into an AC signal through the negative bias switching circuit, and then pass through the rectifying circuit to obtain a negative bias voltage; The modulation circuit is composed of an on-off drive pulse circuit and a modulation switch circuit; the on-pulse drive and the off-pulse drive respectively drive the modulation switch tube through an on-pulse isolation transformer and an off-pulse isolation transformer to modulate the positive bias voltage and the negative bias voltage into a pulse waveform with the required pulse width and period.

2. A digital adjustable gate-controlled power supply according to claim 1, characterized in that: The forward bias drive circuit includes a drive chip N10 and an operational amplifier N11; the drive chip N10 is a PWM control chip, and pin 2 is a reference input terminal, which receives an external DC voltage adjustable from 0 to 10V and is used to set the output voltage reference of the chip; pin 5 is a filter capacitor input terminal, which is connected to one end of the filter capacitor C16, and the other end of the filter capacitor C16 is grounded; pin 6 is a filter resistor input terminal, which is connected to one end of the adjustable resistor R13 and the resistor R14, and the other ends of the adjustable resistor R13 and the resistor R14 are grounded; pin 7 is connected to the discharge resistor R15, and the discharge resistor R15 is grounded through the filter capacitor C16; pin 8 is a soft start terminal, which is connected to one end of the soft start capacitor C17, and the other end of the soft start capacitor C17 is grounded. By adjusting the capacitance of the soft start capacitor C17, the start time of the chip pulse output is changed to realize the soft start function; pin 16 is connected to one end of the capacitor C15, and the other end of the capacitor C15 is grounded; Pin 15 is the positive power supply terminal, which is connected to the power supply to provide the power required for the driver chip N10 to work; Pin 12 is the ground terminal, which is directly grounded to ensure the safe operation of the circuit; Pin 14 and Pin 11 are pulse output terminals, which output control signals for driving subsequent circuits; Pin 10 is the feedback lock control terminal, and the signals of IP5 and IP6 after rectification and sampling are sent to this pin; sampling filter capacitors C21, C22, voltage-dividing sampling resistor chain, filter capacitors C19, C20, and diode chain are connected in parallel between Pin 10 and IP5 and IP6, and the voltage-dividing sampling resistor chain is composed of parallel voltage sampling resistors R17, R18, R19, and R20, and the diode chain is composed of parallel diodes D3, D4, D5, and D6; the signals of IP5 and IP6 after rectification and sampling are sent to this pin; Pin 9 is connected to Pin 1 and participates in the feedback compensation process. IP5 and IP6 come from the forward bias switch circuit and are AC feedback inputs; The operational amplifier N11 is a driver, and its position is located on the right side of the driver chip N10. Pins 10 and 12 are pulse input terminals, which are respectively connected to pins 11 and 14 of the driver chip N10 to receive pulse signals from the driver chip N10. Pins 3 and 9 are the positive terminals of the power supply. Pin 2 is the ground terminal, which is directly grounded; Pin 1 and Pin 7 are the drive pulse output terminals, which output the drive signal to the subsequent circuit; Pin 11 and Pin 13 are low-level lock terminals, which are directly grounded to ensure the normal operation of the driver; Diode D2 is connected between Pin 3 and Pin 6 to suppress backflow and protect the circuit from the impact of reverse voltage; Filter capacitor C18 is connected between Pin 5 and Pin 6; The forward bias switch circuit is composed of a primary switch tube and two groups of secondary switch tubes and an auxiliary circuit. OUT1 and OUT2 are two control pulses sent by the forward bias drive circuit to drive MOS tubes V2 and V3 to work, thereby forming AC signals AC1 and AC2. The switch circuit is a half-bridge circuit. The non-inverting input terminal pin 3 of the voltage comparator N1 is connected to an external 0-10V adjustable DC signal source through a current limiting resistor R3; the inverting input terminal pin 2 of the voltage comparator N1 is connected to a current limiting resistor R4, and the other end of the current limiting resistor R4 is connected to the common end of the voltage dividing sampling resistors R7 and R8; the 8th pin of the voltage comparator N1 is connected to an external 12V power supply, and the 4th pin is grounded; the output terminal pin 1 of the voltage comparator N1 is connected to the base of the transistor V4 through a resistor R6, thereby adjusting the conductivity of the MOS tube V1; The emitter of transistor V4 is grounded; a capacitor C3 and a resistor R5 are connected in series between the output terminal 1 pin and the inverting input terminal 2 pin of the voltage comparator N1; The source, drain and gate of the MOS tube V1 are respectively connected to one end of the bus inductor L1, one end of the capacitor chain C9-C14 and one end of the current limiting resistor R2; the other end of the bus inductor L1 is externally connected to a 48V DC power supply; the diode D1, the resistor R1 and the capacitor C1 are connected in parallel between the source and the gate of the MOS tube V1; the other end of the current limiting resistor R2 is connected to the collector of the transistor V4; the drain of the MOS tube V1 is grounded through the filter capacitors C5 and C6, and is also grounded through the voltage dividing sampling resistors R7 and R8, and the two ends of the voltage dividing sampling resistor R8 are connected in parallel with the sampling filter capacitor C4; The drain of MOS tube V2 is connected to one end of capacitor chain C9-C14, the gate is connected to OUT1 through current limiting resistor R9, and the source is connected to the drain of MOS tube V3 and pin 1 of isolation feedback transformer T2; capacitor C7 is connected between the drain and source of MOS tube V2, and the source of resistor R10 is connected between the gate and source of MOS tube V2; The source of the MOS tube V3 is connected to the other end of the capacitor chain C9-C14 and grounded, the gate is connected to OUT2 through the current limiting resistor R11, and the drain is connected to the source of the MOS tube V2 and the 1st pin of the isolation feedback transformer T2; the capacitor C8 is connected between the drain and source of the MOS tube V3, and the source of the resistor R12 is connected between the gate and source of the MOS tube V3; One end of the capacitor chain C9-C14 is connected to the drain of the MOS tube V2, the other end is grounded, and the middle end is connected to AC1; the isolation feedback transformer T2 is connected to the drain of the MOS tube V3, the AC signal AC2, IP5, and IP6 respectively; The forward bias rectifier circuit includes a forward bias high-voltage isolation transformer T1 and a voltage doubling rectifier circuit. The AC signals AC1 and AC2 generated by the forward bias switching circuit are transmitted to a high potential through the forward bias high-voltage isolation transformer T1, and the AC voltage is rectified into a DC voltage through a double voltage rectifier circuit composed of diodes D7, D8, and capacitors C23 and C24 in parallel. The positive pole of the double voltage rectifier circuit is provided with a filter inductor L2, and a filter capacitor C25 and filter resistors R21, R22, and R23 are connected in parallel between the positive and negative poles of the double voltage rectifier circuit.

3. The digital adjustable gate-controlled power supply according to claim 1, characterized in that: The negative bias driving circuit includes a driving chip N3 and an operational amplifier N2. The driving chip N3 is a PWM control chip. Pin 2 is a reference input terminal, which receives an external DC voltage adjustable from 0 to 10V. Pin 5 is a filter capacitor input terminal, which is connected to one end of the filter capacitor C35, and the other end of the filter capacitor C35 is grounded; Pin 6 is a filter resistor input terminal, which is connected in parallel with a chip filter resistor R32 and an adjustable resistor R34, and the other ends of the resistors R32 and R34 are grounded; Pin 7 is connected to a discharge resistor R31, and the discharge resistor R31 is grounded through the filter capacitor C35; Pin 8 is a soft start terminal, which is connected to one end of the soft start capacitor C33, and the other end of the soft start capacitor C33 is grounded. By adjusting the capacitance of the soft start capacitor C17, the start time of the chip pulse output is changed to realize the soft start function; Pin 16 is connected to one end of the capacitor C34, and the other end of the capacitor C34 is grounded; Pin 15 is a positive power supply terminal, which is connected to a power supply to provide the driving chip N3 with the required power for work; Pin 12 is the ground terminal, which is directly grounded to ensure the safe operation of the circuit; Pin 14 and Pin 11 are pulse output terminals, which output control signals to drive subsequent circuits; Pin 10 is the feedback lock control terminal, and the signals of IP7 and IP8 after rectification and sampling are sent to this pin; sampling filter capacitors C30, C31, voltage-dividing sampling resistor chain, filter capacitors C29, C32, and diode chain are connected in parallel between Pin 10 and IP7 and IP8, and the voltage-dividing sampling resistor chain is composed of parallel voltage sampling resistors R27, R28, R29, and R30, and the diode chain is composed of parallel diodes D11, D12, D13, and D14; Pin 9 is connected to Pin 1 and participates in the feedback compensation process. IP7 and IP8 come from the negative bias switch circuit and are AC feedback inputs; Operational amplifier N2 is a driver, model IR2113, and is located on the right side of driver chip N3. Pins 10 and 12 are pulse input terminals, which are respectively connected to pins 11 and 14 of driver chip N3 to receive pulse signals from driver chip N3. Pins 3 and 9 are the positive terminals of the power supply. Pin 2 is the ground terminal, directly connected to the ground; Pin 1 and Pin 7 are the drive pulse output terminals, outputting the drive signal to the subsequent circuit; Pin 11 and Pin 13 are low-level lock terminals, directly connected to the ground; Diode D15 is connected between Pin 3 and Pin 6 to suppress backflow and protect the circuit from the impact of reverse voltage; Filter capacitor C36 is connected between Pin 5 and Pin 6; The negative bias switch circuit is composed of a primary switch tube and two groups of secondary switch tubes and an auxiliary circuit. OUT3 and OUT4 are sent by a negative bias drive circuit to drive MOS tubes V5 and V6 to work, thereby forming AC signals AC3 and AC signals AC4. The switch circuit is a half-bridge circuit. The non-inverting input terminal pin 3 of the voltage comparator N4 is connected to an external 0-10V adjustable DC signal source through a current limiting resistor R45; the inverting input terminal pin 2 of the voltage comparator N4 is connected to a current limiting resistor R43, and the other end of the current limiting resistor R43 is connected to the common end of the voltage dividing sampling resistors R36 and R44; the 8th pin of the voltage comparator N4 is connected to an external 12V power supply, and the 4th pin is grounded; the output terminal pin 1 of the voltage comparator N4 is connected to the base of the transistor V7 through a resistor R38, thereby adjusting the conductivity of the MOS tube V8; The emitter of transistor V7 is grounded; a capacitor C47 and a resistor R46 are connected in series between the output terminal 1 pin and the inverting input terminal 2 pin of the voltage comparator N4; The source, drain and gate of the MOS tube V8 are respectively connected to one end of the bus inductor L4, one end of the capacitor chain C41, C42, C43, C44, C49 and C50, and one end of the current limiting resistor R37; the other end of the bus inductor L4 is externally connected to a 48V DC power supply; the diode D16, the resistor R35 and the capacitor C37 are connected in parallel between the source and the gate of the MOS tube V8; the other end of the current limiting resistor R37 is connected to the collector of the transistor V7; the drain of the MOS tube V8 is grounded through the filter capacitors C45 and C46, ​​and is also grounded through the voltage dividing sampling resistors R36 and R44, and the two ends of the resistor R44 are connected in parallel with the sampling filter capacitor C48; The drain of MOS tube V5 is connected to one end of capacitor chain C41, C42, C43, C44, C49, and C50, the gate is connected to OUT3 through current limiting resistor R39, and the source is connected to the drain of MOS tube V6 and pin 1 of isolation feedback transformer T4; capacitor C39 is connected between the drain and source of MOS tube V5, and the source of resistor R40 is connected between the gate and source of MOS tube V5; The source of MOS tube V6 is connected to the other end of capacitor chain C41, C42, C43, C44, C49, C50 and grounded, the gate is connected to OUT4 through current limiting resistor R42, the drain is connected to the source of MOS tube V5 and pin 1 of isolation feedback transformer T4; capacitor C40 is connected between the drain and source of MOS tube V6, and the source of resistor R41 is connected between the gate and source of MOS tube V6; One end of the capacitor chain C41, C42, C43, C44, C49, and C50 is connected to the drain of the MOS tube V5, the other end is grounded, and the middle end is connected to AC3; the isolation feedback transformer T4 is connected to the drain of the MOS tube V6, the AC signal AC4, IP7, and IP8 respectively; The negative bias rectifier circuit includes a negative bias high-voltage isolation transformer T3 and a voltage doubling rectifier circuit. The AC signals AC3 and AC4 generated by the negative bias switching circuit are transmitted to a high potential through the negative bias high-voltage isolation transformer T3, and the AC voltage is rectified into a DC voltage through a double voltage rectifier circuit composed of diodes D9, D10, and capacitors C26 and C27 in parallel. The positive electrode of the double voltage rectifier circuit is provided with a filter inductor L3, and a filter capacitor C28 and filter resistors R24, R25, and R26 are connected in parallel between the positive and negative electrodes of the double voltage rectifier circuit.

4. The digitally adjustable gate-controlled power supply according to claim 1, characterized in that: The on-off pulse driving circuit includes an on-pulse driving circuit and an off-pulse driving circuit. The 14th pin of the AND gate chip N5 is an external 5V power supply terminal, and the 7th pin is grounded. The 1st and 2nd pins of the gate chip N5 are connected in parallel, connected to the TTL pulse Ton+ terminal, the TTL pulse Ton- terminal is grounded, the timing filter resistor R48 and the timing filter capacitor C52 are connected in parallel between the Ton+ terminal and the Ton- terminal; the 12th and 13th pins of the gate chip N5 are connected in parallel, connected to the TTL pulse Toff+ terminal, the TTL pulse Toff- terminal is grounded, and the timing filter capacitor C52 is connected in parallel between the Toff+ terminal and the Toff- terminal. Resistor R56, turn off timing filter capacitor C60; the 4th, 5th, 9th and 10th pins of the AND gate chip N5 are connected in parallel, and an external 5V high-level signal is connected as an enable terminal. At the same time, the 5V high-level signal is grounded through resistor R52 and capacitor C56; the 6th pin of the AND gate chip N5 is the start pulse output terminal, which is connected to the 2nd pin of the driver chip N6 through the current limiting resistor R47; the 8th pin of the AND gate chip N5 is the shut-off pulse output terminal, which is connected to the 2nd pin of the driver chip N7 through the current limiting resistor R57; Pins 1 and 8 of the driver chip N6 are connected to a 15V power supply, pin 2 is connected to one end of a current limiting resistor R47 and one end of a filter capacitor C51, the other end of the current limiting resistor R47 is connected to pin 6 of the AND gate chip N5, and the other end of the filter capacitor C51 is grounded; pins 4 and 5 of the driver chip N6 are grounded, pins 6 and 7 are connected to the bases of transistors V10 and V11 through current limiting resistors R51 and filter capacitors C53 connected in series, transistors V10 and V11 constitute complementary power transistors, filter capacitors C55 and current limiting protection resistors R50 are connected in series between the collector of transistor V11 and the 15V power supply, the collector of transistor V10 is grounded, the emitters of transistors V10 and V11 are connected to KQ+ through pulse output DC isolation capacitors C54, resistors R49 and diodes V9 are connected in series between KQ+ and KQ-; KQ+ and KQ- are for turning on pulse output; Pin 1 and Pin 8 of the driver chip N7 are connected to a 15V power supply, Pin 2 is connected to one end of a current limiting resistor R57 and one end of a filter capacitor C61, the other end of the current limiting resistor R57 is connected to Pin 8 of the AND gate chip N5, and the other end of the filter capacitor C61 is grounded; Pin 4 and Pin 5 of the driver chip N7 are grounded, Pin 6 and Pin 7 are connected to the bases of transistors V13 and V14 through current limiting resistors R55 and filter capacitors C57 connected in series, and transistors V13 and V14 constitute complementary power transistors, and filter capacitors C59 and current limiting protection resistors R54 are connected in series between the collector of transistor V14 and the 15V power supply, and the collector of transistor V13 is grounded, and the emitters of transistors V13 and V14 are connected to GD+ through pulse output DC isolation capacitors C58, and resistors R53 and diodes V12 are connected in series between GD+ and GD-; GD+ and GD- are for shutting off pulse outputs; The modulation switch circuit comprises an on-pulse transformer T5, an off-pulse transformer T6 and a modulation switch circuit, the input end of the on-pulse transformer T5 is connected to KQ+ and KQ- respectively, the 1+ end of the on-pulse transformer T5 is connected to the gate of the switch tube Q1 through a current limiting resistor R59; the drain of the switch tube Q1 is connected to the positive bias voltage MOD end through a current limiting resistor R60, and is grounded through a capacitor C65, that is, the output common end K end; the source of the switch tube Q1 is connected to the 1- end of the on-pulse transformer T5, the capacitor C64 is connected between the drain and source of the switch tube Q1, and the delay capacitor C67, the discharge resistor R68, and the voltage regulator diode V16 are connected between the gate and the source of the switch tube Q1; The input ends of the shutdown pulse transformer T6 are connected to GD+ and GD- respectively, the 2+ end of the shutdown pulse transformer T6 is connected to the base of the transistor V18 through the current limiting resistor R61, and the 2- end of the shutdown pulse transformer T6 is connected to the emitter of the transistor V18; V18 is the shutdown transistor of the switch tube Q1, and the base and emitter of the transistor V18 are also connected with a discharge resistor R62 and a delay capacitor C69; the collector of the transistor V18 is connected to the gate of the switch tube Q1 through the current limiting resistor R69; A shutdown pulse current limiting resistor R63 and a voltage stabilizing diode V19 are connected in series between the 3+ terminal of the shutdown pulse transformer T6 and the gate of the switch tube Q2; the drain of the switch tube Q2 is connected to the source of the switch tube Q1, and is connected to the gate output G terminal through current limiting resistors R66 and R70; the source of the switch tube Q2 is connected to the 3- terminal of the shutdown pulse transformer T6, and is connected to the negative bias voltage Bias terminal through a current limiting resistor R67, and is grounded through a capacitor C66, that is, the output common terminal K terminal; a capacitor C63 is connected in parallel between the drain and source of the switch tube Q2, and resistors R65 and R71 are used to quickly discharge the output voltage after the shutdown pulse is applied, and R65 and R71 are connected in series and then connected in parallel between the drain and source of the switch tube Q2; a discharge resistor R64, a delay capacitor C68, and a voltage stabilizing diode V17 are connected in parallel between the gate and source of the switch tube Q2; a capacitor C62 and a discharge tube V15 are connected in parallel between the gate output G terminal and the output common terminal K terminal.

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