High-speed clock and data multiplexing buffer circuit
By designing a buffer circuit that includes a current source, a differential amplification module, an adjustable resistor, a capacitor array, and a buffer circuit, the problem of low-frequency noise amplification when the high-speed clock signal is buffered is solved, and gain stability and low-frequency signal attenuation over a wide frequency range is achieved, improving the performance and integration of the circuit.
Patent Information
- Application Number
- CN202311833860.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-06-27
AI Technical Summary
When the high-speed clock signal is buffered and amplified, the traditional differential CML circuit will amplify the low-frequency noise on the clock path in proportion, resulting in an increase in jitter of the output clock signal and it is difficult to maintain a stable gain over a wide frequency range.
A buffer circuit for high-speed clock and data multiplexing is designed, using current source, differential amplifier module, load resistor, degradation resistor array, degradation capacitor array and load capacitor components. The connection state of the degradation resistor array and degradation capacitor array are adjusted respectively when inputting the clock signal and data signal through the logic control unit to achieve attenuation of low-frequency signals and gain stability in a wide frequency range.
When inputting data signals, this circuit ensures that the gain of the circuit in a wide frequency range is stable; when inputting a clock signal, it can attenuate the low-frequency signal, suppress low-frequency noise such as common mode offset, and reduce jitter of the output clock signal. At the same time, the integration and flexibility of the circuit are improved through the multiplexing structure.
Smart Images
Figure CN120222992A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technologies, and particularly to a buffer circuit for high-speed clock and data multiplexing. Background Art
[0002] FPGA (Field Programmable Gate Array) has strong demands in occasions such as aviation, industry, servers, and edge computing, and needs to support different protocol requirements. High-speed SerDes (SERializer / DESerializer) is an important resource inside the FPGA and is the physical layer of the protocol. When high-speed clock and data are transmitted over a long distance inside Serdes, there will be signal distortion and attenuation, so it is necessary to insert one or more levels of buffers on the path to ensure the signal quality at the receiving end. The CMOS (Complementary Metal Oxide Semiconductor) level is the working level of very large-scale digital circuits. However, compared with CML (Current Mode Logic), because the CMOS logic has a larger output swing and a lower maximum operating rate, the high-speed clock and data buffers inside the SerDes chip usually adopt CML circuits.
[0003] The spectrum components contained in the random data signal are relatively rich, and it is required that the amplitude-frequency characteristic curve of the data buffer has no large fluctuations within the -3dB bandwidth to avoid the amplification or attenuation multiple of the signal in some frequency ranges exceeding the expectation, resulting in an incorrect response output of the subsequent circuit. The buffer for the clock signal can also adopt a CML structure. However, compared with the data signal, the energy of the clock signal mainly exists at discrete frequency points, so the signal in a specified frequency range can be amplified by adopting an active or passive inductive load.
[0004] The traditional differential CML circuit supports the buffering and amplification of high-speed clock or data signals. Its load resistance and the parasitic capacitance of the output node form a pole in the circuit, and the amplitude-frequency response of the buffer shows a low-pass characteristic. When used for the buffering and amplification of the clock signal, it will also amplify the low-frequency noise on the clock path proportionally, resulting in an increase in the jitter of the output clock signal. Summary of the Invention
[0005] An embodiment of the present invention provides a buffer circuit for high-speed clock and data multiplexing, which can ensure the gain stability of the circuit in a wide frequency range when an input data signal is received, and can attenuate low-frequency signals when an input clock signal is received.
[0006] An embodiment of the present invention provides a buffer circuit for high-speed clock and data multiplexing. The circuit includes: a current source, a differential amplification module, a load resistor, a degeneration resistor array and a degeneration capacitor array connected between the current source and the differential amplification module, a load capacitor connected to the load resistor and the ground, and a logic control unit; the degeneration resistor array includes: a fixed resistor unit and an adjustable resistor unit;
[0007] The differential amplification module is configured to input a clock signal or a data signal, and implement the transmission and / or amplification of the clock signal or the data signal;
[0008] The logic control unit is configured to disconnect the degeneration capacitor array when the differential amplification module inputs a data signal; and connect the degeneration capacitor array and disconnect the adjustable resistor unit in the degeneration resistor array when the differential amplification module inputs a clock signal.
[0009] Optionally, the differential amplification module includes: two differentially-connected differential amplifiers; where:
[0010] The first differential amplifier is configured to input the data signal;
[0011] The second differential amplifier is configured to input the clock signal.
[0012] Optionally, two input terminals of the first differential amplifier are respectively connected to the ground through a first switch; two input terminals of the second differential amplifier are respectively connected to the ground through a second switch; the first switch is controlled by a clock enable signal, and the second switch is controlled by a data enable signal; the clock enable signal and the data enable signal are complementary signals.
[0013] Optionally, the differential amplifier includes two differential pair transistors; the degeneration resistor array is connected between the two differential pair transistors; the degeneration capacitor array is connected between the two differential pair transistors.
[0014] Optionally, the differential pair transistor is any one of the following: a MOS transistor, a bipolar transistor.
[0015] Optionally, there is one group or multiple groups of adjustable resistor units, and each group of adjustable resistor units includes two resistors with the same resistance value connected in series between the two differential pair transistors.
[0016] Optionally, there is one group or multiple groups of capacitor units in the degeneration capacitor array, and each group of capacitor units includes two capacitors with the same capacitance value connected in series between the two differential pair transistors.
[0017] Optionally, the differential amplification module includes a first output terminal and a second output terminal for outputting a differential clock signal or a differential data signal; the load capacitors are respectively connected between the first output terminal and the ground, and between the second output terminal and the ground.
[0018] Optionally, the load capacitor is an adjustable capacitor or an adjustable capacitor array.
[0019] Optionally, the logic control unit includes:
[0020] A first logic unit for inputting the data enable signal or the clock enable signal and outputting a first control signal for the degradation resistor array
[0021] A second logic unit for inputting the data enable signal or the clock enable signal and outputting a second control signal for the degradation capacitor array.
[0022] Optionally, the aspect ratios of the two differential pair transistors of the first differential amplifier are smaller than those of the two differential pair transistors of the second differential amplifier.
[0023] Optionally, the capacitance values of the degradation capacitor array and the load capacitor when transmitting a low-speed clock signal are greater than those when transmitting a high-speed clock signal.
[0024] The buffer circuit for high-speed clock and data multiplexing provided by the embodiments of the present invention can configure the transmission characteristics of the circuit according to the characteristics of the input signal. In some application scenarios, such as when it is necessary to transmit a random data signal and a high-speed clock signal simultaneously, the multiplexing structure improves the circuit integration while ensuring the circuit performance. When the circuit operates in the clock buffer mode, the low-frequency gain less than 0 dB can suppress low-frequency noises such as the common-mode offset of the input signal; when the circuit operates in the data buffer mode, while ensuring the stability of the output common-mode point, it provides multiple groups of configurable gains, making it more flexible to use. Description of the Drawings
[0025] Figure 1 is a schematic structural diagram of a traditional CML circuit;
[0026] Figure 2 is a schematic structural diagram of a buffer circuit for high-speed clock and data multiplexing provided by an embodiment of the present invention;
[0027] Figure 3 is another schematic structural diagram of a buffer circuit for high-speed clock and data multiplexing provided by an embodiment of the present invention;
[0028] Figure 4 is a schematic structural diagram of a degradation resistor array in an embodiment of the present invention;
[0029] Figure 5is the schematic structural diagram of the first logic unit for controlling the Figure 4 degraded resistor array shown in
[0030] Figure 6 is a schematic structural diagram of a degraded capacitor array in an embodiment of the present invention;
[0031] Figure 7 is the schematic structural diagram of the second logic unit for controlling the Figure 4 degraded capacitor array shown in
[0032] Figure 8 is a schematic structural diagram of a load capacitor in an embodiment of the present invention;
[0033] Figure 9 is Figure 3 the equivalent circuit schematic diagram of the buffer circuit for high-speed clock and data multiplexing when inputting a data signal shown in
[0034] Figure 10 is Figure 3 the equivalent circuit schematic diagram of the buffer circuit for high-speed clock and data multiplexing when inputting a clock signal shown in
[0035] Figure 11 is the schematic diagram of the gain characteristic of the buffer circuit for high-speed clock and data multiplexing provided by the embodiment of the present invention in the data mode;
[0036] Figure 12 is the schematic diagram of the gain characteristic of the buffer circuit for high-speed clock and data multiplexing provided by the embodiment of the present invention in the clock mode. Detailed implementation manners
[0037] The principles and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the drawings. It should be understood that describing these embodiments is only to enable those skilled in the art to better understand and then implement the present invention, rather than limiting the scope of the present invention in any way.
[0038] The working principle of the CML circuit is to transmit and amplify signals by controlling current. To understand the solution of the present invention more clearly, the traditional CML structure and its working principle will be briefly described below.
[0039] The traditional CML structure is as shown in Figure 1 and mainly consists of two parts, namely the current source Ib and the differential amplifier composed of the differential pair transistors M1 and M2, and the resistor R is the load resistor. The power source Ib is responsible for generating a constant current, and the differential amplifier plays a role in amplifying the signal. Its input signals Vin and Vip are differential signals, that is, signals of positive and negative two phases, and the output differential signals are Voutp and Voutn.
[0040] The gain of the CML structure can be achieved by adjusting the operating current of the differential amplifier, thereby increasing the amplitude of the output signal and realizing the transmission and amplification of the signal.
[0041] In circuits such as high-speed interfaces, clock signals and data information need to be transmitted on certain signal paths. When the signal path needs to transmit data information, on the premise of ensuring sufficient bandwidth, it is necessary to ensure the gain stability of the circuit within the -3dB bandwidth. However, for clock signals, the clock buffer needs to reduce noise and jitter.
[0042] In view of the above application requirements, an embodiment of the present invention provides a buffer circuit for high-speed clock and data multiplexing, which can support the buffering and amplification of high-speed clock and data signals at the same time, and can adjust the device parameters of the circuit according to the characteristics of the input signal to achieve the best circuit performance.
[0043] As Figure 2 shown, it is a schematic structural diagram of a buffer circuit for high-speed clock and data multiplexing provided by an embodiment of the present invention.
[0044] The buffer circuit for high-speed clock and data multiplexing includes:
[0045] A current source Ib, a differential amplification module 20, a load resistor R1, a degeneration resistor array Rd and a degeneration capacitor array Cd connected between the current source Ib and the differential amplification module 20, a load capacitor Cl connected between the load resistor R1 and the ground, and a logic control unit (not shown in the figure). Among them.
[0046] The differential amplification module 20 is used to input differential signals Vin_p and Vin_n, transmit and / or amplify the differential signals, and obtain differential output signals Voutn and Voutp. Its input signal can be a clock signal or a data signal, and it realizes the transmission and / or amplification of the clock signal or the data signal.
[0047] In a non-limiting embodiment, the differential amplification module 20 can be a differential amplifier composed of a pair of differential pair transistors 1 and. The differential pair transistors and can be MOS transistors, such as Figure 2 shown MOS transistors M1 and M2, or bipolar transistors can also be used, and the embodiments of the present invention do not make any limitations in this regard.
[0048] Taking Figure 2 the shown MOS transistors as an example, the gate of each MOS transistor is used as the input terminal to input a clock signal or a data signal; the drain is used as the output terminal; the source is connected to its respective current source Ib, and the drains are respectively connected to the voltage VCC through the load resistor R1. The current source Ib can be generated by a current mirror to provide a controllable current.
[0049] The degenerated resistor array Rd and the degenerated capacitor array Cd are respectively connected between the source electrodes of two MOS transistors and the current source Ib. The load capacitor Cl is connected between the drain electrode of the MOS transistor and the ground.
[0050] In this embodiment, the degenerated resistor array Rd includes: a fixed resistor unit and an adjustable resistor unit.
[0051] Correspondingly, when the differential amplification module 20 inputs a data signal, the logic control unit disconnects the degenerated capacitor array Cd; when the differential amplification module 20 inputs a clock signal, the logic control unit connects the degenerated capacitor array Cd and disconnects the adjustable resistor unit in the degenerated resistor array Rd.
[0052] In this buffer circuit, the low-frequency gain of the circuit can be adjusted through the degenerated resistor array Rd, and the gain range of the circuit is jointly controlled by the degenerated capacitor array Cd and the load capacitor array Cl.
[0053] Through the above circuit structure, the multiplexing of the bias and the load in two working modes can be realized, improving the applicability and flexibility of the buffer circuit.
[0054] Furthermore, considering that the requirements for the size of the transmission transistors for the transmission of the clock signal and the data signal are often different, therefore, as Figure 3 shown, in another non-limiting embodiment, the differential amplification module may adopt two differentially-connected differential amplifiers, that is, Figure 3 the first differential amplifier composed of MOS transistors M1 and M2 for inputting differential data signals Vin_data_p and Vin_data_n; and the second differential amplifier composed of MOS transistors M3 and M4 for inputting differential clock signals Vin_clk_p and Vin_clk_n.
[0055] It should be noted that when transmitting signals, only one type of signal can be transmitted at the same time, that is, the data signal or the clock signal. Therefore, in order to conveniently control the operation of the two differential amplifiers, as Figure 3 shown, the two input terminals of the first differential amplifier are respectively connected to the ground through the first switch K1; the two input terminals of the second differential amplifier are respectively connected to the ground through the second switch K2; the first switch K1 is controlled by the clock enable signal clk_en, and the second switch K2 is controlled by the data enable signal clk_enb; the clock enable signal clk_en and the data enable signal clk_enb are complementary signals, that is, when one of them is at a high level, the other is at a low level.
[0056] When data signals need to be transmitted, the clock enable signal clk_en controls the first switch K1 to open. Correspondingly, the data enable signal clk_enb controls the second switch K2 to close, and both input terminals of the second differential amplifier are grounded. Conversely, when clock signals need to be transmitted, the clock enable signal clk_en controls the first switch K1 to close. Correspondingly, the data enable signal clk_enb controls the second switch K2 to open, and both input terminals of the first differential amplifier are grounded.
[0057] In the embodiment of the present invention, there may be one or more groups of adjustable resistor units in the degeneration resistor array Rd. Each group of adjustable resistor units includes two resistors with the same resistance value and connected in series between the two differential pair transistors.
[0058] Similarly, the degeneration capacitor array Cd may have one or more groups of capacitor units. Each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair transistors.
[0059] To facilitate the control of the above-mentioned degeneration resistor array Rd and degeneration capacitor array Cd, different logic units can be set to control them.
[0060] For example, in a non-limiting embodiment, the logic control unit may include:
[0061] A first logic unit for inputting the data enable signal or the clock enable signal and outputting a first control signal for the degeneration resistor array Rd
[0062] A second logic unit for inputting the data enable signal or the clock enable signal and outputting a second control signal for the degeneration capacitor array Cd.
[0063] Next, the structures of the degeneration resistor array Rd and the degeneration capacitor array Cd in the embodiment of the present invention will be described in detail by way of example.
[0064] Referring to Figure 4 and Figure 5 , Figure 4 FIG. shows a schematic structural diagram of a degeneration resistor array in the embodiment of the present invention, Figure 5 is a schematic structural diagram of a first logic unit for controlling the Figure 4 shown degeneration resistor array.
[0065] Figure 4In the illustrated example, the degradation resistance array Rd is composed of a group of fixed resistance units Rd_on and three groups of adjustable resistance units Rd0, Rd1, and Rd2. Each group of resistance units includes two resistors with the same resistance value, which are connected in series between the nodes A and B of the two differential pair transistors. A control switch is provided between the two resistors of each group of adjustable resistance units, and is controlled by control signals ctrl<0>, ctrl<1>, and ctrl<2> respectively.
[0066] The control signals ctrl<0>, ctrl<1>, and ctrl<2> are generated by corresponding logic circuits, such as Figure 5 the first logic unit shown, which is composed of multiple gate circuits and realizes the decoding logic control of Rd0 to Rd2.
[0067] Figure 5 The first logic unit shown includes three input signals, namely the data enable signal clk_enb, and the resistance logic control signals r_ctrl<0> and r_ctrl<1>. The three output signals ctrl<0>, ctrl<1>, and ctrl<2> respectively control the connection or disconnection of the three groups of adjustable resistance units in the degradation resistance array Rd to the circuit. Among them, the resistance logic control signals r_ctrl<0> and r_ctrl<1> can be generated by an external register or the I / O pins of a control module and input to the first logic unit.
[0068] At the same time, referring to Figure 3 , Figure 4 and Figure 5 , when clk_enb = 1, Rd_on is connected to the circuit, and Rd0 to Rd2 are controlled by Figure 5 the first logic unit shown, and the control logic is as follows:
[0069] When ctrl<0>, ctrl<1>, and ctrl<2> are 1, the resistors Rd0, Rd1, and Rd2 are connected to the circuit, and vice versa, they are disconnected.
[0070] When clk_enb = 0, ctrl<2:0> = 3b000, that is, ctrl<2>, ctrl<1>, and ctrl<0> are all 0, and the resistors Rd0, Rd1, and Rd2 are disconnected and not connected to the circuit;
[0071] When clk_enb = 1, ctrl<2:0> is the thermometer decoding of r_ctrl<1:0>, that is:
[0072] When r_ctrl<1:0> = 2b00, ctrl<2:0> = 3b000, that is, ctrl<2>, ctrl<1>, and ctrl<0> are all 0, and the resistors Rd2, Rd1, and Rd0 are disconnected;
[0073] When r_ctrl<1:0> = 2'b01, ctrl<2:0> = 3'b001, that is, ctrl<2> and ctrl<1> are 0, ctrl<0> is 1, resistor Rd2 and Rd1 are disconnected, and Rd0 is connected to the circuit;
[0074] When r_ctrl<1:0> = 2'b10, ctrl<2:0> = 3'b011, that is, ctrl<2> is 0, ctrl<1> and ctrl<0> are 1, resistor Rd2 is disconnected, and Rd1 and Rd0 are connected to the circuit;
[0075] When r_ctrl<1:0> = 2'b11, ctrl<2:0> = 3'b111, that is, ctrl<2>, ctrl<1>, and ctrl<0> are all 1, resistors Rd2, Rd1, and Rd0 are all connected to the circuit.
[0076] It can be seen that as r_ctrl<1:0> increases, resistors Rd0, Rd1, and Rd2 are connected to the circuit in sequence.
[0077] Refer to Figure 6 and Figure 7 , Figure 6 is a schematic structural diagram of a degraded capacitor array in an embodiment of the present invention, Figure 7 is a schematic structural diagram of a second logic unit for controlling Figure 6 the degraded capacitor array shown.
[0078] Figure 6 In the example shown, the degraded capacitor array Cd is composed of four groups of capacitor units Cd_on, Cd0, Cd1, and Cd2. Each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair transistor nodes A and B. Control switches are provided between the two capacitors in each group of capacitor units and are controlled by control signals clk_en, degc<0>, degc<1>, and degc<2> respectively.
[0079] Figure 7 The second logic unit shown includes three input signals, namely a data enable signal clk_enb, and resistor logic control signals c_ctrl<0> and c_ctrl<1>. The three output signals degc<0>, degc<1>, and degc<2> respectively control three groups of adjustable resistor units Cd0, Cd1, and Cd2 in the degraded capacitor array Cd to be connected to or disconnected from the circuit. Among them, the capacitor logic control signals c_ctrl<0> and c_ctrl<1> can be generated by an external register or the I / O pins of a control module and input to the second logic unit.
[0080] At the same time, refer to Figure 3 , Figure 6 and Figure 7, the control logic of the second logic unit for the capacitor array is as follows:
[0081] When the control signals clk_en, degc<0>, degc<1>, degc<2> are 1, the capacitors Cd_on, Cd0, Cd1, Cd2 are connected to the circuit; otherwise, they are disconnected.
[0082] When clk_en = 0, clk_enb = 1, degc<2:0> = 3b000, that is, the capacitors Cd_on, Cd0, Cd1, Cd2 are not connected to the circuit;
[0083] When clk_en = 1, Cd_on is connected to the circuit, and degc<2:0> is the reverse thermometer decoding of c_ctrl<1:0>, that is:
[0084] When c_ctrl<1:0> = 2b00, degc<2:0> = 3b111, that is, degc<2>, degc<1>, degc<0> are all 1, and the capacitors Cd2, Cd1, Cd1 are all connected to the circuit;
[0085] When c_ctrl<1:0> = 2b01, degc<2:0> = 3b110, that is, degc<2> and degc<1> are both 1, degc<0> is 0, and the capacitors Cd2 and Cd1 are connected to the circuit, and Cd0 is disconnected;
[0086] When c_ctrl<1:0> = 2b10, degc<2:0> = 3b100, that is, degc<2> is 1, degc<1> and degc<0> are 0, and the capacitor Cd2 is connected to the circuit, and Cd1 and Cd0 are disconnected;
[0087] When c_ctrl<1:0> = 2b11, degc<2:0> = 3b000, that is, degc<2>, degc<1> and degc<0> are all 0, and the capacitors Cd2, Cd1 and Cd0 are all disconnected.
[0088] It can be seen that as c_ctrl<1:0> increases, the capacitors Cd0, Cd1, Cd2 are disconnected from the circuit in sequence.
[0089] Continue to refer to Figure 3 , in the embodiment of the present invention, two load capacitors Cl are respectively connected between the first output terminal and the ground, and between the second output terminal and the ground. In a specific application, the load capacitor Cl can be a tunable capacitor or a tunable capacitor array.
[0090] As Figure 8 shown, it is a schematic structural diagram of a load capacitor in the embodiment of the present invention.
[0091] In this example, the load capacitance Cl is an adjustable capacitor array composed of three capacitors Cl0, Cl1, and Cl2. The capacitors Cl0, Cl1, and Cl2 are adjustable capacitors, which are respectively controlled by corresponding switches. These switches can also be controlled by Figure 7 the control signals degc<0>, degc<1>, and degc<2> generated by the second logic unit shown.
[0092] Continue to refer to Figure 3 to detail the process and performance of the buffer circuit for high-speed clock and data multiplexing provided by the present invention in transmitting data signals and clock signals.
[0093] When Figure 3 the buffer circuit shown operates in the data buffer mode, clk_en = 0 and clk_enb = 1. That is, at this time, the input differential pair transistors M1 and M2 work normally, the gates of M3 and M4 are pulled down to ground, and at the same time, the degeneration capacitor Cd is not connected to the circuit. At this time Figure 3 the buffer circuit shown can be simplified to Figure 9 shown.
[0094] Refer to Figure 9 , the resistance value of the adjustable resistor array Rd is much smaller than the output impedance ro of the tail current source Ib. Figure 9 As shown, the resistance value of the resistor array Rd shown decreases with the increase of r_ctrl<1:0>. The low-frequency gain of the circuit can be expressed as gm1×Rl / (1 + gm1×Rd), where gm1 represents the transconductance of the input differential pair transistor in the data mode. Since the data buffer has multiple adjustable gains, by reasonably configuring the resistance values of Rd_on and Rd0 to Rd3, multi-stage gain adjustment of the input data signal from attenuation to amplification can be achieved, and its amplitude-frequency characteristic is as Figure 11 shown.
[0095] When Figure 3 the circuit shown operates in the clock buffer mode, clk_en = 1 and clk_enb = 0. Rd0 to Rd2 of the adjustable resistor array Rd are not connected to the circuit, and the capacitor array Cd is connected in parallel to the sources of the input differential pair transistors M3 and M4. At this time Figure 3 the buffer circuit shown can be simplified to Figure 10 shown.
[0096] Refer to Figure 10, the low-frequency gain of the circuit is less than 0 dB. The zero point formed by the degeneration capacitor Cd and the fixed resistor unit Rd_on in the resistor array Rd is 1 / (Rd_on×Cd), and the main pole of the circuit is (1 + gm3×Rd) / (Rd_on×Cd), where gm3 represents the transconductance of the input differential pair transistors in the clock mode. The output pole is 1 / (Rl×Cl), and the gain of the buffer for signals with frequencies in the range from (1 + gm3×Rd) / (Rd_on×Cd) to 1 / (Rl×Cl) is approximately gm3×Rl.
[0097] By reasonably configuring the capacitance values of the degeneration capacitor Cd and the load capacitor Cl, the fundamental wave of the clock signal can be amplified, and the high-order harmonics and low-frequency components can be attenuated. At this time, the amplitude-frequency characteristic curve of the buffer is as Figure 12 shown.
[0098] For the input clock signal frequency, adjusting the band-pass interval of the circuit can ensure the minimum output noise of the circuit and further reduce the jitter of the clock. Specifically, c_ctrl<1:0> increases as the input clock frequency increases, and the adjustment directions of the degeneration capacitor Cd and the load capacitor Cl are the same, as Figure 8 shown.
[0099] When the input signal of the buffer is a low-speed clock, the capacitance values of Cd and Cl are large, and at this time, the frequencies of the main pole and the output pole are low; when the input signal is a high-speed clock, the capacitance values of Cd and Cl are small, and at this time, the frequencies of the main pole and the output pole are high. In this way, the transmission quality of clock signals with different frequencies can be better guaranteed.
[0100] It should be noted that in specific applications, the aspect ratios of the two groups of differential pair transistors can be the same or different, and the embodiments of the present invention do not make any limitations in this regard. Preferably, when the input signal of the buffer is random data, in order to ensure the linearity of the circuit, the overdrive voltage of the M1 transistor is large, and the aspect ratio of M1 is small; when the input signal is a high-speed clock that conforms to CMOS logic and the high level is less than the buffer power supply voltage, the aspect ratio of M3 is relatively larger, which can better ensure the swing of the output signal.
[0101] In specific implementations, for each module / unit included in the various devices and products described in the above embodiments, it can be a software module / unit, a hardware module / unit, or it can also be partially a software module / unit and partially a hardware module / unit.
[0102] For example, for each device or product applied to or integrated with a chip, each module / unit included therein can be implemented in the form of hardware such as a circuit, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the chip, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as a circuit; for each device or product applied to or integrated with a chip module, each module / unit included therein can be implemented in the form of hardware such as a circuit, and different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the chip module, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as a circuit; for each device or product applied to or integrated with a terminal, each module / unit included therein can be implemented in the form of hardware such as a circuit, and different modules / units can be located in the same component (such as a chip, a circuit module, etc.) or different components inside the terminal, or at least some of the modules / units can be implemented in the form of a software program that runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules / units can be implemented in the form of hardware such as a circuit.
[0103] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A buffer circuit for high-speed clock and data multiplexing, characterized in that, The circuit includes: a current source, a differential amplification module, a load resistor, a degeneration resistor array and a degeneration capacitor array connected between the current source and the differential amplification module, a load capacitor connected to the load resistor and the ground, and a logic control unit; the degeneration resistor array includes: a fixed resistor unit and an adjustable resistor unit; The differential amplification module is configured to input a clock signal or a data signal, and implement the transmission and / or amplification of the clock signal or the data signal; The logic control unit is configured to disconnect the degeneration capacitor array when the differential amplification module inputs a data signal; and connect the degeneration capacitor array and disconnect the adjustable resistor unit in the degeneration resistor array when the differential amplification module inputs a clock signal.
2. The buffer circuit for high-speed clock and data multiplexing according to claim 1, wherein The differential amplification module includes: two differentially-connected differential amplifiers; where: The first differential amplifier is configured to input the data signal; The second differential amplifier is configured to input the clock signal.
3. The buffer circuit for high-speed clock and data multiplexing according to claim 2, wherein: Two input terminals of the first differential amplifier are respectively connected to the ground through a first switch; Two input terminals of the second differential amplifier are respectively connected to the ground through a second switch; The first switch is controlled by a clock enable signal, and the second switch is controlled by a data enable signal; the clock enable signal and the data enable signal are complementary signals.
4. The buffer circuit for high-speed clock and data multiplexing according to claim 3, wherein The differential amplifier includes two differential pair transistors; The degeneration resistor array is connected between the two differential pair transistors; The degeneration capacitor array is connected between the two differential pair transistors.
5. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein The differential pair transistor is any one of the following: a MOS transistor, a bipolar transistor.
6. The buffer circuit for high-speed clock and data multiplexing according to claim 4, characterized in that There is one group or multiple groups of adjustable resistor units, and each group of adjustable resistor units includes two resistors with the same resistance value and connected in series between the two differential pair transistors.
7. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein There is one group or multiple groups of capacitor units in the degeneration capacitor array, and each group of capacitor units includes two capacitors with the same capacitance value and connected in series between the two differential pair transistors.
8. The buffer circuit for high-speed clock and data multiplexing according to claim 1, characterized in that, The differential amplification module includes a first output terminal and a second output terminal, and is configured to output a differential clock signal or a differential data signal; The load capacitors are respectively connected between the first output terminal and the ground, and between the second output terminal and the ground.
9. The buffer circuit for high-speed clock and data multiplexing according to claim 8, wherein The load capacitor is an adjustable capacitor or an adjustable capacitor array.
10. The buffer circuit for high-speed clock and data multiplexing according to claim 3, characterized in that, The logic control unit includes: A first logic unit, configured to input the data enable signal or the clock enable signal, and output a first control signal for the degeneration resistor array A second logic unit, configured to input the data enable signal or the clock enable signal, and output a second control signal for the degeneration capacitor array.
11. The buffer circuit for high-speed clock and data multiplexing according to claim 4, wherein The aspect ratio of the two differential pair transistors of the first differential amplifier is smaller than the aspect ratio of the two differential pair transistors of the second differential amplifier.
12. The buffer circuit for high-speed clock and data multiplexing according to claim 1, wherein The capacitance values of the degeneration capacitor array and the load capacitor when transmitting a low-speed clock signal are greater than the capacitance values when transmitting a high-speed clock signal.