Electronic device

Abstract

An electronic device is disclosed. The electronic device includes: a plurality of first transistors included in a first current path between a first power supply node to which a positive power supply voltage is configured to be applied and a second power supply node to which a negative power supply voltage is configured to be applied in a normal mode; and a first protection transistor connected to the first node, two of the plurality of first transistors being connected to the first node, in which the first protection transistor is configured to be turned off in a normal mode and turned on in a power-off mode to supply a protection voltage to the first node.

Description

[0001] This application is based on and claims the priority of Korean Patent Application No. 10-2023-0193184, filed with the Korean Intellectual Property Office on December 27, 2023, and Korean Patent Application No. 10-2024-0053541, filed with the Korean Intellectual Property Office on April 22, 2024. The disclosures of the Korean patent applications are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosed embodiments relate to a device for protecting a transistor, and more particularly to a device including a transistor that protects other transistors in a power-down mode. Background Art

[0003] An integrated circuit may include elements such as transistors, and the elements may have a withstand voltage to operate normally. For example, when a voltage exceeding the withstand voltage is applied to an element, the element may not be able to provide a desired operation or may be damaged. Therefore, an integrated circuit may include a structure for protecting an element from a voltage exceeding the withstand voltage. The integrated circuit may support a power-down mode, and it may be necessary to protect the element from a voltage exceeding the withstand voltage even in the power-down mode.

[0004] The information disclosed in this background art section was known to the inventors before the realization of the disclosure of the present application or was obtained during the process of realizing the disclosure. Therefore, it may include information that does not form the prior art known to the public. Summary of the Invention

[0005] Disclosed is a device including a structure for protecting an element in a power-down mode.

[0006] According to one aspect of the disclosure, there is provided a device including: a plurality of first transistors included in a first current path between a first power supply node and a second power supply node in a normal mode, a positive power supply voltage being configured to be applied to the first power supply node and a negative power supply voltage being configured to be applied to the second power supply node; and a first protection transistor connected to a first node, two of the plurality of first transistors being connected to the first node, wherein the first protection transistor is configured to be turned off in the normal mode and turned on in the power-down mode to provide a protection voltage to the first node.

[0007] According to another aspect of the disclosure, there is provided an apparatus including: a plurality of first transistors included in a first current path between a first power supply node and a second power supply node in a normal mode, a positive power supply voltage being configured to be applied to the first power supply node and a negative power supply voltage being configured to be applied to the second power supply node; and a protection transistor connected to a gate of a first multifunctional transistor among the plurality of first transistors, wherein the protection transistor is configured to be turned off in the normal mode and turned on in a power-off mode to provide a protection voltage to the gate of the first multifunctional transistor.

[0008] According to still another aspect of the disclosure, there is provided an apparatus including: an input stage circuit configured to generate complementary amplified signals based on complementary input signals in a normal mode; an output stage circuit configured to generate complementary output signals based on the complementary amplified signals in the normal mode; and a bias circuit configured to provide at least one bias voltage to each of the input stage circuit and the output stage circuit; wherein the input stage circuit includes: a first protection transistor and a second protection transistor respectively connected to a first node and a second node where the complementary amplified signals are respectively generated, and the first protection transistor and the second protection transistor are configured to be turned off in the normal mode and turned on in the power-off mode to respectively provide a first protection voltage to each of the first node and the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram showing an apparatus according to one or more embodiments.

[0011] Figures 2A to 2D is a diagram showing an example of a transistor according to one or more embodiments.

[0012] Figure 3 is a circuit diagram showing an amplifier according to one or more embodiments.

[0013] Figure 4 is a graph showing a protection voltage according to one or more embodiments.

[0014] Figure 5A and Figure 5B is a circuit diagram showing an example of a current path according to some embodiments.

[0015] Figure 6 is a circuit diagram showing an amplifier according to one or more embodiments.

[0016] Figure 7 is a circuit diagram showing a current path according to one or more embodiments.

[0017] Figure 8 is a circuit diagram showing an amplifier according to one or more embodiments.

[0018] Figure 9 is a circuit diagram showing a current path according to one or more embodiments.

[0019] Figure 10 is a circuit diagram showing an amplifier according to one or more embodiments.

[0020] Figure 11 is a timing diagram showing the operation of a device according to one or more embodiments.

[0021] Figure 12 is a block diagram showing a system-on-chip (SOC) according to one or more embodiments. DETAILED DESCRIPTION

[0022] The various embodiments disclosed will be described herein with reference to the accompanying drawings. The embodiments described herein are non-limiting example embodiments, and thus, the disclosure is not limited thereto and may be implemented in various other forms. Each of the embodiments provided herein does not exclude being associated with one or more features of additional embodiments or additional embodiments provided herein or additional embodiments or additional embodiments not provided herein but consistent with the disclosure. For example, unless otherwise mentioned in its description, even if the content described in a particular example or embodiment is not described in a different example or embodiment, such content can be understood as being relevant or combinable with the different example or embodiment.

[0023] Figure 1 is a block diagram showing a device 10 according to one or more embodiments. For example, Figure 1 the block diagram shows the device 10 acting as an amplifier that generates an output signal OUT by amplifying an input signal IN. Hereinafter, as Figure 1 shown in, the device 10 acting as an amplifier will be mainly described, but note that some embodiments are not limited to Figure 1 the device 10. As Figure 1 shown in, the device 10 may include an input stage circuit 11, an output stage circuit 12, and a bias circuit 13. Here, the input stage circuit may be referred to as the input stage, and the output stage circuit may be referred to as the output stage.

[0024] The input stage circuit 11 may receive the input signal IN and may generate an amplified signal AMP by amplifying the input signal IN. In some embodiments, the input stage circuit 11 may have a non-inverting input and an inverting input. The input signal IN may include two signals respectively provided to the non-inverting input and the inverting input (e.g., Figure 3IN1 and IN2), and the input stage circuit 11 can generate an amplified signal AMP by amplifying the difference between the two signals. In some embodiments, the amplified signal AMP may include complementary signals. Examples of the input stage circuit 11 will be described later with reference to the accompanying drawings.

[0025] The output stage circuit 12 can receive the amplified signal AMP and generate an output signal OUT based on the amplified signal AMP. In some embodiments, the output stage circuit 12 may have a high current driving ability and may provide a low output impedance at the output node where the output signal OUT is generated. Examples of the output stage circuit 12 will be described later with reference to the accompanying drawings.

[0026] The bias circuit 13 can generate a bias voltage. For example, as Figure 1 shown, the bias circuit 13 can provide at least one first bias voltage B1 to the input stage circuit 11, and the input stage circuit 11 can generate the amplified signal AMP based on the at least one first bias voltage B1 according to the input signal IN. In addition, the bias circuit 13 can provide at least one second bias voltage B2 to the output stage circuit 12, and the output stage circuit 12 can generate the output signal OUT based on the at least one second bias voltage B2 according to the amplified signal AMP.

[0027] The device 10 can receive a positive power supply voltage and a negative power supply voltage, and can operate based on the power provided by the positive power supply voltage and the negative power supply voltage. For example, each of the input stage circuit 11, the output stage circuit 12, and the bias circuit 13 can be connected to a first power supply node to which the positive power supply voltage is applied and / or a second power supply node to which the negative power supply voltage is applied, and can operate based on the current flowing from the first power supply node to the second power supply node.

[0028] The device 10 can support a power-off mode. For example, the device 10 can perform an operation of generating the output signal OUT according to the input signal IN in the normal mode, and can consume no power in the power-off mode. As another example, as Figure 1 shown, the bias circuit 13 can receive a power-off signal PD, and when the power-off signal PD is activated, in the power-off mode, the power consumed by the input stage circuit 11 and the output stage circuit 12 can be cut off by adjusting the at least one first bias voltage B1 and the at least one second bias voltage B2. In some embodiments, the input stage circuit 11 and / or the output stage circuit 12 can receive the power-off signal PD. Here, it is assumed that the power-off signal PD is an active-high signal, and thus, the activated power-off signal PD can have a high level, and the inactivated power-off signal PD can have a low level. Here, the power-off signal PD can be referred to as a control signal.

[0029] In some embodiments, device 10 may include an integrated circuit fabricated through a semiconductor process. For example, the integrated circuit may be fabricated by patterning multiple layers using at least one mask. The front-end-of-line (FEOL) process may include, for example, operations of planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes. Individual components (such as transistors, capacitors, resistors, etc.) may be formed on a substrate through the FEOL process. An example of a transistor will be described below with reference to Figures 2A to 2D In addition, the back-end-of-line (BEOL) process may include, for example, operations of siliciding the gate region, source region, and drain region, adding dielectrics, planarizing, forming vias, adding metal layers, forming through-holes, forming a passivation layer, etc. Individual components (such as transistors, capacitors, resistors, etc.) may be interconnected through the BEOL process. In some embodiments, the middle-of-line (MOL) process may be performed between the FEOL and the BEOL, and contacts may be formed on the individual components. Then the integrated circuit may be packaged in a semiconductor package and used as a component for various applications.

[0030] Each of the input stage circuit 11, the output stage circuit 12, and the bias circuit 13 may include components (such as transistors). The transistor may have a breakdown voltage for normal operation. For example, when a voltage exceeding the breakdown voltage is applied to the transistor, the transistor may not provide the desired operation or may even be damaged. Depending on the structure and / or composition, the transistor may have different breakdown voltages, and the breakdown voltage of the transistor may be reduced due to various factors. For example, when the size of the transistor is reduced or the structure of the transistor is changed, the breakdown voltage may be reduced. Therefore, device 10 may include a structure for protecting the transistor from voltages exceeding the breakdown voltage. In some embodiments, device 10 may include such a transistor: the voltage applied to the transistor in the normal mode and the voltage applied to the transistor in the power-off mode are different from each other. As will be described below with reference to the drawings, the structure for protecting the transistor can protect the transistor from voltages exceeding the breakdown voltage not only in the normal mode but also in the power-off mode. In addition, the structure for protecting the transistor may not cause degradation of the performance of device 10 in the normal mode. In addition, the structure for protecting the transistor may be minimized, and thus, device 10 may achieve a reduced area.

[0031] Figures 2A to 2D is a diagram showing an example of a transistor according to some embodiments. For example, Figure 2A shows a fin field-effect transistor (FinFET) 20a, Figure 2Bshows a gate-all-around field-effect transistor (GAAFET) 20b, Figure 2C shows a multi-bridge-channel field-effect transistor (MBCFET) 20c, and Figure 2D shows a vertical field-effect transistor (VFET) 20d. For ease of illustration, Figures 2A to 2C shows a state in which one of two source / drain regions is omitted to show a channel structure, and Figure 2D shows a cross-section of the VFET 20d that is parallel to the plane formed by the Y-axis and the Z-axis and cuts through the channel CH of the VFET 20d.

[0032] Referring to Figure 2A , the FinFET 20a can be formed by a fin-shaped active pattern extending in the X-axis direction between shallow trench isolations (STIs) and a gate G extending in the Y-axis direction. Source / drain SDs can be formed on each side of the gate G, and thus, the source / drain SDs can be spaced apart from each other in the X-axis direction. An insulating layer can be formed between the channel CH and the gate G. In some embodiments, the FinFET 20a can be formed by a plurality of active patterns spaced apart from each other in the Y-axis direction and the gate G.

[0033] Referring to Figure 2B , the GAAFET 20b can be formed by active patterns (e.g., nanowires) spaced apart from each other in the Z-axis direction and extending in the X-axis direction and a gate G extending in the Y-axis direction. Source / drain SDs can be formed on each side of the gate G, and thus, the source / drain SDs can be spaced apart from each other in the X-axis direction. An insulating layer can be formed between the channel CH and the gate G. Note that the number of nanowires included in the GAAFET 20b is not limited to Figure 2B the number shown in

[0034] Referring to Figure 2C , the MBCFET 20c can be formed by active patterns (e.g., nanosheets) spaced apart from each other in the Z-axis direction and extending in the X-axis direction and a gate G extending in the Y-axis direction. Source / drain SDs can be formed on each side of the gate G, and thus, the source / drain SDs can be spaced apart from each other in the X-axis direction. An insulating layer can be formed between the channel CH and the gate G. Note that the number of nanosheets included in the MBCFET 20c is not limited to Figure 2C the number shown in

[0035] Referring to Figure 2D, the VFET 20d may include a top source / drain T_SD and a bottom source / drain B_SD spaced apart from each other in the Z-axis direction, and a channel CH is disposed between the top source / drain T_SD and the bottom source / drain B_SD. The VFET 20d may include a gate G that surrounds the periphery of the channel CH between the top source / drain T_SD and the bottom source / drain B_SD. An insulating layer may be formed between the channel CH and the gate G.

[0036] Hereinafter, an integrated circuit including the GAAFET 20b or the MBCFET 20c will be mainly described, but note that the elements included in the integrated circuit are not limited to Figures 2A to 2D examples. For example, the integrated circuit may include a ForkFET in which, since the nanosheets for P-type transistors and the nanosheets for N-type transistors are separated by a dielectric wall, the N-type transistors and the P-type transistors have a closer structure. In addition, the integrated circuit may include bipolar junction transistors and FETs (such as complementary field effect transistors (CFETs), negative capacitance field effect transistors (NCFETs), carbon nanotube (CNT) FETs, etc.).

[0037] Figure 3 is a circuit diagram showing an amplifier 30 according to one or more embodiments. For example, Figure 3 the circuit diagram shows the amplifier 30 as Figure 1 an example of the device 10. As Figure 3 shown, the amplifier 30 may include an input stage circuit 31, an output stage circuit 32, and a bias circuit 33. Hereinafter, Figure 3 descriptions redundant with those given above with reference to the drawings will be omitted.

[0038] The input stage circuit 31 may receive a first input signal IN1 and a second input signal IN2, and generate complementary signals (e.g., a first amplified signal AMP1 and a second amplified signal AMP2) by amplifying the difference between the first input signal IN1 and the second input signal IN2. As Figure 3 shown, the input stage circuit 31 may include first transistors M11 to fifth transistors M15. The first transistor M11 and the second transistor M12 may each be a p-channel field effect transistor (PFET), and the third transistor M13 to the fifth transistor M15 may each be an n-channel field effect transistor (NFET).

[0039] The third transistor M13 may have a gate receiving a first input signal IN1, a drain connected to the drain of the first transistor M11, and a source connected to the source of the fifth transistor M15. The fourth transistor M14 may have a gate receiving a second input signal IN2, a drain connected to the drain of the second transistor M12, and a source connected to the source of the fifth transistor M15. The fifth transistor M15 may have a drain connected to the drains of the third transistor M13 and the fourth transistor M14, a source connected to a second power supply node to which a negative power supply voltage VSS is applied, and a gate receiving a third bias voltage VB3. The fifth transistor M15 may be used as a current source.

[0040] The first transistor M11 may have a source connected to a first node N1, a drain connected to the drain of the third transistor M13, and a gate to which a first protection voltage VP1 is applied, wherein a first amplified signal AMP1 is generated at the first node N1. The second transistor M12 may have a source connected to a second node N2, a drain connected to the drain of the fourth transistor M14, and a gate to which a first protection voltage VP1 is applied, wherein a second amplified signal AMP2 is generated at the second node N2. The voltage at each of the first node N1 and the second node N2 may be higher than or equal to the first protection voltage VP1, and the first protection voltage VP1 is applied to the gate of each of the first transistor M11 and the second transistor M12. As will be described below with reference to Figure 4 the first transistor M11 and the second transistor M12 may prevent a voltage higher than or equal to the withstand voltage from being applied to other transistors (e.g., the first transistor M21 and the second transistor M22 of the output stage circuit 32). Transistors that prevent a voltage higher than or equal to the withstand voltage from being applied to another transistor (such as the first transistor M11 and the second transistor M12) may be referred to herein as protection transistors.

[0041] The output stage circuit 32 may receive the first amplified signal AMP1 and the second amplified signal AMP2, and may generate complementary signals (e.g., a first output signal OUT1 and a second output signal OUT2) according to the first amplified signal AMP1 and the second amplified signal AMP2, respectively. In some embodiments, the output stage circuit 32 may be of a single-ended type and may output only the second output signal OUT2. As Figure 3 shown, the output stage circuit 32 may include a first transistor M21 to an eighth transistor M28. The first transistor M21 to the sixth transistor M26 may each be a PFET, and the seventh transistor M27 and the eighth transistor M28 may each be an NFET.

[0042] The first transistor M21 may have a source connected to a first power node to which a positive power supply voltage VDD is applied, a drain connected to the first node N1, and a gate to which a first bias voltage VB1 is applied. The second transistor M22 may have a source connected to the first power node, a drain connected to the second node N2, and a gate to which the first bias voltage VB1 is applied. Each of the first transistor M21 and the second transistor M22 may be used as a current source.

[0043] The third transistor M23 may have a source connected to the first node N1, a drain connected to the fifth transistor M25, and a gate to which a second bias voltage VB2 is applied. The fourth transistor M24 may have a source connected to the second node N2, a drain connected to the sixth transistor M26, and a gate to which the second bias voltage VB2 is applied. The fifth transistor M25 may have a source connected to the third transistor M23, a drain connected to the first output node NO1, and a gate to which a second protection voltage VP2 is applied, where a first output signal OUT1 is generated at the first output node NO1. The sixth transistor M26 may have a source connected to the fourth transistor M24, a drain connected to the second output node NO2, and a gate to which the second protection voltage VP2 is applied, where a second output signal OUT2 is generated at the second output node NO2. Accordingly, the fifth transistor M25 and the sixth transistor M26 may be protection transistors, and the voltage at each of the sources of the fifth transistor M25 and the sixth transistor M26 may be higher than or equal to the second protection voltage VP2. In some embodiments, the second protection voltage VP2 may be the same as the first protection voltage VP1.

[0044] The seventh transistor M27 may have a drain and a gate connected to the first output node NO1, and a source connected to a second power node. The eighth transistor M28 may have a drain connected to the second output node NO2, a source connected to the second power node, and a gate connected to the first output node NO1. The seventh transistor M27 and the eighth transistor M28 may each be used as a current mirror.

[0045] The bias circuit 33 may generate a first bias voltage VB1 to a third bias voltage VB3. As Figure 3 shown, the bias circuit 33 may include a first transistor M31 to an eighth transistor M38 and a current source CS. The first transistor M31 to the third transistor M33 may each be a PFET, and the fourth transistor M34 to the eighth transistor M38 may each be an NFET.

[0046] The current source CS can be connected to the first power supply node and the sixth transistor M36, and the current source CS can supply a current having a predetermined magnitude to the sixth transistor M36. The sixth transistor M36 to the eighth transistor M38 and the fifth transistor M15 of the input stage circuit 31 can each be used as a current mirror. The sixth transistor M36 can generate a third bias voltage VB3 corresponding to the current supplied by the current source CS, and the seventh transistor M37, the eighth transistor M38, and the fifth transistor M15 of the input stage circuit 31 that receive the third bias voltage VB3 can respectively generate currents corresponding to or proportional to the current supplied by the current source CS.

[0047] The second transistor M32, and the first transistor M21 and the second transistor M22 of the output stage circuit 32 can each be used as a current mirror. The second transistor M32 can generate a first bias voltage VB1 corresponding to the current drawn by the seventh transistor M37, and the first transistor M21 and the second transistor M22 of the output stage circuit 32 that receive the first bias voltage VB1 can respectively generate currents corresponding to or proportional to the current drawn by the seventh transistor M37.

[0048] The third transistor M33, and the third transistor M23 and the fourth transistor M24 of the output stage circuit 32 can each be used as a current mirror. The third transistor M33 can generate a second bias voltage VB2 corresponding to the current drawn by the eighth transistor M38, and the third transistor M23 and the fourth transistor M24 of the output stage circuit 32 that receive the second bias voltage VB2 can respectively generate currents corresponding to or proportional to the current drawn by the eighth transistor M38.

[0049] The first transistor M31 can have a source connected to the first power supply node to which a positive power supply voltage VDD is applied, a drain connected to the node at which the first bias voltage VB1 is generated, and a gate that receives the inverted power-down signal PDB. The inverted power-down signal PDB can correspond to an inverted version of the power-down signal PD and can be an active-low signal. The inverted power-down signal PDB can be deactivated to have a high level (e.g., VDD) in the normal mode and activated to have a low level (e.g., VSS) in the power-down mode. When the inverted power-down signal PDB is deactivated in the normal mode, the first transistor M31 can be turned off, and the first bias voltage VB1 can have a magnitude corresponding to the current drawn by the seventh transistor M37. In addition, when the inverted power-down signal PDB is activated in the power-down mode, the first transistor M31 can be turned on, the first bias voltage VB1 can substantially correspond to the positive power supply voltage VDD, and the second transistor M32 and the second transistor M21 and the second transistor M22 of the output stage circuit 32 that are to be turned off can not generate current. Here, the first transistor M31 can be referred to as a switching transistor.

[0050] When the voltages of the first node N1 and the second node N2 decrease due to a first bias voltage VB1 corresponding to the positive power supply voltage VDD in the power-off mode, the source-drain voltages of the first transistor M21 and the second transistor M22 of the output stage circuit 32 may exceed the withstand voltage. However, as described above, the voltages of the first node N1 and the second node N2 may be maintained higher than or equal to a first protection voltage VP1 by the first transistor M11 and the second transistor M12 of the input stage circuit 31, and thus, the source-drain voltages of the first transistor M21 and the second transistor M22 can be prevented from exceeding the withstand voltage. The fifth transistor M25 and the sixth transistor M26 receiving the second protection voltage VP2 can also protect the first transistor M21 and the second transistor M22 in the power-off mode.

[0051] Figure 4 is a graph showing protection voltages according to one or more embodiments. For example, Figure 4 The graph of Figure 3 shows the ranges to which the first protection voltage VP1 to the third protection voltage VP3 of Figure 3 belong. Hereinafter, reference will be made to Figure 4 for a description of

[0052] As described above with reference to Figure 3 the amplifier 30 may include a structure for preventing a voltage exceeding the withstand voltage from being applied to the transistors. For example, the input stage circuit 31 may include a first transistor M11 and a second transistor M12 receiving the first protection voltage VP1, the output stage circuit 32 may include a third transistor M23 and a fourth transistor M24 receiving the second protection voltage VP2, and the bias circuit 33 may include a fourth transistor M34 and a fifth transistor M35 receiving the third protection voltage VP3. The amplifier 30 may include a circuit for generating the first protection voltage VP1 to the third protection voltage VP3, or the amplifier 30 may receive the first protection voltage VP1 to the third protection voltage VP3 from the outside.

[0053] The first protection voltage VP1 to the third protection voltage VP3 may each have an appropriate magnitude for protecting the transistors. In some embodiments, the first transistor M21 and the second transistor M22 of the output stage circuit 32 may each have a withstand voltage VDS, and the first protection voltage VP1 for protecting the first transistor M21 and the second transistor M22 may be higher than or equal to a voltage VX, where the voltage VX is reduced from the positive power supply voltage VDD by the withstand voltage VDS. For example, the first protection voltage VP1 may approximately correspond to the voltage VX. In some embodiments, the second protection voltage VP2 may also approximately correspond to the voltage VX.

[0054] Figure 5A and Figure 5Bis a circuit diagram showing examples of current paths 50a and 50b according to some embodiments. For example, Figure 5A and Figure 5B of the circuit diagram shows the current paths included in Figure 3 the amplifier 30 of Figure 3 The amplifier 30 of Figure 3 may include multiple current paths between a first power supply node to which a positive power supply voltage VDD is applied and a second power supply node to which a negative power supply voltage VSS is applied. Hereinafter, reference will be made to Figure 5A and Figure 5B for description.

[0055] Referring to Figure 5A , the current path 50a may include a first transistor M21 of the output stage circuit 52, and a first transistor M11, a third transistor M13, and a fifth transistor M15 of the input stage circuit 51, which are connected in series between the first power supply node and the second power supply node. In the normal mode, the first transistor M21 of the output stage circuit 52 may generate a current based on a first bias voltage VB1, and the generated current may sequentially pass through the first transistor M11, the third transistor M13, and the fifth transistor M15 of the input stage circuit 51.

[0056] The source-drain voltage of each of the first transistor M21 of the output stage circuit 52 and the first transistor M11, the third transistor M13, and the fifth transistor M15 of the input stage circuit 51 (which are connected in series between the first power supply node and the second power supply node) may be limited to a voltage obtained by dividing the difference between the positive power supply voltage VDD and the negative power supply voltage VSS. When the margin of the source-drain voltage of each of the first transistor M21 of the output stage circuit 52 and the first transistor M11, the third transistor M13, and the fifth transistor M15 of the input stage circuit 51 decreases, it may not easily enter the saturation region, and the performance (such as the gain of the amplifier 30) may deteriorate. Therefore, when the number of transistors connected in series in the current path 50a decreases, the margin of the source-drain voltage may increase, and the performance of the amplifier 30 may increase.

[0057] Referring to Figure 5B , the current path 50b may include a first transistor M21, a third transistor M23, a fifth transistor M25, and a seventh transistor M27 of the output stage circuit 52, which are connected in series between the first power supply node and the second power supply node. In the normal mode, the first transistor M21 may generate a current based on a first bias voltage VB1, and the generated current may sequentially pass through the third transistor M23, the fifth transistor M25, and the seventh transistor M27.

[0058] The source-drain voltage of each of the first transistor M21, the third transistor M23, the fifth transistor M25, and the seventh transistor M27 (which are connected in series between the first power supply node and the second power supply node) can be limited to a voltage obtained by dividing the difference between the positive power supply voltage VDD and the negative power supply voltage VSS. As described above with reference to Figure 5A When the margin of the source-drain voltage of each of the first transistor M21, the third transistor M23, the fifth transistor M25, and the seventh transistor M27 decreases, it may not easily enter the saturation region, and the performance of the amplifier 30 may deteriorate. Therefore, when the number of transistors connected in series in the current path 50b decreases, the margin of the source-drain voltage may increase, and the performance of the amplifier 30 may increase.

[0059] As described above with reference to Figure 3 The first transistor M11 of the input stage circuit 51 and the fifth transistor M25 of the output stage circuit 52 can protect the transistors in the power-off mode. Therefore, as described below with reference to the drawings, when the first transistor M11 of the input stage circuit 51 and the fifth transistor M25 of the output stage circuit 52 are omitted from the current paths 50a and 50b, respectively, in the normal mode, each transistor included in the current paths 50a and 50b can have an extended margin of the source-drain voltage.

[0060] Figure 6 is a circuit diagram showing an amplifier 60 according to one or more embodiments. For example, Figure 6 The circuit diagram shows the amplifier 60 as an example of the device 10 of Figure 1 As shown in Figure 6 The amplifier 60 may include an input stage circuit 61, an output stage circuit 62, and a bias circuit 63. Hereinafter, the descriptions redundant with those given above with reference to the drawings will be omitted. Figure 6

[0061] The input stage circuit 61 may receive a first input signal IN1 and a second input signal IN2, and generate complementary signals (e.g., a first amplified signal AMP1 and a second amplified signal AMP2) by amplifying the difference between the first input signal IN1 and the second input signal IN2. As shown in Figure 6 The input stage circuit 61 may include a third transistor M13 to a seventh transistor M17. The third transistor M13 to the fifth transistor M15 may correspond to the third transistor M13 to the fifth transistor M15 included in the input stage circuit 31 of Figure 3

[0062] Compared with Figure 3 the input stage circuit 31 of Figure 3 ​​The first transistor M11 and the second transistor M12 can be from Figure 6 The input stage circuit 61 of Figure 6 is omitted, and the sixth transistor M16 and the seventh transistor M17, which are NFETs, can be added. The sixth transistor M16 can have a source to which a first protection voltage VP1 is applied, a drain connected to the first node N1, and a gate receiving the power-off signal PD. The seventh transistor M17 can have a source to which the first protection voltage VP1 is applied, a drain connected to the second node N2, and a gate receiving the power-off signal PD.

[0063] In the normal mode, the sixth transistor M16 and the seventh transistor M17 can be turned off due to the deactivated (e.g., having a low level) power-off signal PD. Thus, the sixth transistor M16 and the seventh transistor M17 do not affect the operation of the amplifier 60 in the normal mode. In the power-off mode, the sixth transistor M16 and the seventh transistor M17 can be turned on due to the activated (e.g., having a high level) power-off signal PD. Thus, the voltages of the first node N1 and the second node N2 can be higher than or equal to the first protection voltage VP1, and the transistors (e.g., the first transistor M21 and the second transistor M22) of the output stage circuit 62 can be protected. In some embodiments, different from that shown in Figure 6 the sixth transistor M16 and the seventh transistor M17 can be PFETs and can each have a gate receiving the inverted power-off signal PDB.

[0064] The output stage circuit 62 can receive the first amplified signal AMP1 and the second amplified signal AMP2, and can generate complementary signals (e.g., the first output signal OUT1 and the second output signal OUT2) according to the first amplified signal AMP1 and the second amplified signal AMP2. As shown in Figure 6 the output stage circuit 62 can include the first transistor M21 to the eighth transistor M28. The first transistor M21 to the eighth transistor M28 can respectively correspond to the first transistor M21 to the eighth transistor M28 included in Figure 3 the output stage circuit 32 of Figure 3 .

[0065] The bias circuit 63 can generate the first bias voltage VB1 to the third bias voltage VB3. As shown in Figure 6 the bias circuit 63 can include the first transistor M31 to the eighth transistor M38 and the current source CS. The first transistor M31 to the eighth transistor M38 and the current source CS can respectively correspond to the first transistor M31 to the eighth transistor M38 and the current source CS included in Figure 3 the bias circuit 33 of Figure 3 .

[0066] Figure 7 is a circuit diagram showing a current path 70 according to one or more embodiments. For example, Figure 7 shows included inFigure 6 The current path in the amplifier 60. Figure 6 The amplifier 60 may include a plurality of current paths between a first power supply node to which a positive power supply voltage VDD is applied and a second power supply node to which a negative power supply voltage VSS is applied. Hereinafter, reference will be made to Figure 6 for Figure 7 description.

[0067] The current path 70 may include a first transistor M21 of the output stage circuit 72, and a third transistor M13 and a fifth transistor M15 of the input stage circuit 71, which are connected in series between the first power supply node and the second power supply node. In the normal mode, the first transistor M21 of the output stage circuit 72 may generate a current based on a first bias voltage VB1, and the generated current may sequentially pass through the third transistor M13 and the fifth transistor M15 of the input stage circuit 71.

[0068] The source-drain voltage of each of the first transistor M21 of the output stage circuit 72, the third transistor M13, and the fifth transistor M15 of the input stage circuit 71 may be limited to a voltage obtained by dividing the difference between the positive power supply voltage VDD and the negative power supply voltage VSS. Compared with Figure 5A the current path 50a in which four of the transistors are connected between the first power supply node and the second power supply node, Figure 5A the first transistor M11 may be omitted in Figure 7 the current path 70, and each of the first transistor M21 of the output stage circuit 72, the third transistor M13, and the fifth transistor M15 of the input stage circuit 71 may have an enlarged margin of the source-drain voltage.

[0069] Figure 8 is a circuit diagram showing an amplifier 80 according to one or more embodiments. For example, Figure 8 the circuit diagram shows the amplifier 80 as Figure 1 an example of the device 10 of Figure 8 As shown in Figure 8 descriptions redundant with those given above with reference to the drawings will be omitted.

[0070] The input stage circuit 81 may receive a first input signal IN1 and a second input signal IN2, and generate complementary signals (for example, a first amplified signal AMP1 and a second amplified signal AMP2) by amplifying the difference between the first input signal IN1 and the second input signal IN2. As shown in Figure 8 the input stage circuit 81 may include first transistors M11 to fifth transistors M15. The first transistors M11 to M15 may be respectively included inFigure 3 corresponds to the first transistor M11 to the fifth transistor M15 in the input stage circuit 31.

[0071] The output stage circuit 82 can receive the first amplified signal AMP1 and the second amplified signal AMP2, and can generate complementary signals (such as the first output signal OUT1 and the second output signal OUT2) according to the first amplified signal AMP1 and the second amplified signal AMP2. As Figure 8 shown, the output stage circuit 82 can include the first transistor M21 to the fourth transistor M24, and the seventh transistor M27 to the ninth transistor M29. The first transistor M21 to the fourth transistor M24, the seventh transistor M27, and the eighth transistor M28 can be respectively Figure 3 corresponding to the first transistor M21 to the fourth transistor M24, the seventh transistor M27, and the eighth transistor M28 included in the output stage circuit 32 of

[0072] With Figure 3 compared to the output stage circuit 32 of Figure 3 the fifth transistor M25 and the sixth transistor M26 of Figure 8 can be omitted in the output stage circuit 82 of

[0073] In the normal mode, the ninth transistor M29 may be turned off due to a deactivated (e.g., having a low level) power-down signal PD. Thus, the ninth transistor M29 may not affect the operation of the amplifier 80 in the normal mode, and the second bias voltage VB2 generated by the bias circuit 83 may be applied to the gates of the third transistor M23 and the fourth transistor M24. In the power-down mode, the ninth transistor M29 may be turned on due to an activated (e.g., having a high level) power-down signal PD. Further, as will be described below, the bias circuit 83 may block the second bias voltage VB2 by floating the third node N3 that generates the second bias voltage VB2. Thus, through the third transistor M23 and the fourth transistor M24, the voltage of each of the first node N1 and the second node N2 may be higher than or equal to the second protection voltage VP2, and the transistors (e.g., the first transistor M21 and the second transistor M22) of the output stage circuit 82 may be protected. For example, the third transistor M23 and the fourth transistor M24 may contribute to generating the first output signal OUT1 and the second output signal OUT2 according to the second bias voltage VB2 in the normal mode while protecting the transistors from voltages exceeding the withstand voltage in the power-down mode. Herein, the third transistor M23 and the fourth transistor M24 may be referred to as multifunctional transistors. In some embodiments, different from Figure 8 that shown in Figure 3 , the ninth transistor M29 may be a PFET and may have a gate receiving an inverted power-down signal PDB. Compared with the output stage circuit 32 of

[0074] , the output stage circuit 82 may include a reduced number of transistors. Figure 8 As shown in Figure 3 , the bias circuit 83 may include a first transistor M31 to a ninth transistor M39 and a current source CS. The first transistor M31 to the eighth transistor M38 and the current source CS may respectively correspond to the first transistor M31 to the eighth transistor M38 and the current source CS included in the bias circuit 33 of

[0075] Compared with the bias circuit 33 of Figure 3 , the ninth transistor M39 may be in Figure 8is added in the bias circuit 83. The ninth transistor M39 may have a source to which a positive power supply voltage VDD is applied, a drain connected to the drain of the third transistor M33, and a gate receiving a power-off signal PD. In the normal mode, the ninth transistor M39 may be turned on due to the deactivated (e.g., having a low level) power-off signal PD. Thus, the current drawn by the eighth transistor M38 may pass through the ninth transistor M39, and the third transistor M33 may generate a second bias voltage VB2 corresponding to the current drawn by the ninth transistor M39. In the power-off mode, the ninth transistor M39 may be turned off due to the activated (e.g., having a high level) power-off signal PD. Thus, the current drawn by the eighth transistor M38 may be blocked, and the node (e.g., the third node N3) generating the second bias voltage VB2 may be floating. Thus, the third node N3 may have a second protection voltage VP2 via the ninth transistor M29 that is turned on in the power-off mode of the output stage circuit 82. For example, in the power-off mode, the second bias voltage VB2 may be substantially equal to the second protection voltage VP2. Herein, the ninth transistor M39 may be referred to as a switching transistor.

[0076] Figure 9 is a circuit diagram showing a current path 90 according to one or more embodiments. For example, Figure 9 shows a current path included in Figure 8 the amplifier 80 of Figure 8 The amplifier 80 of Figure 8 may include a plurality of current paths between a first power supply node to which a positive power supply voltage VDD is applied and a second power supply node to which a negative power supply voltage VSS is applied. Hereinafter, reference will be made to Figure 9 for a description of

[0077] The current path 90 may include a first transistor M21, a third transistor M23, and a seventh transistor M27 of the output stage circuit 92, which are connected in series between the first power supply node and the second power supply node. In the normal mode, the first transistor M21 may generate a current based on a first bias voltage VB1, and the generated current may sequentially pass through the third transistor M23 and the seventh transistor M27.

[0078] The source-drain voltage of each of the first transistor M21, the third transistor M23, and the seventh transistor M27 may be limited to a voltage obtained by dividing the difference between the positive power supply voltage VDD and the negative power supply voltage VSS. Compared with Figure 5B the current path 50b in which four of the transistors are connected to each other between the first power supply node and the second power supply node of Figure 5B the fifth transistor M25 of Figure 9is omitted in the current path 90, and each of the first transistor M21, the third transistor M23, and the seventh transistor M27 may have an enlarged margin of source-drain voltage.

[0079] Figure 10 is a circuit diagram showing an amplifier 100 according to one or more embodiments. For example, Figure 10 the circuit diagram shows the amplifier 100 as Figure 1 an example of the device 10. As Figure 10 shown, the amplifier 100 may include an input stage circuit 101, an output stage circuit 102, and a bias circuit 103. Hereinafter, the Figure 10 description redundant to the above description given with reference to the drawings will be omitted.

[0080] The input stage circuit 101 may receive a first input signal IN1 and a second input signal IN2, and generate complementary signals (e.g., a first amplified signal AMP1 and a second amplified signal AMP2) by amplifying the difference between the first input signal IN1 and the second input signal IN2. As Figure 10 shown, the input stage circuit 101 may include a third transistor M13 to a seventh transistor M17. The third transistor M13 to the seventh transistor M17 may respectively correspond to the third transistor M13 to the seventh transistor M17 included in Figure 6 the input stage circuit 61.

[0081] The output stage circuit 102 may receive the first amplified signal AMP1 and the second amplified signal AMP2, and generate complementary signals (e.g., a first output signal OUT1 and a second output signal OUT2) according to the first amplified signal AMP1 and the second amplified signal AMP2. As Figure 10 shown, the output stage circuit 102 may include a first transistor M21 to a fourth transistor M24 and a seventh transistor M27 to a ninth transistor M29. The first transistor M21 to the fourth transistor M24 and the seventh transistor M27 to the ninth transistor M29 may respectively correspond to Figure 8 the first transistor M21 to the fourth transistor M24 and the seventh transistor M27 to the ninth transistor M29 of the output stage circuit 82.

[0082] The bias circuit 103 may generate a first bias voltage VB1 to a third bias voltage VB3. As Figure 10 shown, the bias circuit 103 may include a first transistor M31 to a ninth transistor M39 and a current source CS. The first transistor M31 to the ninth transistor M39 and the current source CS may respectively correspond to the first transistor M31 to the ninth transistor M39 and the current source CS included in Figure 8 the bias circuit 83.

[0083] Figure 11 is a timing diagram showing the operation of the apparatus according to one or more embodiments. For example, Figure 11 The timing diagram of Figure 10 shows the states of the power-down signal PD, the inverted power-down signal PDB, the first transistor M31 and the ninth transistor M39 of the bias circuit 103, the sixth transistor M16 and the seventh transistor M17 of the input stage circuit 101, and the ninth transistor M29 of the output stage circuit 102 in the amplifier 100 according to the operation mode. Hereinafter, reference will be made to Figure 10 for Figure 11 to be described.

[0084] Referring to Figure 11 , in the normal mode, the power-down signal PD can be deactivated and can have a low level as an active-high signal. Since the power-down signal PD has a low level, the sixth transistor M16 and the seventh transistor M17 of the input stage circuit 101 can be turned off, and thus, the first protection voltage VP1 can be prevented from being applied to the first node N1 and the second node N2. In addition, since the power-down signal PD has a low level, the ninth transistor M29 of the output stage circuit 102 can be turned off, and thus, the second protection voltage VP2 can be prevented from being applied to the third node N3. In addition, since the power-down signal PD has a low level, the ninth transistor M39 of the bias circuit 83 can be turned on, and thus, the ninth transistor M39 can provide the current drawn by the eighth transistor M38.

[0085] The amplifier 100 can be set to the normal mode before time t11. In the normal mode, the inverted power-down signal PDB can be deactivated and can have a high level as an active-low signal. Since the inverted power-down signal PDB has a high level, the first transistor M31 of the bias circuit 103 can be turned off, and thus, the positive power supply voltage VDD can be prevented from being applied to the node generating the first bias voltage VB1.

[0086] The amplifier 100 can be set to a power-off mode after time t11. In the power-off mode, the power-off signal PD can be activated and can have a high level as an active-high signal. Since the power-off signal PD has a high level, the sixth transistor M16 and the seventh transistor M17 of the input stage circuit 101 can be turned on. Accordingly, the first node N1 and the second node N2 can each have a voltage that is higher than or equal to the first protection voltage VP1. In addition, since the power-off signal PD has a high level, the ninth transistor M29 of the output stage circuit 102 can be turned on, and accordingly, the second protection voltage VP2 can be applied to the third node N3, and through the third transistor M23 and the fourth transistor M24, the first node N1 and the second node N2 can have a voltage that is higher than or equal to the second protection voltage VP2. In addition, since the power-off signal PD has a high level, the ninth transistor M39 of the bias circuit 103 can be turned off, and accordingly, the current passing through the third transistor M33 can be blocked, and the second bias voltage VB2 can be blocked.

[0087] In the power-off mode, the inverted power-off signal PDB can be activated and can have a low level as an active-low signal. Since the inverted power-off signal PDB has a low level, the first transistor M31 of the bias circuit 103 can be turned on, and accordingly, the first bias voltage VB1 can be substantially equal to the positive power supply voltage VDD. Since the first bias voltage VB1 is substantially equal to the positive power supply voltage VDD, the second transistor M32 of the bias circuit 103, and the first transistor M21 and the second transistor M22 of the output stage circuit 102 can be turned off, and the current flowing out from the first power supply node can be blocked.

[0088] Figure 12 is a block diagram showing a system-on-chip (SoC) 120 according to one or more embodiments. The SoC 120 (which is a semiconductor device) can include devices according to one or more embodiments. The SoC 120 can include transistors that are implemented as complex blocks (such as intellectual property (IP) that performs various functions) in a single chip. Referring to Figure 12 , the SoC 120 can include a modem 122, a display controller 123, a memory 124, an external memory controller 125, a central processing unit (CPU) 126, a transaction unit 127, a power management integrated circuit (PMIC) 128, and a graphics processing unit (GPU) 129, which can communicate with each other through a system bus 121.

[0089] The CPU 126, which is capable of controlling the operations of the SoC 120 at the highest level, can control the operations of the modem 122, the display controller 123, the memory 124, the external memory controller 125, the CPU 126, the transaction unit 127, the PMIC 128, and the GPU 129. The modem 122 can demodulate signals received from outside the SoC 120, or modulate signals generated inside the SoC 120 and send the signals to the outside. The external memory controller 125 can control the operations of sending data to and receiving data from an external memory device connected to the SoC 120. For example, programs and / or data stored in the external memory device can be provided to the CPU 126 or the GPU 129 under the control of the external memory controller 125.

[0090] The GPU 129 can execute program instructions related to graphics processing. The GPU 129 can receive graphic data through the external memory controller 125, or can send the graphic data processed by the GPU 129 to the outside of the SoC 120 through the external memory controller 125. The transaction unit 127 can monitor data transactions of each of the modem 122, the display controller 123, the memory 124, the external memory controller 125, the CPU 126, the transaction unit 127, the PMIC 128, and the GPU 129, and the PMIC 128 can control the power supplied to each of the modem 122, the display controller 123, the memory 124, the external memory controller 125, the CPU 126, the transaction unit 127, the PMIC 128, and the GPU 129 under the control of the transaction unit 127. The display controller 123 can send the data generated inside the SoC 120 to the display through controlling a display (or display device) outside the SoC 120. The memory 124 can include non-volatile memory (such as electrically erasable programmable read-only memory (EPROM), flash memory, etc.), or can include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.).

[0091] At least one of the components included in the SoC 120 can include a structure for protecting transistors from voltages exceeding a tolerance voltage. For example, at least one of the components included in the SoC 120 can include an analog circuit that processes analog signals, and the analog circuit can include transistors and a structure for protecting the transistors. The structure for protecting the transistors can not affect the operation of the analog circuit in the normal mode, and can prevent voltages exceeding the tolerance voltage from being applied to the transistors in the power-off mode. Therefore, the transistors operating in the normal mode can not only be protected from voltages exceeding the tolerance voltage, but also have an expanded voltage margin, and thus, the performance of the analog circuit can be increased.

[0092] Although the disclosure has been specifically shown and described with reference to the disclosed embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An electronic device, comprising: a plurality of first transistors included in a first current path between a first power supply node and a second power supply node in a normal mode, a positive power supply voltage configured to be applied to the first power supply node, and a negative power supply voltage configured to be applied to the second power supply node; as well as a first protection transistor connected to a first node, two first transistors of the plurality of first transistors connected to the first node, The first protection transistor is configured to be turned off in the normal mode and turned on in the power-off mode to provide the protection voltage to the first node.

2. The electronic device according to claim 1, wherein: The two first transistors of the plurality of first transistors include: a P-channel field effect transistor having a source connected to a first power supply node, a drain connected to a first node, and a gate receiving a bias voltage.

3. The electronic device as claimed in claim 2, wherein: The protection voltage is higher than or equal to a voltage reduced from the positive power supply voltage by a withstand voltage of the P-channel field effect transistor.

4. The electronic device as claimed in claim 2, wherein: The two first transistors of the plurality of first transistors include: N-channel field effect transistors having drains connected to a first node.

5. The electronic device as claimed in claim 2, further comprising: A switching transistor is configured to provide a positive supply voltage to a gate of the P-channel field effect transistor in a power-off mode.

6. The electronic device as claimed in claim 1, wherein: The first protection transistor includes an N-channel field effect transistor having a drain connected to the first node, a source to which a protection voltage is configured to be applied, and a gate configured to receive a control signal activated in a power-off mode.

7. The electronic device as claimed in claim 1, further comprising: a plurality of second transistors included in a second current path between the first power supply node and the second power supply node in a normal mode; as well as a second protection transistor connected to the second node, two second transistors of the plurality of second transistors connected to the second node, The second protection transistor is configured to be turned off in the normal mode and turned on in the power-off mode to provide the protection voltage to the second node.

8. The electronic device as claimed in claim 7, wherein: The first node and the second node are configured to respectively generate complementary signals in a normal mode.

9. An electronic device comprising: a plurality of first transistors included in a first current path between a first power supply node and a second power supply node in a normal mode, a positive power supply voltage configured to be applied to the first power supply node, and a negative power supply voltage configured to be applied to the second power supply node; as well as a protection transistor connected to a gate of a first multi-function transistor among the plurality of first transistors, The protection transistor is configured to be turned off in the normal mode and turned on in the power-off mode to provide the protection voltage to the gate of the first multi-function transistor.

10. The electronic device according to claim 9, wherein: The plurality of first transistors include a P-channel field effect transistor having a source connected to a first power supply node, a drain connected to the first multi-function transistor, and a gate configured to receive a first bias voltage.

11. The electronic device according to claim 10, wherein: The protection voltage is higher than or equal to a voltage reduced from the positive power supply voltage by a withstand voltage of the P-channel field effect transistor.

12. The electronic device as claimed in claim 10, further comprising: The first switch transistor is configured to provide a positive power supply voltage to a gate of the P-channel field effect transistor in a power-off mode.

13. The electronic device according to claim 10, wherein: The plurality of first transistors include an N-channel field effect transistor having a source connected to the second power supply node and a drain connected to the P-channel field effect transistor.

14. The electronic device according to claim 9, wherein: The gate of the first multi-function transistor is configured to receive a second bias voltage in a normal mode.

15. The electronic device as claimed in claim 14, further comprising: a bias transistor configured to generate a second bias voltage; as well as The second switch transistor is configured to be turned on in a normal mode to provide the positive power supply voltage to the bias transistor, and to be turned off in a power-off mode to block the positive power supply voltage from the bias transistor.

16. The electronic device as claimed in claim 9, wherein: The protection transistor is an N-channel field effect transistor having a drain connected to the gate of the first multi-function transistor, a source to which a protection voltage is configured to be applied, and a gate configured to receive a control signal activated in a power-off mode.

17. The electronic device as claimed in claim 9, further comprising: a plurality of second transistors included in a second current path between the first power supply node and the second power supply node in a normal mode, wherein the protection transistor is connected to the gate of the second multifunctional transistor among the plurality of second transistors, The protection transistor is configured to be turned off in the normal mode and turned on in the power-off mode to provide the protection voltage to the gate of the second multi-function transistor.

18. The electronic device as claimed in claim 17, wherein: The drain of the first multi-function transistor and the drain of the second multi-function transistor are configured to respectively generate complementary signals in a normal mode.

19. An electronic device comprising: an input stage circuit configured to generate a complementary amplified signal from a complementary input signal in a normal mode; an output stage circuit configured to generate a complementary output signal according to the complementary amplified signal in a normal mode; as well as a bias circuit configured to provide at least one bias voltage to each of the input stage circuit and the output stage circuit in a normal mode; The input stage circuit includes: a first protection transistor and a second protection transistor, connected to a first node and a second node respectively, and complementary amplification signals are generated at the first node and the second node respectively. The first protection transistor and the second protection transistor are configured to be turned off in the normal mode and turned on in the power-off mode to provide the first protection voltage to the first node and the second node respectively.

20. The electronic device as claimed in claim 19, wherein: The at least one bias voltage includes a first bias voltage, and The output stage circuit includes: a first P-channel field effect transistor and a second P-channel field effect transistor, each having a gate configured to receive a first bias voltage, the first P-channel field effect transistor and the second P-channel field effect transistor are configured to provide current from a first power supply node to a first node and a second node, respectively, and a positive power supply voltage is configured to be applied to the first power supply node.

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