Dual-mode analog front end with full-speed clock-free decision feedback equalizer

Abstract

The invention discloses a dual-mode analog front end with a full-speed clock-free decision feedback equalizer (UC-DFE). The dual-mode analog front end comprises a terminating impedance matching network, a linear processing link, the UC-DFE and a signal output module, the terminating impedance matching network realizes broadband impedance matching and electrostatic protection; the linear processing link comprises a CTLE and a VGA and is used for compensating channel attenuation and expanding signal bandwidth; the UC-DFE comprises a summator, a static comparator, a delay unit and a feedback tap, and realizes high-speed signal processing and feedback equalization; and the signal output module converts the balanced signal into a target coding format and outputs the signal. According to the invention, the overall performance of the circuit is improved, the problems of time sequence tension, bandwidth limitation and the like of the traditional DFE architecture at a high speed are solved, and the circuit is suitable for 128Gbps high-speed PAM4 and NRZ signal transmission and shows better comprehensive performance.

Description

Technical Field

[0001] The present invention relates to the technical fields of integrated circuit design and data transmission, and particularly to a dual-mode analog front end with a full-speed clockless decision feedback equalizer (UC-DFE). Background Art

[0002] When a high-speed serial interface performs data transmission, the attenuation existing in the channel will cause the attenuation of high-frequency components to be greater than that of low-frequency components, affecting signal integrity, resulting in the closing of the eye diagram and ultimately affecting the bit error rate. To achieve error-free transmission, an equalization circuit needs to be added to the high-speed serial interface transceiver to compensate for the channel attenuation, such as a transmitter feed-forward equalizer (FFE), a receiver CTLE, and a DFE. Among them, to implement the DFE, the first tap timing needs to be satisfied, that is, the total delay from signal sampling decision to the last tap generating current and feeding back to the summer for summation should be less than 1 unit interval (UI) of the highest data rate. As the data rate increases, the first tap timing becomes increasingly tight. In addition, for PAM4 signals, the number of comparators and taps both increase by three times, posing challenges to the DFE bandwidth and power consumption.

[0003] To solve this problem, various improvement methods for the DFE have emerged, such as half-speed, quarter-speed architectures, speculative DFE, soft decision DFE, etc. However, for 32G Nyquist frequency signals, one UI is approximately 15 ps, and the CLK-Q delay brought by circuits such as dynamic comparators, digital selectors, and D flip-flops can no longer meet the requirements of this data rate.

[0004] It should be noted that the information disclosed in the above background art section is only used for understanding the background of the present application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The main objective of the present invention is to overcome the defects existing in the above background art, and provide a dual-mode analog front end with a full-speed clockless decision feedback equalizer.

[0006] To achieve the above objective, the present invention adopts the following technical solutions:

[0007] A dual-mode analog front end with a full-speed clockless decision feedback equalizer, comprising:

[0008] A termination impedance matching network configured to perform broadband impedance matching and electrostatic protection on the input signal;

[0009] A linear processing link, connected to the output end of the termination impedance matching network, includes a continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA) cascaded in sequence, and is used to compensate for channel attenuation and expand the signal bandwidth;

[0010] A full-speed clockless decision feedback equalizer (UC-DFE), connected to the output end of the linear processing link, includes: a summer, configured to superimpose the output signal of the linear processing link and the feedback tap signal; a static comparator, connected to the output end of the summer, configured to perform high-speed level decision on the superimposed signal; a delay unit, connected to the output end of the static comparator, and used to generate a delayed decision feedback signal; feedback taps, including discrete-time (DT) taps and infinite impulse response (IIR) taps, respectively injecting the output signal of the delay unit into the summer, where the DT tap provides an immediate feedback signal, and the IIR tap generates a long-term feedback signal through resistor-capacitor degeneration;

[0011] A signal output module, connected to the output end of the UC-DFE, is configured to convert the equalized signal into a target coding format and output it.

[0012] The present invention has the following beneficial effects:

[0013] Through the innovative design of the full-speed clockless decision feedback equalizer (UC-DFE) architecture, the present invention solves the performance bottleneck problem of traditional decision feedback equalizers caused by tight timing at high data rates. Specifically, it uses a clockless analog comparator and a delay unit to directly process signals, avoiding the clock synchronization delay of dynamic comparators and digital logic, thereby achieving efficient equalization under 128Gbps PAM4 and 64Gbps NRZ dual-mode coding. Further, by replacing the traditional design with a complementary current mode logic (CML) structure, the power supply rejection ratio, noise performance of the analog front end, and the common-mode stability of the multi-stage cascaded circuit are significantly improved, and the signal amplitude is enlarged in combination with the swing enhancement technology to improve the signal-to-noise ratio. The delay unit inserts two-stage non-inductive peaking structures in the second tap (IIR tap) chain to isolate the first tap (DT tap) signal from the RC degeneration circuit, ensuring the reliability of the feedback timing. In addition, the termination impedance matching network uses a T-type coil and an adjustable resistor array to optimize the broadband impedance matching. Combined with the source degeneration adjustment and frequency band expansion technology of the CTLE and VGA, the system can still recover an eye diagram quality significantly better than the reference design under 24dB channel attenuation (such as an eye height of 86mV and an eye width of 7.48ps at 128Gbps PAM4). The comprehensive performance achieves a double breakthrough in data rate and equalization ability under non-advanced process conditions, providing a highly reliable solution for high-speed serial interfaces to cope with complex channel environments.

[0014] Other beneficial effects in the embodiments of the present invention will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is the overall structural block diagram of the analog front-end receiver (RX) in the embodiments of the present invention.

[0016] Figure 2 is the structural block diagram of UC-DFE in the embodiments of the present invention.

[0017] Figure 3 is the circuit diagram of termination matching and linear link (CTLE, VGA) in the embodiments of the present invention.

[0018] Figure 4 is the circuit diagram of the summer and Tap in the embodiments of the present invention.

[0019] Figure 5 is the core layout and module schematic of the test chip in the embodiments of the present invention.

[0020] Figure 6 is the pre-simulation result of 64Gbps NRZ with 24dB channel attenuation in the embodiments of the present invention.

[0021] Figure 7 is the post-simulation result of 64Gbps NRZ with 24dB channel attenuation in the embodiments of the present invention.

[0022] Figure 8 is the pre-simulation result of 128Gbps PAM-4 with 24dB channel attenuation in the embodiments of the present invention.

[0023] Figure 9 is the post-simulation result of 128Gbps PAM-4 with 24dB channel attenuation in the embodiments of the present invention.

[0024] Figure 10 is the comparison of the performance of the embodiments of the present invention with the reference work. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following provides a detailed description of the embodiments of the present invention. It should be emphasized that the following description is merely exemplary and not intended to limit the scope of the present invention and its applications.

[0026] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, the connection can be for fixing or for coupling or communicating.

[0027] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0028] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0029] Referring to Figures 1 to 5 , an embodiment of the present invention provides a dual-mode analog front end with a full-speed clockless decision feedback equalizer (UC-DFE), including: a termination impedance matching network, a linear processing link, a full-speed clockless decision feedback equalizer, and a signal output module.

[0030] The termination impedance matching network is configured to perform broadband impedance matching and electrostatic protection on the input signal. The linear processing link is connected to the output end of the termination impedance matching network and includes a cascaded continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA) in sequence, which are used to compensate for channel attenuation and expand the signal bandwidth.

[0031] The full-speed clockless decision feedback equalizer (UC-DFE), connected to the output end of the linear processing link, includes a summer, a static comparator, a delay unit, and feedback taps. The summer is used to superimpose the output signal of the linear processing link and the feedback tap signal. The static comparator is connected to the output end of the summer and is configured to perform high-speed level decision on the superimposed signal. The delay unit is connected to the output end of the static comparator and is used to generate a delayed decision feedback signal. The feedback taps include discrete-time (DT) taps and infinite impulse response (IIR) taps, which respectively inject the output signal of the delay unit into the summer, where the DT taps provide an immediate feedback signal and the IIR taps generate a long-term feedback signal through resistor-capacitor degeneration.

[0032] The signal output module is connected to the output end of the UC-DFE and is configured to convert the equalized signal into a target coding format and output it.

[0033] Compared with the prior art, the dual-mode analog front-end with a full-speed clockless decision feedback equalizer proposed by the present invention can alleviate the problem of tight timing of the first loop of the traditional DFE at a high data rate of 128 Gbps, and the circuit bandwidth and equalization performance meet the requirements of high-speed serial interfaces at high data rates of PAM-4 and NRZ.

[0034] In a preferred embodiment, the termination impedance matching network includes: a T-shaped coil connected to the receiver input for splitting the pad (PAD) capacitance and the ESD capacitance to achieve broadband impedance matching; an adjustable resistor array connected in parallel with the T-shaped coil for dynamically adjusting the input impedance to adapt to the channel characteristics.

[0035] In a preferred embodiment, the continuous-time linear equalizer (CTLE) adopts a complementary current-mode logic (CML) source degeneration structure, controls the equalization ability by adjusting the source degeneration resistor-capacitor array, and uses an inductor to broaden the frequency band.

[0036] In a preferred embodiment, the variable gain amplifier (VGA) shunts a capacitor across the source degeneration resistor to generate additional zeros, and uses a negative coupling coefficient T-shaped coil to improve the load driving ability and bandwidth.

[0037] In a preferred embodiment, the delay unit includes: a delay unit with inductive peaking connected between the output of the static comparator and the discrete-time (DT) tap for providing gain compensation and basic delay; a delay unit without inductive peaking connected in series between the output of the DT tap and the input of the infinite impulse response (IIR) tap for isolating the DT tap feedback signal from the RC degeneration circuit of the IIR tap.

[0038] In a preferred embodiment, the infinite impulse response (IIR) tap generates a long-term feedback signal through an RC degeneration circuit to replace the equalization function of the traditional multi-tap decision feedback equalizer.

[0039] In a preferred embodiment, the summing unit includes: a complementary CML structure directly coupled to the output stage of the linear processing link (CTLE / VGA) for superimposing signals and maintaining common-mode stability; a negative coupling coefficient T-shaped coil connected across the differential output of the summing unit for expanding the frequency band and suppressing high-frequency signal attenuation.

[0040] In a preferred embodiment, the signal output module includes: a quarter-speed sampling circuit connected to the output of the UC-DFE for sampling the equalized PAM4 or NRZ signal at a quarter of the data rate; an encoding conversion circuit connected to the output of the sampling circuit for converting the PAM4 or NRZ encoding into binary parallel data and outputting it to a demultiplexer (DEMUX).

[0041] In a preferred embodiment, the analog front end as a whole adopts swing enhancement technology to improve the signal amplitude and signal-to-noise ratio through a complementary CML structure.

[0042] The specific embodiments of the present invention are further described below.

[0043] A dual-mode analog front end (AFE) with a full-speed clockless decision feedback equalizer (Unclocked Decision Feedback Equalization, UC-DFE). By canceling the DFE clock, this circuit uses circuits such as analog comparators and analog delay units, and cooperates with on-chip passive inductive spread spectrum to alleviate the timing problem of the first tap of the DFE, enabling it to work at high data rates with 4-Level Pulse Amplitude Modulation (PAM4) and Non Return Zero (NRZ) encoding. The DFE includes a Discrete-time (DT) tap and an Infinite Impulse Response (IIR) tap, enhancing the equalization ability of the DFE. Based on the existing analog front end with UC-DFE, the present invention improves the structures of the continuous-time linear equalizer (CTLE), variable gain amplifier (VGA), summer (SUM), analog comparator, delay unit, etc., improving the overall performance of the circuit. The specific improvements are as follows: The analog front end as a whole adopts a complementary current mode logic (CML) structure to replace the traditional CML, improving the power supply rejection ratio and noise performance of the analog front end, and improving the common-mode stability under the series connection of multi-stage analog circuits. In addition, the analog front end adopts swing enhancement technology, increasing the signal amplitude and the signal-to-noise ratio compared with the traditional structure. The performance of UC-DFE is mainly restricted by the static comparator, and the bandwidth and gain of the comparator directly determine the correctness and quality of the feedback signal. Finally, the present invention improves the UC-DFE architecture by inserting two stages of inductorless peaking delay units on the second tap delay chain to isolate the first tap signal from the second tap resistor-capacitor (RC) degradation unit, improving the performance of the first tap.

[0044] A 128 Gbps dual-mode analog front end with a full-speed clockless decision feedback equalizer, including the receiver structure block diagram of the analog front end as shown in Figure 2 The circuit consists of: (1) a termination impedance matching network, (2) a CTLE, (3) a VGA, and (4) a 2-Tap UC-DFE circuit. The termination impedance matching network includes electrostatic protection (ESD), a T-coil, an adjustable resistor array, etc., performing broadband impedance matching on the channel and providing electrostatic protection for the internal circuit at the same time.

[0045] 1. High - bandwidth receiver termination and linear chain:

[0046] This circuit consists of a termination impedance matching network, CTLE, and VGA. For PAM - 4 signals with a Nyquist frequency reaching 32 GHz, the present invention uses dual - port inductors and T - coils to ensure that the termination impedance matching network has broadband impedance matching, and extends the peaking frequency of CTLE and the bandwidth of VGA beyond 32G Nyquist frequency. In addition, both CTLE and VGA adopt complementary CML structures, enhancing the noise performance, power supply rejection ratio, and common - mode stability of the analog front - end.

[0047] 2. Clockless UC - DFE:

[0048] UC - DFE is composed of a summer, a static comparator, two types of delay units, and two types of feedback taps. The summer uses a T - coil for frequency expansion to ensure that the summing signal is fully established. The output signal of the static comparator is sent to the delay unit for delay, generating DT tap and IIR tap feedback signals, which are then summed through the summer.

[0049] Figure 1 This is the overall structural block diagram of the analog front - end receiver (RX). After the high - speed serial signal enters the receiver from the channel, it undergoes broadband impedance matching through the termination impedance matching network. Subsequently, the signal is equalized and amplified by CTLE and VGA, and then restored to a relatively ideal NRZ or PAM - 4 signal through UC - DFE. It is converted into binary signals through a quarter - speed architecture sampling circuit and a coding conversion circuit, and finally enters circuits such as a deserialiser (DEMUX) according to the input signal coding method to restore 64 - way parallel data, completing the data reception and deserialization functions.

[0050] Figure 2 This is the structural block diagram of UC - DFE. After the summer sums the currents of the CTLE, DT tap 1, and IIR tap 2 signals, the output is sent to three static comparators to compare the three thresholds (DH, DZ, DL) of the PAM - 4 signal. The output comparison results provide a certain gain and delay through a delay unit with inductive peaking, generating a DT tap signal that is fed back to DT tap 1. The delay unit without inductive peaking takes the DT tap signal as input, isolates the DT tap signal from the RC degradation circuit, ensures the quality of the DT tap signal while providing the basic second - tap delay, and generates the IIR tap 2 signal after RC degradation. Based on the non - clock control and always - on of the UC - DFE taps, UC - DFE can simultaneously have an FIR filter and an IIR filter. The IIR filter can significantly improve the DFE equalization ability and can replace multiple taps of traditional DFE.

[0051] Figure 3It is a circuit diagram for termination matching and linear link (CTLE, VGA). The termination impedance matching network uses a T-shaped coil and a dual-port inductive split pad (PAD) capacitor, ESD capacitor, and RX input capacitor. While providing ESD protection, it performs broadband impedance matching and common-mode setting on the input signal to ensure the quality of the received signal. Both CTLE and VGA adopt a complementary CML source degeneration structure. This structure is similar to the resonant cavity CTLE, but the resonant cavity CTLE controls the equalization ability by controlling the quality factor Q of the resonant inductor. In this invention, the gain is adjusted by regulating the source degeneration resistor-capacitor array, and the CTLE inductor plays a role in broadening the frequency band. In this invention, CTLE has an equalization ability of 14 dB and a gain of +7 dB at the 32G Nyquist frequency. The VGA structure is similar to that of CTLE. In this invention, an additional capacitor is connected in parallel to the VGA source degeneration resistor to generate additional zeros to broaden the VGA bandwidth, and the load-bearing ability and bandwidth of the VGA are improved by a negative coupling coefficient T-coil. In this invention, the VGA can provide a gain from -2 dB to +2 dB.

[0052] Figure 4 It is a circuit diagram for a summator and Tap. The summator structure is similar to that of the VGA. The introduction of the complementary CML structure can ensure the common-mode stability under the series connection of multiple-stage analog circuits and improve the circuit noise performance and current efficiency. The summator uses a negative coupling coefficient T-coil for frequency band expansion. The summator in this invention can maintain a gain of 5 dB up to 90 GHz, a 3 dB bandwidth of 110 GHz, and an in-band gain fluctuation <1 dB. The bandwidth far greater than the Nyquist frequency ensures that the summator has sufficient establishment accuracy, thereby reducing the summation error. The DT tap determines the direction of the current injected into the summator according to the high and low levels of the feedback signal, and its bias current determines the tap coefficient. The output current of the IIR tap changes linearly with the input signal, and the introduction of the source degeneration resistor ensures that the tap has sufficient linearity.

[0053] Figure 5 It is a schematic diagram of the core layout and modules of the test chip, including ESD, termination impedance matching network, CTLE, VGA, summator, static comparator, delay unit and tap, test clock path, and digital part. Figure 6 、 7 Figures 8 and 9 are respectively the pre- and post-simulation results of 64Gbps NRZ with a 24 dB channel attenuation and the pre- and post-simulation results of 128Gbps PAM-4 with a 24 dB channel attenuation. The peak-to-peak value of the RX input signal is 600 mV, and the code pattern is PRBS15. Among them, the post-simulation UC-DFE eye height of 64Gbps NRZ is 382 mV, and the eye width is 14.40 ps (0.92UI); the post-simulation UC-DFE eye height of 128Gbps PAM-4 is 86 mV, and the eye width is 7.48 ps (0.48UI).

[0054] Figure 10 For comparison with the reference working performance, the reference work is the TSMC 7nm process, and the circuit performance is also obtained from post-layout simulation. When the process lags behind the reference work, the data rate of the present invention is increased to 64 / 128 Gbps. Under the PAM-4 and NRZ line codes, the maximum channel insertion loss reaches 24 dB / 30 dB. Finally, the eye height and eye width of the recovered eye diagram by the AFE are significantly better than those of the reference work under both line codes, demonstrating good comprehensive performance.

[0055] The above content is a further detailed description of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several alternatives or modifications can be made to these described embodiments, and these alternative or modified forms should be regarded as belonging to the protection scope of the present invention. In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "preferred embodiment", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the scope of protection of the patent application.

Claims

1. A dual-mode analog front end with a full-speed clockless decision feedback equalizer, characterized in that: include: A terminating impedance matching network configured to perform broadband impedance matching and electrostatic protection on an input signal; A linear processing link, connected to the output end of the termination impedance matching network, comprising a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA) cascaded in sequence, for compensating for channel attenuation and extending signal bandwidth; A full-rate clockless decision feedback equalizer (UC-DFE), connected to the output of the linear processing chain, includes: a summer, configured to superimpose the output signal of the linear processing link with the feedback tap signal; a static comparator connected to the output end of the summer and configured to perform high-speed level determination on the superimposed signal; A delay unit, connected to the output end of the static comparator, for generating a delayed decision feedback signal; A feedback tap, including a discrete time (DT) tap and an infinite impulse response (IIR) tap, respectively injecting the output signal of the delay unit into the summer, wherein the DT tap provides an immediate feedback signal, and the IIR tap generates a long-term feedback signal through resistance and capacitance degradation; The signal output module is connected to the output end of the UC-DFE and is configured to convert the equalized signal into a target coding format and output it.

2. The dual-mode analog front end according to claim 1, characterized in that: The termination impedance matching network comprises: A T-coil connected to the receiver input is used to separate the pad (PAD) capacitance and the ESD capacitance to achieve broadband impedance matching; The adjustable resistor array is connected in parallel with the T-coil and is used to dynamically adjust the input impedance to adapt the channel characteristics.

3. The dual-mode analog front end according to claim 1, characterized in that: The continuous time linear equalizer (CTLE) adopts a complementary current mode logic (CML) source degeneration structure, controls the equalization capability by adjusting the source degeneration resistor and capacitor array, and uses inductance to widen the frequency band.

4. The dual-mode analog front end according to claim 1, characterized in that: The variable gain amplifier (VGA) connects a capacitor in parallel to a source degeneration resistor to generate an additional zero point, and adopts a negative coupling coefficient T-coil to improve load capacity and bandwidth.

5. The dual-mode analog front end according to claim 1, characterized in that: The delay unit comprises: A delay unit with inductive peaking, connected between the static comparator output and the discrete time (DT) tap, for providing gain compensation and basic delay; The delay unit without inductor peaking is connected in series between the DT tap output and the infinite impulse response (IIR) tap input, and is used to isolate the DT tap feedback signal from the RC degeneration circuit of the IIR tap.

6. The dual-mode analog front end according to claim 1, characterized in that: The infinite impulse response (IIR) tap generates a long-term feedback signal through an RC degeneration circuit, replacing the equalization function of a traditional multi-tap decision feedback equalizer.

7. The dual-mode analog front end according to claim 1, characterized in that: The summer comprises: A complementary CML structure directly coupled to the output stage of the linear processing chain (CTLE / VGA) for superimposing signals and maintaining common mode stability; The negative coupling coefficient T-coil is connected across the differential output terminals of the summer to extend the frequency band and suppress the attenuation of high frequency signals.

8. The dual-mode analog front end according to claim 1, characterized in that: The signal output module comprises: A quarter-rate sampling circuit connected to the output of the UC-DFE and configured to sample the equalized PAM4 or NRZ signal at one-quarter the data rate; The encoding conversion circuit is connected to the output end of the sampling circuit and is used to convert the PAM4 or NRZ encoding into binary parallel data and output it to the deserializer (DEMUX).

9. The dual-mode analog front end according to claim 1, characterized in that: The analog front end adopts the swing enhancement technology as a whole, and improves the signal amplitude and signal-to-noise ratio through the complementary CML structure.

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