Image sensor and power supply noise compensation method

Abstract

The invention provides an image sensor and a power supply noise compensation method, the image sensor comprises a plurality of columns of current sources and a shared compensation unit, each column of current source is connected with the output end of a corresponding pixel unit through a corresponding column line, and the shared compensation unit is connected with each column of current source through a shared node; and each column of current sources introduces the first power supply noise to the output end of the corresponding pixel unit through the sharing compensation unit so as to suppress the second power supply noise in the pixel voltage output by the corresponding pixel unit. The problem that the signal-to-noise ratio of an existing image sensor is reduced due to the fact that the image sensor is affected by power noise is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and particularly to an image sensor and a power supply noise compensation method. Background Art

[0002] Figure 1 A typical circuit structure of an image sensor is shown, including a pixel unit 100, a column current source 200, and a column readout unit 300. The column readout unit 300 includes a ramp generator 310, a voltage buffer 320, a comparator 330, a counter 340, and a memory 350. The connections of each part are as shown in the figure. Among them, the output end of the pixel unit 100 is connected to the column current source 200 and the column readout unit 300 through a column line.

[0003] The signal processing process of the above image sensor is as follows: The pixel unit 100 converts an optical signal into a pixel voltage signal and transmits it to one input end of the comparator 330. The ramp voltage signal generated by the ramp generator 310 is transmitted to the other input end of the comparator 330 after passing through the voltage buffer 320. After the two voltage signals are compared, the output of the comparator 330 will flip. The counter 340 then obtains the corresponding quantization result according to the different flip times of the comparator 330 and stores it in the memory 350, thereby completing the conversion from an analog signal to a digital signal.

[0004] However, during the signal processing process, it will be interfered by power supply noise. Since there is a capacitance Cp between the power supply voltage AVDD and the floating diffusion node FD in the pixel unit 100, the power supply noise on the power supply voltage AVDD will be coupled to the floating diffusion node FD and transmitted to the input end of the comparator 330 through the source follower M3, affecting the flip time of the comparator 330 and ultimately affecting the signal quantization result, resulting in a decrease in the signal-to-noise ratio of the image sensor.

[0005] Therefore, how to compensate for power supply noise and avoid its influence on the signal quantization result, so as to improve the signal-to-noise ratio of the image sensor, is a technical problem that those skilled in the art urgently want to solve. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an image sensor and a power supply noise compensation method, which are used to solve the problem that the signal-to-noise ratio of the existing image sensor is reduced due to the influence of power supply noise.

[0007] To achieve the above object and other related objects, the present invention provides an image sensor, which includes:

[0008] A plurality of column current sources and a shared compensation unit, each of the column current sources is connected to the output end of a corresponding pixel unit through a corresponding column line, and the shared compensation unit is connected to each of the column current sources through a shared node;

[0009] Each of the column current sources introduces a first power supply noise to the output end of a corresponding pixel unit through the shared compensation unit to suppress a second power supply noise in the pixel voltage output by the corresponding pixel unit.

[0010] Optionally, each of the column current sources includes a first MOS transistor and a first switch, the gate of the first MOS transistor is connected to a first bias voltage through the first switch, the drain is connected to the output end of a corresponding pixel unit, and the source is grounded; wherein, the gates of the first MOS transistors in each of the column current sources are connected to each other to form the shared node.

[0011] Optionally, each of the column current sources further includes a second MOS transistor, the drain of the first MOS transistor is connected to the output end of a corresponding pixel unit through the second MOS transistor; wherein, the gate of the second MOS transistor is connected to a second bias voltage, the drain is connected to the output end of a corresponding pixel unit through a corresponding column line, and the source is connected to the drain of the first MOS transistor.

[0012] Optionally, each of the column current sources further includes a second switch connected between the gate of the first MOS transistor and the shared compensation unit.

[0013] Optionally, the shared compensation unit includes a first capacitor and a second capacitor, the first capacitor is connected between the power supply voltage and the shared node, and the second capacitor is connected between the shared node and the ground.

[0014] Optionally, the shared compensation unit includes a plurality of compensation modules, each of the compensation modules includes a third capacitor, a third switch and a fourth switch, wherein, one end of the third capacitor is connected to the shared node, and the other end is connected to the power supply voltage through the third switch and grounded through the fourth switch.

[0015] Optionally, the capacitance ratio of the third capacitors in each of the compensation modules satisfies 2 0 :2 1 :…:2 n-1 , where n is the number of compensation modules.

[0016] Optionally, the image sensor further includes a plurality of pixel units and a plurality of column readout units;

[0017] Each of the pixel units is arranged in an array by rows and columns, the pixel units in each pixel column are connected to corresponding column current sources through corresponding column lines, and the pixel units are used to convert an optical signal into a pixel voltage for output;

[0018] Each of the column readout units is connected to a corresponding column line and is configured to quantify the pixel voltage according to a comparison result between the pixel voltage and a ramp voltage.

[0019] The present invention also provides a power supply noise compensation method applied to the image sensor as described above. The power supply noise compensation method includes:

[0020] When quantifying and reading out the pixel voltage of a pixel unit, a corresponding column current source introduces a first power supply noise to an output end of the pixel unit through a shared compensation unit to suppress a second power supply noise in the pixel voltage.

[0021] Optionally, each of the column current sources includes a first MOS transistor and a first switch. After closing and then opening the first switch in the column current source, a gate of the first MOS transistor in the column current source becomes a high-impedance node, so as to introduce the first power supply noise to the output end of the pixel unit through the shared compensation unit to suppress the second power supply noise in the pixel voltage.

[0022] As described above, the image sensor and the power supply noise compensation method of the present invention, through the design of the column current source and the shared compensation unit, realize introducing a compensation power supply noise at the column current source to perform noise compensation on the output end of the pixel unit, directly reducing the power supply noise of the output signal on the column line, avoiding affecting the signal quantization result, and improving the signal-to-noise ratio of the image sensor; by sharing the same shared compensation unit among multiple column current sources, the area utilization rate of the shared capacitor can be improved, the chip area overhead can be saved, meeting the requirements of the increasingly high resolution and increasingly small process pitch of the image sensor. Moreover, the unit capacitance size of the compensation capacitor can be appropriately increased, thereby reducing the influence of capacitance mismatch. Description of the Drawings

[0023] Figure 1 Shown is a schematic diagram of a typical structure of an image sensor.

[0024] Figure 2 Shown is a schematic diagram of a structure of the image sensor of the present invention.

[0025] Figure 3 Shown is another schematic diagram of a structure of the image sensor of the present invention.

[0026] Figure 4 Shown is yet another schematic diagram of a structure of the image sensor of the present invention.

[0027] Figure 5 Shown is still another schematic diagram of a structure of the image sensor of the present invention.

[0028] Description of Reference Numerals

[0029] 100 Pixel unit

[0030] 200 - column current source

[0031] 300 - column read - out unit

[0032] 310 ramp generator

[0033] 320 voltage buffer

[0034] 330 comparator

[0035] 340 counter

[0036] 350 memory

[0037] 400 shared compensation unit

[0038] 410 compensation module Detailed implementation manners

[0039] The following illustrates the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to Figures 1 to 5 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the layout form of the components may also be more complex.

[0041] As Figures 1 to 5 shown, this embodiment provides an image sensor, including a plurality of columns of current sources 200 and a shared compensation unit 400; further, it also includes a plurality of pixel units 100 and a plurality of columns of read - out units 300.

[0042] When the image sensor includes a plurality of pixel units 100, the pixel units 100 are arranged in an array by rows and columns, and the pixel units 100 in each pixel column are connected to the corresponding column current source 200 through the corresponding column lines; the pixel units 100 are used to convert optical signals into pixel voltages for output.

[0043] As Figure 1 shown, the pixel unit 100 includes a photosensitive element PD, a transfer transistor M1, a reset transistor M2, a source - follower transistor M3, and a selection transistor M4; further, it also includes a gain transistor (not shown in the figure).

[0044] The gate of the transfer transistor M1 receives a transfer control signal TX, the source is grounded via the photosensitive unit PD, and the drain is connected to the floating diffusion node FD; the gate of the reset transistor M2 receives a reset control signal RST, the source is connected to the floating diffusion node FD, and the drain is connected to the power supply voltage AVDD; the gate of the source follower transistor M3 is connected to the floating diffusion node FD, the source is connected to the drain of the selection transistor M4, and the drain is connected to the power supply voltage AVDD; the gate of the selection transistor M4 is connected to a selection signal RS, and the source serves as the output terminal of the pixel unit 100.

[0045] When the pixel unit 100 includes a gain transistor, the gain transistor is connected in series between the source of the reset transistor M2 and the floating diffusion node FD. For example, the drain of the gain transistor is connected to the source of the reset transistor M2, the source is connected to the floating diffusion node FD, and the gate is connected to a gain control signal.

[0046] Where Cfd is the total capacitance of the floating diffusion node FD, and Cp is the capacitance between the power supply voltage AVDD and the floating diffusion node FD. Due to the existence of the capacitance Cp, the power supply noise on the power supply voltage AVDD will be coupled to the floating diffusion node FD and transferred to the output terminal of the pixel unit 100 through the source follower transistor M3 and the selection transistor. This power supply noise is denoted as the second power supply noise.

[0047] Each column current source 200 is connected to the output terminal of the corresponding pixel unit 100 through a corresponding column line. For example, it is connected to the output terminal of the pixel unit in the corresponding pixel column. The shared compensation unit 400 is connected to each column current source 200 through a shared node SJ; each column current source 200 introduces the first power supply noise to the output terminal of the corresponding pixel unit 100 through the shared compensation unit 400 to suppress the second power supply noise in the pixel voltage output by the corresponding pixel unit 100.

[0048] In one embodiment, as Figure 2 shown, each column current source 200 includes a first MOS transistor Mc1 and a first switch S1. The gate of the first MOS transistor Mc1 is connected to a first bias voltage V1 through the first switch S1, the drain is connected to the output terminal of the corresponding pixel unit 100. For example, it is connected to the output terminal of the pixel unit 100 in the corresponding pixel column through a corresponding column line, and the source is grounded; among them, the gates of the first MOS transistors Mc1 in each column current source 200 are connected to each other to form a shared node SJ.

[0049] In another embodiment, as Figure 3As shown, compared with the above-mentioned one embodiment, each column current source 200 in this embodiment further includes a second MOS transistor Mc2. The first MOS transistor Mc1 and the second MOS transistor Mc2 form a cascode current source. At this time, the drain of the first MOS transistor Mc1 is connected to the output end of the corresponding pixel unit 100 through the second MOS transistor Mc2. For example, the gate of the second MOS transistor Mc2 is connected to the second bias voltage V2, and the drain is connected to the output end of the corresponding pixel unit 100 through the corresponding column line, such as, connected to the output end of the pixel unit 100 in the corresponding pixel column, and the source is connected to the drain of the first MOS transistor Mc1.

[0050] In yet another embodiment, as Figure 4 shown, compared with the above two embodiments, each column current source 200 in this embodiment further includes a second switch S2, which is connected between the gate of the first MOS transistor Mc1 and the shared compensation unit 400 for selecting whether to use the noise compensation function. When selecting the noise compensation function, usually the selection of each column current source is the same, either all select to use this function or all select not to use this function. It is very rare that some select to use this function. In addition, although Figure 4 is the illustration of adding the second switch S2 on the Figure 3 basis, those skilled in the art should understand that it is also feasible to add the second switch S2 on the Figure 2 basis.

[0051] In practical applications, for the convenience of circuit design, usually the structures of each column current source 200 are designed to be the same. For example, they can all be the Figure 2 shown structure, or they can all be the Figure 3 shown structure, or even they can all be the Figure 4 shown structure.

[0052] In one embodiment, as Figures 2 to 4 shown, the shared compensation unit 400 includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the power supply voltage AVDD and the shared node SJ, and the second capacitor C2 is connected between the shared node SJ and the ground. Among them, the first capacitor C1 is the capacitor of the shared node SJ to the power supply voltage AVDD, and its capacitance value is greater than zero; the second capacitor C2 is the capacitor of the shared node SJ to the ground, and its capacitance value is greater than or equal to zero.

[0053] In this embodiment, the capacitance values of the capacitor of the shared node SJ to the power supply voltage AVDD (i.e., the first capacitor C1) and the capacitor of the shared node SJ to the ground (i.e., the second capacitor C2) are fixed values and cannot be adjusted. Generally, they are designed according to actual requirements during application. In order to realize the adjustable capacitance values of the capacitor of the shared node SJ to the power supply voltage AVDD and the capacitor of the shared node SJ to the ground, another embodiment is proposed.

[0054] In another embodiment, as Figure 5 shown, the shared compensation unit 400 includes a plurality of compensation modules 410. Each compensation module 410 includes a third capacitor C3, a third switch S3, and a fourth switch S4. One end of the third capacitor C3 is connected to the shared node SJ, and the other end is connected to the power supply voltage AVDD through the third switch S3 and grounded through the fourth switch S4. Among them, the capacitance values of the third capacitors C3 in each compensation module 410 satisfy 2 0 :2 1 :…:2 n-1 , where n is the number of compensation modules 410. It should be noted that the number of compensation modules 410 should be designed according to actual needs, and this embodiment does not limit this.

[0055] In this embodiment, the third switch S3 and the fourth switch S4 are controlled by a set of mutually inverted control signals, so that when the third switch S3 is closed, the fourth switch S4 is opened, and when the third switch S3 is opened, the fourth switch S4 is closed. In addition, the two switches in each compensation module 410 can be controlled by different control signals. For example, taking the shared compensation unit 400 including four compensation modules 410 as an example, the first and second compensation modules 410 are controlled by a first set of control signals such that the third switch S3 is opened and the fourth switch S4 is closed, and the third and fourth compensation modules 410 are controlled by a second set of control signals such that the third switch S3 is closed and the fourth switch S4 is opened. Of course, other combination methods are also feasible, which has no substantial impact on this embodiment. In fact, in this embodiment, by controlling the switches of each compensation module 410, the capacitance values of the shared node SJ to the power supply voltage AVDD and the capacitance of the shared node SJ to the ground are adjusted to better compensate for the power supply noise.

[0056] When using the shared compensation unit 400 to suppress power supply noise, designing the shared compensation unit 400 as multi-column sharing can improve the area utilization rate of the shared capacitors (such as the first capacitor C1 and the second capacitor C2, or the third capacitor C3), save the chip area overhead, and meet the increasingly high resolution and increasingly small process pitch of the image sensor. Moreover, the unit capacitor size of the compensation capacitor can also be appropriately increased, thereby reducing the influence of capacitor mismatch. It should be noted that the number of column current sources sharing the same shared compensation unit 400 should be designed according to actual needs, and this embodiment does not limit this.

[0057] When the image sensor includes a plurality of columns of readout units 300, each column of readout units 300 is connected to the corresponding column line and is used to quantify the pixel voltage according to the comparison result between the pixel voltage and the ramp voltage.

[0058] As Figure 1As shown in the figure, the column readout unit 300 includes a ramp generator 310, a voltage buffer 320, a comparator 330, a counter 340, and a memory 350; further, it also includes a voltage buffer 320.

[0059] The ramp generator 310 is used to provide a ramp voltage; the voltage buffer 320 is used to buffer and output the ramp voltage; the comparator 330 receives the pixel voltage and the ramp voltage, and is used to compare the pixel voltage and the ramp voltage and output a comparison result; the counter 340 is connected to the comparator 330, and is used to quantize the pixel voltage according to the comparison result and output a quantization result; the memory 350 is connected to the counter 340, and is used to store the quantization result; thus, the conversion of the pixel voltage from an analog signal to a digital signal is completed.

[0060] Correspondingly, this embodiment also provides a power supply noise compensation method, including the following steps; wherein, this method is applied to the image sensor described above.

[0061] The specific method includes: when quantifying and reading out the pixel voltage of the pixel unit 100, the corresponding column current source 200 introduces the first power supply noise to the output end of the pixel unit 100 through the shared compensation unit 400 to suppress the second power supply noise in the pixel voltage.

[0062] When each column current source 200 at least includes a first MOS transistor Mc1 and a first switch S1, the method of introducing the first power supply noise to the output end of the pixel unit 100 includes: controlling the first switch S1 in the corresponding column current source 200 to be closed and then opened, so that the gate of the first MOS transistor Mc1 in the column current source 200 becomes a high-impedance node, thereby introducing the first power supply noise to the output end of the pixel unit 100 through the shared compensation unit 400 to achieve suppressing the second power supply noise in the pixel voltage.

[0063] Taking Figure 3 the shown image sensor as an example, assuming that the power supply noise of the power supply voltage AVDD is Vn, when the corresponding column current source 200 compensates the power supply noise of the output end of the corresponding pixel unit 100 through the shared compensation unit 400:

[0064] The second power supply noise (introduced via the source follower transistor M3 and the selection transistor M4) at the output end of the corresponding pixel unit 100 can be expressed as: wherein, Vn2 is the second power supply noise, Cp is the capacitance between the power supply voltage AVDD and the floating diffusion node FD, Cfd is the total capacitance of the floating diffusion node FD, Asf is the gain of the source follower transistor M3, gmsf is the transconductance of the source follower transistor M3, and gmbsf is the body effect transconductance of the source follower transistor M3.

[0065] The first power supply noise (introduced by the corresponding column current source 200 through the shared compensation unit 400) can be expressed at the output of the corresponding pixel unit 100 as follows: Where, Vn1 is the first power supply noise, C1 is the capacitance value of the first capacitor, C2 is the capacitance value of the second capacitor, Cgs is the gate-source parasitic capacitance of the first MOS transistor Mc1, Amc is the gain of the column current source, and gmmc is the transconductance of the first MOS transistor Mc1.

[0066] Finally, the total power supply noise Vno at the output of the corresponding pixel unit 100 can be expressed as: By adjusting the capacitance values of the first capacitor C1 and the second capacitor C2 in the shared compensation unit 400, the total power supply noise Vno at the output of the corresponding pixel unit 100 is made close to zero, thereby suppressing the power supply noise.

[0067] In summary, for an image sensor and a power supply noise compensation method according to the present invention, through the design of the column current source and the shared compensation unit, a compensation power supply noise is introduced at the column current source to perform noise compensation on the output of the pixel unit, directly reducing the power supply noise of the output signal on the column line, avoiding affecting the signal quantization result, and improving the signal-to-noise ratio of the image sensor; by sharing the same shared compensation unit among multiple column current sources, the area utilization rate of the shared capacitor can be increased, the chip area overhead can be saved, meeting the increasingly high resolution and increasingly small process pitch of the image sensor. Moreover, the unit capacitor size of the compensation capacitor can also be appropriately increased, thereby reducing the influence of capacitor mismatch. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0068] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that, The image sensor includes: A plurality of column current sources and a shared compensation unit. Each of the column current sources is connected to the output end of a corresponding pixel unit through a corresponding column line, and the shared compensation unit is connected to each of the column current sources through a shared node; Each of the column current sources introduces a first power supply noise to the output end of the corresponding pixel unit through the shared compensation unit to suppress a second power supply noise in the pixel voltage output by the corresponding pixel unit.

2. The image sensor according to claim 1, wherein Each of the column current sources includes a first MOS transistor and a first switch. The gate of the first MOS transistor is connected to a first bias voltage through the first switch, the drain is connected to the output end of the corresponding pixel unit, and the source is grounded; wherein, the gates of the first MOS transistors in each of the column current sources are connected to each other to form the shared node.

3. The image sensor according to claim 2, wherein Each of the column current sources further includes a second MOS transistor. The drain of the first MOS transistor is connected to the output end of the corresponding pixel unit through the second MOS transistor; wherein, the gate of the second MOS transistor is connected to a second bias voltage, the drain is connected to the output end of the corresponding pixel unit through the corresponding column line, and the source is connected to the drain of the first MOS transistor.

4. The image sensor according to claim 2 or 3, characterized in that, Each of the column current sources further includes a second switch connected between the gate of the first MOS transistor and the shared compensation unit.

5. The image sensor according to claim 1, characterized in that, The shared compensation unit includes a first capacitor and a second capacitor. The first capacitor is connected between the power supply voltage and the shared node, and the second capacitor is connected between the shared node and the ground.

6. The image sensor according to claim 1, characterized in that, The shared compensation unit includes a plurality of compensation modules. Each of the compensation modules includes a third capacitor, a third switch, and a fourth switch. One end of the third capacitor is connected to the shared node, and the other end is connected to the power supply voltage through the third switch and grounded through the fourth switch.

7. The image sensor according to claim 6, characterized in that, The capacitance ratios of the third capacitors in each of the compensation modules satisfy 2 0 :2 1 :…:2 n-1 , where n is the number of compensation modules.

8. The image sensor according to claim 1, wherein The image sensor further includes a plurality of pixel units and a plurality of column readout units, wherein, Each of the pixel units is arranged in an array by rows and columns. The pixel units in each pixel column are connected to the corresponding column current sources through corresponding column lines. The pixel units are used to convert an optical signal into a pixel voltage for output; Each of the column readout units is connected to the corresponding column line and is used to quantize the pixel voltage according to a comparison result between the pixel voltage and a ramp voltage.

9. A power supply noise compensation method, characterized in that, Applied to the image sensor according to any one of claims 1-8, the power supply noise compensation method includes: When quantizing and reading out the pixel voltage of a pixel unit, the corresponding column current source introduces a first power supply noise to the output end of the pixel unit through the shared compensation unit to suppress a second power supply noise in the pixel voltage.

10. The power supply noise compensation method according to claim 9, wherein, Each of the column current sources includes a first MOS transistor and a first switch; Controlling the first switch in the column current source to be closed and then opened, so that the gate of the first MOS transistor in the column current source becomes a high-impedance node, realizing introducing the first power supply noise to the output end of the pixel unit through the shared compensation unit to suppress the second power supply noise in the pixel voltage.

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