Pixel circuit and driving method thereof

Abstract

The invention discloses a pixel circuit and a driving method thereof, two transistors shared by control ends are additionally arranged for each pixel, and the newly added transistors of a plurality of pixels are connected and shared as a variable capacitor; by controlling the number of the transistors which are conducted in pairs, the capacitance of the conversion gain can be adjusted, and the conversion gain of various gears can be designed, so that the conversion gain of the appropriate gear can be selected according to different scenes, the signal-to-noise ratio loss during conversion gain gear switching is reduced, and the signal-to-noise ratio of the whole image is optimized; control end sharing can reduce arrangement of control signal lines, and the area is saved.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and particularly to a pixel circuit and a driving method thereof. Background Art

[0002] An image sensor uses the photoelectric conversion function of optoelectronic devices in a pixel array to convert the optical image on the photosensitive surface into an electrical signal proportional to the optical image, and then through the processing and storage of the peripheral circuit, etc., to record the image information. The performance requirements of image sensors are increasing day by day, and the dynamic range has become a key performance parameter of CMOS image sensors. Currently, the most commonly used is the single-exposure method, which uses the capacitors in the pixel unit to make conversion gains of different levels, and realizes high dynamic range (HDR) by switching the conversion gains of different levels.

[0003] Figure 1 The following shows an example of an existing circuit adapted to this method. The circuit of each pixel unit includes: a photodiode PD, a transfer transistor TG, a reset transistor RST, a conversion gain control transistor DCG, a source follower SF, and a metal capacitor CAP. Among them, the photodiode PD is used to convert the sensed incident light into charge; the transfer transistor TG is coupled between the photodiode PD and the floating diffusion region FD, and is used to selectively transfer the charge accumulated by the photodiode PD to the floating diffusion region FD. The floating diffusion region FD is used to accumulate the received charge. The metal capacitor CAP is coupled to the node between the reset transistor RST and the conversion gain control transistor DCG; the conversion gain control transistor DCG is used to selectively switch between two conversion gains, and by connecting or disconnecting the metal capacitor CAP from the floating diffusion region FD, to change the capacitance at the floating diffusion region FD (when the metal capacitor CAP is connected, the capacitance at the floating diffusion region FD increases, and the conversion gain of a single pixel unit decreases; when the metal capacitor CAP is not connected, the capacitance at the floating diffusion region FD decreases, and the conversion gain of a single pixel unit increases); the reset transistor RST is coupled to the power supply voltage VDD, and is used to selectively reset the charge accumulated at the floating diffusion region FD and the photodiode PD. The source follower SF is used to amplify the potential change of the floating diffusion region FD and output a PXD signal corresponding to the amplification result.

[0004] In the circuit design of the existing solution, the circuit working timing is as follows:

[0005] Clearing electrons: RST is turned on, DCG is turned on, TG is turned on, and the electrons in PD and FD are cleared;

[0006] Integration: TG is turned off, RST is turned on, DCG is turned on;

[0007] Readout process (LHHL mode):

[0008] LCG reference signal: TG off, RST off, DCG on, read the LCG reference signal;

[0009] HCG reference signal: TG off, RST off, DCG off, read the HCG reference signal;

[0010] HCG signal: TG on, RST off, DCG off, read the HCG signal;

[0011] LCG signal: TG on, RST off, DCG on, read the LCG signal.

[0012] For the above existing circuit, it can be read in the high conversion gain (HCG) gear under low light, and can be read in the low conversion gain (LCG) gear under bright light; however, on the one hand, the conversion gain can only be switched between two gears with fixed capacitance values. In the design of high dynamic range, in order to take into account both dark field and high-brightness scenarios, the capacitance difference between the two gears is large. Therefore, when switching from the HCG gear to the LCG gear, the signal-to-noise ratio will jump; for points with different brightnesses in a scene, the darker points will lose part of the signal-to-noise ratio, reducing the image quality. On the other hand, the functions of each transistor in the existing circuit are independent, and the control terminals cannot be shared. Corresponding control signal lines need to be arranged separately, which not only makes the control scheme more complex, consumes more resources, but also occupies more area, increasing the difficulty of circuit design layout. Summary of the Invention

[0013] To solve the problem of signal-to-noise ratio loss caused by fixed-gear conversion gain in the prior art, the present invention proposes a new pixel circuit and its driving method. The new transistors added in multiple pixel units are connected and shared as variable capacitors to adjust the capacitance size of the conversion gain, obtaining multiple gears of conversion gain and improving the problem of signal-to-noise ratio loss. By sharing the control terminals of the transistors used as variable capacitors in each pixel unit, the layout of control signal lines can be reduced, effectively saving area.

[0014] The present invention provides a driving method for a pixel circuit. The pixel circuit includes: pixel units, and one or more of the pixel units form a pixel array; each pixel unit includes:

[0015] One or more photodiodes;

[0016] One or more first transistors, correspondingly connected to the one or more photodiodes; the first transistor is coupled between the corresponding photodiode and a floating diffusion region of the present pixel unit;

[0017] A second transistor, coupled between the power supply voltage and the floating diffusion region of the present pixel unit;

[0018] A third transistor, coupled between the first capacitor and the floating diffusion region of the present pixel unit;

[0019] Each pixel unit further includes a fourth transistor and a fifth transistor sharing a control terminal;

[0020] Wherein, there are at least a first pixel unit, a second pixel unit, and a third pixel unit;

[0021] The fourth transistor of the first pixel unit is coupled between the floating diffusion region of the first pixel unit and one end of the fifth transistor of the second pixel unit; The other end of the fifth transistor of the second pixel unit is coupled to the floating diffusion region of the second pixel unit;

[0022] The fifth transistor of the first pixel unit is coupled between the floating diffusion region of the first pixel unit and one end of the fourth transistor of the third pixel unit, and the other end of the fourth transistor of the third pixel unit is coupled to the floating diffusion region of the third pixel unit;

[0023] The driving method includes controlling the number of shared control terminals of one or more pixel units among the first pixel unit, the second pixel unit, and the third pixel unit to control the gain level.

[0024] Optionally, the first pixel unit, the second pixel unit, and the third pixel unit are in the same column; Or, the first pixel unit, the second pixel unit, and the third pixel unit are in the same row; Or, the first pixel unit, the second pixel unit, and the third pixel unit are not in the same column and not in the same row.

[0025] Optionally, the first pixel unit, the second pixel unit, and the third pixel unit are in adjacent rows or adjacent columns.

[0026] Optionally, the first pixel unit is separated from the second pixel unit and the third pixel unit by i rows respectively, where i≥1 and i is an integer;

[0027] And / or, the first pixel unit is separated from the second pixel unit and the third pixel unit by j columns respectively, where j≥1 and j is an integer.

[0028] Optionally, in at least one column of pixel units, the fourth transistors of any odd rows and the fifth transistors of adjacent odd rows are pairwise connected to form a first connection group with non-shared control terminals; The fourth transistors of any even rows and the fifth transistors of adjacent even rows are pairwise connected to form a second connection group with non-shared control terminals;

[0029] Alternatively, in at least one row of pixel units, the fourth transistors in any odd-numbered column are pairwise connected to the fifth transistors in the adjacent odd-numbered column to form a first connection group with non-shared control terminals, and the fourth transistors in even-numbered columns and the fifth transistors in adjacent even-numbered columns are pairwise connected to form a second connection group with non-shared control terminals.

[0030] Optionally, in at least one column of pixel units, one end of the fourth transistor of the first row of pixel units is connected to the fifth transistor of the row below it, and the other end of the fourth transistor of the first row of pixel units is grounded; one end of the fifth transistor of the last row of pixel units in the same column is connected to the fourth transistor of the row above it, and the other end of the fifth transistor of the last row of pixel units is grounded;

[0031] Alternatively, in at least one row of pixel units, one end of the fourth transistor of the first column of pixel units is connected to the fifth transistor of the column to its right, and the other end of the fourth transistor of the first column of pixel units is grounded; one end of the fifth transistor of the last column of pixel units in the same row is connected to the fourth transistor of the column to its left, and the other end of the fifth transistor of the last column of pixel units is grounded.

[0032] Optionally, the fourth and fifth transistors with shared control terminals are fabricated within or outside the area of the present pixel unit.

[0033] Optionally, each of the pixel units includes 4, or 8, or 9, or 16 of the photodiodes.

[0034] Optionally, each of the pixel units further includes a second capacitor; the second capacitor is coupled to the connection node between the fourth transistor and the floating diffusion region of the present pixel unit, or coupled to the connection node between the fifth transistor and the floating diffusion region of the present pixel unit.

[0035] Optionally, each of the pixel units further includes:

[0036] a sixth transistor, the control terminal of the sixth transistor being connected to the floating diffusion region of the present pixel unit;

[0037] a seventh transistor, coupled between the sixth transistor and the signal output line of the present pixel unit for selective output.

[0038] Optionally, the first transistor includes a transfer transistor;

[0039] the second transistor includes a reset transistor;

[0040] the third transistor includes a gain conversion transistor;

[0041] the sixth transistor includes a source follower transistor;

[0042] The seventh transistor includes a selection output transistor.

[0043] Optionally, the fourth transistor and / or the fifth transistor are fabricated synchronously with at least one of the first, second, third, sixth, and seventh transistors.

[0044] The present invention also provides a pixel circuit applied to the driving method described in any one of the above.

[0045] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In this solution, two transistors T1 and T2 with shared control terminals are added to each pixel unit, and the transistors T1 and T2 of different pixel units across rows and / or columns are connected in common (and the control terminals are not shared), forming a variable capacitance that can be shared by different pixel units; among the multiple pixel units sharing the variable capacitance, by controlling the number of pairs of transistors T1 and T2 conducting in a certain or certain pixel units, the capacitance size of the conversion gain can be adjusted, and conversion gains of multiple gears can be designed.

[0046] In each pixel unit of this solution, the reset transistor RST and the conversion gain control transistor DCG are connected in parallel to the transistors T1 and T2 sharing the control terminal; the conversion gain control transistor DCG can selectively connect or disconnect a capacitor (such as a metal capacitor, but not limited to this) connected to it to the floating diffusion region FD of this pixel unit. Thus, outside the transistors T1 and T2 or the shared capacitor where they are located, an independent capacitance value can be provided to the floating diffusion region FD for adjusting the capacitance size of the conversion gain, providing more gear selection for the readout circuit. Therefore, this solution provides variable low conversion gain gears (LCG), medium conversion gain gears (MCG), and high conversion gain gears (HCG), and the appropriate conversion gain gear can be selected according to the current scene, making the signal-to-noise ratio of the entire image optimal and reducing the signal-to-noise ratio loss. In this solution, the control terminals of the transistors T1 and T2 of each pixel unit are shared, which can also simplify the control signal, reduce the layout of control signal lines, and effectively save area. Description of the Drawings

[0047] The drawings of the present invention form a part of this specification and are used to further understand the present invention. The drawings show embodiments of the present invention and are used together with the specification to illustrate the principle of the present invention.

[0048] Figure 1 is a circuit schematic diagram of each pixel in the pixel circuit of the prior art.

[0049] Figure 2 is a schematic diagram when a pixel circuit provided by the present invention includes two pixel units.

[0050] Figure 3It is a schematic diagram when a pixel circuit provided by the present invention includes four pixel units.

[0051] Figure 4 In an example of the present invention, it is a schematic diagram of setting a basic capacitor between transistor T2 and floating diffusion region FD. Detailed implementation manners

[0052] The following detailed descriptions are all illustrative and are intended to provide further explanations of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0053] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention.

[0054] The present invention proposes a new pixel circuit design scheme. As Figure 2 shown, the circuit of each pixel unit includes: a photodiode PD, a transfer transistor TG, a reset transistor RST, a conversion gain control transistor DCG, a source follower SF, and a first capacitor (a metal capacitor CAP in this example); the present invention adds two transistors T1 and T2 with shared gates for each pixel unit, and also connects the reset transistor RST and the conversion gain control transistor DCG in parallel to the transistors T1 and T2. Among them, the transistors T1 and T2 are connected across rows (or columns) as a common capacitor, and by controlling the opening or closing of the common capacitor, a variable capacitor is provided for the low conversion gain gear; the parallel setting of the conversion gain control transistor DCG makes the readout gear of the entire pixel circuit have three gears: a variable low conversion gain gear (LCG), a medium conversion gain gear (MCG), and a high conversion gain gear (HCG), providing more gear selection for the readout circuit. This scheme can select a conversion gain gear suitable for the current scenario, reduce the signal-to-noise loss when switching the conversion gain, and effectively optimize the signal-to-noise ratio of the entire pixel unit. At the same time, since the gates of the transistors T1 and T2 are shared, the layout of the control signal lines can be effectively reduced, saving area.

[0055] In each pixel unit, the photodiode PD can convert the incident light it senses into electrons and accumulate the charges generated by the electrons; the transfer transistor TG is coupled between the photodiode PD and the floating diffusion region FD. When the transfer transistor TG responds to a first control signal issued by an external control circuit and is placed in the conducting state, the electrons of the photodiode PD can be transferred to the floating diffusion region FD; the floating diffusion region FD receives the electrons and accumulates the charges generated by the electrons.

[0056] Each pixel unit in this example is provided with a photodiode PD and a corresponding transfer transistor TG. In other examples, each pixel unit may also include multiple photodiodes PD, and a corresponding transfer transistor TG is provided for each photodiode PD. These transfer transistors TG are commonly coupled to the floating diffusion region PD of the pixel unit; the multiple photodiodes PD share other components in the circuit of the pixel unit except the transfer transistors TG; for example but not limited to, each pixel unit may include 4, 8, 9, or 16 photodiodes PD and their respective corresponding transfer transistors TG.

[0057] One end of the conversion gain control transistor DCG and the reset transistor RST are respectively coupled to the floating diffusion region FD, and the other end of the reset transistor RST is coupled to the power supply voltage VDD. When the reset transistor RST responds to the second control signal issued by the external control circuit and is placed in the conducting state, it can release the charges accumulated in the floating diffusion region FD and the photodiode PD for resetting.

[0058] The other end of the conversion gain control transistor DCG is coupled to one end of the metal capacitor CAP, and the other end of the metal capacitor CAP can be grounded or connected to a specified voltage according to application requirements. The conversion gain control transistor DCG is used to selectively switch the conversion gain. When it responds to the third control signal issued by the external control circuit and is placed in the conducting or off state, it connects or disconnects the capacitance of the metal capacitor CAP from the floating diffusion region FD respectively, so as to change the capacitance at the floating diffusion region FD, thereby entering or exiting the medium conversion gain gear (MCG).

[0059] The control terminal (gate) of the source follower transistor SF is connected to the floating diffusion region FD, and it can receive the charges accumulated in the floating diffusion region FD, amplify the potential change at the floating diffusion region FD, and output a corresponding PXD signal according to the amplification result. In some examples, the source follower transistor SF is coupled between the power supply voltage VDD and a selection output transistor SEL, and it can transmit the PXD signal to the selection output transistor SEL; the selection output transistor SEL is used to selectively output the PXD signal amplified corresponding to the charge amount of the floating diffusion region FD. When it responds to the fourth control signal issued by the external control circuit and is placed in the conducting state, it can transmit the received PXD signal to the signal output line to which the selection output transistor SEL is connected.

[0060] In the pixel circuit of this solution, the transistors T1 in each row share the same gate with the transistors T2 in the same row, and their control terminals (gates) are coupled together and share the same fourth control signal from an external control circuit. Moreover, the transistors T1 in each row are also coupled to the transistors T2' in another row between the floating diffusion regions FD and FD' of these two rows of pixel units to form a shared capacitance for these two rows (the addition of a prime is to distinguish transistors belonging to different rows, and the same meaning applies when there are the same markings hereinafter). The control signals of the transistors T1 and T2' in different rows and without shared control terminals are independent and can be set to the same or different on-off states according to needs at different stages.

[0061] In each row of pixel units, when the transistors T1 and T2 respond to the shared fourth control signal and are simultaneously turned on, at least the capacitances of these two transistors T1 and T2 are connected in parallel to the floating diffusion region FD of this row. If the transistor T2' in another row connected to the transistor T1 that is turned on in this row is turned on, then the floating diffusion regions FD and FD' of these two rows are connected. After the capacitances of these two transistors T1 and T2' are allocated as the shared capacitance, they are respectively connected to the floating diffusion regions FD and FD' of these two rows. Among them, one path of the shared capacitance corresponding to the transistors T1 and T2' and the capacitance provided by the transistor T2 are connected in parallel to the floating diffusion region FD of this row; the other path of the shared capacitance corresponding to the transistors T1 and T2' and the capacitance provided by the transistor T1' are connected in parallel to the floating diffusion region FD' of another row (the situation where there are transistors in other rows connected to the transistor T1' or T2 to form a shared capacitance is not considered here for the time being).

[0062] If the transistor T2' in another row connected to the transistor T1 that is turned on in this row is turned off, then the floating diffusion regions FD and FD' of these two rows are not connected. The capacitances of the transistors T1 and T2 in this row are connected in parallel to the floating diffusion region FD of this row, and no additional shared capacitance provided by other rows is connected. Thus, a capacitance with a conversion gain different from the previous case (when T1 is on and T2' is off) is obtained at the floating diffusion region FD of this row, realizing the switching of the conversion gain gear.

[0063] Therefore, by pairwise controlling the on-off states of the transistors T1 and T2 in this row and combining at least with the on-off states of the transistors T2' in the interlaced rows, capacitances with multiple different low conversion gain (LCG) gears can be obtained to select a suitable conversion gain for different scenarios, optimize the signal-to-noise ratio of the entire pixel circuit, and obtain higher-quality images.

[0064] Exemplarily, the two rows of pixel units with the shared capacitance are set interlaced in the same column, such as Figure 3Show the (n - 2)-th row, the n-th row, the (n + 2)-th row, and the (n + 4)-th row; for the convenience of subsequent narration, the marks of each transistor will be followed by (n - 2), n, (n + 2), (n + 4), etc. to distinguish the pixel units in different rows.

[0065] The T1n transistor in the n-th row is connected to the T2(n + 2) transistor in the (n + 2)-th row and is coupled between the floating diffusion regions FDn and FD(n + 2) of these two rows; meanwhile, in the n-th row, one end of the T2n transistor sharing the gate with the T1n transistor is coupled to the floating diffusion region FDn of this row, and the other end of the T2n transistor is coupled to one end of the T1(n - 2) transistor of the pixel unit in the (n - 2)-th row, so that the T2n transistor is connected to the T1(n - 2) transistor. The (n - 2)-th row and the (n + 2)-th row are pixel units arranged in a staggered manner on both sides of the n-th row in the same column; similarly, in the (n + 2)-th row, one end of the T1(n + 2) transistor sharing the gate with the T2(n + 2) transistor is coupled to the floating diffusion region FD(n + 2) of this row, and the other end of the T1(n + 2) transistor is coupled to one end of the T2(n + 4) transistor of the pixel unit in the (n + 4)-th row, so that the T1(n + 2) is connected to the T2(n + 4). The n-th row and the (n + 4)-th row are pixel units arranged in a staggered manner on both sides of the (n + 2)-th row in the same column. From the above relationships, the connection methods of the T1 and T2 transistors of each pixel unit in the first group of pixels can be deduced (the first group of pixel units includes... the (n - 2)-th row, the n-th row, the (n + 2)-th row, the (n + 4)-th row... in the same column, and every two pixel units are arranged with one row in between); among the first group of pixels, one end of the T1 transistor of the first pixel unit and one end of the T2 transistor of the last pixel unit are not connected to other transistors, and this end can be grounded.

[0066] Based on the above method, after the T1 and T2 transistors of each row of pixel units share the same gate and are respectively connected to the T1' and T2' transistors in the staggered rows to form a shared capacitor, when the number of pairs of transistors that conduct simultaneously at the shared control terminal (gate) is different (including but not limited to controlling the on / off conditions of the paired transistors in the pixels of this row, or in the other pixels connected to one or both sides of this row), different conversion gain levels can be obtained (in this example, the on / off conditions of the DCG transistors in each row are not considered for the time being).

[0067] For example, when the T1n transistor in the n-th row is turned on, if the T2(n+2) transistor in the (n+2)-th row is turned on, it is coupled between the floating diffusion regions FDn and FD(n+2) in the n-th row and the (n+2)-th row. The capacitors corresponding to the T1n transistor and the T2(n+2) transistor are shared by the pixel units in these two rows (referred to as the first shared capacitor), and after distribution, they are simultaneously connected to the two floating diffusion regions FDn and FD(n+2). At this time, the T2n transistor in the n-th row that shares the same gate with the T1n transistor is also turned on. If the T2n transistor is not connected to the transistor T1 in other rows (such as the T1(n-2) transistor in the (n-2)-th row) or the transistor T1 in the other rows it is connected to is not turned on, then the capacitor corresponding to the T2n transistor and one path of the first shared capacitor corresponding to the T1n transistor and the T2(n+2) transistor are connected in parallel to the floating diffusion region FDn in the n-th row, and the pixel unit in the n-th row is in the first gear of its low conversion gain mode (LCG).

[0068] Or, if the T2n transistor is connected to the T1(n-2) transistor in the (n-2)-th row and the T1(n-2) transistor is also turned on, the capacitors of the T2n transistor and the T1(n-2) transistor are shared by the pixel units in the n-th row and the (n-2)-th row (referred to as the second shared capacitor); then for the n-th row, one path of the second shared capacitor corresponding to the T2n transistor and the T1(n-2) transistor and one path of the first shared capacitor corresponding to the T1n transistor and the T2(n+2) transistor are connected in parallel to the floating diffusion region FDn in this row, and the pixel in the n-th row is in the second gear of its low conversion gain mode (LCG), and the capacitance value is different from that in the previous low conversion gain gear of the n-th row.

[0069] In the example where the T1n transistor is turned on and the T2(n + 2) transistor is turned on, the pixel unit in the n-th row is at a certain low-gain conversion level at this time (refer to the first level or the second level mentioned above); for the (n + 2)-th row, the T1(n + 2) transistor is turned on together with the T2(n + 2) transistor, and the floating diffusion region FD(n + 2) of this row can obtain at least two capacitances connected in parallel through the T1(n + 2) transistor and the T2(n + 2) transistor at the same time, so that the (n + 2)-th row is also at a certain low conversion gain level; the specific level of the low conversion gain also depends on whether there are other shared capacitances connected to the floating diffusion region FD(n + 2) of the (n + 2)-th row, that is, whether the T2(n + 4) transistor of the (n + 4)-th row is connected and turned on with the T1(n + 2) transistor of the (n + 2)-th row. If so, the floating diffusion region FD(n + 2) can obtain a first shared capacitance connected in parallel and a shared capacitance corresponding to the T1(n + 2) transistor and the T2(n + 4) transistor, and the (n + 2)-th row is at the second level of its low conversion gain mode (LCG); conversely, if the T1(n + 2) transistor is not connected to the T2(n + 4) transistor of the (n + 4)-th row or the T2(n + 4) transistor is not turned on, the floating diffusion region FD(n + 2) obtains a first shared capacitance connected in parallel and the capacitance corresponding to the T1(n + 2) transistor, so that the (n + 2)-th row is at the first level of its low conversion gain.

[0070] In the example where the T1n transistor is turned on and the T2(n + 2) transistor is turned off, the capacitance of the T1n transistor is connected to the floating diffusion region FDn of the n-th row, but the floating diffusion regions FDn and FD(n + 2) of these two rows cannot obtain capacitance from the T2(n + 2) transistor; at this time, the T2n transistor is turned on together with the T1n transistor (and there is no shared capacitance from the T2(n - 2) transistor), and the floating diffusion region FD of the pixel unit in the n-th row can obtain capacitances corresponding to the T1n transistor and the T2n transistor connected in parallel, and is at the third level of its low conversion gain mode (LCG). The third level is different from the capacitance values in the first two low conversion gain levels of the n-th row. At the same time, the T1(n + 2) transistor of the pixel unit in the (n + 2)-th row is turned off together with the T2(n + 2) transistor, and the floating diffusion region FD(n + 2) of the (n + 2)-th row cannot obtain the capacitances corresponding to the T1(n + 2) transistor and the T2(n + 2) transistor or the shared capacitances of other rows; at this time, if the DCG(n + 2) transistor is turned off, there is no additional capacitance connected to the floating diffusion region FD(n + 2) of the (n + 2)-th row, and the (n + 2)-th row is at its high conversion gain level (HCG); if the DCG(n + 2) transistor is turned on, at least the capacitance value of the metal capacitance CAP is connected to the floating diffusion region FD(n + 2), and it is at the medium conversion gain level (MCG).

[0071] Similarly, in the example where the T1n and T2n transistors of the common gate of this row are turned off together, the on / off states of the T2(n+2) and T1(n-2) transistors respectively connected to them will not affect the capacitance of the conversion gain of the pixel unit in the nth row. At the floating diffusion region FDn of the pixel unit in the nth row, no capacitance corresponding to the T1n and T2n transistors or other shared capacitances can be obtained; at this time, if the DCGn transistor is turned off, no additional capacitance is connected to the floating diffusion region FDn in the nth row, and the nth row is in its high conversion gain gear (HCG); if the DCGn transistor is turned on, at least the capacitance value of the metal capacitance CAP is connected to the floating diffusion region FDn, and it is in the medium conversion gain gear (MCG). That is, when a certain row is in the LCG gear, the DCG transistor of that row can be selected to be turned on or off.

[0072] The above example describes the first group of pixel units corresponding to... the (n-2)th row, the nth row, the (n+2)th row, the (n+4)th row... in the same column (where the T1 transistors of each row are connected to the T2 transistors of every other row); it can be understood that in some examples, the remaining pixel units in the same column, such as... the (n-3)th row, the (n-1)th row, the (n+1)th row, the (n+3)th row... can be similarly used as the second group of pixels (where the T1 transistors of each row are connected to the T2 transistors of every other row), thereby forming a connection group based on the first group of pixel units in the same column and forming another connection group based on the second group of pixel units, and these two connection groups can be independently controlled.

[0073] The above are only some examples of connecting transistor T1 and transistor T2 between different pixel units in this solution (the T1 and T2 transistors in the same pixel unit share the gate, and will not be elaborated one by one in the following examples). In other examples, for instance, the T1 transistors in a certain row can be connected to the T2 transistors in the same column that are separated by multiple rows; or, the T1 transistors in a certain row are connected to the T2 transistors in the adjacent row in the same column, and there is no other row separating the two rows. In different embodiments, multiple connected pixels can be multiple columns in the same row. The T1 transistor of a certain column of pixels can be connected to the T2 transistor of another pixel in the same row that is adjacent to it or separated by one or more columns. Or, between multiple pixels in different rows and different columns in a pixel array, their respective T1 transistors are connected to the T2 transistors of other pixels. Or, in the same pixel array, different pixels are combined and connected together, and multiple connection groups are formed at the same time (the T1 transistors of the pixels in each connection group are connected to the T2 transistors of other pixels in the group); the combination relationship between pixel units in different connection groups can be the same or different. For example, when the combination relationship is different, the pixel units in the odd rows in the same column can be connected into one group, and the pixel units in the even rows can be connected into another group; or the pixel units in the odd columns in the same row can be connected into one group, and the pixel units in the even columns can be connected into another group. Another example is that in a certain connection group, every two connected pixel units belong to adjacent rows or adjacent columns; in a certain connection group, every two connected pixel units are separated by one row or one column; in a certain connection group, every two connected pixel units are separated by multiple rows or multiple columns; in a certain connection group, each connected pixel unit is in a different row and a different column, and so on.

[0074] In addition, in some embodiments, each pixel unit is further provided with a basic capacitor, which can have a fixed capacitance value. Exemplarily, the basic capacitor C 01 can be coupled to the connection node between the T1 or T2 transistor of a pixel unit and the floating diffusion region FD (see Figure 4 ), then regardless of the switching states of the T1 and T2 transistors, at least the capacitance value of the basic capacitor C 01 can be connected to the floating diffusion region FD.

[0075] In summary, in the solution of the present invention, transistors T1 and T2 with shared control terminals are added for each pixel unit, and are respectively connected and shared with the transistors T2' and T1" of two other pixel units, forming a variable capacitor that can be shared by different pixel units; in multiple connected pixel units, by controlling the number of pairs of transistors that conduct in one or some pixel units, the capacitance size of the conversion gain can be adjusted, so as to design multiple gears of conversion gain, and select an appropriate conversion gain gear according to the current scenario, making the signal-to-noise ratio of the entire image optimal and reducing the signal-to-noise ratio loss.

[0076] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to the present invention. Such modifications, improvements, and corrections are proposed in the present invention, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention.

[0077] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A driving method for a pixel circuit, the pixel circuit comprising: A pixel unit, and one or more of the pixel units form a pixel array; Each of the pixel units includes: One or more photodiodes; One or more first transistors, correspondingly connected to the one or more photodiodes; the first transistor is coupled between the corresponding photodiode and a floating diffusion region of the present pixel unit; A second transistor, coupled between a power supply voltage and the floating diffusion region of the present pixel unit; A third transistor, coupled between a first capacitor and the floating diffusion region of the present pixel unit; characterized in that each pixel unit further includes a fourth transistor and a fifth transistor sharing a control terminal; Wherein, there are at least a first pixel unit, a second pixel unit and a third pixel unit; The fourth transistor of the first pixel unit is coupled between the floating diffusion region of the first pixel unit and one end of the fifth transistor of the second pixel unit; the other end of the fifth transistor of the second pixel unit is coupled to the floating diffusion region of the second pixel unit; The fifth transistor of the first pixel unit is coupled between the floating diffusion region of the first pixel unit and one end of the fourth transistor of the third pixel unit, and the other end of the fourth transistor of the third pixel unit is coupled to the floating diffusion region of the third pixel unit; The driving method includes controlling the number of the shared control terminals of one or more pixel units among the first pixel unit, the second pixel unit and the third pixel unit to control the gain level.

2. The driving method of the pixel circuit according to claim 1, wherein The first pixel unit, the second pixel unit and the third pixel unit are located in the same column; Or, the first pixel unit, the second pixel unit and the third pixel unit are located in the same row; or, the first pixel unit, the second pixel unit and the third pixel unit are not located in the same column and not located in the same row.

3. The driving method of the pixel circuit according to claim 2, wherein The first pixel unit, the second pixel unit and the third pixel unit are located in adjacent rows or adjacent columns.

4. The driving method of the pixel circuit according to claim 2, characterized in that The first pixel unit is separated from the second pixel unit and the third pixel unit by i rows respectively, where i≥1 and i is an integer; And / or, the first pixel unit is separated from the second pixel unit and the third pixel unit by j columns respectively, where j≥1 and j is an integer.

5. The driving method of the pixel circuit according to claim 4, characterized in that In at least one column of pixel units, the fourth transistors of any odd rows and the fifth transistors of adjacent odd rows are pairwise connected to form a first connection group with non-shared control terminals; the fourth transistors of any even rows and the fifth transistors of adjacent even rows are pairwise connected to form a second connection group with non-shared control terminals; or, in at least one row of pixel units, the fourth transistors of any odd columns and the fifth transistors of adjacent odd columns are pairwise connected to form a first connection group with non-shared control terminals, and the fourth transistors of even columns and the fifth transistors of adjacent even columns are pairwise connected to form a second connection group with non-shared control terminals.

6. The driving method of the pixel circuit according to any one of claims 1 to 4, characterized in that, In at least one column of pixel units, one end of the fourth transistor of the first row of pixel units is connected to the fifth transistor of the next row, and the other end of the fourth transistor of the first row of pixel units is grounded; one end of the fifth transistor of the last row of pixel units in the same column is connected to the fourth transistor of the previous row, and the other end of the fifth transistor of the last row of pixel units is grounded. Alternatively, in at least one row of pixel units, one end of the fourth transistor of the first column of pixel units is connected to the fifth transistor of the next column, and the other end of the fourth transistor of the first column of pixel units is grounded; one end of the fifth transistor of the last column of pixel units in the same row is connected to the fourth transistor of the previous column, and the other end of the fifth transistor of the last column of pixel units is grounded.

7. The driving method of the pixel circuit according to claim 1, characterized in that The fourth transistor and the fifth transistor having a shared control terminal are fabricated within or outside the region of the present pixel unit.

8. The driving method of the pixel circuit according to claim 1, wherein Each of the pixel units includes 4, or 8, or 9, or 16 of the photodiodes.

9. The driving method of the pixel circuit according to claim 1, wherein, Each of the pixel units further includes a second capacitor; the second capacitor is coupled to the connection node between the fourth transistor and the floating diffusion region of the present pixel unit, or is coupled to the connection node between the fifth transistor and the floating diffusion region of the present pixel unit.

10. The driving method of the pixel circuit according to any one of claims 1 to 9, characterized in that Each of the pixel units further includes: a sixth transistor, the control terminal of which is connected to the floating diffusion region of the present pixel unit; a seventh transistor, coupled between the sixth transistor and the signal output line of the present pixel unit for selective output.

11. The driving method of the pixel circuit according to claim 10, wherein the first transistor includes a transfer transistor; the second transistor includes a reset transistor; the third transistor includes a gain conversion transistor; the sixth transistor includes a source follower transistor; the seventh transistor includes a selective output transistor.

12. The driving method of the pixel circuit according to claim 11, wherein the fourth transistor and / or the fifth transistor are fabricated synchronously with at least one of the first, second, third, sixth, and seventh transistors.

13. A pixel circuit applied to the driving method according to any one of claims 1 to 12.

Images