Semiconductor structure

Abstract

The invention provides a semiconductor structure, relates to the technical field of semiconductors, and is used for solving the technical problems of relatively low yield and reliability. The semiconductor structure comprises an array chip and a control chip which are bonded, wherein the array chip comprises a word line, a bit line, a first connecting pad, a second connecting pad, a first connecting structure and a second connecting structure. The first connection structure connects the bit line and the first connection pad, and the second connection structure connects the word line and the second connection pad. The control chip comprises a sensing circuit, a driving circuit, a third connecting pad and a fourth connecting pad. The third connecting pad is correspondingly connected with the first connecting pad and is connected with the sensing circuit, and the fourth connecting pad is correspondingly connected with the second connecting pad and is connected with the driving circuit, so that on the basis of realizing that the sensing circuit controls bit lines and the driving circuit controls word lines, the condition of line breakage caused by overlarge height difference between the array chip and the control chip can be avoided; and the yield and the reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure. Background Art

[0002] With the continuous development of semiconductor technology and storage technology, electronic devices are constantly evolving towards miniaturization and integration. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] A dynamic random access memory has an array region and a peripheral region. The array region is provided with a plurality of word lines (WL for short), bit lines (BL for short), and a plurality of memory cells. Each memory cell typically includes a control transistor and a capacitor. The gate of the control transistor is electrically connected to the word line, one of the source and drain is electrically connected to the bit line, and the other of the source and drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the control transistor, so that data information stored in the capacitor can be read through the bit line, or data information can be written into the capacitor. The peripheral region is provided with a driving circuit for a plurality of word lines and a sensing circuit for a plurality of bit lines.

[0004] However, the height of the memory cells in the array region is continuously increasing, and the yield and reliability of the semiconductor structure are continuously decreasing. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure to improve its yield and reliability.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, which includes an array chip and a control chip bonded to each other;

[0007] The array chip includes:

[0008] Word lines and bit lines, the word lines and the bit lines intersect and are arranged on the array chip to form an array region;

[0009] A first connection pad, the first connection pad is arranged in a first region and a second region respectively near both ends of the bit line in the array region;

[0010] A second connection pad, the second connection pad is arranged in a third region and a fourth region of the array region, and the third region and the fourth region are located between the first region and the second region;

[0011] A first connection structure, the first connection structure connects the bit line and the first connection pad;

[0012] A second connection structure that connects the word line and the second connection pad;

[0013] The control chip includes:

[0014] A sensing circuit for controlling the bit line;

[0015] A driving circuit for controlling the word line;

[0016] A third connection pad that is correspondingly connected to the first connection pad and is connected to the sensing circuit;

[0017] A fourth connection pad that is correspondingly connected to the second connection pad and is connected to the driving circuit.

[0018] In some possible implementation manners, the array chip and the control chip are hybrid-bonded.

[0019] In some possible implementation manners, the array chip further includes a first stacked structure, and the word line, the bit line, the first connection structure, and the second connection structure are all located in the first stacked structure, and the first connection pad and the second connection pad are both exposed on the surface of the first stacked structure facing the control chip;

[0020] The control chip further includes a second stacked structure, and the sensing circuit and the control circuit are both located in the second stacked structure, and the third connection pad and the fourth connection pad are both exposed on the surface of the second stacked structure facing the array chip;

[0021] And / or, the first connection structure is axially symmetrically distributed, and the second connection structure is centrosymmetrically distributed.

[0022] In some possible implementation manners, the array chip includes a plurality of the array regions;

[0023] The sensing circuit includes two sub-sensing circuits, and the projections of the two sub-sensing circuits on the array chip are respectively located in two adjacent array regions and are respectively close to the adjacent ends of the bit line;

[0024] The driving circuit includes two sub-driving circuits, and the projections of the two sub-driving circuits on the array chip are respectively located in the same array region and are respectively close to the two ends of the word line.

[0025] In some possible implementation manners, the fourth connection pads corresponding to the second connection pads in the third region and the fourth region of the same array region are respectively connected to the sub-driving circuits of two different driving circuits;

[0026] And / or, the third connection pads corresponding to the first connection pads of the first region and the second region of the same array region are respectively connected to different sensing circuits.

[0027] In some possible implementation manners, along the first direction, there are at least N first connection pads in both the first region and the second region of each array region, where N is a positive integer greater than 1;

[0028] The bit lines of each array region are divided into a plurality of bit line groups, each bit line group includes 2N adjacent bit lines, the first ends of N bit lines in the same group are respectively connected to N first connection pads arranged along the first direction in the first region, and the second ends of the remaining N bit lines are respectively connected to N first connection pads arranged along the first direction in the second region.

[0029] In some possible implementation manners, the bit lines arranged in odd positions are correspondingly connected to the first connection pads of the first region, and the bit lines arranged in even positions are correspondingly connected to the first connection pads of the second region.

[0030] In some possible implementation manners, the third region includes a first sub-region, and a second sub-region and a third sub-region provided in the first sub-region away from the fourth region, the second sub-region is adjacent to the second region, the fourth region includes a fourth sub-region, and a fifth sub-region and a sixth sub-region provided in the fourth sub-region away from the third region, the fifth sub-region is adjacent to the first region;

[0031] Along the first direction, both the third region and the fourth region have at least M second connection pads; along the second direction, each of the third sub-region and the fifth sub-region of each array region has at least P second connection pads, where M and P are positive integers greater than 1, and the second direction intersects with the first direction;

[0032] The word lines located in the third sub-region and the fifth sub-region are divided into a plurality of first word line groups, each first word line group includes 2P adjacent word lines, the first ends of P word lines in the same group in the third sub-region are respectively correspondingly connected to P second connection pads arranged along the second direction in the third sub-region, and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines of the corresponding group of the adjacent array region connected to the second connection pads;

[0033] The second ends of P word lines in the same group within the fifth partition are respectively and correspondingly connected to P second connection pads arranged along the second direction within the fifth partition, and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region that are connected to the second connection pads;

[0034] The word lines located in the first region and the second region are evenly divided into a plurality of second word line groups, and each second word line group includes 2M adjacent word lines. The second ends of M word lines in the same group within the first region are respectively and correspondingly connected to M second connection pads arranged along the first direction within the fourth partition, and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region that are connected to the second connection pads;

[0035] The first ends of M word lines in the same group within the second region are respectively and correspondingly connected to M second connection pads arranged along the first direction within the first partition, and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region that are connected to the second connection pads.

[0036] In some possible implementation manners, the control chip further includes a first contact plug disposed between the sensing circuit and the third connection pad, and the first contact plug is arranged in a zigzag pattern on the sensing circuit;

[0037] And / or, the control chip further includes a second contact plug disposed between the driving circuit and the fourth connection pad, and the second contact plug is arranged in a zigzag pattern on the driving circuit.

[0038] In some possible implementation manners, the control chip further includes a control circuit, and the traces of the control circuit pass between the first contact plug and / or the second contact plug.

[0039] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0040] The semiconductor structure provided by the embodiments of the present disclosure includes an array chip and a control chip. The array chip includes word lines, bit lines, a first connection pad, a second connection pad, a first connection structure, and a second connection structure. The first connection structure connects the bit line to the first connection pad, and the second connection structure connects the word line to the second connection pad. The control chip includes a sensing circuit, a driving circuit, a third connection pad, and a fourth connection pad. The third connection pad is connected to the sensing circuit, and the fourth connection pad is connected to the driving circuit. By bonding the array chip and the control chip, the third connection pad is correspondingly connected to the first connection pad, and the fourth connection pad is correspondingly connected to the second connection pad. On the basis of realizing that the sensing circuit controls the bit line and the driving circuit controls the word line, the situation of disconnection caused by too large a height difference between the array chip and the control chip can be avoided, and the yield and reliability of the semiconductor structure are improved. In addition, the word lines and the bit lines form an array region on the array chip. The first connection pads are arranged in a first region and a second region of the array region near both ends of the bit line respectively, and the second connection pads are arranged in a third region and a fourth region of the array region. The third region and the fourth region are located between the first region and the second region, so that the first connection pads and the second connection pads are arranged in a partitioned manner in the array region, which is convenient for wiring. Description of the Drawings

[0041] Figure 1 Schematic diagram before bonding the control chip and the array chip in an embodiment of the present disclosure;

[0042] Figure 2 Schematic diagram after bonding the control chip and the array chip in an embodiment of the present disclosure;

[0043] Figure 3 Schematic diagram of the array region in an embodiment of the present disclosure;

[0044] Figure 4 Schematic diagram of the connection between the first connection structure and the first connection pad in an embodiment of the present disclosure;

[0045] Figure 5 Partial schematic diagram of the second connection structure and the second connection pad in an embodiment of the present disclosure;

[0046] Figure 6 Schematic diagram of the connection between the second connection structure and the second connection pad in an embodiment of the present disclosure;

[0047] Figure 7 Schematic diagram of the control chip in an embodiment of the present disclosure;

[0048] Figure 8 Top view position diagram of the sensing circuit and the first contact plug in an embodiment of the present disclosure;

[0049] Figure 9 is Figure 8 Cross-sectional schematic diagram at A-A in

[0050] Description of reference numerals:

[0051] 10-array chip; 11-array area; 12-first area; 13-second area; 14-first partition; 15-second partition; 16-third partition; 17-fourth partition; 18-fifth partition; 19-sixth partition;

[0052] 20-control chip; 21-control area;

[0053] 31-first connection pad; 32-second connection pad; 33-third connection pad;

[0054] 41-first connection structure; 42-second connection structure; 43-third connection structure; 44-fourth connection structure;

[0055] 51 - second substrate; 52 - second stacking structure; 53 - first contact plug;

[0056] 61 - a first end of a bit line;

[0057] 71 - sensing circuit; 72 - sub-sensing circuit; 73 - driving circuit; 74 - sub-driving circuit; 75 - control circuit; 76 - routing. DETAILED DESCRIPTION

[0058] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0059] See also Figures 1 to 9 The embodiment of the present disclosure provides a semiconductor structure, which includes an array chip 10 and a control chip 20. The array chip 10 is used to store data, and the control chip 20 is used to control the writing or reading of data in the array chip 10. The array chip 10 and the control chip 20 are bonded, and illustratively, the array chip 10 and the control chip 20 are hybrid bonded (HybridBonding), and the hybrid bonding can include metal-metal bonding and dielectric-dielectric bonding at the same time.

[0060] The height of the array chip 10 is relatively high, while the height of the control chip 20 is relatively low. By separately manufacturing the array chip 10 and the control chip 20 and attaching them face to face, compared with manufacturing the array chip 10 and the control chip 20 on the same layer, the influence of the height difference between the array chip 10 and the control chip 20 on manufacturing can be reduced, the connection disconnection caused by the height difference between the array chip 10 and the control chip 20 can be avoided, and the yield and reliability of the semiconductor structure can be improved.

[0061] Refer to Figure 3 , the array chip 10 includes word lines and bit lines. The word lines and the bit lines are arranged intersectingly on the array chip 10 to form an array region 11. There can be multiple array regions 11, and both the word lines and the bit lines can have multiple ones. The multiple word lines and the multiple bit lines intersect vertically and are spaced apart from each other. Exemplarily, the bit lines extend in a first direction and are arranged at intervals in a second direction, the word lines extend in the second direction and are arranged at intervals in the first direction, and the first direction intersects with the second direction, for example, is perpendicular. The first direction is like Figure 1 the Y direction shown in Figure 1 , and the second direction is like

[0062] The array region 11 includes a first region 12, a second region 13, a third region, and a fourth region. The first region 12 and the second region 13 are respectively close to both ends of the bit line, and both the third region and the fourth region are located between the first region 12 and the second region 13. Among them, the first region 12 and the second region 13 are oppositely arranged along the extension direction of the bit line (i.e., along the first direction), the first region 12 is close to the first end of the bit line, and the second region 13 is close to the second end of the bit line. As Figure 3 shown, the first region 12 and the second region 13 are arranged one above the other, the first region 12 is located above, and the second region 13 is located below.

[0063] The third region is located between the first region 12 and the second region 13, and the fourth region is located between the first region 12 and the second region 13. The third region and the fourth region are arranged side by side. For example, the third region and the fourth region are oppositely arranged along the extension direction of the word line (i.e., along the second direction). As Figure 3 shown, the third region and the fourth region are arranged side by side left and right, the third region is located on the left, and the fourth region is located on the right.

[0064] In some possible examples, the third region includes a first sub-region 14, and a second sub-region 15 and a third sub-region 16 arranged away from the fourth region in the first sub-region 14. The third sub-region 16 is adjacent to the second region 13, that is, the second sub-region 15 is adjacent to the first region 12. The fourth region includes a fourth sub-region 17, and a fifth sub-region 18 and a sixth sub-region 19 arranged away from the third region in the fourth sub-region 17. The fifth sub-region 18 is adjacent to the first region 12, that is, the sixth sub-region 19 is adjacent to the second region 13.

[0065] Among them, the second partition 15 and the third partition 16 are arranged opposite to each other in the first direction, and the fifth partition 18 and the sixth partition 19 are arranged opposite to each other in the first direction. The second partition 15 and the fifth partition 18 are arranged opposite to each other in the second direction, and the third partition 16 and the sixth partition 19 are arranged opposite to each other in the second direction. The first partition 14, the second partition 15, the third partition 16, the fourth partition 17, the fifth partition 18, and the sixth partition 19 are symmetrically distributed about the center as a whole.

[0066] Refer to Figures 4 to 6 , the array chip 10 further includes a first connection structure 41, a second connection structure 42, a first connection pad 31, and a second connection pad 32. The first connection structure 41 connects the bit line to the first connection pad 31, and the second connection structure 42 connects the word line to the second connection pad 32. The first connection pad 31 is disposed in a first region 12 and a second region 13 of the array region 11 near both ends of the bit line respectively, and the second connection pad 32 is disposed in a third region and a fourth region of the array region 11. There are a plurality of first connection pads 31 and a plurality of second connection pads 32. A plurality of first connection pads 31 are respectively disposed in the first region 12 and the second region 13, and a plurality of second connection pads 32 are respectively disposed in the third region and the fourth region.

[0067] The plurality of first connection pads 31 and the plurality of second connection pads 32 are distributed in an array as a whole. For example, the plurality of first connection pads 31 are arranged at intervals in the first direction and at intervals in the second direction, and the plurality of second connection pads 32 are arranged at intervals in the first direction and at intervals in the second direction. The first direction is the row direction, and the second direction is the column direction.

[0068] The sum of the number of columns of the second connection pads 32 in the third region and the fourth region is equal to the number of columns of the first connection pads 31 in the first region 12 and is equal to the number of columns of the first connection pads 31 in the second region 13. One column of the second connection pads 32 in the third region is aligned with one column of the first connection pads 31 in the first region 12 and one column of the first connection pads 31 in the second region 13, and one column of the second connection pads 32 in the fourth region is aligned with one column of the first connection pads 31 in the first region 12 and one column of the first connection pads 31 in the second region 13. The number of rows of the second connection pads 32 in the third region is equal to the number of rows of the fourth connection pads. One row of the second connection pads 32 in the third region is aligned with one row of the second connection pads 32 in the fourth region.

[0069] In an example where the third region includes the first partition 14, the second partition 15, and the third partition 16, and the fourth region includes the fourth partition 17, the fifth partition 18, and the sixth partition 19, the third partition 16 and the sixth partition 19 can be dummy regions, or the second partition 15 and the fifth partition 18 can be dummy regions, and the second connection pads 32 of the dummy regions are not connected.

[0070] In some possible implementation manners, refer to Figure 4and Figure 5 Along the first direction, in the first region 12 and the second region 13 of each array region 11, there are at least N first connection pads 31, where N is a positive integer greater than 1. Exemplarily, along the first direction, the first region 12 of each array region 11 has 10 first connection pads 31, and the second region 13 of each array region 11 has 10 first connection pads 31.

[0071] The bit lines of each array region 11 are divided into multiple bit line groups, each bit line group includes 2N adjacent bit lines, and the first ends 61 of N bit lines in the same group are respectively connected to N first connection pads 31 arranged along the first direction in the first region 12, and the second ends of the remaining N bit lines are respectively connected to N first connection pads 31 arranged along the first direction in the second region 13.

[0072] Exemplarily, the bit lines of each array region 11 can be divided into multiple bit line groups, each bit line group includes 20 adjacent bit lines. Among the 20 bit lines in the same bit line group, the first ends 61 of 10 bit lines are respectively connected to 10 first connection pads 31 arranged along the first direction in the first region 12 through a part of the first connection structure 41, and the second ends of the remaining 10 bit lines are respectively connected to 10 first connection pads 31 arranged along the first direction in the second region 13 through another part of the first connection structure 41, so as to reduce the arrangement density of the first connection structure 41 and facilitate wiring.

[0073] Among them, the bit lines ranked in odd positions are correspondingly connected to the first connection pads 31 in the first region 12, and the bit lines ranked in even positions are correspondingly connected to the first connection pads 31 in the second region 13. Specifically, along the first direction, the first ends 61 (such as the upper ends) of the 1st bit line, the 3rd bit line,..., the (2k + 1)th bit line are connected to the first connection pads 31 in the first region 12 through a part of the first connection structure 41, and the second ends (such as the lower ends) of the 2nd bit line, the 4th bit line,..., the 2kth bit line are connected to the first connection pads 31 in the second region 13 through another part of the first connection structure 41, so as to improve the symmetry of the first connection structure 41. Where k is a positive integer greater than 1.

[0074] It can be understood that along the second direction, the number of first connection pads 31 in each of the first region 12 and the second region 13 is adapted to the number of bit lines, and the specific value is at least greater than the number of bit lines divided by 2N, that is, at least greater than the number of bit line groups divided by the bit lines. When the number of bit lines is difficult to be evenly divided into multiple bit line groups, the number of bit lines in one of the bit line groups can be less than 2N, and the number of bit lines in the remaining bit line groups is 2N. The first ends 61 of some bit lines in the bit line group with fewer bit lines are connected to I corresponding first connection pads 31 in the first region 12, and the second ends of the other part of the bit lines are connected to L corresponding first connection pads 31 in the second region 13, where both I and L are less than or equal to N, and the sum of I and L is less than 2N.

[0075] Refer to Figure 3 and Figure 6 Along the first direction, both the third region and the fourth region each have at least M second connection pads 32; along the second direction, both the third partition 16 and the fifth partition 18 each have at least P second connection pads 32, where M and P are both positive integers greater than 1. Exemplarily, along the first direction, the third region of each array region 11 has 9 second connection pads 32, and the fourth region has 9 second connection pads 32. Along the second direction, the third partition 16 has 14 second connection pads 32, and the fifth partition 18 has 14 second connection pads 32.

[0076] The word lines located in the third partition 16 and the fifth partition 18 are divided into multiple first word line groups, each first word line group includes 2P adjacent word lines, and the first ends of P word lines in the same group within the third partition 16 are respectively connected to P second connection pads 32 arranged along the second direction within the third partition 16 where they are located. The first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region 11 that are connected to the second connection pads 32.

[0077] The second ends of P word lines in the first word line group of the same group in the fifth partition 18 are respectively connected to P second connection pads 32 arranged along the second direction within the fifth partition 18. The second ends of the remaining P word lines in this first word line group are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region 11, and the second ends of these P word lines in the corresponding group are connected to the opposite second connection pads 32.

[0078] In some possible examples, the word lines within the third partition 16 of each array region 11 are divided into multiple first word line groups, each first word line group includes 28 adjacent word lines. Among the 28 word lines in the same first word line group within the third partition 16, the first ends of 14 word lines are respectively connected to 14 second connection pads 32 arranged along the second direction within the third partition 16 through a partial second connection structure 42. The first ends of the remaining 14 word lines are connected to the second ends of 14 word lines in the opposite first word line group in the adjacent array region 11 (such as the left array region 11) that are connected to the second connection pads 32. The connection manner between the word lines within the fifth partition 18 of each array region 11 and the second connection pads 32 refers to the connection manner between the word lines within the third partition 16 and the second connection pads 32.

[0079] For example, in two corresponding first word line groups in adjacent array regions 11, the first ends of the word lines arranged in odd positions in each first word line group are all connected to the second connection pads 32, and the first ends of the word lines arranged in even positions in one of the first word line groups are respectively connected to the first ends of the word lines arranged in odd positions in the other first word line group.

[0080] Continue to refer to Figure 3 and Figure 6, the word lines in the first region 12 and the second region 13 are evenly divided into a plurality of second word line groups, each second word line group includes 2M adjacent word lines. The second ends of M word lines in the same group in the first region 12 are respectively connected to M second connection pads 32 arranged along the first direction in the fourth partition 17, and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group in the adjacent array region 11 that are connected to the second connection pads 32.

[0081] The word lines in the second region 13 are divided into a plurality of second word line groups, each second word line group includes 2M adjacent word lines. The first ends of M word lines in the same second word line group in the second region 13 are respectively connected to M second connection pads 32 arranged along the second direction in the first partition 14. The first ends of the remaining M word lines in this second word line group are respectively connected to the second ends of M word lines in the corresponding group in the adjacent array region 11, and the first ends of these M word lines in the corresponding group are connected to the opposite second connection pads 32.

[0082] In some possible examples, the word lines in the first region 12 of each array region 11 are divided into a plurality of second word line groups, each second word line group includes 18 adjacent word lines. Among the 18 word lines in the same second word line group in the first region 12, the second ends of 9 word lines are respectively connected to 9 second connection pads 32 arranged along the first direction in the fourth partition 17 through part of the second connection structure 42. The second ends of the remaining 9 word lines are connected to the first ends of 9 word lines in the opposite second word line group in the adjacent array region 11 (such as the left array region 11) that are connected to the second connection pads 32. The connection manner between the word lines in the second region 13 of each array region 11 and the second connection pads 32 in the first partition 14 refers to the connection manner between the word lines in the first region 12 and the second connection pads 32 in the fourth partition 17.

[0083] In order to realize the support and fabrication of the first connection structure 41, the second connection structure 42, the first connection pads 31 and the second connection pads 32, in some possible examples, the array chip 10 further includes a first substrate and a first stacked structure disposed on the first substrate. The first substrate is a semiconductor substrate, such as a single crystal silicon substrate, a single crystal germanium substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc., and it can be a P-type doped semiconductor substrate or an N-type doped semiconductor substrate.

[0084] Among them, the word lines, bit lines, the first connection structure 41 and the second connection structure 42 are all located in the first stacked structure. Among them, the word lines and bit lines can partially extend into the first substrate or be completely located on the first substrate. The first connection pads 31 and the second connection pads 32 are both exposed on the surface of the first stacked structure facing the control chip 20. The first connection pads 31 and the second connection pads 32 are arranged in the same layer for easy external connection.

[0085] Refer to Figures 7 to 9, the control chip 20 includes a sensing circuit 71, a driving circuit 73, a third connection pad 33, and a fourth connection pad. The sensing circuit 71 is used to control the bit lines to perform sensing and amplification during the data reading phase. The driving circuit 73 is used to control the word lines to drive the corresponding word lines. The third connection pad 33 is correspondingly connected to the first connection pad 31 and is connected to the sensing circuit 71 to realize the connection between the sensing circuit 71 and the bit lines. The fourth connection pad is correspondingly connected to the second connection pad 32 and is connected to the driving circuit 73 to realize the connection between the driving circuit 73 and the word lines.

[0086] Among them, the third connection pad 33 and the corresponding first connection pad 31 have at least a partial overlapping area. For example, the arrangement pattern of the third connection pad 33 is the same as that of the first connection pad 31. The third connection pad 33 and the corresponding first connection pad 31 are in one-to-one correspondence and completely coincide to make full use of the space of the array chip 10 and the control chip 20 and facilitate the manufacture of the third connection pad 33 and the first connection pad 31.

[0087] The fourth connection pad and the second connection pad 32 have at least a partial overlapping area. For example, the arrangement pattern of the fourth connection pad is the same as that of the second connection pad 32. The fourth connection pad and the corresponding second connection pad 32 are in one-to-one correspondence and completely coincide to make full use of the space of the array chip 10 and the control chip 20 and facilitate the manufacture of the fourth connection pad and the second connection pad 32.

[0088] It can be understood that the control chip 20 has a control area 21, and the orthographic projection of the control area 21 on the array chip 10 coincides with the array area 11. In an example where the array chip 10 includes multiple array areas 11, the control chip 20 includes multiple control areas 21, and the control areas 21 are in one-to-one correspondence with the array areas 11. The structure of each control area 21 and the positions of the third connection pad 33 and the fourth connection pad therein refer to the structure of the corresponding array area 11 and the positions of the first connection pad 31 and the second connection pad 32 therein, for example, being the same.

[0089] In some possible examples, the array chip 10 includes multiple array areas 11, the sensing circuit 71 includes two sub-sensing circuits 72, and the projections of the two sub-sensing circuits 72 on the array chip 10 are respectively located in two adjacent array areas 11 and are respectively close to one end where the bit lines are adjacent to each other. Among them, the two sub-sensing circuits 72 are arranged in a staggered manner along the arrangement direction of the bit lines to facilitate the connection between the two sub-sensing circuits 72 and the third connection pad 33.

[0090] As Figure 7 shown, the two sub-sensing circuits 72 are arranged one above the other and are staggered left and right. The projection of one sub-sensing circuit 72 on the array chip 10 is adjacent to the second end of the bit line in one array area 11, and the projection of the other sub-sensing circuit 72 on the array chip 10 is adjacent to the first end 61 of the bit line in the other array area 11.

[0091] Based on the above example, in some possible implementation manners, the third connection pads 33 corresponding to the first connection pads 31 in the first region 12 and the second region 13 of the same array region 11 are respectively connected to different sensing circuits 71. As Figure 7 shown, a sub-sensing circuit 72 of a sensing circuit 71 is correspondingly provided at the first end 61 of the bit line in the same array region 11, and a sub-sensing circuit 72 of another sensing circuit 71 is correspondingly provided at the second end of the bit line in the array region 11.

[0092] For ease of description, the two sensing circuits 71 correspondingly connected to one array region 11 are respectively defined as a first sensing circuit and a second sensing circuit, and both the first sensing circuit and the second sensing circuit include two sub-sensing circuits 72. The projections of a sub-sensing circuit 72 of the first sensing circuit and a sub-sensing circuit 72 of the second sensing circuit on the array chip 10 are both located in the corresponding array region 11, and the projections of the other sub-sensing circuit 72 of the first sensing circuit and the other sub-sensing circuit 72 of the second sensing circuit on the array chip 10 are respectively located in the array regions 11 on both sides of the corresponding array region 11.

[0093] Among them, the third connection pads 33 corresponding to the first connection pads 31 in the first region 12 of one array region 11 are connected to the first sensing circuit. These third connection pads 33 are connected to the two sub-sensing circuits 72 of the first sensing circuit in the vicinity. Among these third connection pads 33, the left-side part of these third connection pads 33 is connected to the sub-sensing circuit 72 whose projection is located in this array region 11 in the first sensing circuit, and the right-side part of these third connection pads 33 is connected to the sub-sensing circuit 72 whose projection is located in the adjacent array region 11 in the first sensing circuit. The third connection pads 33 corresponding to the first connection pads 31 in the second region 13 of the array region 11 are connected to the second sensing circuit. These third connection pads 33 are connected to the two sub-sensing circuits 72 of the second sensing circuit in the vicinity. Among these third connection pads 33, the right-side part of these third connection pads 33 is connected to the sub-sensing circuit 72 whose projection is located in this array region 11 in the second sensing circuit, and the left-side part of these third connection pads 33 is connected to the sub-sensing circuit 72 whose projection is located in the adjacent array region 11 in the second sensing circuit.

[0094] Exemplarily, among the third connection pads 33 corresponding to the first connection pads 31 in the first region 12 of one array region 11, a plurality of third connection pads 33 arranged along the first direction are respectively connected to one ends of adjacent plurality of first lines 77 in the two sub-sensing circuits 72 of the first sensing circuit, and the other ends of these first lines 77 are respectively connected to the third connection pads 33 corresponding to the second connection pads 32 in the second region 13 of the adjacent array region 11.

[0095] In the third connection pads 33 corresponding to the first connection pads 31 in the second region 13 of an array region 11, a plurality of third connection pads 33 arranged along the first direction are respectively connected to one ends of adjacent plurality of second lines in two sub-sensing circuits 72 of the second sensing circuit, and the other ends of these second lines are respectively connected to the third connection pads 33 corresponding to the second connection pads 32 in the first region 12 of the adjacent array region 11.

[0096] With such an arrangement, the bit lines in two adjacent array regions 11 are respectively connected to two ends of the same first line 77. When reading data from one of the bit lines, the other bit line can be used as a reference bit line. The connection manner between the first line 77 and the corresponding third connection pad 33, and the connection manner between the second line and the corresponding third connection pad 33 can refer to the connection manner between the bit line and the first connection pad 31.

[0097] For ease of understanding, the control region 21 includes a fifth region, a sixth region, a seventh region, and an eighth region, and the fifth region, the sixth region, the seventh region, and the eighth region respectively correspond to the first region 12, the second region 13, the third region, and the fourth region. Along the first direction, there are at least N third connection pads 33 in the fifth region and the sixth region of each control region 21, where N is a positive integer greater than 1.

[0098] Both of the two sub-sensing circuits 72 of the first sensing circuit include a plurality of first lines 77. The first lines 77 of each sub-sensing circuit 72 are divided into a plurality of first line groups, and each first line group includes adjacent N first lines 77. One ends of the N first lines 77 in the same group are connected to N third connection pads 33 arranged along the first direction in the fifth region of one of the two adjacent control regions 21, and the other ends are connected to N third connection pads 33 arranged along the first direction in the sixth region of the other control region 21.

[0099] Both of the two sub-sensing circuits 72 of the second sensing circuit include a plurality of second lines. The second lines of each sub-sensing circuit 72 are divided into a plurality of second line groups, and each second line group includes adjacent N second lines. One ends of the N second lines in the same group are connected to N third connection pads 33 arranged along the first direction in the sixth region of one of the two adjacent control regions 21, and the other ends are connected to N third connection pads 33 arranged along the first direction in the fifth region of the other control region 21.

[0100] Among them, the third connection pads 33 in the sixth region connected to the second line and the third connection pads 33 in the fifth region connected to the first line 77 are located in the same control region 21. The third connection pads 33 in the fifth region connected to the second line and the third connection pads 33 in the sixth region connected to the first line 77 are respectively located in two control regions 21 on both sides of the control region 21.

[0101] Continue to refer to Figure 2 , the driving circuit 73 includes two sub-driving circuits 74. The projections of the two sub-driving circuits 74 on the array chip 10 are located in the same array region 11 and are respectively close to both ends of the word line. Among them, the two sub-driving circuits 74 are arranged in a staggered manner along the arrangement direction of the word line to facilitate the connection of the two sub-driving circuits 74 to the fourth connection pads.

[0102] Specifically, the projections of the two sub-driving circuits 74 on the array chip 10 are located in the same array region 11, and are opposite to each other along the second direction and staggered along the first direction. One end of the word line in the same array region 11 is correspondingly provided with a sub-driving circuit 74 of the driving circuit 73, and the other end of the word line in this array region 11 is correspondingly provided with the sub-driving circuit 74 of the driving circuit 73.

[0103] Based on the above example, in some possible implementation manners, the fourth connection pads corresponding to the second connection pads 32 in the third region and the fourth region of the same array region 11 are respectively connected to the sub-driving circuits 74 of the same driving circuit 73. Among them, the fourth connection pad corresponding to the second connection pad 32 in the third region is connected to one of the sub-driving circuits 74, and the fourth connection pad corresponding to the second connection pad 32 in the fourth region is connected to the other sub-driving circuit 74. The connection manner between the fourth connection pad and the corresponding sub-driving circuit 74 can refer to the connection manner between the word line and the second connection pad 32.

[0104] In the example where the control region 21 includes a fifth region, a sixth region, a seventh region, and an eighth region, the seventh region includes a seventh sub-region, an eighth sub-region, and a ninth sub-region, and the eighth region includes a tenth sub-region, an eleventh sub-region, and a twelfth sub-region. The seventh sub-region, the eighth sub-region, the ninth sub-region, the tenth sub-region, the eleventh sub-region, and the twelfth sub-region are respectively opposite to the first sub-region 14, the second sub-region 15, the third sub-region 16, the fourth sub-region 17, the fifth sub-region 18, and the sixth sub-region 19.

[0105] Both of the two sub-control circuits 75 include a plurality of third lines. The plurality of third lines located in the fifth region and the sixth region are respectively correspondingly connected to a plurality of fourth connection pads in the tenth sub-region and the eleventh sub-region. The plurality of third lines located in the ninth sub-region and the eleventh sub-region are respectively correspondingly connected to a plurality of fourth connection pads in their respective sub-regions.

[0106] Exemplarily, along the first direction, both the seventh region and the eighth region each have at least M second connection pads 32, and along the second direction, both the ninth partition and the eleventh partition each have at least P second connection pads 32. Both M and P are positive integers greater than 1.

[0107] A plurality of third lines in the sub-control circuit 75 located in the fifth region and the sixth region are divided into a plurality of third line groups, and each third line group includes M adjacent third lines. The M third lines in the same group in the fifth region are respectively and correspondingly connected to the M second connection pads 32 arranged along the first direction in the tenth partition, and the M third lines in the same group in the sixth region are respectively and correspondingly connected to the M second connection pads 32 arranged along the first direction in the seventh partition.

[0108] A plurality of third lines in the sub-control circuit 75 located in the ninth partition and the eleventh partition are divided into a plurality of fourth line groups, and each fourth line group includes P adjacent third lines. The P third lines in the same group in the ninth partition are respectively and correspondingly connected to the P second connection pads 32 arranged along the second direction in the ninth partition, and the P third lines in the same group in the eleventh partition are respectively and correspondingly connected to the P second connection pads 32 arranged along the second direction in the eleventh partition.

[0109] In some possible examples, referring to Figure 8 and Figure 9 , the control chip 20 further includes a second substrate 51 and a second stacked structure 52 disposed on the second substrate 51. The second substrate 51 is a semiconductor substrate, such as a single-crystal silicon substrate, a single-crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. It can be a P-type doped semiconductor substrate or an N-type doped semiconductor substrate.

[0110] Among them, both the sensing circuit 71 and the control circuit 75 are located within the first stacked structure, and can also partially extend into the second substrate 51 or be completely located on the second substrate 51. The third connection pads 33 and the fourth connection pads are both exposed on the surface of the second stacked structure 52 facing the array chip 10. The third connection pads 33 and the fourth connection pads can be arranged in the same layer for easy external connection.

[0111] In order to achieve the corresponding connection between the sensing circuit 71 and the third connection pads 33, and / or between the control circuit 75 and the fourth connection pads, the control chip 20 further includes a first contact plug 53 and / or a second contact plug. The first contact plug 53 is disposed between the sensing circuit 71 and the third connection pads 33, and is arranged in a zigzag pattern on the sensing circuit 71. The second contact plug is disposed between the driving circuit 73 and the fourth connection pads, and is arranged in a zigzag pattern on the driving circuit 73. With such an arrangement, the distance between the first contact plugs 53 can be increased, as well as the distance between the second contact plugs, to avoid the first contact plugs 53 being arranged as a retaining wall and avoid the second contact plugs being arranged as a retaining wall.

[0112] In an example where the control chip 20 includes a second substrate 51 and a second stacked structure 52, the control chip 20 further includes a third connection structure 43 and a fourth connection structure 44 disposed within the second stacked structure 52. The third connection structure 43 is connected to the third connection pad 33, for example, by a via. The fourth connection structure 44 is connected to the fourth connection pad, for example, by a via. Among them, a first contact plug 53 is connected between the third connection structure 43 and the sensing circuit 71, and a second contact plug is connected between the fourth connection structure 44 and the control circuit 75.

[0113] In some possible examples, the control chip 20 further includes a control circuit 75. The trace 76 of the control circuit 75 passes between the first contact plug 53 and / or the second contact plug to connect two adjacent control regions 21, thereby realizing the control of multiple array regions 11. Among them, the control circuit 75 can be disposed on the same layer as the sensing circuit 71 and the driving circuit 73, and the projection of the control circuit 75 on the array chip 10 is opposite to the central region of the array region 11.

[0114] In summary, the semiconductor structure in the embodiments of the present disclosure includes an array chip 10 and a control chip 20. The array chip 10 includes word lines, bit lines, a first connection pad 31, a second connection pad 32, a first connection structure 41, and a second connection structure 42. The first connection structure 41 connects the bit line to the first connection pad 31, and the second connection structure 42 connects the word line to the second connection pad 32. The control chip 20 includes a sensing circuit 71, a driving circuit 73, a third connection pad 33, and a fourth connection pad. The third connection pad 33 is connected to the sensing circuit 71, and the fourth connection pad is connected to the driving circuit 73. By bonding the array chip 10 and the control chip 20, the third connection pad 33 is correspondingly connected to the first connection pad 31, and the fourth connection pad is correspondingly connected to the second connection pad 32. On the basis of realizing that the sensing circuit 71 controls the bit line and the driving circuit 73 controls the word line, it is possible to avoid the situation of disconnection due to too large a height difference between the array chip 10 and the control chip 20, and improve the yield and reliability of the semiconductor structure. In addition, the word lines and the bit lines form an array region 11 on the array chip 10. The first connection pad 31 is disposed in a first region 12 and a second region 13 respectively near both ends of the bit line in the array region 11. The second connection pad 32 is disposed in a third region and a fourth region of the array region 11. The third region and the fourth region are located between the first region 12 and the second region 13, so that the first connection pad 31 and the second connection pad 32 are arranged in a partitioned manner in the array region 11, facilitating wiring.

[0115] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. The descriptions with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0116] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, It includes a phase-bonded array chip and a control chip; The array chip includes: Word lines and bit lines, which intersect on the array chip to form an array region; First connection pads, which are arranged in a first region and a second region of the array region respectively near both ends of the bit line; Second connection pads, which are arranged in a third region and a fourth region of the array region, and the third region and the fourth region are located between the first region and the second region; A first connection structure, which connects the bit line and the first connection pad; A second connection structure, which connects the word line and the second connection pad; The control chip includes: A sensing circuit, which is used to control the bit line; A driving circuit, which is used to control the word line; A third connection pad, which is correspondingly connected to the first connection pad and is connected to the sensing circuit; A fourth connection pad, which is correspondingly connected to the second connection pad and is connected to the driving circuit.

2. The semiconductor structure according to claim 1, wherein The array chip and the control chip are hybrid-bonded.

3. The semiconductor structure according to claim 1, wherein The array chip further includes a first stacked structure, the word lines, the bit lines, the first connection structure and the second connection structure are all located in the first stacked structure, and the first connection pads and the second connection pads are both exposed on the surface of the first stacked structure facing the control chip; The control chip further includes a second stacked structure, the sensing circuit and the control circuit are both located in the second stacked structure, and the third connection pads and the fourth connection pads are both exposed on the surface of the second stacked structure facing the array chip; And / or, the first connection structure is axially symmetrically distributed, and the second connection structure is centrosymmetrically distributed.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The array chip includes a plurality of the array regions; The sensing circuit includes two sub-sensing circuits, and the projections of the two sub-sensing circuits on the array chip are respectively located in two adjacent array regions and are respectively close to one end of the bit line adjacent to each other; The driving circuit includes two sub-driving circuits, and the projections of the two sub-driving circuits on the array chip are respectively located in the same array region and are respectively close to two ends of the word line.

5. The semiconductor structure according to claim 4, wherein The fourth connection pads corresponding to the second connection pads in the third region and the fourth region of the same array region are respectively connected to the sub-driving circuits of two different driving circuits; And / or, the third connection pads corresponding to the first connection pads in the first region and the second region of the same array region are respectively connected to different sensing circuits.

6. The semiconductor structure according to any one of claims 4, characterized in that, Along a first direction, there are at least N first connection pads in the first region and the second region of each array region, and N is a positive integer greater than 1; The bit lines of each of the array regions are divided into a plurality of bit line groups, each of the bit line groups includes 2N adjacent bit lines, the first ends of N bit lines in the same group are respectively connected to N first connection pads arranged along the first direction in the first region, and the second ends of the remaining N bit lines are respectively connected to N first connection pads arranged along the first direction in the second region.

7. The semiconductor structure according to claim 6, characterized in that, The bit lines arranged in odd positions are correspondingly connected to the first connection pads in the first region, and the bit lines arranged in even positions are correspondingly connected to the first connection pads in the second region.

8. The semiconductor structure according to claim 6, wherein The third region includes a first sub-region, and a second sub-region and a third sub-region provided in the first sub-region away from the fourth region, the second sub-region is adjacent to the second region, the fourth region includes a fourth sub-region, and a fifth sub-region and a sixth sub-region provided in the fourth sub-region away from the third region, the fifth sub-region is adjacent to the first region; Along the first direction, both the third region and the fourth region have at least M second connection pads; Along the second direction, both the third sub-region and the fifth sub-region of each of the array regions have at least P second connection pads, M and P are positive integers greater than 1, and the second direction intersects with the first direction; The word lines in the third sub-region and the fifth sub-region are divided into a plurality of first word line groups, each of the first word line groups includes 2P adjacent word lines, the first ends of P word lines in the same group in the third sub-region are respectively correspondingly connected to P second connection pads arranged along the second direction in the third sub-region, and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region connected to the second connection pads; The second ends of P word lines in the same group in the fifth sub-region are respectively correspondingly connected to P second connection pads arranged along the second direction in the fifth sub-region, and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region connected to the second connection pads; The word lines in the first region and the second region are divided into a plurality of second word line groups, each of the second word line groups includes 2M adjacent word lines, the second ends of M word lines in the same group in the first region are respectively correspondingly connected to M second connection pads arranged along the first direction in the fourth sub-region, and the second ends of the remaining P word lines are respectively connected to the first ends of P word lines in the corresponding group of the adjacent array region connected to the second connection pads; The first ends of M word lines in the same group in the second region are respectively correspondingly connected to M second connection pads arranged along the first direction in the first sub-region, and the first ends of the remaining P word lines are respectively connected to the second ends of P word lines in the corresponding group of the adjacent array region connected to the second connection pads.

9. The semiconductor structure according to any one of claims 1-3, characterized in that, The control chip further includes first contact plugs provided between the sensing circuit and the third connection pads, and the first contact plugs are arranged in a zigzag pattern on the sensing circuit; And / or, the control chip further includes a second contact plug disposed between the driving circuit and the fourth connection pad, and the second contact plugs are arranged in a zigzag pattern on the driving circuit.

10. The semiconductor structure according to claim 5, wherein The control chip further includes a control circuit, and the traces of the control circuit pass between the first contact plug and / or the second contact plug.

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