Memory circuit, resistive non-volatile memory and operation method thereof

Abstract

The invention provides a memory circuit, a resistive non-volatile memory and an operation method thereof. The resistive non-volatile memory comprises at least one resistance variable field effect transistor and a unipolar source / channel / drain diode. The at least one resistance variable field effect transistor is electrically connected to the at least one bit line. The unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode, and two ends of the unipolar source / channel / drain diode are electrically connected with a source line and at least one resistance variable field effect transistor respectively. According to the resistive non-volatile memory, extra word lines and related circuits are not needed, and the ultra-miniature wafer size is achieved.

Description

Technical Field

[0001] The present invention relates to a storage circuit and an operation method thereof, and particularly to a memory circuit, a resistive non-volatile memory, and an operation method thereof. Background Art

[0002] With the progress rate of Moore's Law, various embedded memories have been mass-produced in foundries. In many application fields, semiconductor memories are widely used in various electronic products.

[0003] However, traditional embedded memories are formed in the front-end process and the back-end process of complementary metal oxide semiconductor (CMOS) technology, which increases the number of masks and manufacturing steps, resulting in high costs. In addition, the technologies of traditional embedded memories all use three-terminal active elements as control transistors, which require additional word lines and related circuits, resulting in increased power consumption and excessive area. Summary of the Invention

[0004] The present invention provides a memory circuit, a resistive non-volatile memory, and an operation method thereof to improve the problems of the prior art.

[0005] In some embodiments of the present invention, the resistive non-volatile memory proposed by the present invention includes at least one resistive variable field effect transistor and a unipolar source / channel / drain diode. At least one resistive variable field effect transistor is electrically connected to at least one bit line. The unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode, and both ends of the unipolar source / channel / drain diode are electrically connected to the source line and at least one resistive variable field effect transistor respectively.

[0006] In some embodiments of the present invention, the gate of at least one resistive variable field effect transistor is electrically connected to at least one bit line, the first end of at least one resistive variable field effect transistor is floating, both ends of the unipolar source / channel / drain diode are electrically connected to the source line and the second end of at least one resistive variable field effect transistor respectively, and the unipolar source / channel / drain diode is an npn-type diode or a nin-type diode.

[0007] In some embodiments of the present invention, the unipolar source / channel / drain diode includes a floating virtual gate, a first source / drain diffusion region, and a second source / drain diffusion region. The first source / drain diffusion region and the second source / drain diffusion region are respectively located on opposite sides of the floating virtual gate, and one end of the first source / drain diffusion region contacts a contact plug, and the other end of the contact plug contacts the source line.

[0008] In some embodiments of the present invention, the unipolar source / channel / drain diode shares the second source / drain diffusion region with at least one resistive variable field effect transistor, and the at least one resistive variable field effect transistor includes a shallow trench isolation. The shallow trench isolation directly contacts the gate of the at least one resistive variable field effect transistor. The shallow trench isolation and the second source / drain diffusion region are respectively located on opposite sides of the gate of the at least one resistive variable field effect transistor. The shallow trench isolation serves as the first end of the at least one resistive variable field effect transistor, and the second source / drain diffusion region serves as the second end of the at least one resistive variable field effect transistor.

[0009] In some embodiments of the present invention, the two ends of the unipolar source / channel / drain diode are electrically connected to the source line and the gate of the at least one resistive variable field effect transistor respectively. The first end of the at least one resistive variable field effect transistor is floating, and the second end of the at least one resistive variable field effect transistor is electrically connected to at least one bit line. The unipolar source / channel / drain diode is a pnp-type diode or a pip-type diode.

[0010] In some embodiments of the present invention, the unipolar source / channel / drain diode includes a floating virtual gate, a first source / drain diffusion region, and a second source / drain diffusion region. The first source / drain diffusion region and the second source / drain diffusion region are respectively located on opposite sides of the floating virtual gate.

[0011] In some embodiments of the present invention, the resistive non-volatile memory further includes a first conductive layer, a second conductive layer, a first contact plug, a second contact plug, a third contact plug, and a fourth contact plug. The first conductive layer and the second conductive layer are electrically isolated from each other. The two ends of the first contact plug respectively contact the first source / drain diffusion region and the first conductive layer. The two ends of the second contact plug respectively contact the first conductive layer and the source line. The two ends of the third contact plug respectively contact the second source / drain diffusion region and the second conductive layer. The two ends of the fourth contact plug respectively contact the gate of the at least one resistive variable field effect transistor and the second conductive layer.

[0012] In some embodiments of the present invention, the at least one resistive variable field effect transistor includes a shallow trench isolation and a third source / drain diffusion region. The shallow trench isolation directly contacts the gate of the at least one resistive variable field effect transistor. The shallow trench isolation serves as the first end of the at least one resistive variable field effect transistor. The third source / drain diffusion region and the shallow trench isolation are respectively located on opposite sides of the gate of the at least one resistive variable field effect transistor. The third source / drain diffusion region serves as the second end of the at least one resistive variable field effect transistor.

[0013] In some embodiments of the present invention, the resistive non-volatile memory further includes a fifth contact plug. The two ends of the fifth contact plug respectively contact the third source / drain diffusion region and the at least one bit line.

[0014] In some embodiments of the present invention, the memory circuit proposed by the present invention includes a plurality of memory cells arranged in an array. Each memory cell includes a resistive non-volatile memory, and the resistive non-volatile memory includes at least one resistive variable field effect transistor and a unipolar source / channel / drain diode. At least one resistive variable field effect transistor is electrically connected to at least one bit line. The unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode, and both ends of the unipolar source / channel / drain diode are electrically connected to the source line and at least one resistive variable field effect transistor respectively.

[0015] In some embodiments of the present invention, each memory cell includes another resistive non-volatile memory. One end of the another resistive non-volatile memory is electrically connected to the resistive non-volatile memory and at least one bit line, and the other end of the another resistive non-volatile memory is electrically connected to another source line.

[0016] In some embodiments of the present invention, each memory cell includes another resistive non-volatile memory. One end of the another resistive non-volatile memory is electrically connected to the resistive non-volatile memory and the source line, and the other end of the another resistive non-volatile memory is electrically connected to at least one bit line.

[0017] In some embodiments of the present invention, the gate of at least one resistive variable field effect transistor is electrically connected to at least one bit line, a first end of the at least one resistive variable field effect transistor is floating, both ends of the unipolar source / channel / drain diode are electrically connected to the source line and a second end of the at least one resistive variable field effect transistor respectively. Each memory cell includes another resistive non-volatile memory, and the another resistive non-volatile memory includes at least one additional resistive variable field effect transistor and another unipolar source / channel / drain diode. For the at least one additional resistive variable field effect transistor, its gate is electrically connected to at least one additional bit line, and a first end of the at least one additional resistive variable field effect transistor is floating.

[0018] The another unipolar source / channel / drain diode is formed by another field effect transistor without a gate electrode, and both ends of the another unipolar source / channel / drain diode are electrically connected to the source line and a second end of the at least one additional resistive variable field effect transistor respectively.

[0019] In some embodiments of the present invention, two ends of a unipolar source / channel / drain diode are electrically connected to a source line and a gate of at least one resistive random access memory (RRAM) transistor respectively. A first end of the at least one RRAM transistor is floating. A second end of the at least one RRAM transistor is electrically connected to at least one bit line. Each memory cell includes another resistive non-volatile memory which includes at least one additional RRAM transistor and another unipolar source / channel / drain diode. For the at least one additional RRAM transistor, a first end thereof is floating and a second end thereof is electrically connected to at least one bit line. The another unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode. Two ends of the another unipolar source / channel / drain diode are electrically connected to another source line and a gate of the at least one additional RRAM transistor respectively.

[0020] In some embodiments of the present invention, for an operation method of the resistive non-volatile memory proposed by the present invention, the resistive non-volatile memory includes a resistive random access memory (RRAM) transistor and a unipolar source / channel / drain diode which are connected to each other. The operation method includes the following steps: applying a zero voltage to one of the bit line and the source line, and applying a non-zero voltage to the other one of the bit line and the source line to operate the resistive non-volatile memory, wherein the RRAM transistor is electrically connected to the bit line, and the unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode, and two ends of the unipolar source / channel / drain diode are electrically connected to the source line and the RRAM transistor respectively.

[0021] In some embodiments of the present invention, a gate of the RRAM transistor is electrically connected to the bit line, a first end of the RRAM transistor is floating, two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a second end of the RRAM transistor respectively, and the unipolar source / channel / drain diode is an npn type diode or a nin type diode. The operation method further includes: in a startup stage, when the resistive non-volatile memory is selected, applying a startup voltage to the bit line and applying a zero voltage to the source line; in a set stage, when the resistive non-volatile memory is selected, applying a set voltage to the bit line and applying a zero voltage to the source line, wherein an absolute value of the set voltage is less than or equal to an absolute value of the startup voltage; in a reset stage, when the resistive non-volatile memory is selected, applying a reset voltage to the bit line and applying a zero voltage to the source line, wherein an absolute value of the reset voltage is less than an absolute value of the set voltage; in a read stage, when the resistive non-volatile memory is selected, applying a read voltage to the bit line and applying a zero voltage to the source line, wherein an absolute value of the read voltage is less than an absolute value of the reset voltage.

[0022] In some embodiments of the present invention, the operation method further includes: in the startup stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the startup voltage to the source line and applying a zero voltage to the bit line; in the programming stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the programming voltage to the source line and applying a zero voltage to the bit line; in the reset stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the reset voltage to the source line and applying a zero voltage to the bit line; in the read stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the read voltage to the source line and applying a zero voltage to the bit line.

[0023] In some embodiments of the present invention, two ends of a unipolar source / channel / drain diode are electrically connected to the source line and a gate of a resistive variable field effect transistor respectively. A first end of the resistive variable field effect transistor is floatingly connected, and a second end of the resistive variable field effect transistor is electrically connected to the bit line. The unipolar source / channel / drain diode is a pnp-type diode or a pip-type diode. The operation method further includes: in the startup stage, when the resistive non-volatile memory is selected, applying a startup voltage to the source line and applying a zero voltage to the bit line; in the programming stage, when the resistive non-volatile memory is selected, applying a programming voltage to the source line and applying a zero voltage to the bit line, where the absolute value of the programming voltage is less than or equal to the absolute value of the startup voltage; in the reset stage, when the resistive non-volatile memory is selected, applying a reset voltage to the source line and applying a zero voltage to the bit line, where the absolute value of the reset voltage is less than the absolute value of the programming voltage; in the read stage, when the resistive non-volatile memory is selected, applying a read voltage to the source line and applying a zero voltage to the bit line, where the absolute value of the read voltage is less than the absolute value of the reset voltage.

[0024] In some embodiments of the present invention, the operation method further includes: in the startup stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the startup voltage to the bit line and applying a zero voltage to the source line; in the programming stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the programming voltage to the bit line and applying a zero voltage to the source line; in the reset stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the reset voltage to the bit line and applying a zero voltage to the source line; in the read stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the read voltage to the bit line and applying a zero voltage to the source line.

[0025] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The resistive non-volatile memory of the present invention does not require an additional word line and its related circuits, achieving ultra-miniaturized chip size, which is beneficial to the continuous miniaturization of CMOS, a more streamlined chip configuration layout, and higher cost efficiency.

[0026] The following will describe the above description in detail with embodiments and provide a further explanation of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the description of the accompanying drawings is as follows:

[0028] Figure 1A is a circuit diagram of a unipolar source / channel / drain diode according to some embodiments of the present invention;

[0029] Figure 1B is a circuit diagram of a unipolar source / channel / drain diode according to some embodiments of the present invention;

[0030] Figure 1C is a circuit diagram of a unipolar source / channel / drain diode according to some embodiments of the present invention;

[0031] Figure 1D is a circuit diagram of a unipolar source / channel / drain diode according to some embodiments of the present invention;

[0032] Figure 2 illustrates Figure 1D the electrical characteristics of the unipolar source / channel / drain diode;

[0033] Figure 3A is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0034] Figure 3B is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0035] Figure 3C is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0036] Figure 3D is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0037] Figure 4A is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0038] Figure 4BA circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0039] Figure 4C A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0040] Figure 4D A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0041] Figure 5A A circuit diagram of a memory circuit according to some embodiments of the present invention;

[0042] Figure 5B A circuit diagram of a memory circuit according to some embodiments of the present invention;

[0043] Figure 5C A circuit diagram of a memory circuit according to some embodiments of the present invention;

[0044] Figure 6A A circuit diagram of a memory cell according to some embodiments of the present invention;

[0045] Figure 6B A layout diagram of a memory cell according to some embodiments of the present invention;

[0046] Figure 6C A cross-sectional view of a memory cell according to some embodiments of the present invention;

[0047] Figure 7A A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0048] Figure 7B A layout diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0049] Figure 7C A cross-sectional view of a resistive non-volatile memory according to some embodiments of the present invention;

[0050] Figure 8A A circuit diagram of a memory cell according to some embodiments of the present invention;

[0051] Figure 8B A layout diagram of a memory cell according to some embodiments of the present invention;

[0052] Figure 8C A cross-sectional view of a memory cell according to some embodiments of the present invention;

[0053] Figure 9AA circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0054] Figure 9B A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0055] Figure 10A A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0056] Figure 10B A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0057] Figure 10C A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0058] Figure 10D A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0059] Figure 11 A circuit diagram of a memory circuit according to some embodiments of the present invention;

[0060] Figure 12A A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0061] Figure 12B A layout diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0062] Figure 12C A cross-sectional view of a resistive non-volatile memory according to some embodiments of the present invention;

[0063] Figure 13A A circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention;

[0064] Figure 13B A layout diagram of a resistive non-volatile memory according to some embodiments of the present invention; and

[0065] Figure 13C A cross-sectional view of a resistive non-volatile memory according to some embodiments of the present invention.

[0066]

Symbol Description

[0067] 110, 120, 130, 140: Unipolar source / channel / drain diode

[0068] 110a, 110b: Unipolar source / channel / drain diode

[0069] 140a, 140b: Unipolar source / channel / drain diodes

[0070] 111, 112, 121, 122, 131, 132, 141, 142: Terminals

[0071] 200: Electrical characteristics

[0072] 301 to 304: Resistive non-volatile memories

[0073] 301a, 301b: Resistive non-volatile memories

[0074] 310, 320, 330, 340: Resistive variable field effect transistors

[0075] 310a, 310b: Resistive variable field effect transistors

[0076] 311, 321, 331, 341: First terminals

[0077] 312, 322, 332, 342: Second terminals

[0078] 313, 323, 333, 343: Gates

[0079] 401 to 404: Resistive non-volatile memories

[0080] 403a, 403b: Resistive non-volatile memories

[0081] 410, 420, 430, 440: Resistive variable field effect transistors

[0082] 410_0 to 410_n: Resistive variable field effect transistors

[0083] 430a, 430b: Resistive variable field effect transistors

[0084] 411, 421, 431, 441: First terminals

[0085] 412, 422, 432, 442: Second terminals

[0086] 413, 423, 433, 443: Gates

[0087] 505, 506, 507: Memory cells

[0088] 501, 502a, 502b, 503a, 503b: Resistive non-volatile memories

[0089] 511, 512, 521, 522, 531, 532: Circuits

[0090] 600: Memory cell

[0091] 601: Gate dielectric layer

[0092] 602: Gate electrode layer

[0093] 611, 612: Diffusion region

[0094] 621, 622: Floating virtual gate

[0095] 630: Channel region

[0096] 640: Gate spacer

[0097] 651, 652: Shallow trench isolation

[0098] 661: First source / drain diffusion region

[0099] 662: Second source / drain diffusion region

[0100] 663: Third source / drain diffusion region

[0101] 670: Contact plug

[0102] 700: Resistive non-volatile memory

[0103] 711: N-type well region

[0104] 712: P-type well region

[0105] 721: Floating virtual gate

[0106] 751, 752: Shallow trench isolation

[0107] 761: First source / drain diffusion region

[0108] 762: Second source / drain diffusion region

[0109] 763: Third source / drain diffusion region

[0110] 771: First contact plug

[0111] 772: Second contact plug

[0112] 773: Third contact plug

[0113] 774: Fourth contact plug

[0114] 775: Fifth contact plug

[0115] 781: First conductive layer

[0116] 782: Second conductive layer

[0117] 800: Memory cell

[0118] 811, 812: Diffusion region

[0119] 821, 822: Floating virtual gate

[0120] 851, 852: Shallow trench isolation

[0121] 861 - 865: Source / drain diffusion region

[0122] 870 - 877: Contact plug

[0123] 880 - 882: Conductive layer

[0124] 901, 902: Resistive non-volatile memory

[0125] 1001 - 1004: Resistive non-volatile memory

[0126] 1101: Resistive non-volatile memory

[0127] 1105: Memory cell

[0128] 1111, 1112: Circuit

[0129] 1200: Resistive non-volatile memory

[0130] 1211, 1212: Active region

[0131] 1221: Floating virtual gate

[0132] 1251, 1252: Shallow trench isolation

[0133] 1261 - 1266: Source / drain diffusion region

[0134] 1270 - 1278: Contact plug

[0135] 1280 - 1283: Conductive layer

[0136] 1290 - 1293: Contact plug

[0137] 1300: Resistive non-volatile memory

[0138] 1311, 1312: Active region

[0139] 1321: Floating virtual gate

[0140] 1330: Channel region

[0141] 1351 - 1355: Shallow trench isolation

[0142] 1360~1365: Source / drain diffusion region

[0143] 1370~1378: Contact plug

[0144] 1380~1383: Conductive layer

[0145] 1390~1393: Contact plug

[0146] BL, BL0~BLn, BLn+1~BLh, BLh+1~BLp, BLm-k-2~BLm: Bit line SL, SL0~SLn: Source line Detailed implementation manners

[0147] In order to make the description of the present invention more detailed and complete, reference may be made to the accompanying drawings and the following various embodiments. The same numbers in the drawings represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations to the present invention.

[0148] Figure 1A is a circuit diagram of a unipolar source / channel / drain diode 110 according to some embodiments of the present invention. As Figure 1A shown, the unipolar source / channel / drain diode 110 is an npn-type diode. The unipolar source / channel / drain diode 110 is composed of a field-effect transistor without a gate electrode to be compatible with semiconductor processes. For example, the two ends 111, 112 of the unipolar source / channel / drain diode 110 are the source and the drain respectively.

[0149] Figure 1B is a circuit diagram of a unipolar source / channel / drain diode 120 according to some embodiments of the present invention. As Figure 1B shown, the unipolar source / channel / drain diode 120 is a nin-type diode. The unipolar source / channel / drain diode 120 is composed of a field-effect transistor without a gate electrode to be compatible with semiconductor processes. For example, the two ends 121, 122 of the unipolar source / channel / drain diode 120 are the source and the drain respectively.

[0150] Figure 1C is a circuit diagram of a unipolar source / channel / drain diode 130 according to some embodiments of the present invention. As Figure 1C shown, the unipolar source / channel / drain diode 130 is a pip-type diode. The unipolar source / channel / drain diode 130 is composed of a field-effect transistor without a gate electrode to be compatible with semiconductor processes. For example, the two ends 131, 132 of the unipolar source / channel / drain diode 130 are the source and the drain respectively.

[0151] Figure 1D is a circuit diagram of a unipolar source / channel / drain diode 140 according to some embodiments of the present invention. As Figure 1D shown, the unipolar source / channel / drain diode 140 is a pnp-type diode. The unipolar source / channel / drain diode 140 is composed of a field effect transistor without a gate electrode, which is compatible with semiconductor processes. For example, both ends 141 and 142 of the unipolar source / channel / drain diode 140 are a source and a drain respectively.

[0152] Figure 2 shows Figure 1D the electrical characteristics 200 of the unipolar source / channel / drain diode 140. As Figure 2 shown, the unipolar source / channel / drain diode 140 has a unipolar rectification characteristic. When the drain-to-source voltage of the unipolar source / channel / drain diode 140 is greater than zero voltage, the drain current conducts forward; when the drain-to-source voltage of the unipolar source / channel / drain diode 140 is less than zero voltage, the drain current is reversely saturated.

[0153] Please refer to Figures 3A to 3D and Figures 4A to 4D . The technical aspect of the present invention is a resistive non-volatile memory 301-304, 401-404, which can be applied to an embedded resistive non-volatile memory or widely used in related technical processes. The resistive non-volatile memory 301-304, 401-404 of this technical aspect can achieve quite a lot of technical progress and has wide industrial utilization value. The following will be combined with Figures 3A to 3D and Figures 4A to 4D to respectively illustrate the specific implementation manners of the resistive non-volatile memory 301-304, 401-404.

[0154] It should be understood that various implementation manners of the resistive non-volatile memory 301-304, 401-404 are described in combination with Figures 3A to 3D and Figures 4A to 4D . In the following description, for the sake of explanation, many specific details are further set to provide a comprehensive elaboration of one or more implementation manners. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these implementation manners, known structures and devices are shown in block diagram form. The term "for example" used herein means "as an example, instance or illustration". Any embodiment described herein as "for example" does not need to be interpreted as better or superior to other embodiments.

[0155] Figure 3A is a circuit diagram of a resistive non-volatile memory 301 according to some embodiments of the present invention. As Figure 3AAs shown, the resistive non-volatile memory 301 includes a resistive variable field effect transistor 310 and a unipolar source / channel / drain diode 110. Structurally, the resistive variable field effect transistor 310 is electrically connected to the bit line BL, and both ends 111, 112 of the unipolar source / channel / drain diode 110 are electrically connected to the source line SL and the resistive variable field effect transistor 310 respectively.

[0156] In Figure 3A it, the gate 313 of the resistive variable field effect transistor 310 is electrically connected to the bit line BL, the first end 311 of the resistive variable field effect transistor 310 is floating, both ends 111, 112 of the unipolar source / channel / drain diode 110 are electrically connected to the source line SL and the second end 312 of the resistive variable field effect transistor 310 respectively, the unipolar source / channel / drain diode 110 is an npn type diode, and the resistive variable field effect transistor 310 is an npn type resistive variable field effect transistor.

[0157] It should be noted that although terms such as "first", "second", etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the embodiment, the first element can be called the second element, and similarly, the second element can be called the first element.

[0158] Figure 3B is a circuit diagram of a resistive non-volatile memory 302 according to some embodiments of the present invention. As Figure 3B shown, the resistive non-volatile memory 302 includes a resistive variable field effect transistor 320 and a unipolar source / channel / drain diode 110. Structurally, the resistive variable field effect transistor 320 is electrically connected to the bit line BL, and both ends 111, 112 of the unipolar source / channel / drain diode 110 are electrically connected to the source line SL and the resistive variable field effect transistor 320 respectively.

[0159] In Figure 3B it, the gate 323 of the resistive variable field effect transistor 320 is electrically connected to the bit line BL, the first end 321 of the resistive variable field effect transistor 320 is floating, both ends 111, 112 of the unipolar source / channel / drain diode 110 are electrically connected to the source line SL and the second end 322 of the resistive variable field effect transistor 320 respectively, the unipolar source / channel / drain diode 110 is an npn type diode, and the resistive variable field effect transistor 320 is a pnp type resistive variable field effect transistor.

[0160] Figure 3C is a circuit diagram of a resistive non-volatile memory 303 according to some embodiments of the present invention. As Figure 3CAs shown, the resistive non-volatile memory 303 includes a resistive variable field effect transistor 330 and a unipolar source / channel / drain diode 120. Structurally, the resistive variable field effect transistor 330 is electrically connected to the bit line BL, and both ends 121 and 122 of the unipolar source / channel / drain diode 120 are electrically connected to the source line SL and the resistive variable field effect transistor 330 respectively.

[0161] In Figure 3C it, the gate 333 of the resistive variable field effect transistor 330 is electrically connected to the bit line BL, the first end 331 of the resistive variable field effect transistor 330 is floating, both ends 121 and 122 of the unipolar source / channel / drain diode 120 are electrically connected to the source line SL and the second end 332 of the resistive variable field effect transistor 330 respectively, the unipolar source / channel / drain diode 120 is a nin-type diode, and the resistive variable field effect transistor 330 is a nin-type resistive variable field effect transistor.

[0162] Figure 3D is a circuit diagram of a resistive non-volatile memory 304 according to some embodiments of the present invention. As Figure 3D shown, the resistive non-volatile memory 304 includes a resistive variable field effect transistor 340 and a unipolar source / channel / drain diode 120. Structurally, the resistive variable field effect transistor 340 is electrically connected to the bit line BL, and both ends 121 and 122 of the unipolar source / channel / drain diode 120 are electrically connected to the source line SL and the resistive variable field effect transistor 340 respectively.

[0163] In Figure 3D it, the gate 343 of the resistive variable field effect transistor 340 is electrically connected to the bit line BL, the first end 341 of the resistive variable field effect transistor 340 is floating, both ends 121 and 122 of the unipolar source / channel / drain diode 120 are electrically connected to the source line SL and the second end 342 of the resistive variable field effect transistor 340 respectively, the unipolar source / channel / drain diode 120 is a nin-type diode, and the resistive variable field effect transistor 330 is a pip-type resistive variable field effect transistor.

[0164] In some embodiments of the present invention, the operating methods of the resistive non-volatile memories 301 to 304 are the same. For the sake of simplicity of description, hereinafter, taking the operation of the resistive non-volatile memory 301 as an example, a zero voltage is applied to one of the bit line BL and the source line SL, and a non-zero voltage is applied to the other of the bit line BL and the source line SL to operate the resistive non-volatile memory 301.

[0165] Specifically, in the FORMing stage, when the resistive non-volatile memory 301 is selected, a FORMing voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL, so that a conductive filament is formed in the gate dielectric layer of the gate of the resistive variable field effect transistor 310; in the SETting stage, when the resistive non-volatile memory 301 is selected, a SETting voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL, so that the gate dielectric layer of the gate of the resistive variable field effect transistor 310 is in the first resistance state, where the absolute value of the SETting voltage is less than or equal to the absolute value of the FORMing voltage; in the RESETting stage, when the resistive non-volatile memory 301 is selected, a RESETting voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL, so that the gate dielectric layer of the gate of the resistive variable field effect transistor 310 is in the second resistance state, where the absolute value of the RESETting voltage is less than the absolute value of the SETting voltage; in the READing stage, when the resistive non-volatile memory 301 is selected, a READing voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL, where the absolute value of the READing voltage is less than the absolute value of the RESETting voltage. The read circuit determines whether the resistive non-volatile memory 301 is SET or RESET based on the level of the read current.

[0166] On the other hand, in the FORMing stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the FORMing voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL; in the SETting stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the SETting voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL; in the RESETting stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the RESETting voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL; in the READing stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the READing voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL.

[0167] Figure 4A is a circuit diagram of a resistive non-volatile memory 401 according to some embodiments of the present invention. As Figure 4A shown, the resistive non-volatile memory 401 includes a resistive variable field effect transistor 410 and a unipolar source / channel / drain diode 140. Structurally, the resistive variable field effect transistor 410 is electrically connected to the bit line BL, and both ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the resistive variable field effect transistor 410, respectively.

[0168] In Figure 4AIn the figure, two ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the gate 413 of the resistive variable field effect transistor 410 respectively. The first end 411 of the resistive variable field effect transistor 410 is floating, and the second end 412 of the resistive variable field effect transistor 410 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 140 is a pnp type diode, and the resistive variable field effect transistor 410 is a pnp type resistive variable field effect transistor.

[0169] Figure 4B is a circuit diagram of a resistive non-volatile memory 402 according to some embodiments of the present invention. As Figure 4B shown, the resistive non-volatile memory 402 includes a resistive variable field effect transistor 420 and a unipolar source / channel / drain diode 130. Structurally, the resistive variable field effect transistor 420 is electrically connected to the bit line BL, and two ends 131 and 132 of the unipolar source / channel / drain diode 130 are electrically connected to the source line SL and the resistive variable field effect transistor 420 respectively.

[0170] In Figure 4B the figure, two ends 131 and 132 of the unipolar source / channel / drain diode 130 are electrically connected to the source line SL and the gate 423 of the resistive variable field effect transistor 420 respectively. The first end 421 of the resistive variable field effect transistor 420 is floating, and the second end 422 of the resistive variable field effect transistor 420 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 130 is a pip type diode, and the resistive variable field effect transistor 420 is a pip type resistive variable field effect transistor.

[0171] Figure 4C is a circuit diagram of a resistive non-volatile memory 403 according to some embodiments of the present invention. As Figure 4C shown, the resistive non-volatile memory 403 includes a resistive variable field effect transistor 430 and a unipolar source / channel / drain diode 140. Structurally, the resistive variable field effect transistor 430 is electrically connected to the bit line BL, and two ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the resistive variable field effect transistor 430 respectively.

[0172] In Figure 4C the figure, two ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the gate 433 of the resistive variable field effect transistor 430 respectively. The first end 431 of the resistive variable field effect transistor 430 is floating, and the second end 432 of the resistive variable field effect transistor 430 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 140 is a pnp type diode, and the resistive variable field effect transistor 430 is an npn type resistive variable field effect transistor.

[0173] Figure 4D is a circuit diagram of a resistive non-volatile memory 404 according to some embodiments of the present invention. As Figure 4D shown, the resistive non-volatile memory 404 includes a resistive variable field effect transistor 440 and a unipolar source / channel / drain diode 140. Structurally, the resistive variable field effect transistor 440 is electrically connected to the bit line BL, and both ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the resistive variable field effect transistor 440 respectively.

[0174] In Figure 4D it, both ends 141 and 142 of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the gate 443 of the resistive variable field effect transistor 440 respectively. The first end 441 of the resistive variable field effect transistor 440 is floating, the second end 442 of the resistive variable field effect transistor 440 is electrically connected to the bit line BL, the unipolar source / channel / drain diode 140 is a pnp-type diode, and the resistive variable field effect transistor 440 is a nin-type resistive variable field effect transistor.

[0175] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 401-404 are the same. For the sake of simplicity of description, hereinafter, taking the operation of the resistive non-volatile memory 403 as an example, a zero voltage is applied to one of the bit line BL and the source line SL, and a non-zero voltage is applied to the other of the bit line BL and the source line SL to operate the resistive non-volatile memory 403.

[0176] Specifically, in the startup phase, when the resistive non-volatile memory 403 is selected, a startup voltage is applied to the source line SL, and a zero voltage is applied to the bit line, so that a conductive filament is formed in the gate dielectric layer of the resistive variable field effect transistor 430; in the setting phase, when the resistive non-volatile memory 403 is selected, a setting voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL, so that the gate dielectric layer of the resistive variable field effect transistor 430 is in a first resistance state, where the absolute value of the setting voltage is less than or equal to the absolute value of the startup voltage; in the reset phase, when the resistive non-volatile memory 403 is selected, a reset voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL, so that the gate dielectric layer of the resistive variable field effect transistor 430 is in a second resistance state, where the absolute value of the reset voltage is less than the absolute value of the setting voltage; in the reading phase, when the resistive non-volatile memory 403 is selected, a reading voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL, where the absolute value of the reading voltage is less than the absolute value of the reset voltage. The read circuit determines whether the resistive non-volatile memory 403 is set or reset according to the level of the read current.

[0177] On the other hand, in the startup stage, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL; in the set stage, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the set voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL; in the reset stage, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL; in the read stage, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the read voltage is applied to the bit line BL, and a zero voltage is applied to the source line SL.

[0178] Figure 5A is a circuit diagram of a memory circuit according to some embodiments of the present invention. As Figure 5A shown, the memory circuit includes a plurality of memory cells 505, arranged in an array. Each memory cell 505 includes a resistive non-volatile memory 501. In practice, for example, the architecture of the resistive non-volatile memory 501 can be any one of the above resistive non-volatile memories 301-304, 401-404.

[0179] In Figure 5A , the circuit 511 is electrically connected to one end of the unipolar source / channel / drain diode in the corresponding resistive non-volatile memory 501 through the source lines SL0-SLn respectively, and the circuit 512 is electrically connected to the resistive variable field effect transistor in the corresponding resistive non-volatile memory 501 through the bit lines BL1-BLn respectively. In practice, for example, the circuit 511 includes a source line peripheral circuit and a control circuit, the circuit 512 includes a bit line peripheral circuit and a control circuit, and the read circuit can be selectively arranged in the circuit 511 or the circuit 512.

[0180] Figure 5B is a circuit diagram of a memory circuit according to some embodiments of the present invention. As Figure 5B shown, the memory circuit includes a plurality of memory cells 506, arranged in an array. Each memory cell 506 includes resistive non-volatile memories 502a, 502b. In practice, for example, the architecture of the resistive non-volatile memory 502a can be any one of the above resistive non-volatile memories 301-304, 401-404; similarly, the architecture of the resistive non-volatile memory 502b can be any one of the above resistive non-volatile memories 301-304, 401-404.

[0181] Taking the memory cell 506 at the corner as an example, the resistive non-volatile memories 502a and 502b share the same bit line BL1. One end of the resistive non-volatile memory 502b is electrically connected to one end of the resistive non-volatile memory 502a and the bit line BL1. The other end of the resistive non-volatile memory 502b is electrically connected to the source line SL1, and the other end of the resistive non-volatile memory 502a is electrically connected to the source line SL0.

[0182] In Figure 5B circuit 521 is electrically connected to one end of the unipolar source / channel / drain diode of each of the corresponding resistive non-volatile memories 502a and 502b through the source lines SL0 to SLn respectively, and circuit 522 is electrically connected to the resistive variable field effect transistors of each of the corresponding resistive non-volatile memories 502a and 502b through the bit lines BL1 to BLn. In practice, for example, circuit 521 includes a source line peripheral circuit and a control circuit, circuit 522 includes a bit line peripheral circuit and a control circuit, and the reading circuit can be selectively disposed in circuit 521 or circuit 522.

[0183] Figure 5C is a circuit diagram of a memory circuit according to some embodiments of the present invention. As Figure 5C shown, the memory circuit includes a plurality of memory cells 507 arranged in an array. Each memory cell 507 includes resistive non-volatile memories 503a and 503b. In practice, for example, the architecture of the resistive non-volatile memory 503a can be any one of the above resistive non-volatile memories 301 to 304, 401 to 404; similarly, the architecture of the resistive non-volatile memory 503b can be any one of the above resistive non-volatile memories 301 to 304, 401 to 404.

[0184] Taking the memory cell 507 at the corner as an example, the resistive non-volatile memories 503a and 503b share the same bit line BL1 and the same source line SL0. One end of the resistive non-volatile memory 503b is electrically connected to one end of the resistive non-volatile memory 503a and the source line SL0. The other end of the resistive non-volatile memory 503b is electrically connected to the bit line BL1, and the other end of the resistive non-volatile memory 503a is electrically connected to the bit line BL1.

[0185] In Figure 5CIn [the figure], circuit 531 is electrically connected to one end of the unipolar source / channel / drain diode of each of the corresponding resistive non-volatile memories 503a and 503b through source lines SL0 to SLn respectively. Circuit 532 is electrically connected to the resistive variable field effect transistors of each of the corresponding resistive non-volatile memories 503a and 502b through bit lines BL1 to BLn respectively. In practice, for example, circuit 531 includes a source line peripheral circuit and a control circuit, circuit 532 includes a bit line peripheral circuit and a control circuit, and the reading circuit can be selectively disposed in circuit 531 or circuit 532.

[0186] Figure 6A is a circuit diagram of a memory cell 600 according to some embodiments of the present invention. As Figure 6A shown, the memory cell 600 includes resistive non-volatile memories 301a and 301b, the structures of which are substantially the same and are arranged symmetrically with respect to each other. Figure 6A Each of the resistive non-volatile memories 301a and 301b is substantially the same as the Figure 3A resistive non-volatile memory 301.

[0187] In Figure 6A [the figure], the gate of the resistive variable field effect transistor 310b is electrically connected to the bit line BL1, the first end 311 of the resistive variable field effect transistor 310b is floating, and both ends 111 and 112 of the unipolar source / channel / drain diode 110b are electrically connected to the source line SL1 and the second end 312 of the resistive variable field effect transistor 310b respectively. The gate of the resistive variable field effect transistor 310a is electrically connected to the bit line BL0, the first end 311 of the resistive variable field effect transistor 310a is floating, and both ends 111 and 112 of the unipolar source / channel / drain diode 110a are electrically connected to the source line SL1 and the second end 312 of the resistive variable field effect transistor 310a respectively.

[0188] Figure 6B is a layout diagram of a memory cell 600 according to some embodiments of the present invention. As Figure 6B shown, the source line SL0 is located above the diffusion region 612, and the source line SL1 is located above the diffusion region 611.

[0189] Figure 6C is a cross-sectional view of a memory cell 600 according to some embodiments of the present invention. As Figure 6CAs shown, the unipolar source / gate / drain diode 110b includes a floating virtual gate 621, a first source / drain diffusion region 661, and a second source / drain diffusion region 662. The first source / drain diffusion region 661 and the second source / drain diffusion region 662 are respectively located on opposite sides of the floating virtual gate 621. One end of the first source / drain diffusion region 661 contacts one end of a contact plug 670, and the other end of the contact plug 670 contacts a source line SL1. In practice, for example, the floating virtual gate 621 has no gate electrode and is not connected to any wire. Figure 6C The first source / drain diffusion region 661 and the second source / drain diffusion region 662 of Figure 6A serve as the two ends 111, 112 of the unipolar source / gate / drain diode 110b of

[0190] The unipolar source / gate / drain diodes 110a and 110b share the first source / drain diffusion region 661. The unipolar source / gate / drain diode 110a includes a floating virtual gate 622, a first source / drain diffusion region 661, and a third source / drain diffusion region 663. In practice, for example, the floating virtual gate 622 has no gate electrode and is not connected to any wire. Figure 6C The second source / drain diffusion region 661 and the third source / drain diffusion region 663 of Figure 6A serve as the two ends 111, 112 of the unipolar source / gate / drain diode 110a of

[0191] In Figure 6C , the unipolar source / gate / drain diode 110b and the resistive variable field effect transistor 310b share the second source / drain diffusion region 662. The resistive variable field effect transistor 310b includes a shallow trench isolation 651. The shallow trench isolation 651 directly contacts the gate 313 of the resistive variable field effect transistor 310b. The shallow trench isolation 651 and the second source / drain diffusion region 662 are respectively located on opposite sides of the gate 313 of the resistive variable field effect transistor 310b, and a channel region 630 is between the shallow trench isolation 651 and the second source / drain diffusion region 662. Figure 6C The shallow trench isolation 651 of Figure 6A serves as the first end 311 of the resistive variable field effect transistor 310b of Figure 6C The second source / drain diffusion region 622 of Figure 6A serves as the second end 312 of the resistive variable field effect transistor 310b of

[0192] In practice, for example, the gate 313 of the resistive variable field effect transistor 310b includes a gate dielectric layer 601 and a gate electrode layer 602. The outer side of the gate dielectric layer 601 is connected to the gate spacer 640, the inner side of the gate dielectric layer 601 is connected to the outer side of the gate electrode layer 602, and the inner side of the gate electrode layer 602 is connected to the bit line BL1.

[0193] The unipolar source / channel / drain diode 110a shares the third source / drain diffusion region 663 with the resistive variable field effect transistor 310a. The resistive variable field effect transistor 310a includes a shallow trench isolation 652. The shallow trench isolation 652 directly contacts the gate 313 of the resistive variable field effect transistor 310a. The shallow trench isolation 652 and the third source / drain diffusion region 663 are respectively located on opposite sides of the gate 313 of the resistive variable field effect transistor 310a, and the channel region is between the shallow trench isolation 652 and the third source / drain diffusion region 663. Figure 6C The shallow trench isolation 652 serves as Figure 6A the first end 311 of the resistive variable field effect transistor 310a of Figure 6C The third source / drain diffusion region 663 serves as Figure 6A the second end 312 of the resistive variable field effect transistor 310a of

[0194] In other embodiments, Figures 3A to 3D the circuits of the resistive non-volatile memories 301 to 304 of Figure 6C can all be applied to the

[0195] Figure 7A is a circuit diagram of a resistive non-volatile memory 700 according to some embodiments of the present invention. Figure 7A The internal structure of the resistive non-volatile memory 700 of Figure 4C is substantially the same as the internal structure of the resistive non-volatile memory 403 of

[0196] Figure 7B is a layout diagram of a resistive non-volatile memory 700 according to some embodiments of the present invention. Figure 7B The N-type well region 711 and the P-type well region 712 are presented in

[0197] Figure 7C is a cross-sectional view of a resistive non-volatile memory 700 according to some embodiments of the present invention. As Figure 7C shown, the unipolar source / channel / drain diode 140 includes a floating virtual gate 721, a first source / drain diffusion region 761, and a second source / drain diffusion region 762. The first source / drain diffusion region 761 and the second source / drain diffusion region 762 are respectively located on opposite sides of the floating virtual gate 721.

[0198] In Figure 7C Figure 7C , the resistive non-volatile memory 700 further includes a first conductive layer 781, a second conductive layer 782, a first contact plug 771, a second contact plug 772, a third contact plug 773, and a fourth contact plug 774. The first conductive layer 781 and the second conductive layer 782 are electrically isolated from each other. Two ends of the first contact plug 771 are respectively in contact with the first source / drain diffusion region 761 and the first conductive layer 781. Two ends of the second contact plug 772 are respectively in contact with the first conductive layer 781 and the source line SL0. Two ends of the third contact plug 773 are respectively in contact with the second source / drain diffusion region 762 and the second conductive layer 782. Two ends of the fourth contact plug 774 are respectively in contact with the gate 433 of the resistive variable field effect transistor 430 and the second conductive layer 782.

[0199] In Figure 7C Figure 7C , the resistive variable field effect transistor 430 includes a shallow trench isolation 751 and a third source / drain diffusion region 763. The shallow trench isolation 751 directly contacts the gate 433 of the resistive variable field effect transistor 430, Figure 7C the shallow trench isolation 751 of Figure 7A serves as the first end 431 of the resistive variable field effect transistor 430 of Figure 7C The third source / drain diffusion region 763 and the shallow trench isolation 751 are respectively located on opposite sides of the gate 433 of the resistive variable field effect transistor 430,

[0200] In Figure 7C Figure 7C , the resistive non-volatile memory 700 further includes a fifth contact plug 775. Two ends of the fifth contact plug 775 are respectively in contact with the third source / drain diffusion region 763 and the bit line BL0.

[0201] In other embodiments, Figures 4A to 4D the circuits of the resistive non-volatile memories 401-404 of Figure 7C can all be applied to the cross-sectional structure of

[0202] Figure 8A Figure 8A is a circuit diagram of a memory cell 800 according to some embodiments of the present invention. The memory cell 800 includes resistive non-volatile memories 403a, 403b, which have substantially the same structure and are arranged symmetrically with respect to each other. Figure 8A Each of the resistive non-volatile memories 403a, 403b of Figure 4C is the same as the resistive non-volatile memory 403 of

[0203] Figure 8Bis a layout schematic diagram of a memory cell 800 according to some embodiments of the present invention. As Figure 8B shown, bit line BL0 is located above diffusion region 812, and bit line BL1 is located above diffusion region 811.

[0204] Figure 8C is a cross-sectional view of a memory cell 800 according to some embodiments of the present invention. As Figure 8C shown, the unipolar source / channel / drain diode 140a includes a floating virtual gate 822, source / drain diffusion regions 865 and 864. The source / drain diffusion regions 865 and 864 are respectively located on opposite sides of the floating virtual gate 822. Both ends of the contact plug 877 are in contact with the source / drain diffusion region 865 and the source line SL1 respectively.

[0205] The resistive random access field effect transistor 430a includes a gate 433, a shallow trench isolation 852, and source / drain diffusion regions 863. The shallow trench isolation 852 and the source / drain diffusion regions 863 are respectively located on opposite sides of the gate 433 of the resistive random access field effect transistor 430a. The shallow trench isolation 852 is in direct contact with the gate 433 of the resistive random access field effect transistor 430a. The shallow trench isolation 852 is located beside the source / drain diffusion region 864. Both ends of the contact plug 875 are in contact with the source / drain diffusion region 864 and the conductive layer 882 respectively, and both ends of the contact plug 876 are in contact with the gate 433 of the resistive random access field effect transistor 430a and the conductive layer 882 respectively.

[0206] Both ends of the contact plug 870 are in contact with the source / drain diffusion region 863 and the conductive layer 880 respectively. Both ends of the contact plug 871 are in contact with the conductive layer 880 and the bit line BL1 respectively.

[0207] The unipolar source / channel / drain diode 140b includes a floating virtual gate 821, source / drain diffusion regions 861 and 862. The source / drain diffusion regions 861 and 862 are respectively located on opposite sides of the floating virtual gate 821. Both ends of the contact plug 874 are in contact with the source / drain diffusion region 861 and the source line SL2 respectively. Both ends of the contact plug 872 are in contact with the source / drain diffusion region 862 and the conductive layer 881 respectively.

[0208] The resistive variable field effect transistor 430b includes a gate 433, a shallow trench isolation 851, and source / drain diffusion regions 862. The shallow trench isolation 851 and the source / drain diffusion regions 863 are respectively located on opposite sides of the gate 433 of the resistive variable field effect transistor 430b. The shallow trench isolation 851 directly contacts the gate 433 of the resistive variable field effect transistor 430b. The shallow trench isolation 851 is located beside the source / drain diffusion regions 862. Both ends of a contact plug 873 respectively contact the gate 433 of the resistive variable field effect transistor 430b and a conductive layer 881.

[0209] Figure 9A is a circuit diagram of a resistive non-volatile memory 901 according to some embodiments of the present invention. Figure 9A The resistive non-volatile memory 901 of Figure 3A is an extended architecture of the resistive non-volatile memory 301 of Figure 9A As shown, a plurality of resistive variable field effect transistors 310 are respectively electrically connected to bit lines BL0, BL1... BLn, and both ends of a unipolar source / channel / drain diode 110 are respectively electrically connected to a source line SL and the plurality of resistive variable field effect transistors 310.

[0210] Figure 9B is a circuit diagram of a resistive non-volatile memory 902 according to some embodiments of the present invention. Figure 9B The resistive non-volatile memory 902 of Figure 3B is an extended architecture of the resistive non-volatile memory 302 of Figure 9B As shown, a plurality of resistive variable field effect transistors 320 are respectively electrically connected to bit lines BL0, BL1... BLn, and both ends of a unipolar source / channel / drain diode 110 are respectively electrically connected to a source line SL and the plurality of resistive variable field effect transistors 320.

[0211] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 901 to 902 are the same. For the sake of simplicity of description, hereinafter, taking the operation of the resistive non-volatile memory 901 as an example, a zero voltage is applied to one of the bit lines BL0, BL1... BLn and the source line SL, and a non-zero voltage is applied to the other of the bit lines BL0, BL1... BLn and the source line SL to operate the resistive non-volatile memory 901.

[0212] Specifically, in the startup stage, when the resistive variable field-effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a startup voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the startup voltage is applied to the bit lines BL1...BLn, and a zero voltage is applied to the source line SL, so that a conductive filament is formed in the gate dielectric layer of the gate of the resistive variable field-effect transistor 310 connected to the bit line BL0; in the setting stage, when the resistive variable field-effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a setting voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the setting voltage is applied to the bit lines BL1...BLn, and a zero voltage is applied to the source line SL, so that the gate dielectric layer of the gate of the resistive variable field-effect transistor 310 connected to the bit line BL0 is in the first resistance state, where the absolute value of the setting voltage is less than or equal to the absolute value of the startup voltage; in the reset stage, when the resistive variable field-effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a reset voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the reset voltage is applied to the bit lines BL1...BLn, and a zero voltage is applied to the source line SL, so that the gate dielectric layer of the gate of the resistive variable field-effect transistor 310 connected to the bit line BL0 is in the second resistance state, where the absolute value of the reset voltage is less than the absolute value of the setting voltage; in the read stage, when the resistive variable field-effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a read voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the read voltage is applied to the bit lines BL1...BLn, and a zero voltage is applied to the source line SL, where the absolute value of the read voltage is less than the absolute value of the reset voltage. The read circuit determines whether the resistive non-volatile memory 301 connected to the bit line BL0 is set or reset according to the level of the read current.

[0213] On the other hand, in the startup stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the source line SL, and zero voltages are applied to the bit lines BL0, BL1...BLn; in the setting stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the source line SL, and zero voltages are applied to the bit lines BL0, BL1...BLn; in the reset stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the source line SL, and zero voltages are applied to the bit lines BL0, BL1...BLn; in the read stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the read voltage is applied to the source line SL, and zero voltages are applied to the bit lines BL0, BL1...BLn.

[0214] Figure 10A It is a circuit diagram of a resistive non-volatile memory 1001 according to some embodiments of the present invention. Figure 10A The resistive non-volatile memory 1001 is Figure 4A an extended architecture of the resistive non-volatile memory 401. As Figure 10A shown, a plurality of resistive variable field effect transistors 410 are electrically connected to bit lines BL0, BL1... BLn respectively, and both ends of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the plurality of resistive variable field effect transistors 410.

[0215] Figure 10B It is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention. Figure 10B The resistive non-volatile memory 1002 is Figure 4C an extended architecture of the resistive non-volatile memory 403. As Figure 10B shown, a plurality of resistive variable field effect transistors 430 are electrically connected to bit lines BL0, BL1... BLn respectively, and both ends of the unipolar source / channel / drain diode 140 are electrically connected to the source line SL and the plurality of resistive variable field effect transistors 430.

[0216] Figure 10C It is a circuit diagram of a resistive non-volatile memory 1003 according to some embodiments of the present invention. Figure 10C The resistive non-volatile memory 1003 is Figure 4D an extended architecture of the resistive non-volatile memory 404. As Figure 10C shown, a plurality of resistive variable field effect transistors 440 are electrically connected to bit lines BL0, BL1... BLn respectively, and both ends of the unipolar source / channel / drain diode 130 are electrically connected to the source line SL and the plurality of resistive variable field effect transistors 440.

[0217] Figure 10D It is a circuit diagram of a resistive non-volatile memory 1004 according to some embodiments of the present invention. Figure 10D The resistive non-volatile memory 1004 is Figure 4D an extended architecture of the resistive non-volatile memory 402. As Figure 10D shown, a plurality of resistive variable field effect transistors 420 are electrically connected to bit lines BL0, BL1... BLn respectively, and both ends of the unipolar source / channel / drain diode 130 are electrically connected to the source line SL and the plurality of resistive variable field effect transistors 420.

[0218] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 1001 to 1004 are the same, and are opposite to the voltage application methods of the operation methods of 901 to 902, so they will not be described in detail herein.

[0219] Figure 11 is a circuit diagram of a memory circuit according to some embodiments of the present invention. As Figure 11 shown, the memory circuit includes a plurality of memory cells 1105 arranged in an array. Each memory cell 1105 includes a resistive non-volatile memory 1101. In practice, for example, the architecture of the resistive non-volatile memory 1101 can be any one of the above resistive non-volatile memories 901 to 902, 1001 to 1004.

[0220] In Figure 11 it, the circuit 1111 is electrically connected to one end of the unipolar source / channel / drain diode in the corresponding resistive non-volatile memory 1101 through the source lines SL0 to SLn respectively. On the other hand, the circuit 1112 is electrically connected to the resistive variable field effect transistor in the corresponding resistive non-volatile memory 1101 through the bit lines BL0 to BLn, BLn+1 to BLh, BLh+1 to BLp, BLm-k-2 to BLm respectively. In practice, for example, the circuit 1111 includes a source line peripheral circuit and a control circuit, the circuit 1112 includes a bit line peripheral circuit and a control circuit, and the read circuit can be selectively arranged in the circuit 1111 or the circuit 1112.

[0221] Figure 12A is a circuit diagram of a resistive non-volatile memory 1200 according to some embodiments of the present invention. Figure 12A The internal structure of the resistive non-volatile memory 1200 is substantially the same as that of Figure 10A the internal structure of the resistive non-volatile memory 1001. The structure of each of the resistive variable field effect transistors 410_0 to 410_n is substantially the same as the structure of the resistive variable field effect transistor 410.

[0222] Figure 12B is a layout diagram of a resistive non-volatile memory 1200 according to some embodiments of the present invention. As Figure 12B shown, the source line SL0 is located above the active region 1212, and the source line SL1 is located above the active region 1211.

[0223] Figure 12C is a cross-sectional view of a resistive non-volatile memory 1200 according to some embodiments of the present invention. As Figure 12CAs shown, the unipolar source / drain diode 140 includes a floating virtual gate 1221, source / drain diffusion regions 1261 and 1262. The source / drain diffusion regions 1261 and 1262 are respectively located on opposite sides of the floating virtual gate 1221. The two ends of the contact plug 1270 are respectively in contact with the source / drain diffusion region 1261 and the conductive layer 1280. The two ends of the contact plug 1271 are respectively in contact with the conductive layer 1280 and the conductive layer 1282. The two ends of the contact plug 1272 are respectively in contact with the conductive layer 1282 and the source line SL0. The two ends of the contact plug 1273 are respectively in contact with the source / drain diffusion region 1262 and the conductive layer 1281. The two ends of the contact plug 1274 are respectively in contact with the conductive layer 1281 and the conductive layer 1283.

[0224] The resistive random access memory transistor 410_0 includes a gate 413, a shallow trench isolation 1251, and a source / drain diffusion region 1263. The shallow trench isolation 1251 and the source / drain diffusion region 1263 are respectively located on opposite sides of the gate 413 of the resistive random access memory transistor 410_0. The shallow trench isolation 1251 is in direct contact with the gate 413 of the resistive random access memory transistor 410_0. The shallow trench isolation 1251 is located beside the source / drain diffusion region 1262. The two ends of the contact plug 1275 are respectively in contact with the gate 413 of the resistive random access memory transistor 410_0 and the conductive layer 1283. The two ends of the contact plug 1290 are respectively in contact with the source / drain diffusion region 1263 and the bit line BL0.

[0225] The resistive random access memory transistor 410_1 includes a gate 413, a source / drain diffusion region 1263, and a source / drain diffusion region 1264. The source / drain diffusion region 1263 and the source / drain diffusion region 1264 are respectively located on opposite sides of the gate 413 of the resistive random access memory transistor 410_1. The two ends of the contact plug 1276 are respectively in contact with the gate 413 of the resistive random access memory transistor 410_1 and the conductive layer 1283. The two ends of the contact plug 1291 are respectively in contact with the source / drain diffusion region 1264 and the bit line BL1.

[0226] The resistive random access memory transistor 410_2 includes a gate 413, a source / drain diffusion region 1264, and a source / drain diffusion region 1265. The source / drain diffusion region 1264 and the source / drain diffusion region 1265 are respectively located on opposite sides of the gate 413 of the resistive random access memory transistor 410_2. The two ends of the contact plug 1277 are respectively in contact with the gate 413 of the resistive random access memory transistor 410_2 and the conductive layer 1283. The two ends of the contact plug 1292 are respectively in contact with the source / drain diffusion region 1265 and the bit line BL2.

[0227] The resistive variable field effect transistor 410_3 includes a gate 413, a source / drain diffusion region 1265, and a source / drain diffusion region 1266. The source / drain diffusion region 1265 and the source / drain diffusion region 1266 are respectively located on opposite sides of the gate 413 of the resistive variable field effect transistor 410_3. Two ends of a contact plug 1278 respectively contact the gate 413 of the resistive variable field effect transistor 410_3 and a conductive layer 1283, and two ends of a contact plug 1293 respectively contact the source / drain diffusion region 1266 and a bit line BL3. A shallow trench isolation 1252 is located beside the source / drain diffusion region 1266.

[0228] Figure 13A is a circuit diagram of a resistive non-volatile memory 1300 according to some embodiments of the present invention. Figure 13A The internal structure of the resistive non-volatile memory 1200 is substantially the same as Figure 10A the internal structure of the resistive non-volatile memory 1001.

[0229] Figure 13B is a layout schematic diagram of a resistive non-volatile memory 1300 according to some embodiments of the present invention. As Figure 13B shown, a source line SL0 is located above an active region 1312, and a source line SL1 is located above an active region 1311.

[0230] Figure 13C is a cross-sectional view of a resistive non-volatile memory 1300 according to some embodiments of the present invention. As Figure 13C shown, a unipolar source / channel / drain diode 140 includes a floating virtual gate 1321, a source / drain diffusion region 1361, and a source / drain diffusion region 1360. The source / drain diffusion region 1361 and the source / drain diffusion region 1360 are respectively located on opposite sides of the floating virtual gate 1321. Two ends of a contact plug 1370 respectively contact the source / drain diffusion region 1361 and a conductive layer 1380, two ends of a contact plug 1371 respectively contact the conductive layer 1380 and a conductive layer 1382, and two ends of a contact plug 1272 respectively contact a conductive layer 1282 and a source line SL0. Two ends of a contact plug 1273 respectively contact the source / drain diffusion region 1360 and a conductive layer 1381, and two ends of a contact plug 1374 respectively contact the conductive layer 1381 and a conductive layer 1383.

[0231] The resistive variable field effect transistor 410_0 includes a gate 413, a shallow trench isolation 1351, and a source / drain diffusion region 1362. The shallow trench isolation 1351 and the source / drain diffusion region 1362 are respectively located on opposite sides of the gate 413 of the resistive variable field effect transistor 410_0. A channel region 1330 is between the shallow trench isolation 1351 and the source / drain diffusion region 1362. The shallow trench isolation 1351 directly contacts the gate 413 of the resistive variable field effect transistor 410_0. The shallow trench isolation 1351 is located beside the source / drain diffusion region 1360. Two ends of a contact plug 1375 respectively contact the gate 413 of the resistive variable field effect transistor 410_0 and a conductive layer 1383, and two ends of a contact plug 1390 respectively contact the source / drain diffusion region 1362 and a bit line BL0.

[0232] The resistive variable field effect transistor 410_1 includes a gate 413, a shallow trench isolation 1352, and a source / drain diffusion region 1363. The shallow trench isolation 1352 and the source / drain diffusion region 1363 are respectively located on opposite sides of the gate 413 of the resistive variable field effect transistor 410_1. The shallow trench isolation 1352 directly contacts the gate 413 of the resistive variable field effect transistor 410_1. The shallow trench isolation 1352 is located beside the source / drain diffusion region 1362. Two ends of a contact plug 1376 respectively contact the gate 413 of the resistive variable field effect transistor 410_1 and a conductive layer 1383, and two ends of a contact plug 1391 respectively contact the source / drain diffusion region 1363 and a bit line BL1.

[0233] The resistive variable field effect transistor 410_2 includes a gate 413, a shallow trench isolation 1353, and a source / drain diffusion region 1364. The shallow trench isolation 1353 and the source / drain diffusion region 1364 are respectively located on opposite sides of the gate 413 of the resistive variable field effect transistor 410_2. The shallow trench isolation 1353 directly contacts the gate 413 of the resistive variable field effect transistor 410_2. The shallow trench isolation 1353 is located beside the source / drain diffusion region 1363. Two ends of a contact plug 1377 respectively contact the gate 413 of the resistive variable field effect transistor 410_2 and a conductive layer 1383, and two ends of a contact plug 1392 respectively contact the source / drain diffusion region 1364 and a bit line BL2.

[0234] The resistive variable field effect transistor 410_3 includes a gate 413, a shallow trench isolation 1354, and a source / drain diffusion region 1365. The shallow trench isolation 1354 and the source / drain diffusion region 1365 are respectively located on opposite sides of the gate 413 of the resistive variable field effect transistor 410_3. The shallow trench isolation 1354 directly contacts the gate 413 of the resistive variable field effect transistor 410_3. The shallow trench isolation 1354 is located beside the source / drain diffusion region 1364. Both ends of the contact plug 1378 respectively contact the gate 413 of the resistive variable field effect transistor 410_3 and the conductive layer 1384, and both ends of the contact plug 1393 respectively contact the source / drain diffusion region 1365 and the bit line BL3.

[0235] In summary, compared with the prior art, the technical solution of the present invention has obvious advantages and beneficial effects. The resistive non-volatile memory of the present invention does not require an additional word line and its related circuits, realizes an ultra-miniaturized chip size, is beneficial to the continuous miniaturization of CMOS, and a more streamlined chip configuration layout and higher cost efficiency.

[0236] Although the present invention has been disclosed as above in embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the appended claims.

Claims

1. A resistive non-volatile memory, characterized in that: Include: at least one resistance variable field effect transistor electrically connected to at least one bit line; as well as A unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode. Two ends of the unipolar source / channel / drain diode are electrically connected to a source line and the at least one variable resistance field effect transistor respectively.

2. The resistive non-volatile memory according to claim 1, wherein: A gate of the at least one resistance variable field effect transistor is electrically connected to the at least one bit line, a first end of the at least one resistance variable field effect transistor is floating, two ends of the unipolar source / channel / drain diode are respectively electrically connected to the source line and a second end of the at least one resistance variable field effect transistor, and the unipolar source / channel / drain diode is an npn type diode or a nin type diode.

3. The resistive non-volatile memory according to claim 2, wherein: This unipolar source / channel / drain diode contains: a floating dummy gate; and A first source / drain diffusion region and a second source / drain diffusion region are respectively located at two opposite sides of the floating virtual gate. The first source / drain diffusion region contacts one end of a contact plug, and the other end of the contact plug contacts the source line.

4. The resistive non-volatile memory as claimed in claim 3, wherein: The unipolar source / channel / drain diode shares the second source / drain diffusion region with the at least one resistance variable field effect transistor, and the at least one resistance variable field effect transistor comprises: A shallow trench isolation directly contacts the gate of the at least one resistance variable field effect transistor. The shallow trench isolation and the second source / drain diffusion region are respectively located on opposite sides of the gate of the at least one resistance variable field effect transistor. The shallow trench isolation serves as the first end of the at least one resistance variable field effect transistor, and the second source / drain diffusion region serves as the second end of the at least one resistance variable field effect transistor.

5. The resistive non-volatile memory according to claim 1, wherein: Two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a gate of the at least one variable resistance field effect transistor, respectively. A first end of the at least one variable resistance field effect transistor is floating. A second end of the at least one variable resistance field effect transistor is electrically connected to the at least one bit line. The unipolar source / channel / drain diode is a pnp type diode or a pip type diode.

6. The resistive non-volatile memory according to claim 5, wherein: The unipolar source / channel / drain diode comprises: a floating dummy gate; and A first source / drain diffusion region and a second source / drain diffusion region are respectively located at two opposite sides of the floating dummy gate.

7. The resistive non-volatile memory according to claim 6, wherein: Also includes: A first conductive layer and a second conductive layer are electrically isolated from each other; a first contact plug, two ends of which contact the first source / drain diffusion region and the first conductive layer respectively; a second contact plug, two ends of which contact the first conductive layer and the source line respectively; a third contact plug, two ends of which contact the second source / drain diffusion region and the second conductive layer respectively; and A fourth contact plug has two ends contacting the gate of the at least one resistance variable field effect transistor and the second conductive layer respectively.

8. The resistive non-volatile memory according to claim 7, wherein: The at least one resistance variable field effect transistor comprises: a shallow trench isolation directly contacting the gate of the at least one resistance variable field effect transistor, the shallow trench isolation serving as the first end of the at least one resistance variable field effect transistor; and A third source / drain diffusion region and the shallow trench isolation are respectively located on two opposite sides of the gate of the at least one resistance variable field effect transistor, and the third source / drain diffusion region serves as the second end of the at least one resistance variable field effect transistor.

9. The resistive non-volatile memory according to claim 8, wherein: Also includes: A fifth contact plug has two ends contacting the third source / drain diffusion region and the at least one bit line respectively.

10. A memory circuit, characterized in that: Include: A plurality of memory cells are arranged in an array, each of the memory cells comprises a resistive non-volatile memory, and the resistive non-volatile memory comprises: at least one resistance variable field effect transistor electrically connected to at least one bit line; and A unipolar source / channel / drain diode is formed by a field effect transistor without a gate electrode. Two ends of the unipolar source / channel / drain diode are electrically connected to a source line and the at least one variable resistance field effect transistor respectively.

11. The memory circuit according to claim 10, wherein: Each of the memory cells includes another resistive non-volatile memory, one end of the other resistive non-volatile memory is electrically connected to the resistive non-volatile memory and the at least one bit line, and the other end of the other resistive non-volatile memory is electrically connected to another source line.

12. The memory circuit according to claim 10, wherein: Each of the memory cells includes another resistive non-volatile memory. One end of the other resistive non-volatile memory is electrically connected to the resistive non-volatile memory and the source line, and the other end of the other resistive non-volatile memory is electrically connected to the at least one bit line.

13. The memory circuit according to claim 10, wherein: A gate of the at least one resistance variable field effect transistor is electrically connected to the at least one bit line, a first terminal of the at least one resistance variable field effect transistor is floating, two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a second terminal of the at least one resistance variable field effect transistor, respectively, each of the memory cells includes another resistance non-volatile memory, and the other resistance non-volatile memory includes: At least one other resistance variable field effect transistor, a gate of which is electrically connected to at least one other bit line, and a first terminal of the at least one other resistance variable field effect transistor is floating; and Another unipolar source / channel / drain diode is formed by another field effect transistor without a gate electrode, and two ends of the other unipolar source / channel / drain diode are respectively electrically connected to the source line and a second end of the at least one other variable resistance field effect transistor.

14. The memory circuit according to claim 10, wherein: Two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a gate of the at least one resistance variable field effect transistor, respectively. A first end of the at least one resistance variable field effect transistor is floating, and a second end of the at least one resistance variable field effect transistor is electrically connected to the at least one bit line. Each of the memory cells includes another resistance non-volatile memory, and the other resistance non-volatile memory includes: Another at least one resistance variable field effect transistor, a first terminal of which is floating, and a second terminal of the another at least one resistance variable field effect transistor is electrically connected to the at least one bit line; and Another unipolar source / channel / drain diode is formed by another field effect transistor without a gate electrode. Two ends of the other unipolar source / channel / drain diode are respectively electrically connected to another source line and a gate of the at least one other variable resistance field effect transistor.

15. A method for operating a resistive non-volatile memory, characterized in that: The resistive non-volatile memory comprises a resistance variable field effect transistor and a unipolar source / channel / drain diode connected to each other, and the operating method comprises the following steps: A zero voltage is applied to one of a bit line and a source line, and a non-zero voltage is applied to the other of the bit line and the source line to operate the resistive non-volatile memory, wherein the resistance variable field effect transistor is electrically connected to the bit line, the unipolar source / channel / drain diode is composed of a field effect transistor without a gate electrode, and two ends of the unipolar source / channel / drain diode are electrically connected to the source line and the resistance variable field effect transistor respectively.

16. The operating method according to claim 15, characterized in that: A gate of the resistance variable field effect transistor is electrically connected to the bit line, a first end of the resistance variable field effect transistor is floating, two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a second end of the resistance variable field effect transistor respectively, the unipolar source / channel / drain diode is an npn type diode or a nin type diode, and the operation method further includes: In a startup phase, when the resistive non-volatile memory is selected, a startup voltage is applied to the bit line and the zero voltage is applied to the source line; In a setting phase, when the resistive non-volatile memory is selected, a setting voltage is applied to the bit line and the zero voltage is applied to the source line, wherein the absolute value of the setting voltage is less than or equal to the absolute value of the start-up voltage; In a reset phase, when the resistive non-volatile memory is selected, a reset voltage is applied to the bit line and the zero voltage is applied to the source line, wherein the absolute value of the reset voltage is smaller than the absolute value of the set voltage; and In a read phase, when the resistive non-volatile memory is selected, a read voltage is applied to the bit line and the zero voltage is applied to the source line, wherein the absolute value of the read voltage is smaller than the absolute value of the reset voltage.

17. The operating method according to claim 16, characterized in that: Also includes: In the startup phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the source line, and a zero voltage is applied to the bit line; In the setting phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the source line, and a zero voltage is applied to the bit line; In the reset phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the source line, and a zero voltage is applied to the bit line; and In the reading phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the reading voltage is applied to the source line, and the zero voltage is applied to the bit line.

18. The operating method according to claim 15, characterized in that: Two ends of the unipolar source / channel / drain diode are electrically connected to the source line and a gate of the variable resistance field effect transistor, respectively. A first end of the variable resistance field effect transistor is floating. A second end of the variable resistance field effect transistor is electrically connected to the bit line. The unipolar source / channel / drain diode is a pnp type diode or a pip type diode. The operation method further includes: In a startup phase, when the resistive non-volatile memory is selected, a startup voltage is applied to the source line and the zero voltage is applied to the bit line; In a setting phase, when the resistive non-volatile memory is selected, a setting voltage is applied to the source line and the zero voltage is applied to the bit line, wherein the absolute value of the setting voltage is less than or equal to the absolute value of the start-up voltage; In a reset phase, when the resistive non-volatile memory is selected, a reset voltage is applied to the source line and the zero voltage is applied to the bit line, wherein the absolute value of the reset voltage is smaller than the absolute value of the set voltage; and In a read phase, when the resistive non-volatile memory is selected, a read voltage is applied to the source line and the zero voltage is applied to the bit line, wherein the absolute value of the read voltage is smaller than the absolute value of the reset voltage.

19. The operating method according to claim 18, characterized in that: Also includes: In the startup phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the bit line, and a zero voltage is applied to the source line; In the setting phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the bit line, and a zero voltage is applied to the source line; In the reset phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the bit line, and zero voltage is applied to the source line; and In the reading phase, when the resistive non-volatile memory is not selected, a voltage between one-half and one-fifth of the reading voltage is applied to the bit line, and the zero voltage is applied to the source line.

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