A high-reliability UIS planar gate silicon carbide VDMOS and its preparation method

Abstract

The present invention provides a high-reliability UIS planar gate silicon carbide VDMOS and a preparation method thereof. The method comprises: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; performing epitaxial growth on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a gate protection zone, a shunt zone, and a source protection zone; grounding the source protection zone; performing ion implantation again to form a P-type well zone, and forming a convex portion on the drift layer; reforming the barrier layer, etching, and ion implanting to form a P-type source zone and an N-type source zone; reforming the barrier layer, etching, and depositing to form an insulating dielectric layer, a gate metal layer, and a source metal layer, wherein the gate protection zone and the source protection zone connected to the ground ensure that a parasitic NPN transistor inside the device is turned off when a drain voltage impacts, thereby improving the UIS resistance of the device and improving the device reliability.

Description

Technical Field

[0001] The invention relates to a high-reliability UIS planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to their wide bandgap characteristics, silicon carbide VDMOS devices naturally have the characteristics of low gate charge and high switching speed compared to Si VDMOS devices. However, under high voltage (above 1000V) and high current (above 100A) application conditions, a single silicon carbide VDMOS device cannot meet the application requirements, and multiple devices need to be used in parallel. During the shutdown process of the parallel application devices, since the device distribution cannot be completely stacked, current will rush to a single silicon carbide VDMOS device, causing the VDMOS device to burn out. Therefore, existing technologies have higher requirements for the UIS characteristics of VDMOS devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-reliability UIS planar gate silicon carbide VDMOS and a preparation method thereof. By using a gate protection zone and a source protection zone connected to the ground, the parasitic NPN transistor inside the device is guaranteed to be turned off when the drain voltage surges, thereby improving the UIS resistance of the device and improving the device reliability.

[0004] In a first aspect, the present invention provides a method for preparing a high-reliability UIS planar gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a gate protection area;

[0007] Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a shunt area;

[0008] Step 4: remove the barrier layer of step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a source protection zone; and ground the source protection zone;

[0009] Step 5: Perform ion implantation again to form a P-type well region, and form a raised portion on the drift layer;

[0010] Step 6: remove the barrier layer in step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type source region;

[0011] Step 7: remove the barrier layer in step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region;

[0012] Step 8: removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer;

[0013] Step 9: removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate metal layer;

[0014] Step 10: remove the barrier layer of step 9, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form a source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a high-reliability UIS planar gate silicon carbide VDMOS, which is prepared by the method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to the first aspect.

[0016] The advantages of the present invention are:

[0017] First, the present invention constructs a source protection zone, which is grounded. The P-type region in the middle of the NPN transistor in the device's N-type source region-P-type well region-source protection zone-drift layer is always at a low potential, preventing the NPN transistor from conducting, thereby improving the source UIS characteristics of the device;

[0018] 2. The present invention constructs a gate protection zone and a shunt zone structure. When the drain is subjected to a high voltage, the gate protection zone forms a protection for the gate structure. The shunt zone realizes the potential transfer from the drift layer close to the drain to the drift layer close to the gate, thereby ensuring that the NPN structure of the device in the horizontal and vertical directions will not be turned on. In addition to realizing the function of potential transfer, the shunt zone can also reduce the body resistance of the device, which can effectively reduce the on-resistance of the device and reduce the conduction loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0020] Figure 1 This is a schematic diagram of a high-reliability UIS planar gate silicon carbide VDMOS according to the present invention.

[0021] Figure 2 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 1 .

[0022] Figure 3 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 2 .

[0023] Figure 4 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 3 .

[0024] Figure 5 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 4 .

[0025] Figure 6 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 5 .

[0026] Figure 7 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 6 .

[0027] Figure 8 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 7 .

[0028] Figure 9 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 8 .

[0029] Figure 10 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 9 .

[0030] Figure 11 This is a cross-sectional view of the process of a high-reliability UIS planar gate silicon carbide VDMOS of the present invention Figure 10 . DETAILED DESCRIPTION

[0031] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0033] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0034] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0035] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a high-reliability UIS planar gate silicon carbide VDMOS, comprising the following steps:

[0037] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0038] Step 2: forming a barrier layer 100 on the drift layer 2, etching the barrier layer 100 to form a through hole, and performing ion implantation to form a gate protection area 21;

[0039] Step 3: removing the barrier layer 100 of step 2, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a shunt region 22;

[0040] Step 4: removing the barrier layer 100 of step 3, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a source protection zone 3; and grounding the source protection zone 3;

[0041] Step 5: Perform ion implantation again to form a P-type well region 4 and a protrusion 23 on the drift layer 2;

[0042] Step 6: removing the barrier layer 100 of step 4, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form a P-type source region 42;

[0043] Step 7: removing the barrier layer 100 in step 6, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and implanting ions to form an N-type source region 41;

[0044] Step 8: removing the barrier layer 100 of step 7, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing to form an insulating dielectric layer 5;

[0045] Step 9: removing the barrier layer 100 of step 8, re-forming the barrier layer 100, etching the barrier layer 100 to form a through hole, and depositing to form a gate metal layer 6;

[0046] Step 10: remove the barrier layer 100 of step 9, re-form the barrier layer 100, etch the barrier layer 100 to form a through hole, deposit to form a source metal layer 7, remove the barrier layer 100, and complete the preparation.

[0047] In this embodiment, preferably, the width of the gate protection zone 21 is equal to the width of the protrusion 23 , and the gate protection zone 21 is located directly below the protrusion 23 .

[0048] In this embodiment, preferably, the thickness of the gate protection area 21 is smaller than the thickness of the shunt area 22 , and the lower side surface of the gate protection area 21 and the lower side surface of the shunt area 22 are located in the same plane.

[0049] In this embodiment, preferably, the doping concentration of the gate protection area 21 is lower than the doping concentration of the shunt area 22 .

[0050] In this embodiment, preferably, the width of the shunt region 22 is equal to the width of the source protection region 3 , and the shunt region 22 is located directly below the source protection region 3 .

[0051] In this embodiment, preferably, the doping concentration of the source protection region 3 is greater than the doping concentration of the drift layer 2 , and the doping concentration of the source protection region 3 is greater than the doping concentration of the P-type well region 4 .

[0052] In this embodiment, preferably, the doping concentration of the P-type well region 4 is lower than the doping concentration of the drift layer 2 .

[0053] In this embodiment, preferably, the silicon carbide substrate 1 , the drift layer 2 and the shunt region 22 are N-type; and the gate protection zone 21 and the source protection zone 3 are P-type.

[0054] like Figure 1 As shown, the planar gate silicon carbide VDMOS obtained by the above manufacturing method includes:

[0055] Silicon carbide substrate 1,

[0056] a drift layer 2, wherein the lower side of the drift layer 2 is connected to the silicon carbide substrate 1, a gate protection area 21 and a shunt area 22 are provided in the drift layer 2, and the outer side of the gate protection area 21 is connected to the inner side of the shunt area 22; and a protrusion 23 is provided on the drift layer 2;

[0057] a source protection zone 3, wherein the lower side of the source protection zone 3 is connected to the upper side of the drift layer 2, and the inner side of the source protection zone 3 is connected to the outer side of the protrusion 23; and the source protection zone 3 is grounded;

[0058] A P-type well region 4, wherein the lower side of the P-type well region 4 is connected to the upper side of the source protection region 3, the inner side of the P-type well region 4 is connected to the outer side of the protrusion 23, an N-type source region 41 and a P-type source region 42 are provided on the P-type well region 4, the outer side of the N-type source region 41 is connected to the inner side of the P-type source region 42, and the inner side of the N-type source region 41 is connected to the P-type well region 4;

[0059] an insulating dielectric layer 5 , wherein the lower side of the insulating dielectric layer 5 is connected to the P-type well region 4 and the protrusion 23 ;

[0060] A gate metal layer 6, wherein the lower side of the gate metal layer 6 is connected to the upper side of the insulating dielectric layer 5;

[0061] a source metal layer 7 , the source metal layer 7 being connected to the P-type source region 42 and the N-type source region 41 ;

[0062] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0063] In another embodiment of the present invention, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of drift layer 2 is 6-10e16cm -3 The doping concentration of the gate protection zone 21 is 5-8e16cm -3 , the doping concentration of the shunt region 22 is 1-5e18cm -3 , the doping concentration of the source protection zone 3 is 5-8e18cm -3 , the doping concentration of the P-type well region 4 is 1-5e15cm -3 , the doping concentration of the P-type source region 42 is 1-5e19cm -3 The insulating dielectric layer 5 may be made of silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm -3 ;

[0064] The doping concentration of the silicon carbide substrate 1 is designed to ensure a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device. The doping concentration of the drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device. The doping concentration of the gate protection zone 21 is designed to reduce the impact on the device's conduction characteristics while ensuring device protection. The doping concentration of the shunt region 22 is not only designed to reduce the device's body resistance and reduce the device's conduction loss, but also to transfer the potential from below the gate protection zone 21 to above the gate protection zone 21, thereby preventing the NPN transistor inside the device from turning on and affecting device reliability. The doping concentration of the source protection zone 3 is designed to transfer the low potential to the P-type well region inside the device, thereby preventing the device's N-type source region 41-P-type well region 4-source protection zone 3-drift layer 2 structure from turning on, thereby improving the device's UIS resistance.

[0065] The doping concentration of the P-type source region 42 is not only to reduce the contact resistance between the P-type source region 42 and the source metal layer 7, thereby reducing the conduction loss of the parasitic PN junction diode of the device, but also to ensure that the diffusion speed of the space charge region in the P-type source region 42 to the gate and source of the device is reduced when the drain voltage is high;

[0066] The doping concentration of the P-type well region 4 is to reduce the gate control charge of the device gate and improve the switching speed of the device. It is also to form a buffer zone between the P-type source region 42 and the N-type source region 41, thereby reducing the electric field strength near the N-type source region 41 and improving the reliability of the device near the N-type source region 41.

[0067] The thickness of the silicon carbide substrate 1 of the device is 1μm, and the thickness of the drift layer 2 is 50-100μm, which is adjusted within the above range according to different requirements for the device's voltage resistance characteristics. The thickness of the gate protection zone 21 is 1μm, and its top is 10μm away from the bottom of the source protection zone 3. The thickness of the gate protection zone 21 is designed to ensure the structure's ability to protect the device gate. The distance between the gate protection zone 21 and the source protection zone 3 is designed to avoid affecting the device's conductive channel while making the ion implantation depth as shallow as possible to reduce the difficulty of preparation. The thickness of the shunt region 22 is 1.5 times the thickness of the gate protection region 21, and the lower side of the shunt region 22 is flush with the lower side of the gate protection region 21. Such a structure can transfer the potential from the lower side of the gate protection region 21 to the upper side of the gate protection region 21, thereby ensuring that the parasitic body diode is not conductive. The thickness relationship between the shunt region 22 and the gate protection region 21 can reduce the body resistance of the device and reduce the conduction loss; the thickness of the source protection region 3 is 500nm, which is to ensure the protection effect of the device source, the thickness of the P-type well region 4 is 600nm, the thickness of the N-type source region 41 and the P-type source region 42 is 300nm, and the thickness of the device insulating dielectric layer 5 is 50nm.

[0068] The width of the device's P-type source region 42 is 1 μm, the width of the N-type source region 41 is 500 nm, and the width of the P-type well region 4 is 1.8 μm. The width of the P-type source region 42 is designed to ensure the device's body diode freewheeling capability. The width of the N-type source region 41 only needs to ensure a low-resistance ohmic contact with the source metal layer 7, and its width has little effect on the device's characteristics. The width of the P-type well region 4 is a gate-controlled structure formed on the basis of the P-type source region 42 and the N-type source region 41. The width of the source protection zone 3 is 1.8 μm to ensure that the potential is fully transferred to the P-type well region 4. The width of the device's insulating dielectric layer 5 is 2.7 μm, distributed in the middle of the device. The width of the device's gate metal layer 6 is 2.6 μm. This is to ensure the device's gate control capability and gate structure preparation margin. The thickness of the device's gate metal layer 6 is 250 nm, the thickness of the source metal layer 7 is 300 nm, the width of the shunt region 22 is 1.8 μm, and the width of the gate protection region 21 is 2 μm. This is because the shunt region 22 can be prepared using the same photoresist as the source protection region 3 without affecting the device's characteristics, thereby reducing process costs.

[0069] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a high-reliability UIS planar gate silicon carbide VDMOS, characterized by: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a gate protection area; Step 3: removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a shunt area; Step 4: remove the barrier layer of step 3, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a source protection zone; and ground the source protection zone; Step 5: Perform ion implantation again to form a P-type well region, and form a raised portion on the drift layer; Step 6: remove the barrier layer in step 4, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form a P-type source region; Step 7: remove the barrier layer in step 6, re-form the barrier layer, etch the barrier layer to form a through hole, and implant ions to form an N-type source region; Step 8: removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9: removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate metal layer; Step 10: remove the barrier layer of step 9, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form a source metal layer, remove the barrier layer, and complete the preparation; The lower side of the drift layer is connected to the silicon carbide substrate, a gate protection area and a shunt area are provided in the drift layer, and the outer side of the gate protection area is connected to the inner side of the shunt area; a protrusion is provided on the drift layer; The lower side surface of the source protection zone is connected to the upper side surface of the drift layer, and the inner side surface of the source protection zone is connected to the outer side surface of the protrusion; The lower side of the P-type well region is connected to the upper side of the source protection zone, the inner side of the P-type well region is connected to the outer side of the protrusion, an N-type source region and a P-type source region are provided on the P-type well region, the outer side of the N-type source region is connected to the inner side of the P-type source region, and the inner side of the N-type source region is connected to the P-type well region; The lower side of the insulating dielectric layer is connected to the P-type well region and the protruding portion.

2. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The width of the gate protection zone is equal to the width of the protrusion, and the gate protection zone is located directly below the protrusion.

3. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the gate protection area is smaller than the thickness of the shunt area, and the lower side surface of the gate protection area and the lower side surface of the shunt area are located in the same plane.

4. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the gate protection area is lower than the doping concentration of the shunt area.

5. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The width of the shunt region is equal to the width of the source protection region, and the shunt region is located directly below the source protection region.

6. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the source protection region is greater than the doping concentration of the drift layer, and the doping concentration of the source protection region is greater than the doping concentration of the P-type well region.

7. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the P-type well region is lower than the doping concentration of the drift layer.

8. The method for preparing a high-reliability UIS planar gate silicon carbide VDMOS according to claim 1, wherein: The silicon carbide substrate, drift layer and shunt region are N-type; the gate protection zone and source protection zone are P-type.

9. A high-reliability UIS planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

Images