Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, relating to the field of semiconductor technology. The method comprises: providing a substrate, doping the substrate to form a channel doping region, forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region, removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall, and forming a semiconductor layer in the region where the substrate is removed. Because the semiconductor layer is undoped or the doping concentration of the semiconductor layer is lower than the doping concentration of the channel doping region, the gate induced drain leakage current of the semiconductor device, such as a MOS transistor, can be reduced, thereby improving the reliability of the semiconductor device, such as the MOS transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the size of Metal Oxide Semiconductor (MOS) transistors becomes smaller and smaller, the thickness of their gate oxide layer becomes thinner and thinner, resulting in an increasing gate-induced drain leakage (GIDL) current caused by band-to-band tunneling between the valence band and the conduction band of electrons in the substrate near the gate-drain overlap interface, leading to increasingly poor reliability. Summary of the Invention

[0003] The invention discloses a semiconductor device and a manufacturing method thereof, which are used to solve the problem of poor reliability of the semiconductor device caused by large gate-induced drain leakage current.

[0004] In a first aspect, the present invention discloses a method for manufacturing a semiconductor device, comprising: providing a substrate; doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region; removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall, as well as the substrate located at the bottom of the offset sidewall; forming a semiconductor layer in the area where the substrate is removed, wherein the material of the semiconductor layer is the same as that of the substrate, the semiconductor layer is undoped or the doping concentration of the semiconductor layer is less than the doping concentration of the channel doping region.

[0005] In some embodiments of the present invention, the substrate includes a first region, a second region, and a shallow trench isolation structure located between the first region and the second region, the first region is at least used to form a PMOS transistor, and the second region is at least used to form an NMOS transistor; doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region include: doping the substrates of the first region and the second region in sequence to form a channel doping region; synchronously forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping regions of the first region and the second region; removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall include: synchronously removing the substrate in the channel doping region of the first region and the second region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall; forming a semiconductor layer in the region where the substrate is removed includes: synchronously forming a semiconductor layer in the region where the substrate is removed in the first region and the second region, and the semiconductor layer is undoped.

[0006] In some embodiments of the present invention, removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall includes: removing a portion of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall; removing the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall.

[0007] In some embodiments of the present invention, removing the portion of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall includes: performing anisotropic etching on the portion of the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall; removing the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall includes: performing isotropic etching on the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall.

[0008] In some embodiments of the present invention, the thickness of the portion of the substrate is greater than or equal to the difference between the thickness of the channel doping region and the thickness of the offset sidewall; the thickness of the remaining substrate is equal to the thickness of the offset sidewall.

[0009] In some embodiments of the present invention, doping the substrate to form a channel doping region includes: forming a mask layer on the substrate to expose the entire active area; using the mask layer as a mask, doping the active area of the substrate to form a channel doping region; the channel doping region includes a first channel doping region and a second channel doping region, the first channel doping region and the second channel doping region are a double-layer structure, the doping concentration of the first channel doping region is greater than the doping concentration of the second channel doping region, and the doping ions of the first channel doping region include fluorine ions.

[0010] In some embodiments of the present invention, the method further includes: doping the semiconductor layer on both sides of the gate structure to form a lightly doped drain region, a pocket doped region, a source region, and a drain region.

[0011] In some embodiments of the present invention, the upper surface of the semiconductor layer is flush with the upper surface of the substrate; and the thickness of the semiconductor layer is greater than or equal to the thickness of the channel doping region.

[0012] In some embodiments of the present invention, the semiconductor layer includes a single crystal silicon layer.

[0013] In a second aspect, the present invention discloses a semiconductor device, which is manufactured using the semiconductor device manufacturing method as described in any one of the above items.

[0014] The semiconductor device and its manufacturing method disclosed in the present invention provide a substrate, dope the substrate to form a channel doping region, form a gate structure and an offset sidewall surrounding the gate structure on the channel doping region, remove the substrate in the channel doping region not covered by the gate structure and the offset sidewall and the substrate located at the bottom of the offset sidewall, and form a semiconductor layer in the region where the substrate is removed. The material of the semiconductor layer is the same as that of the substrate. Because the semiconductor layer is undoped or the doping concentration of the semiconductor layer is lower than the doping concentration of the channel doping region, the doping concentration of the substrate in the region where the semiconductor layer is located, i.e., the region near the gate-drain overlap interface, can be reduced, thereby reducing the impurity state energy level of electrons in the substrate in the band gap between the valence band and the conduction band, thereby reducing the probability of band-to-band tunneling, thereby reducing the gate-induced drain leakage current of semiconductor devices such as MOS transistors, and improving the reliability of semiconductor devices such as MOS transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0016] Figure 1 The present invention discloses a flow chart of a method for manufacturing a semiconductor device.

[0017] Figures 2 to 9 Schematic diagram of the cross-sectional structure of a semiconductor device in various manufacturing steps disclosed in an embodiment of the present invention.

[0018] Figures 10 to 17 Schematic diagram of the cross-sectional structure of another semiconductor device in various manufacturing steps disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] As described in the background, current MOS transistors suffer from high gate-induced drain leakage (GIDL), resulting in poor reliability. GIDL is caused by electrons in the substrate near the gate-drain overlap interface undergoing band-to-band tunneling between the valence band and the conduction band.

[0021] The inventors have discovered that in conventional MOS transistor manufacturing processes, channel doping ions are usually implanted into the entire active area of the MOS transistor to form a channel doping region. However, this increases the impurity state energy level of electrons in the substrate near the gate-drain overlap interface in the band gap between the valence band and the conduction band, thereby increasing the probability of band-to-band tunneling, resulting in a large gate-induced drain leakage current of the MOS transistor and poor reliability of the MOS transistor.

[0022] Based on this, the present invention discloses a manufacturing scheme for semiconductor devices such as MOS transistors. By removing the substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall, and forming an undoped or low-doping semiconductor layer in the region where the substrate is removed, the doping concentration of the substrate in the region where the semiconductor layer is located, i.e., the region near the gate-drain overlap interface, is reduced, thereby reducing the impurity state energy level of electrons in the substrate in the band gap between the valence band and the conduction band, reducing the probability of band-to-band tunneling, reducing gate-induced drain leakage current, and improving the reliability of the semiconductor device.

[0023] As an optional implementation of the present disclosure, an embodiment of the present invention discloses a method for manufacturing a semiconductor device, such as Figure 1 As shown, the production method includes:

[0024] S101: providing a substrate.

[0025] In some embodiments of the present invention, the semiconductor device includes an NMOS transistor and / or a PMOS transistor. In some embodiments of the present invention, the semiconductor device includes an NMOS transistor or a PMOS transistor as an example for description. Figure 2 As shown, a substrate 10 is first provided, which has a plurality of shallow trench isolation structures 101 spaced apart. The material of the substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire or silicon wafer, etc.; the shallow trench isolation structure 101 is a shallow trench structure filled with an insulating material such as silicon oxide.

[0026] Of course, the present invention is not limited to this, and in other embodiments, the substrate 10 may not have the shallow trench isolation structure 101. It should be noted that if the semiconductor device includes multiple transistors, the substrate 10 requires the shallow trench isolation structure 101 to achieve isolation between the transistors. However, if the semiconductor device includes only one transistor, the substrate 10 may not have the shallow trench isolation structure 101.

[0027] S102: doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region.

[0028] In some embodiments of the present invention, Figure 3 As shown, first, a mask layer 100 is formed on the substrate 10 using a preset pattern mask to expose the entire active area. The mask layer 100 includes a photoresist layer. Then, using the mask layer 100 as a mask, the substrate 10 in the entire active area is sequentially doped with wells and channels to form a structure as shown in FIG. Figure 4 The well region 102 and the channel doping region 103 are shown, wherein the well doping and the channel doping can share a mask or mask. Then, a gate structure layer is formed on the substrate 10, and the gate structure layer is anisotropically etched to form a gate structure layer as shown in FIG. Figure 5 The gate structure 20 shown in FIG. 2 may include a gate dielectric layer 201, a gate layer 202, and a cap layer 203. Then, an offset spacer layer is formed on the substrate 10, and the offset spacer layer is anisotropically etched to form a gate dielectric layer 201, a gate layer 202, and a cap layer 203. Figure 6 Offset side walls 30 are shown.

[0029] Of course, the present invention is not limited to this. In other embodiments, the substrate 10 of the entire active area may not be doped to form the channel doping region 103. That is, as long as the offset sidewall 30 covers the channel doping region 103, the subsequent steps of the embodiment of the present invention can be used to manufacture semiconductor devices.

[0030] Among them, the material of the gate dielectric layer 201 can be one or more of silicon oxide, silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, zirconium oxynitrosilicate, hafnium silicate, hafnium oxynitrosilicate, lanthanum hafnium oxynitride or hafnium aluminum oxide; the material of the gate layer 202 can be polycrystalline silicon, etc.; the material of the covering layer 203 can be silicon oxynitride or silicon carbide, etc.; the offset sidewall 30 can be a stacked structure composed of silicon oxide and silicon nitride.

[0031] S103: removing the substrate in the channel doping region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer.

[0032] In some embodiments of the present invention, Figure 7 As shown, the portion of the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset spacer 30 is first removed, and then, as shown in FIG. Figure 8 As shown, the remaining substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset spacer 30 and the substrate 10 at the bottom of the offset spacer 30 are removed.

[0033] On this basis, in some embodiments of the present invention, the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 can be anisotropically etched to remove the portion of the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30, and then the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 at the bottom of the offset sidewall 30 can be isotropically etched to remove the remaining substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 at the bottom of the offset sidewall 30.

[0034] Of course, the present invention is not limited to this. In other embodiments, the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 at the bottom of the offset sidewall 30 may be isotropically etched first, and then the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 may be anisotropically etched. Other methods may also be used to remove the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset sidewall 30 and the substrate 10 at the bottom of the offset sidewall 30, which will not be repeated here.

[0035] It should be noted that if Figure 8As shown, after removing the portion of the substrate 10 in the channel doping region 103 that is not covered by the gate structure 20 and the offset spacer 30, as well as the portion of the substrate 10 at the bottom of the offset spacer 30, a recess 104 is formed in the substrate 10. Furthermore, the inner sidewalls of the recess 104 are flush with the outer sidewalls of the gate structure 20, thereby minimizing the doping concentration in the region near the gate-drain overlap interface while ensuring the performance of the semiconductor device. The region of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer, as well as the region of the substrate at the bottom of the offset spacer, includes the region near the gate-drain overlap interface.

[0036] In some embodiments of the present invention, Figure 7 As shown, the thickness D1 of the removed portion of the substrate 10 is equal to the difference between the thickness D of the channel doping region 103 and the thickness D2 of the offset sidewall 30, as shown in FIG. Figure 7 and Figure 8 As shown, the thickness of the remaining substrate 10 after removal is equal to the thickness D2 of the offset spacer 30 . At this time, the depth of the groove 104 is equal to the thickness D of the channel doping region 103 .

[0037] Of course, the present invention is not limited to this. In other embodiments, the thickness D1 of the removed portion of the substrate 10 may also be greater than the difference between the thickness D of the channel doping region 103 and the thickness D2 of the offset sidewall 30 , and the depth of the groove 104 may also be greater than the thickness D of the channel doping region 103 .

[0038] S104: forming a semiconductor layer in the area where the substrate is removed, wherein the material of the semiconductor layer is the same as that of the substrate, and the semiconductor layer is undoped or the doping concentration of the semiconductor layer is lower than the doping concentration of the channel doping region.

[0039] In some embodiments of the present invention, Figure 9 As shown, the semiconductor layer 40 is formed in the area where the substrate 10 is removed, that is, in the groove 104. For example, the semiconductor layer 40 can be epitaxially grown in the area where the substrate 10 is removed, that is, in the groove 104, using a selective epitaxial growth process.

[0040] The material of the semiconductor layer 40 is the same as that of the substrate 10. For example, the material of the semiconductor layer 40 and the substrate 10 are both silicon or silicon germanium. In some embodiments of the present invention, the substrate 10 is a silicon substrate and the semiconductor layer 40 is a single crystal silicon layer. Because NMOS transistors and other devices require tensile stress rather than compressive stress in the channel, making the material of the semiconductor layer 40 the same as that of the substrate 10 can prevent the semiconductor layer 40 from applying stress to the channel and affecting the performance of the NMOS transistor and other devices.

[0041] Furthermore, the semiconductor layer 40 is undoped or the doping concentration of the semiconductor layer 40 is lower than the doping concentration of the channel doping region 103. For example, when the semiconductor device includes only a PMOS transistor, the doping concentration of the semiconductor layer 40 may be lower than the doping concentration of the channel doping region 103. However, when the semiconductor device includes an NMOS transistor or includes both an NMOS transistor and a PMOS transistor, the semiconductor layer 40 needs to be an undoped semiconductor layer to prevent the semiconductor layer 40 from applying stress to the channel doping region 103 and affecting the performance of the NMOS transistor.

[0042] Based on this, the doping concentration of the substrate 10 in the area where the semiconductor layer 40 is located, i.e., near the gate-drain overlap interface, can be reduced, thereby reducing the impurity state energy level of electrons in the substrate 10 in this area in the band gap between the valence band and the conduction band, thereby reducing the probability of band-to-band tunneling, thereby reducing the gate-induced drain leakage current of semiconductor devices such as MOS transistors, and improving the reliability of semiconductor devices such as MOS transistors.

[0043] In some embodiments of the present invention, the upper surface of the semiconductor layer 40 is flush with the upper surface of the substrate 10, and the thickness of the semiconductor layer 40 is equal to the thickness of the channel doping region 103. For example, when the depth of the groove 104 is equal to the thickness of the channel doping region 103, the thickness of the formed semiconductor layer 40 is equal to the thickness of the channel doping region 103. Of course, the present invention is not limited to this. In other embodiments, the thickness of the semiconductor layer 40 may also be greater than the thickness of the channel doping region 103. For example, when the depth of the groove 104 is greater than the thickness of the channel doping region 103, the thickness of the formed semiconductor layer 40 is greater than the thickness of the channel doping region 103.

[0044] In other embodiments of the present invention, a semiconductor device including an NMOS transistor and a PMOS transistor is used as an example for description. Figure 10 As shown, a substrate 10 is first provided, which includes a first region A1, a second region A2 and a shallow trench isolation structure 101 located between the first region A1 and the second region A2, wherein the first region A1 is at least used to form a PMOS transistor, and the second region A2 is at least used to form an NMOS transistor.

[0045] Then, if Figure 11 As shown, a mask layer 100 is formed on the substrate 10 using a preset pattern mask to expose the entire active area of the first area A1, and the mask layer 100 is used as a mask to sequentially perform well doping and channel doping on the entire active area of the first area A1 to form a well region 102 and a channel doping region 103 of the first area A1. Then, as shown in FIG. Figure 12As shown, a mask layer 100 is formed on the substrate 10 using a photomask having a preset pattern, exposing the entire active area of the second region A2. Using the mask layer 100 as a mask, well doping and channel doping are sequentially performed on the entire active area of the second region A2 to form a well region 102 and a channel doping region 103 of the second region A2. The first region A1 and the second region A2 can share a single photomask, eliminating the need to increase the number of photomasks.

[0046] Then, a gate structure layer is formed on the substrate 10 in the first area A1 and the second area A2 simultaneously, and the gate structure layer is anisotropically etched to simultaneously form the gate structure layer. Figure 13 Then, an offset spacer layer is formed on the substrate 10 in the first area A1 and the second area A2 simultaneously, and the offset spacer layer is anisotropically etched to simultaneously form the gate structure 20 of the first area A1 and the gate structure 20 of the second area A2. Figure 14 The offset sidewall 30 of the first area A1 and the offset sidewall 30 of the second area A2 are shown.

[0047] Then, if Figure 15 As shown, the substrate 10 in the channel doping region 103 of the first area A1 and the second area A2 that is not covered by the gate structure 20 and the offset spacer 30 is anisotropically etched, and the portion of the substrate 10 in the channel doping region 103 of the first area A1 and the second area A2 that is not covered by the gate structure 20 and the offset spacer 30 is simultaneously removed. Then, as shown in FIG. Figure 16 As shown, the substrate 10 in the channel doping region 103 of the first area A1 and the second area A2 that is not covered by the gate structure 20 and the offset spacer 30 and the substrate 10 at the bottom of the offset spacer 30 are isotropically etched, and the remaining substrate 10 in the channel doping region 103 of the first area A1 and the second area A2 that is not covered by the gate structure 20 and the offset spacer 30 and the substrate 10 at the bottom of the offset spacer 30 are simultaneously removed.

[0048] Then, if Figure 17 As shown, regions of the substrate 10 are removed simultaneously in the first region A1 and the second region A2 to form a semiconductor layer 40. The material of the semiconductor layer 40 is the same as that of the substrate 10. For example, the material of the semiconductor layer 40 and the substrate 10 are both silicon or silicon germanium. Furthermore, the semiconductor layer 40 is undoped to prevent the semiconductor layer 40 from applying stress to the channel doping region 103 and affecting the performance of the NMOS transistor.

[0049] Because the material of the semiconductor layer 40 is the same as that of the substrate 10 and the semiconductor layer 40 is undoped, the first region A1 and the second region A2 can be simultaneously subjected to epitaxial growth steps, which not only simplifies the process steps and reduces the production cost, but also does not apply stress to the channel doping region 103, thereby affecting the performance of the NMOS transistor.

[0050] It should be noted that when well doping is performed on the first region A1, i.e., the PMOS transistor, the doping ions may be phosphorus ions. When channel doping is performed on the first region A1, i.e., the PMOS transistor, fluorine ions are first implanted at a certain depth from the surface of the substrate 10 to form a first channel doping region. The role of the fluorine ion implantation is to inhibit the diffusion of the channel doping ions, which is conducive to the formation of an inverted doped well. Then, a higher concentration of phosphorus ions is implanted into the substrate 10 to form a second channel doping region, and the implantation depth is the same as the implantation depth of the fluorine ions, so that the first channel doping region and the second channel doping region form a double-layer structure. The threshold voltage of the NMOS transistor is adjusted by the phosphorus ion doping of this part, wherein the doping concentration of the first channel doping region is greater than the doping concentration of the second channel doping region. Then, a lower concentration of phosphorus ions is implanted into the substrate 10, and the implantation depth is between above the higher concentration phosphorus ion doping region and the surface of the substrate 10, so as to reduce the doping concentration of the channel surface, i.e., the surface of the substrate 10, thereby improving carrier mobility and improving the performance of the semiconductor device.

[0051] When well doping is performed on the second region A2, i.e., the NMOS transistor, the doping ions may be boron ions. When channel doping is performed on the second region A2, i.e., the NMOS transistor, fluorine ions are first implanted at a certain depth from the surface of the substrate 10 to form a first channel doping region. The role of the fluorine ion implantation is to inhibit the diffusion of the channel doping ions, which is conducive to the formation of an inverted doped well. Then, a higher concentration of boron ions is implanted into the substrate 10 to form a second channel doping region, and the implantation depth is the same as the implantation depth of the fluorine ions, so that the first channel doping region and the second channel doping region form a double-layer structure. The boron ion doping of this portion determines the adjustment of the threshold voltage of the NMOS transistor, wherein the doping concentration of the first channel doping region is greater than the doping concentration of the second channel doping region. Then, a lower concentration of boron ions is implanted into the substrate 10, and the implantation depth is between above the higher concentration boron ion doping region and the surface of the substrate 10, so as to reduce the doping concentration of the channel surface, i.e., the surface of the substrate 10, thereby improving carrier mobility and improving the performance of the semiconductor device.

[0052] It should also be noted that, in some embodiments of the present invention, the gate structure formed on the channel doping region is a gate structure, but the present invention is not limited to this. In other embodiments, the gate structure formed on the channel doping region may also be a dummy gate structure. Based on this, after forming the semiconductor layer, the steps of doping the semiconductor layer on both sides of the dummy gate structure to form a lightly doped drain region (LDD) and a pocket implantation (PKT) doping region, depositing a main sidewall film and anisotropically etching the main sidewall film to form a main sidewall structure, removing the covering layer by a wet etching process, doping the source and drain regions of the semiconductor layer on both sides of the dummy gate structure to form a source region and a drain region, replacing the dummy gate layer with a metal gate layer, and forming a source and a drain.

[0053] As another optional implementation of the present disclosure, an embodiment of the present disclosure further discloses a semiconductor device, which is manufactured using the manufacturing method disclosed in any of the above embodiments. The semiconductor device includes but is not limited to an NMOS transistor and / or a PMOS transistor.

[0054] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; Doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region; Removing the substrate in the channel doping region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer to form a groove; the inner sidewall of the groove is flush with the outer sidewall of the gate structure; A semiconductor layer is formed in the groove, wherein the material of the semiconductor layer is the same as that of the substrate, the semiconductor layer is undoped or the doping concentration of the semiconductor layer is less than the doping concentration of the channel doping region, so as to reduce the doping concentration of the substrate in the area near the gate-drain overlap interface.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate includes a first region, a second region, and a shallow trench isolation structure located between the first region and the second region, the first region is at least used to form a PMOS transistor, and the second region is at least used to form an NMOS transistor; The step of doping the substrate to form a channel doping region, and forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping region comprises: doping the substrates of the first region and the second region in sequence to form a channel doping region; and simultaneously forming a gate structure and an offset sidewall surrounding the gate structure on the channel doping regions of the first region and the second region; The removing of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer to form the groove comprises: simultaneously removing the substrate in the channel doping region of the first region and the second region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer to form the groove; The forming of the semiconductor layer in the groove includes: forming the semiconductor layer in the grooves of the first region and the second region simultaneously, wherein the semiconductor layer is undoped.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The removing of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer to form a groove comprises: removing a portion of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer; The remaining substrate in the channel doping region that is not covered by the gate structure and the offset spacer and the substrate at the bottom of the offset spacer are removed to form a groove.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The removing of the portion of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer comprises: performing anisotropic etching on the portion of the substrate in the channel doping region that is not covered by the gate structure and the offset spacer; The step of removing the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall to form a groove includes: isotropically etching the remaining substrate in the channel doping region that is not covered by the gate structure and the offset sidewall and the substrate at the bottom of the offset sidewall to form a groove.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The thickness of the portion of the substrate is greater than or equal to the difference between the thickness of the channel doping region and the thickness of the offset sidewall; the thickness of the remaining substrate is equal to the thickness of the offset sidewall.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of doping the substrate to form a channel doping region includes: forming a mask layer on the substrate to expose the entire active area; Using the mask layer as a mask, doping the substrate of the active area to form a channel doping area; The channel doping region includes a first channel doping region and a second channel doping region, the first channel doping region and the second channel doping region are a double-layer structure, the doping concentration of the first channel doping region is greater than the doping concentration of the second channel doping region, and the doping ions of the first channel doping region include fluorine ions.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: Also includes: The semiconductor layers on both sides of the gate structure are doped to form a lightly doped drain region, a pocket doped region, a source region and a drain region.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The upper surface of the semiconductor layer is flush with the upper surface of the substrate; and the thickness of the semiconductor layer is greater than or equal to the thickness of the channel doping region.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor layer includes a single crystal silicon layer.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 9.

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