Semiconductor device, preparation method, packaging structure and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method, a packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for eliminating an electric leakage phenomenon of the semiconductor device. The semiconductor device includes: an epitaxial layer; a source electrode structure, a drain electrode structure and a grid electrode structure located between the source electrode structure and the drain electrode structure are arranged on the epitaxial layer; a first dielectric layer and a second dielectric layer are laminated on the epitaxial layer; the source electrode structure and the drain electrode structure penetrate through the first dielectric layer; the first region of the second dielectric layer penetrates through the first dielectric layer and is in contact with the epitaxial layer; the gate structure penetrates through the first region of the second dielectric layer and is in contact with the epitaxial layer; the dielectric constant of the material of the first dielectric layer is higher than that of the material of the second dielectric layer.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technologies, and in particular, to a semiconductor device, a preparation method thereof, a packaging structure, and an electronic device. Background Art

[0002] With the continuous development of technologies, higher requirements are put forward for the energy consumption, power, efficiency, and miniaturization of semiconductor devices. The high electron mobility transistor (HEMT) prepared by gallium nitride materials has advantages such as a high critical breakdown electric field, a high electron saturation velocity, a high thermal conductivity, and a strong anti-irradiation ability. However, due to the gate electrode electric field concentration effect, there is an easy leakage phenomenon in semiconductor devices. Summary of the Invention

[0003] Embodiments of the present application provide a semiconductor device, a preparation method thereof, a packaging structure, and an electronic device, which are used to eliminate the leakage phenomenon of semiconductor devices.

[0004] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided. The semiconductor device includes: an epitaxial layer; a source electrode structure, a drain electrode structure, and a gate electrode structure located between the source electrode structure and the drain electrode structure are disposed on the epitaxial layer; a first dielectric layer and a second dielectric layer are further stacked on the epitaxial layer; the source electrode structure and the drain electrode structure penetrate the first dielectric layer; a first region of the second dielectric layer penetrates the first dielectric layer and contacts the epitaxial layer; the gate electrode structure penetrates the first region of the second dielectric layer and contacts the epitaxial layer; the dielectric constant of the material of the first dielectric layer is higher than the dielectric constant of the material of the second dielectric layer.

[0006] The semiconductor device provided by the embodiment of the present application includes a source electrode structure, a drain electrode structure disposed on the epitaxial layer, and a gate electrode structure located between the source electrode structure and the drain electrode structure. Among them, the source electrode structure and the drain electrode structure penetrate the first dielectric layer, a first region of the second dielectric layer penetrates the first dielectric layer and contacts the epitaxial layer, and the gate electrode structure penetrates the first region of the second dielectric layer, that is, the second dielectric layer is disposed around the gate electrode structure, and the first dielectric layer is disposed in the region outside the periphery of the gate electrode structure. Since the dielectric constant of the material of the first dielectric layer is higher than the dielectric constant of the material of the second dielectric layer, the second dielectric layer can improve the leakage problem of the gate electrode structure. At the same time, since the material of the first dielectric layer has a high dielectric constant, a greater electrode polarization effect can be generated under the same electric field strength, so as to form a greater electric field gradient in the first dielectric layer, making the electric field distribution in the first dielectric layer more uniform, thereby improving the breakdown characteristics and power density of the semiconductor device and enabling it to have better radio frequency characteristics.

[0007] In a possible implementation, the semiconductor device further includes: a third dielectric layer that covers the second dielectric layer and the gate structure. Thus, the third dielectric layer can insulate the gate structure from the field plate structure, preventing breakdown between the gate structure and the field plate structure.

[0008] In a possible implementation, the semiconductor device further includes a field plate structure disposed on the third dielectric layer. A second dielectric layer and a third dielectric layer are included between a first part of the field plate structure and the epitaxial layer; a first dielectric layer, a second dielectric layer, and a third dielectric layer are included between a second part of the field plate structure and the epitaxial layer; a third dielectric layer and a gate structure are included between a third part of the field plate structure and the epitaxial layer.

[0009] In this implementation, the first part, the second part, and the third part of the field plate structure enclose a sunken area, so that the electric field can be distributed over a larger area, reducing the concentration effect of the electric field. This helps to reduce the electric field strength, lower the risk of leakage current and breakdown, and improve the breakdown voltage withstand capacity of the semiconductor device. Moreover, there is no need to etch each dielectric layer, reducing the loss to the gate structure, improving the reliability of the device, and simplifying the manufacturing process at the same time.

[0010] In a possible implementation, the semiconductor device further includes a fourth dielectric layer disposed between the first dielectric layer and the second dielectric layer. The fourth dielectric layer covers the source structure and the drain structure, and a first region of the second dielectric layer penetrates through the fourth dielectric layer.

[0011] In a possible implementation, the gate structure includes a first part and a second part located on the first part. The first part of the gate structure is embedded in the second dielectric layer, and the cross-sectional area of the second part of the gate structure in the stacking direction is larger than the cross-sectional area of the first part in the stacking direction. Thus, the gate structure can have a larger width, so that the semiconductor device has a lower resistance. The lower resistance can reduce power consumption and voltage drop, and improve the working efficiency of the semiconductor device.

[0012] In a possible implementation, the material of the first dielectric layer includes at least one or a combination of more than one of the following: aluminum nitride, silicon oxide, and silicon nitride.

[0013] In a second aspect, a method for manufacturing a semiconductor device is provided. The manufacturing method includes: forming a first dielectric layer on an epitaxial layer, and a source structure and a drain structure that penetrate the first dielectric layer; forming a first groove that penetrates the first dielectric layer; forming a second dielectric layer that covers the first dielectric layer and the first groove. A first region of the second dielectric layer fills the first groove and contacts the epitaxial layer, and the dielectric constant of the material of the first dielectric layer is higher than that of the material of the second dielectric layer; forming a gate structure that penetrates the first region of the second dielectric layer and contacts the epitaxial layer.

[0014] In a possible implementation manner, the preparation method further includes: forming a third dielectric layer covering the second dielectric layer and the gate structure.

[0015] In a possible implementation manner, the preparation method further includes: forming a field plate structure on the third dielectric layer, and a projection of the field plate structure on the epitaxial layer covers a part of a projection of the gate structure on the epitaxial layer.

[0016] In a possible implementation manner, before forming the first groove penetrating the first dielectric layer, the preparation method further includes: forming a fourth dielectric layer covering the source structure, the drain structure, and the first dielectric layer; forming a second groove penetrating the fourth dielectric layer, and the second groove is opposite to the first groove.

[0017] In a third aspect, a chip packaging structure is provided, including a packaging substrate and the semiconductor device provided in the first aspect; the semiconductor device is electrically connected to the packaging substrate.

[0018] In a fourth aspect, an electronic device is provided, including a printed circuit board and the chip packaging structure provided in the second aspect; the chip packaging structure is electrically connected to the printed circuit board.

[0019] Wherein, for the technical effects brought by any possible implementation manner in the second aspect, the third aspect, and the fourth aspect, reference may be made to the technical effects brought by different implementation manners in the above-mentioned first aspect, and details are not described herein again. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

[0022] Figure 3 It is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

[0023] Figure 4 It is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

[0024] Figure 5 It is a schematic flow chart of a preparation method of a semiconductor device provided by an embodiment of the present application;

[0025] Figures 6 - 14 It is a schematic structural diagram of a semiconductor device at each stage during the preparation process provided by another embodiment of the present application;

[0026] Figure 15 It is a schematic diagram of an output characteristic curve of a semiconductor device provided by an embodiment of the present application;

[0027] Figure 16 It is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application;

[0028] Figure 17 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Specific Embodiments

[0029] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B can mean A or B; herein, "and / or" is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.

[0030] Hereinafter, the terms "first" and "second" are only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0031] In the description of the embodiments of the present application, unless otherwise specified, "a plurality" means two or more. In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0032] To solve the gate electric field concentration effect, an embodiment of the present application provides a semiconductor device, such as Figure 1As shown, the semiconductor device includes: an epitaxial layer 110, on which a source structure 112, a drain structure 113, and a gate structure 114 located between the source structure 112 and the drain structure 113 are provided. In a specific example, the epitaxial layer 110 includes a nucleation layer, a buffer layer, a barrier layer, and a channel layer. A first dielectric layer 115 is also provided on the epitaxial layer 110. The source structure 112 and the drain structure 113 penetrate through the first dielectric layer 115. A fourth dielectric layer 150 covers the source structure 112, the drain structure 113, and the first dielectric layer 115. The gate structure 114 penetrates through the first dielectric layer 115 and the fourth dielectric layer 150 and contacts the epitaxial layer 110. A third dielectric layer 130 covers the gate structure 114 and the fourth dielectric layer 150. A field plate structure 140 is provided on the third dielectric layer 130. A first part of the field plate structure 140 and the epitaxial layer 110 includes the first dielectric layer 115, the fourth dielectric layer 150, and the third dielectric layer 130; a second part of the field plate structure 140 and the epitaxial layer 110 includes the third dielectric layer 130 and the gate structure 114.

[0033] When a voltage is applied to the gate structure 114, the formed electric field will change the carrier concentration in the semiconductor device, thereby affecting the current flow between the gate structure 114 and the source structure 112. For example, it will increase the leakage current in the semiconductor device, thereby reducing the reliability of the transistor. However, the semiconductor device provided by the embodiment of the present application sets a field plate structure 140 on the side of the gate structure 114 away from the epitaxial layer 110, and makes the projection on the substrate 101 cover a part of the projection of the gate structure 114 on the substrate 101. The current flow between the gate structure 114 and the source structure 112 can be adjusted by adjusting the electric field applied to the field plate structure 140, weakening the influence brought by the gate electric field concentration effect, thereby increasing the breakdown voltage of the semiconductor device, weakening the strong electric field electron effect and thus suppressing current collapse, and increasing the output power density.

[0034] However, different field plate structures 140 have very different effects on the electrical characteristics of the semiconductor device; reducing the distance between the field plate structure 140 and the channel layer can improve the radio frequency electrical characteristics of the semiconductor device, but will increase the field strength at the edge of the field plate structure 140. By locally sinking the field plate, the field strength at the edge of the field plate can be effectively weakened, the breakdown voltage can be increased, and the reliability of the device can be improved.

[0035] In order to reduce the field strength at the edge of the field plate structure 140, the embodiment of the present application also provides a semiconductor device, such as Figure 2As shown, the semiconductor device includes: a substrate 101, an epitaxial layer 110 covering the substrate 101, a source structure 112, a drain structure 113 provided on the epitaxial layer 110, and a gate structure 114 located between the source structure 112 and the drain structure 113. A fourth dielectric layer 150 is also provided on the epitaxial layer 110. The fourth dielectric layer 150 covers the source structure 112 and the drain structure 113. The gate structure 114 penetrates through the fourth dielectric layer 150 and contacts the epitaxial layer 110. A third dielectric layer 130 covers the gate structure 114 and the fourth dielectric layer 150. A field plate structure 140 is provided on the third dielectric layer 130. The field plate structure 140 includes a connected first part 141, a second part 142, and a third part 143. The first part 141 of the field plate structure 140 penetrates through the third dielectric layer 130 and contacts the fourth dielectric layer 150. Between the second part 142 of the field plate structure 140 and the epitaxial layer 110, there are the fourth dielectric layer 150 and the third dielectric layer 130; between the third part 143 of the field plate structure 140 and the epitaxial layer 110, there are the third dielectric layer 130 and the gate structure 114.

[0036] In some alternative examples, the semiconductor device further includes a fifth dielectric layer 160. The fifth dielectric layer 160 covers the third dielectric layer 130 and the field plate structure 140. A source-drain cavity 165 penetrating through the fifth dielectric layer 160 and the third dielectric layer 130 is provided between the field plate structure 140 and the drain structure 113. The source-drain cavity 165 is formed by removing the fifth dielectric layer 160 and the third dielectric layer 130 between the field plate structure 140 and the drain structure 113, while retaining the first dielectric layer 115. While ensuring the surface passivation of the semiconductor device, the dielectric constant between the field plate structure 140 and the drain structure is reduced, and the source-drain capacitance Cds is further reduced.

[0037] The field plate structure 140 in the semiconductor device provided by the embodiment of the present application includes a connected first part 141, a second part 142, and a third part 143. Among them, the distance between the first part 141 of the field plate structure 140 and the epitaxial layer 110 is the thickness of the fourth dielectric layer 150, the distance between the second part 142 of the field plate structure 140 and the epitaxial layer 110 is the sum of the thicknesses of the fourth dielectric layer 150 and the third dielectric layer 130, and the distance between the third part 143 of the field plate structure 140 and the epitaxial layer 110 is the sum of the thicknesses of the third dielectric layer 130 and the gate structure 114, thereby forming a stepped field plate structure 140. Among them, the first part 141 of the field plate structure 140 is close to the channel, which can effectively modulate the electric field and suppress the gate-drain capacitance; the distance between the second part 142 and the channel is lengthened, which can reduce the source-drain capacitance between the field plate structure 140 and the drain, and at the same time adjust the electric field distribution in the channel and reduce the peak intensity of the electric field. However, in the semiconductor device provided by the embodiment of the present application, only a source-drain cavity can be formed between the field plate structure 140 and the drain structure 113, and the adjustable region is relatively narrow, and the adjustment effect on the semiconductor device is not obvious. At the same time, when forming the field plate structure 140, it is necessary to etch the third dielectric layer 130 to form a groove in the third dielectric layer 130. The process is complex, and there is a problem of alignment deviation between the groove and the gate structure 114 during the formation of the groove, which will have a greater impact on the performance and reliability of the semiconductor device.

[0038] The embodiment of the present application also provides a semiconductor device. Refer to Figure 3 in (1). The semiconductor device includes: a substrate 101, an epitaxial layer 110 covering the substrate 101, a source electrode structure 112, a drain electrode structure 113, and a gate structure 114 located between the source electrode structure 112 and the drain electrode structure 113 are arranged on the epitaxial layer 110. A first dielectric layer 115 is also arranged on the epitaxial layer 110. The source electrode structure 112 and the drain electrode structure 113 penetrate through the first dielectric layer 115. The fourth dielectric layer 150 covers the source electrode structure 112 and the drain electrode structure 113. The gate structure 114 penetrates through the fourth dielectric layer 150 and the first dielectric layer 115 and contacts the epitaxial layer 110. The third dielectric layer 130 covers the gate structure 114 and the fourth dielectric layer 150. Among them, the first part of the third dielectric layer 130 penetrates through the fourth dielectric layer 150 and the first dielectric layer 115 and contacts the epitaxial layer 110. The field plate structure 140 is arranged on the third dielectric layer 130. The field plate structure 140 includes a connected first part 141, a second part 142, and a third part 143. The first part 141 of the field plate structure 140 covers the first part of the third dielectric layer 130. The second part 142 of the field plate structure 140 includes the fourth dielectric layer 150 and the third dielectric layer 130 between it and the epitaxial layer 110; the third part 143 of the field plate structure 140 includes the third dielectric layer 130 and the gate structure 114 between it and the epitaxial layer 110.

[0039] When forming the gate structure 114 and the field plate structure 140 in the semiconductor device provided by the embodiment of the present application, referring to Figure 3 in (2) below, it is necessary to use the same photomask plate to synchronously form the third groove 153 and the fourth groove 154 penetrating the first dielectric layer 115 and the fourth dielectric layer 150, and then form the gate structure 114 in the third groove 153, and form the first part of the third dielectric layer 130 and the first part 141 of the field plate structure 140 in the fourth groove 154, so as to save steps, simplify the process, further reduce the process complexity, improve the device manufacturing efficiency, and the distance between the third groove 153 and the fourth groove 154 only depends on the designed distance of the photomask plate and has nothing to do with the alignment offset of the lithography process, and can also improve the alignment accuracy of the gate structure 114 and the field plate structure 140, and improve the device stability. However, the depth of the field plate structure 140 in the semiconductor device provided by the embodiment of the present application is only determined by the thicknesses of the first dielectric layer 115 and the fourth dielectric layer 150, and the adjustment ability of the semiconductor device is limited.

[0040] The embodiment of the present application also provides a semiconductor device. Referring to Figure 4 , the semiconductor device includes: an epitaxial layer 110; a source structure 112, a drain structure 113 are disposed on the epitaxial layer 110, and a gate structure 114 is located between the source structure 112 and the drain structure 113; a first dielectric layer 115 and a second dielectric layer 120 are further stacked on the epitaxial layer 110; the source structure 112 and the drain structure 113 penetrate the first dielectric layer 115; a first region of the second dielectric layer 120 penetrates the first dielectric layer 115 and contacts the epitaxial layer 110; the gate structure 114 penetrates the first region of the second dielectric layer 120 and contacts the epitaxial layer 110; the dielectric constant of the material of the first dielectric layer 115 is higher than the dielectric constant of the material of the second dielectric layer 120.

[0041] In a specific embodiment, as Figure 5 shown, the process of manufacturing the above semiconductor device is as follows: S11: Form the first dielectric layer 115 on the epitaxial layer 110, and the source structure 112 and the drain structure 113 penetrating the first dielectric layer 115. S21: Form the first groove penetrating the first dielectric layer 115. S31: Form the second dielectric layer 120 covering the first dielectric layer 115 and the first groove. The first region of the second dielectric layer 120 fills the first groove and contacts the epitaxial layer 110, and the dielectric constant of the material of the first dielectric layer 115 is higher than the dielectric constant of the material of the second dielectric layer 120. S41: Form the gate structure 114, and the gate structure 114 penetrates the first region of the second dielectric layer 120 and contacts the epitaxial layer 110.

[0042] The semiconductor device provided by the embodiment of the present application includes a source structure 112, a drain structure 113 disposed on an epitaxial layer 110, and a gate structure 114 located between the source structure 112 and the drain structure 113. The source structure 112 and the drain structure 113 penetrate through a first dielectric layer 115. A first region of a second dielectric layer 120 penetrates through the first dielectric layer 115 and contacts the epitaxial layer 110. The gate structure 114 penetrates through the first region of the second dielectric layer 120, that is, the second dielectric layer 120 is disposed around the gate structure 114, and the first dielectric layer 115 is disposed in the region outside the periphery of the gate structure 114. Since the dielectric constant of the material of the first dielectric layer 115 is higher than that of the material of the second dielectric layer 120, the second dielectric layer 120 can improve the leakage problem of the gate structure 114. At the same time, since the material of the first dielectric layer 115 has a high dielectric constant, a greater electrode polarization effect can be generated under the same electric field strength, so as to form a greater electric field gradient in the first dielectric layer 115, making the electric field distribution in the first dielectric layer 115 more uniform, thereby improving the breakdown characteristics and power density of the semiconductor device and endowing it with better radio frequency characteristics.

[0043] In an optional embodiment below, the manufacturing process of the above semiconductor device and the device structure formed during the manufacturing process will be specifically described.

[0044] S10: Form the epitaxial layer 110.

[0045] See Figure 6 , exemplarily, the above epitaxial layer 110 includes a nucleation layer, a buffer layer, a barrier layer, and a channel layer. Specifically, the channel layer and the barrier layer can also be gallium nitride material, indium gallium nitride material, etc. The specific materials of the channel layer and the barrier layer are not limited here, as long as a heterojunction structure can be formed. The barrier layer can be aluminum gallium nitride (AlGaN), aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride, etc. Those skilled in the art can determine the specific materials and thicknesses of forming the nucleation layer, the buffer layer, the barrier layer, and the channel layer by themselves, and the embodiments of the present application do not make limitations.

[0046] It can be understood that before forming the epitaxial layer 110, a substrate can be formed first. The substrate can be a silicon wafer, silicon carbide, or sapphire, etc. The epitaxial layer 110 is formed on the substrate by an epitaxial process, and then the surface of the epitaxial layer 110 is cleaned to remove residual substances. In some optional examples, after forming the epitaxial layer 110, the substrate can be removed, so that the final semiconductor device does not include the substrate.

[0047] S11: Form a first dielectric layer 115 on the epitaxial layer 110, and a source structure 112 and a drain structure 113 that penetrate through the first dielectric layer 115.

[0048] In a specific example, the above S11: forming a first dielectric layer 115 on the epitaxial layer 110, and the source structure 112 and the drain structure 113 penetrating the first dielectric layer 115 include the following steps:

[0049] S12: Forming a first dielectric layer 115 on the epitaxial layer 110 through a deposition process.

[0050] As Figure 7 shown, a first dielectric layer 115 is formed on the epitaxial layer 110 through a deposition process, wherein the deposition process such as atomic layer deposition (ALD), physical vapor deposition (PVD), or plasma enhanced chemical vapor deposition (PECVD). Optionally, the first dielectric layer 115 is a multi-layer structure made of a variety of dielectric materials. For example, the material of the first dielectric layer 115 can be SiN, SiO, SiON, AlO, AlN or AlON. For example, the first dielectric layer 115 is a double-layer structure. The material of the first layer of the first dielectric layer 115 close to the epitaxial layer 110 can be aluminum nitride, and the material of the other layer of the first dielectric layer 115 is silicon oxide. Thus, the first dielectric layer can generate a greater electrode polarization effect under the same electric field strength, thereby forming a greater electric field gradient in the first dielectric layer 115, making the electric field distribution in the first dielectric layer 115 more uniform, while the second layer of the first dielectric layer 115 can protect the first dielectric layer from damage in subsequent processes.

[0051] S13: Forming a source structure 112 and a drain structure 113 on the epitaxial layer 110.

[0052] As Figure 8As shown, both the source structure 112 and the drain structure 113 may adopt a stacked structure, which may be composed of a titanium layer, an aluminum layer, a nickel layer, and a gold layer stacked in sequence, for example. Exemplarily, a fifth groove and a sixth groove may be formed in the first dielectric layer 115, and then ion doping materials may be injected into the epitaxial layer 110 through the fifth groove and the sixth groove to form a first part of the source structure 112 and a first part of the drain structure 113 in the epitaxial layer 110. Then, for example, a vapor deposition process may be used to form a second part of the source structure 112 on the first part of the source structure 112, and a second part of the drain structure 113 on the first part of the drain structure 113. For example, when the semiconductor device is a P-type semiconductor device, the ion doping material may be a P-type ion doping material, which may be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. In some aspects of the present invention, boron (B) ions may be used as the impurity ion doping material to be injected into the epitaxial layer 110, so as to form a first part of the source structure 112 and a first part of the drain structure 113 in the epitaxial layer 110. When the semiconductor device is an N-type semiconductor device, the ion doping material may be an N-type ion doping material, which may be at least one of phosphorus (P), PHx+ and / or P2Hx+ (where x = 1, 2, 3...), or a combination thereof. In some aspects of the present invention, phosphorus (P) ions may be used as the impurity ion doping material to be injected into the epitaxial layer 110, so as to form a first part of the source structure 112 and a first part of the drain structure 113 in the epitaxial layer 110.

[0053] It can be understood that in other alternative examples, when fabricating the semiconductor device, the source structure 112 and the drain structure 113 may be formed first, and then the first dielectric layer 115 may be formed, so that the source structure 112 and the drain structure 113 can be electrically isolated through the first dielectric layer 115.

[0054] S14: Form a fourth dielectric layer 150 covering the source structure 112, the drain structure 113, and the first dielectric layer 115.

[0055] As Figure 9As shown, optionally, in this embodiment, the material of the fourth dielectric layer 150 is SiN, SiO, SiON, AlO, AlN or AlON. In this embodiment, the sum of the thicknesses of the first dielectric layer 115 and the fourth dielectric layer 150 is controlled to be 150 nm or less. Since the thinner the thickness of these two dielectric layers, the stronger the gate control ability, but the corresponding gate parasitic capacitance is relatively large and the RF performance degrades; while the thicker the thickness of these two dielectric layers, the smaller the gate parasitic capacitance, but the gate control ability weakens and the peak electric field of the device increases, affecting the device reliability. Therefore, to make the device performance better, the total thickness of the first dielectric layer 115 and the fourth dielectric layer 150 is controlled to be about 150 nm.

[0056] S15: Form a second groove penetrating the fourth dielectric layer 150.

[0057] In this embodiment, as Figure 10 shown, the second groove 151 can be formed in the fourth dielectric layer 150 through a patterning process, and the patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (such as spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing and drying (such as hard baking). The etching process includes a dry etching process or a wet etching process.

[0058] S21: Form a first groove 116 penetrating the first dielectric layer 115.

[0059] In the embodiment of the present application, as Figure 10 shown, the first groove 116 can be formed in the first dielectric layer 115 through a dry etching process or a wet etching process, and the first groove 116 is opposite to the second groove 151. In some embodiments, the dry etching process includes using etching gases such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2) or a combination thereof.

[0060] It can be understood that the first groove 116 and the second groove 151 in the embodiment of the present application can be formed in the same step or in different steps. When formed in different steps, the second groove 151 should be formed in the fourth dielectric layer 150 first, and then the fourth dielectric layer 150 is used as a mask to etch the first dielectric layer 115. At the same time, when forming the first groove 116 and the second groove 151, the sidewall slopes of the first groove 116 and the second groove 151 can be adjusted so that the second dielectric layer 120 can better fill the first groove 116 and the second groove 151.

[0061] S31: Form a second dielectric layer 120 covering the fourth dielectric layer 150, the first groove 116, and the second groove 151. The first region of the second dielectric layer 120 fills the first groove 116 and the second groove 151 and contacts the epitaxial layer 110. The dielectric constant of the material of the first dielectric layer 115 is higher than that of the material of the second dielectric layer 120.

[0062] In an embodiment of the present application, as Figure 11 shown, the second dielectric layer 120 can be deposited by a chemical vapor deposition (CVD) process, a spin-on glass process, or other applicable processes. The first region of the formed second dielectric layer 120 fills the first groove 116 and contacts the epitaxial layer 110, and the region of the second dielectric layer 120 other than the first region covers the fourth dielectric layer 150.

[0063] S41: Form a gate structure 114 that penetrates the first region of the second dielectric layer 120 and contacts the epitaxial layer 110.

[0064] In a specific example, the above S41: forming the gate structure 114, where the gate structure 114 penetrates the first region of the second dielectric layer 120 and contacts the epitaxial layer 110, includes the following steps:

[0065] S42: Coat a first photoresist layer on the second dielectric layer 120 and pattern the first photoresist layer to form a first via hole that penetrates the first photoresist layer. Using the patterned first photoresist as a mask, form a seventh groove 121 in the first region of the second dielectric layer 120.

[0066] It can be understood that after the seventh groove 121 is formed, the first photoresist layer can be dissolved using a stripping solution to remove the first photoresist layer, or the first photoresist layer can be peeled off using a stripping device.

[0067] S43: Coat a second photoresist layer 135 on the second dielectric layer 120 and pattern the second photoresist layer 135 to form a second via hole 136.

[0068] Exemplarily, as shown in (1) of Figure 12 , the above second via hole 136 penetrates the second photoresist layer 135, and the orthographic projection of the second via hole 136 on the epitaxial layer 110 covers the seventh groove 121 and does not coincide with the seventh groove 121, that is, the aperture of the second via hole 136 is larger than the aperture of the seventh groove 121. In this way, the subsequently formed gate structure 114 is a T-shaped structure.

[0069] Specifically, those skilled in the art can determine the apertures of the above seventh groove 121 and the second via hole 136 according to the size of the gate structure 114 to be formed, and the embodiments of the present application do not make specific limitations.

[0070] S44: Evaporate metal within the second photoresist layer 135, the seventh groove 121, and the second via 136, and strip the second photoresist layer 135 to obtain the gate structure 114 within the seventh groove 121 and the second via 136.

[0071] Evaporate metal over the entire surface of the second photoresist layer 135. At this time, the metal can be deposited within the second via 136 and the seventh groove 121, thereby forming the first part 114-1 of the gate structure 114 within the seventh groove 121 and the second part 114-2 of the gate structure 114 within the second via 136. The first part 114-1 and the second part 114-2 of the gate structure 114 are connected, and the cross-sectional area of the second part 114-2 of the gate structure 114 in the stacking direction is larger than the cross-sectional area of the first part 114-1 of the gate structure 114 in the stacking direction. After evaporating the metal, the second photoresist layer 135 is removed through a stripping process. The semiconductor device formed in this way is as Figure 12 shown in (2) of [reference]. Among them, the gate structure 114 is a T-shaped structure. The T-shaped gate structure 114 has a larger width, so that the semiconductor device has a lower resistance. The lower resistance can reduce power consumption and voltage drop and improve the working efficiency of the semiconductor device.

[0072] S51: Form a third dielectric layer 130 covering the second dielectric layer 120 and the gate structure 114.

[0073] Exemplarily, the third dielectric layer 130 can adopt a single-layer structure or a stacked structure, and the material can be various dielectric materials, such as: silicon nitride, silicon oxide, and aluminum oxide, etc.

[0074] In the embodiment of the present application, as Figure 13 shown, the third dielectric layer 130 covers the second dielectric layer 120 and the exposed gate structure 114. The distances from different regions of the third dielectric layer 130 to the epitaxial layer 110 are different. For example, the second dielectric layer 120 is included between the first part of the third dielectric layer 130 and the epitaxial layer 110; the first dielectric layer 115, the second dielectric layer 120, and the fourth dielectric layer 150 are included between the second part of the third dielectric layer 130 and the epitaxial layer 110; the gate structure 114 is included between the third part of the third dielectric layer 130 and the epitaxial layer 110. Since the total thickness of the first dielectric layer 115, the second dielectric layer 120, and the fourth dielectric layer 150, the thickness of the gate structure 114, and the thickness of the second dielectric layer 120 are different from each other, the groove structure formed by enclosing the first part, the second part, and the third part of the third dielectric layer 130 can be obtained. In this way, the subsequent formed field plate structure 140 can have a sinking area.

[0075] When the thickness of the third dielectric layer 130 is too small, it may cause breakdown of the gate structure 114 and the field plate structure 140, or a large leakage current. On the other hand, it may cause a large capacitance Cgs between the gate structure 114 and the source structure 112, resulting in deterioration of the radio frequency performance of the semiconductor device. When the thickness of the third dielectric layer 130 is too large, it may significantly weaken the improvement of the device performance by the sinking region of the field plate structure 140. Exemplarily, the thickness of the third dielectric layer 130 in the embodiments of the present application is 30 nm - 300 nm.

[0076] It should be understood that the thickness relationship among the first dielectric layer 115, the second dielectric layer 120, the third dielectric layer 130, and the gate structure 114 should all satisfy the condition that a groove structure can be formed in the third dielectric layer 130.

[0077] S61: Form a field plate structure 140 on the third dielectric layer 130, and the projection of the field plate structure 140 on the epitaxial layer 110 covers a part of the projection of the gate structure 114 on the epitaxial layer 110.

[0078] In the embodiments of the present application, as Figure 14 shown, the field plate structure 140 includes a connected first part 141, a second part 142, and a third part 143. Among them, between the first part 141 of the field plate structure 140 and the epitaxial layer 110, there are the second dielectric layer 120 and the third dielectric layer 130; between the second part 142 of the field plate structure 140 and the epitaxial layer 110, there are the first dielectric layer 115, the second dielectric layer 120, the third dielectric layer 130, and the fourth dielectric layer 150; between the third part 143 of the field plate structure 140 and the epitaxial layer 110, there are the third dielectric layer 130 and the gate structure 114. Since the total thickness of the second dielectric layer 120 and the third dielectric layer 130, the total thickness of the first dielectric layer 115, the second dielectric layer 120, the third dielectric layer 130, and the fourth dielectric layer 150, and the total thickness of the gate structure 114 and the third dielectric layer 130 are different from each other, the first part 141, the second part 142, and the third part 143 of the field plate structure 140 enclose a sinking region.

[0079] Compared with Figure 1 the semiconductor device shown, the semiconductor device shown in the embodiments of the present application has a field plate structure 140 with a sinking structure. Thus, the field plate structure 140 can distribute the electric field over a larger area to reduce the concentration effect of the electric field. This helps to reduce the electric field strength, lower the risk of leakage current and breakdown, and improve the breakdown voltage resistance of the semiconductor device. And there is no need to etch each dielectric layer, reducing the loss of the gate structure 114, improving the reliability of the device, and simplifying the manufacturing process at the same time.

[0080] Exemplarily, the field plate structure 140 may be a stacked structure, and the stacked structure includes a first titanium layer, a platinum layer, a gold layer, and a second titanium layer stacked in sequence. The present application does not limit the thickness of the field plate structure 140.

[0081] The present application provides a semiconductor device. As Figure 14 shown, the semiconductor device includes an epitaxial layer 110; a source electrode structure 112, a drain electrode structure 113, and a gate electrode structure 114 located between the source electrode structure 112 and the drain electrode structure 113 are disposed on the epitaxial layer 110; a first dielectric layer 115, a fourth dielectric layer 150, and a second dielectric layer 120 are further stacked on the epitaxial layer 110; the source electrode structure 112 and the drain electrode structure 113 penetrate through the first dielectric layer 115; the fourth dielectric layer 150 covers the source electrode structure 112, the drain electrode structure 113, and the first dielectric layer 115, and a first region of the second dielectric layer 120 penetrates through the first dielectric layer 115 and the fourth dielectric layer 150 to contact the epitaxial layer 110; the gate electrode structure 114 penetrates through the first region of the second dielectric layer 120 to contact the epitaxial layer 110. That is, the second dielectric layer 120 is disposed in the area around the gate electrode structure 114, and the first dielectric layer 115 is disposed in the area outside the periphery of the gate electrode structure 114. Since the dielectric constant of the material of the first dielectric layer 115 is higher than that of the material of the second dielectric layer 120, the second dielectric layer 120 can improve the leakage problem of the gate electrode structure 114. At the same time, since the material of the first dielectric layer 115 has a high dielectric constant, a greater electrode polarization effect can be generated under the same electric field strength, so as to form a greater electric field gradient in the first dielectric layer 115, making the electric field distribution in the first dielectric layer 115 more uniform, thereby improving the snapback characteristics and power density of the semiconductor device and endowing it with better radio frequency characteristics.

[0082] The semiconductor device further includes a third dielectric layer 130, and the third dielectric layer 130 covers the second dielectric layer 120 and the gate structure 114. A field plate structure 140 is disposed on the third dielectric layer 130. Between the first portion 141 of the field plate structure 140 and the epitaxial layer 110, there are included the second dielectric layer 120 and the third dielectric layer 130; between the second portion 142 of the field plate structure 140 and the epitaxial layer 110, there are included the first dielectric layer 115, the second dielectric layer 120, the third dielectric layer 130, and the fourth dielectric layer 150; between the third portion 143 of the field plate structure 140 and the epitaxial layer 110, there are included the third dielectric layer 130 and the gate structure 114. The first portion 141, the second portion 142, and the third portion 143 of the field plate structure 140 enclose a sunken area, so that the electric field can be distributed over a larger area to reduce the concentration effect of the electric field. This helps to reduce the electric field intensity, and reduce the risk of leakage current and breakdown, improving the breakdown voltage capability of the semiconductor device. And there is no need to etch each dielectric layer, reducing the loss of the gate structure 114, improving the reliability of the device, and simplifying the manufacturing process at the same time.

[0083] Figure 15 The solid lines in Figure 1 show the output characteristic curves of the semiconductor device shown in Figure 15 The dashed lines in Figure 14 show the output characteristic curves of the semiconductor device shown in. The output characteristic curves show the relationship between the voltage (Vd) and the current (Id) of the semiconductor device, that is, the output current change curve of the semiconductor device under different voltages. It can be seen from this that the semiconductor device provided by the embodiment of the present application has good performance.

[0084] It can be understood that the above examples are only examples listed for better understanding of the technical solutions of the embodiments of the present invention, and are not the only limitations on the embodiments of the present invention. In this example, a fourth dielectric layer 150 is provided between the first dielectric layer 115 and the second dielectric layer 120. In some alternative examples, the fourth dielectric layer 150 may not be provided between the first dielectric layer 115 and the second dielectric layer 120. Correspondingly, the specific structure and manufacturing process of the semiconductor device should also be adjusted accordingly. For example, between the first portion 141 of the field plate structure 140 and the epitaxial layer 110, there are included the second dielectric layer 120 and the third dielectric layer 130; between the second portion 142 of the field plate structure 140 and the epitaxial layer 110, there are included the first dielectric layer 115, the second dielectric layer 120, and the third dielectric layer 130; between the third portion 143 of the field plate structure 140 and the epitaxial layer 110, there are included the third dielectric layer 130 and the gate structure 114.

[0085] It should be noted that the semiconductor device proposed in the embodiments of the present invention is not limited to the specific structure formed by using the manufacturing method of the above embodiments of the present application, and the specific structure of the semiconductor device can also be formed by other processing techniques by those skilled in the art.

[0086] Embodiments of the present application further provide a chip packaging structure 300. As Figure 16 shown, the chip packaging structure 300 includes a semiconductor device 100 and a packaging substrate 200, and the semiconductor device 100 is electrically connected to the packaging substrate 200.

[0087] In some embodiments, the chip packaging structure 300 may further include micro bumps (ubumps) 201, and the packaging substrate may be electrically connected to the semiconductor device 100 through a plurality of micro bumps 201. Additionally, in some embodiments, as Figure 16 shown, the electronic device may further include a connecting member 202; the packaging substrate 200 in the chip packaging structure is connected to other electronic devices through the connecting member 202, for example, electrically connected to a printed circuit board. In this way, communication between the semiconductor device 100 and other electronic devices can be achieved. Here, the connecting member 202 may be a solder ball or a micro bump.

[0088] The semiconductor device according to the embodiments of the present application can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (such as other forms of transistors, etc.), electrically connecting them to a printed circuit board, and thus constructing an electronic device. Therefore, embodiments of the present application further provide an electronic device. As Figure 17 shown, the electronic device may include the chip packaging structure 300 and a printed circuit board (PCB) 400 provided in the above embodiments. The electronic device may include electronic products such as a CMOS image sensor, a NAND flash memory, a high-bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, etc. Embodiments of the present application do not impose special restrictions on the specific form of the above electronic devices.

[0089] The above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: An epitaxial layer; A source structure, a drain structure, and a gate structure located between the source structure and the drain structure are provided on the epitaxial layer; A first dielectric layer and a second dielectric layer are further stacked on the epitaxial layer; The source structure and the drain structure penetrate through the first dielectric layer; A first region of the second dielectric layer penetrates through the first dielectric layer to contact the epitaxial layer; The gate structure penetrates through the first region of the second dielectric layer to contact the epitaxial layer; the dielectric constant of the material of the first dielectric layer is higher than that of the material of the second dielectric layer.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further comprises: a third dielectric layer covering the second dielectric layer and the gate structure.

3. The semiconductor device according to claim 2, wherein The semiconductor device further comprises a field plate structure provided on the third dielectric layer. A first part of the field plate structure includes the second dielectric layer and the third dielectric layer between it and the epitaxial layer; a second part of the field plate structure includes the first dielectric layer, the second dielectric layer, and the third dielectric layer between it and the epitaxial layer; a third part of the field plate structure includes the third dielectric layer and the gate structure between it and the epitaxial layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further comprises a fourth dielectric layer provided between the first dielectric layer and the second dielectric layer. The fourth dielectric layer covers the source structure and the drain structure, and a first region of the second dielectric layer penetrates through the fourth dielectric layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The gate structure includes a first part and a second part located on the first part. The first part of the gate structure is embedded in the second dielectric layer, and the cross-sectional area of the second part of the gate structure in the stacking direction is larger than that of the first part of the gate structure in the stacking direction.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The material of the first dielectric layer at least comprises one or more combinations of the following: aluminum nitride, aluminum oxide, aluminum oxynitride, silicon oxide, silicon nitride, silicon oxynitride.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a first dielectric layer on the epitaxial layer, and a source structure and a drain structure penetrating through the first dielectric layer; Forming a first groove penetrating through the first dielectric layer; Forming a second dielectric layer covering the first dielectric layer and the first groove. A first region of the second dielectric layer fills the first groove and contacts the epitaxial layer. The dielectric constant of the material of the first dielectric layer is higher than that of the material of the second dielectric layer; Forming a gate structure that penetrates through the first region of the second dielectric layer to contact the epitaxial layer.

8. The preparation method according to claim 7, wherein The preparation method further comprises: Forming a third dielectric layer covering the second dielectric layer and the gate structure.

9. The preparation method according to claim 8, characterized in that, The preparation method further comprises: Forming a field plate structure on the third dielectric layer. A first part of the field plate structure includes the second dielectric layer and the third dielectric layer between it and the epitaxial layer; a second part of the field plate structure includes the first dielectric layer, the second dielectric layer, and the third dielectric layer between it and the epitaxial layer; a third part of the field plate structure includes the third dielectric layer and the gate structure between it and the epitaxial layer.

10. The preparation method according to any one of claims 7-9, characterized in that, Before forming the first groove penetrating through the first dielectric layer, the preparation method further comprises: Form a fourth dielectric layer covering the source structure, the drain structure, and the first dielectric layer; Form a second groove penetrating the fourth dielectric layer, the second groove being opposite to the first groove.

11. A chip packaging structure, characterized in that, Comprising a package substrate and a semiconductor device according to any one of claims 1-6; the semiconductor device is electrically connected to the package substrate.

12. An electronic device, characterized in that, Comprising a printed circuit board and a chip package structure according to claim 11; the chip package structure is electrically connected to the printed circuit board.

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