Semiconductor device and manufacturing method thereof

Abstract

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor device includes a semiconductor layer including silicon, a first silicide layer on the semiconductor layer, and a second silicide layer disposed on the first silicide layer. The first silicide layer includes a metal different from titanium, and the second silicide layer includes TiSi2 having a C54 crystal structure. Contact resistance of the semiconductor device may be reduced.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2023 - 0193167, filed on December 27, 2023, and Korean Patent Application No. 10 - 2024 - 0121131, filed on September 5, 2024, in the Korean Intellectual Property Office, the entire disclosures of which are hereby incorporated by reference herein in their entirety. Technical Field

[0003] Various example embodiments generally relate to semiconductor devices including a first silicide layer that induces and promotes crystallization of a second silicide layer and / or methods of manufacturing semiconductor devices. Background Art

[0004] A semiconductor device may include a junction of metal and semiconductor at a certain part of the semiconductor device; the junction may exchange electrical signals. This is because metal has a relatively lower resistance compared to semiconductor and is easy to wire to the outside. However, in this case, due to the semiconductor / metal heterojunction structure, contact resistance (Schottky resistance) appears.

[0005] To reduce the contact resistance, various methods of reducing the Schottky barrier between semiconductor and metal have been proposed. For example, a metal having a work function of about 4 eV may be used for an n - type semiconductor, and a metal having a work function of about 5 eV may be used for a p - type semiconductor. However, due to the pinning of the work function of the metal on the surface of the semiconductor, there are limitations in reducing the Schottky barrier regardless of the type of metal. As another proposal, the depletion width may be reduced by doping the surface of the semiconductor in contact with the metal to a high concentration. However, as smaller - sized semiconductor devices are required, the doping concentration has to be further increased, but in such a case, there are limitations in methods of increasing the doping concentration, methods of stably maintaining the doped state, and reducing the depletion width by increasing the doping concentration. Summary of the Invention

[0006] Provided is a semiconductor device including a first silicide layer that induces and promotes crystallization of a second silicide layer.

[0007] Provided is a method of manufacturing a semiconductor device including a first silicide layer for inducing and promoting crystallization of a second silicide layer.

[0008] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0009] According to some example embodiments, a semiconductor device includes: a semiconductor layer including silicon, a first silicide layer on the semiconductor layer; and a second silicide layer on the first silicide layer including titanium and having a crystalline structure, wherein the first silicide layer includes a metal different from titanium, and the second silicide layer includes TiSi2 having a C54 crystalline structure.

[0010] The first silicide layer may include at least one of hafnium silicide, zirconium silicide, nickel silicide, and cobalt silicide.

[0011] The first silicide layer may have a thickness in the range of 3 Å to 30 Å.

[0012] The first silicide layer may have a crystalline structure.

[0013] The second silicide layer may have a thickness of 5 Å to 70 Å.

[0014] The first silicide layer may include ZrSi, ZrSi2, Zr5Si3, or Zr3Si2.

[0015] The second silicide layer may have a Schottky barrier height of 0.7 eV or less.

[0016] The semiconductor device may further include a metal layer on the second silicide layer.

[0017] The metal layer may include magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pb), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or any combination thereof.

[0018] The semiconductor layer may include a channel layer, the metal layer may include a source electrode disposed on one side surface of the channel layer and a drain electrode disposed on the other side surface of the channel layer, the second silicide layer may include a 2-1 silicide layer between the source electrode and the channel layer and a 2-2 silicide layer between the drain electrode and the channel layer, and the first silicide layer may include a 1-1 silicide layer between the 2-1 silicide layer and the channel layer and a 1-2 silicide layer between the 2-2 silicide layer and the channel layer.

[0019] The semiconductor layer may include a single crystal or polycrystalline structure.

[0020] The first silicide layer may be undoped.

[0021] The second silicide layer may be undoped.

[0022] The first silicide layer may be in direct contact with the semiconductor layer.

[0023] The first silicide layer may be in direct contact with the second silicide layer.

[0024] The semiconductor layer may include a well region doped with a first conduction type, and a source region and a drain region doped with a second conduction type that is electrically opposite to the first conduction type.

[0025] The semiconductor device may further include a gate electrode and a gate insulating layer disposed on the gate electrode, wherein the semiconductor layer may include a channel layer disposed on the gate insulating layer.

[0026] The semiconductor layer may include a channel layer, and the semiconductor device may further include a gate insulating layer on an upper surface of the channel layer and a gate electrode on the gate insulating layer.

[0027] Alternatively or additionally, according to some example embodiments, a method of manufacturing a semiconductor device includes: forming a semiconductor layer including silicon, forming a first silicide layer on the semiconductor layer, forming an amorphous second silicide layer including titanium on the first silicide layer, and crystallizing the amorphous second silicide layer to obtain a second silicide layer, wherein the first silicide layer includes a metal different from titanium, and the second silicide layer includes TiSi2 having a C54 crystal structure.

[0028] Crystallizing the amorphous second silicide layer is performed at a temperature in the range of 200 °C to 400 °C. Description of the Drawings

[0029] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description when considered in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some example embodiments;

[0031] Figure 2 is a graph showing the resistivity of titanium silicide according to temperature for thicknesses of 60 nm, 40 nm, and 25 nm of titanium silicide;

[0032] Figure 3 is a graph showing the crystallization state (crystallinity) of titanium silicide according to a comparative example at about 400 °C;

[0033] Figure 4 is a graph showing the crystallization state of titanium silicide according to a comparative example at about 500 °C;

[0034] Figure 5It is a diagram showing the crystallization states of titanium silicide in a semiconductor device according to some example embodiments for thicknesses of 5 Å, 10 Å, and 20 Å of a first silicide layer;

[0035] Figure 6 It is a transmission electron microscope (TEM) image of a semiconductor device according to some example embodiments;

[0036] Figure 7 It is a TEM image of a semiconductor device according to some example embodiments;

[0037] Figure 8 It is a diagram showing the crystalline phase of titanium silicide in a semiconductor device;

[0038] Figure 9 It is a diagram showing the crystallization state in a comparative example in which ZrSi x is arranged on a TiSi x layer;

[0039] Figure 10 It is a TEM image of a comparative example in which ZrSi with a thickness of 2 nm x is arranged on a TiSi x layer;

[0040] Figure 11 It is a TEM image of a comparative example in which ZrSi with a thickness of 0.5 nm x is arranged on a TiSi x layer;

[0041] Figure 12 It is a diagram for describing a manufacturing method of a semiconductor device according to some example embodiments;

[0042] Figure 13 It is a schematic cross-sectional view of a field effect transistor (FET) including a semiconductor device according to some example embodiments;

[0043] Figure 14 It is a schematic cross-sectional view of an FET including a semiconductor device according to some example embodiments;

[0044] Figure 15 It is a diagram schematically showing an image sensor including a semiconductor device according to some example embodiments;

[0045] Figure 16 It is a schematic cross-sectional view showing an FET according to some example embodiments;

[0046] Figure 17 It is a schematic cross-sectional view showing an FET according to some example embodiments;

[0047] Figure 18 is a perspective view schematically showing a FET according to some example embodiments;

[0048] Figure 19 is schematically showing Figure 18 a cross-sectional view of a source / drain structure of

[0049] Figure 20 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) and a display device including the DDI according to some example embodiments;

[0050] Figure 21 is a circuit diagram of a complementary metal oxide semiconductor (CMOS) inverter according to some example embodiments;

[0051] Figure 22 is a circuit diagram of a CMOS static random access memory (SRAM) device according to some example embodiments;

[0052] Figure 23 is a circuit diagram of a CMOS NAND circuit according to some example embodiments;

[0053] Figure 24 is a block diagram of an electronic device according to some example embodiments; and

[0054] Figure 25 is a block diagram of an electronic device according to some example embodiments. DETAILED DESCRIPTION

[0055] Various embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by way of example with reference to the accompanying drawings to illustrate aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The phrase such as “at least one (of)” when preceding or following a list of elements modifies the entire list of elements and not individual elements of the list

[0056] Hereinafter, semiconductor devices according to some example embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals denote like components, and for ease of explanation, the dimensions of components in the drawings may be enlarged. It will be understood that although the terms “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one element from another.

[0057] The singular forms include the plural forms unless the context clearly dictates otherwise. It will be further understood that when a part is referred to as "comprising" a component, the part may not exclude additional components but may further include additional components unless the context otherwise indicates. In addition, in the drawings, for clarity of description, the dimensions or thicknesses of the components may be exaggerated. In the following description, when a layer is described as being on another layer, the layer may be directly on the other layer or an intermediate layer may be interposed therebetween.

[0058] As used herein, the term "TiSi x " generally refers to "TiSi2" and may be used interchangeably with "TiSi2" unless otherwise expressly stated. Additionally, the term "ZrSi x " generally refers to "ZrSi2" and may be used interchangeably with "ZrSi2" unless otherwise expressly stated.

[0059] Figure 1 is a diagram schematically showing a semiconductor device 10 according to some example embodiments.

[0060] The semiconductor device 10 may include a semiconductor layer 11, a first silicide layer 12 disposed on the semiconductor layer 11 and including a first silicide, and a second silicide layer 13 disposed on the first silicide layer 12.

[0061] The semiconductor layer 11 may include silicon (Si), such as single-crystalline silicon. The semiconductor layer 11 may form various regions of the semiconductor device 10. The semiconductor device 10 may be applied to, for example, one or more of the following devices: transistors such as field effect transistors (FETs), semiconductor memory devices, logic devices, image sensors, etc., and the semiconductor layer 11 may be used as a source / drain region, a channel region, etc. of the device. The semiconductor layer 11 may be an undoped layer, an n-type doped layer, or a p-type doped layer. When the semiconductor layer 11 is an n-type doped layer, the semiconductor layer 11 may include at least one dopant from arsenic (As), phosphorus (P), and antimony (Sb). When the semiconductor layer 11 is a p-type doped layer, the semiconductor layer 11 may include a boron (B) dopant. The semiconductor layer 11 may include single-crystalline silicon or polycrystalline silicon. In some cases, the semiconductor layer 11 may be or may correspond to an n-type doped layer that includes an n-type dopant and includes a p-type dopant at a concentration much lower than the concentration of the n-type dopant; in some cases, the semiconductor layer 11 may be or may correspond to a p-type doped layer that includes a p-type dopant and includes an n-type dopant at a concentration much lower than the concentration of the p-type dopant.

[0062] The first silicide layer 12 can strengthen and promote the crystallization of the second silicide layer 13. The first silicide layer 12 can include a material having a crystallization temperature lower than that of the material of the second silicide layer 13. The first silicide layer 12 can include, for example, hafnium silicide (HfSi x ), zirconium silicide (ZrSi x ), nickel silicide (NiSi x ), and cobalt silicide (CoSi x ) at least one of. Alternatively or additionally, the first silicide layer 12 can include, for example, ZrSi, ZrSi2, Zr5Si3, or Zr3Si2.

[0063] The second silicide layer 13 can include a metal and silicon. For example, the second silicide layer 13 can include Ti and silicon. The second silicide layer 13 can include TiSi2. Additionally, the first silicide layer 12 can include a metal different from titanium (Ti).

[0064] The first silicide layer 12 can induce the second silicide layer 13 to be thin and crystallize at a low temperature. The first silicide layer 12 can include, for example, zirconium silicide (Zi x Si y ) to promote the crystallization of the second silicide layer 13 with a small thickness at a relatively low temperature. When the first silicide layer 12 includes Zr x Si y , the first silicide layer 12 can include ZrSi, ZrSi2, Zr5Si3, or Zr3Si2. The first silicide layer 12 can be disposed between the semiconductor layer 11 and the second silicide layer 13. The upper surface of the first silicide layer 12 can be in direct contact with the lower surface of the second silicide layer 13. Alternatively or additionally, the lower surface of the first silicide layer 12 can be in direct contact with the semiconductor layer 11, and the upper surface of the first silicide layer 12 can be in direct contact with the second silicide layer 13.

[0065] The second silicide layer 13 may have a thickness of 70 Å or less. For example, the second silicide layer 13 may have a thickness in the range of 5 Å to 70 Å. For example, the second silicide layer 13 may have a thickness in the range of 5 Å to 50 Å. However, as described above, it is difficult to crystallize the second silicide layer 13 while reducing its thickness. This may be because, when the thickness is reduced, the crystallization process can easily damage the second silicide layer 13. However, when crystallizing the second silicide layer 13 having a thickness of 70 Å or less, the crystallization of the second silicide layer 13 can be induced, promoted, and strengthened by the first silicide layer 12, and thus, the second silicide layer 13 can be crystallized at a relatively low temperature, and the possibility of occurrence of damage to the second silicide layer 13 or other layers that may occur at high temperatures and / or the influence from the occurrence can be prevented or reduced. For example, compared with the case where the first silicide layer 12 is absent, the crystallization temperature of the second silicide layer 13 can be reduced, and when the crystallization temperature is reduced, the possibility of occurrence of damage to the second silicide layer 13 during crystallization of the second silicide layer 13 having a reduced thickness and / or the influence from the occurrence can be prevented or reduced. The crystallization temperature of the second silicide layer 13 may be 500 °C or lower. For example, the crystallization temperature of the second silicide layer 13 may be 450 °C or lower. For example, the crystallization temperature of the second silicide layer 13 may be 400 °C or lower. For example, the crystallization temperature of the second silicide layer 13 may be in the range of 200 °C to 400 °C, such as 300 °C to 400 °C, 350 °C to 400 °C, or 380 °C to 400 °C. It should be understood that the "crystallization temperature of the second silicide layer 13" refers to the temperature at which the amorphous second silicide layer crystallizes. In addition, the thickness of the second silicide layer 13 may refer to the thickness of the amorphous second silicide layer before crystallization or the thickness of the second silicide layer after crystallization.

[0066] A metal layer 14 may be further provided on the second silicide layer 13. Based on the second silicide layer 13, the metal layer 14 may be disposed oppositely (relatively) to the first silicide layer 12. The metal layer 14 may be provided in direct contact with the second silicide layer 13. However, the metal layer 14 is not limited thereto. The metal layer 14, for example, may be used as an electrode layer. The metal layer 14 may include magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pb), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or any combination thereof.

[0067] As semiconductor memory devices or logic devices employing semiconductor device 10 are reduced in their size and area, the following is necessary or desirable: to maintain ohmic characteristics even in a narrow region (area) to maintain device performance. To maintain ohmic characteristics, metal layer 14 should have a low resistivity and a low contact resistance. However, in the junction structure of semiconductor layer 11 and metal layer 14, due to the pinning effect generated on the bonding (combining) surface, a Schottky barrier height appears on the bonding surface between silicon and metal layer 14, which results in a high contact resistance. Here, a second silicide layer 13 is provided between metal layer 14 and silicon semiconductor layer 11 (i.e., semiconductor layer 11 including silicon) to reduce the Schottky barrier height on the bonding surface between silicon semiconductor layer 11 and metal layer 14, and thus, the contact resistance can be reduced. Alternatively or additionally, since the second silicide layer 13 has excellent resistivity characteristics, the resistance characteristics between semiconductor layer 11 including Si and metal layer 14 can be improved. By including titanium silicide (TiSi x ), the second silicide layer 13 can improve the resistance characteristics. Because titanium silicide has relatively excellent thermal stability and / or a low resistivity, titanium silicide can be effectively applied as a contact material for silicon-based semiconductor devices. Since the second silicide layer 13 has one or more of a low work function, a low resistivity, and good crystal coherency (consistency, coherency) with respect to silicon semiconductor layer 11, the second silicide layer 13 can be used as an intermediate resistance material between silicon semiconductor layer 11 and metal layer 14.

[0068] The first silicide layer 12 can lower the crystallization temperature of the second silicide layer 13 and can allow the second silicide layer 13 to have a crystalline phase. When the second silicide layer 13 includes titanium silicide (TiSi x ), the second silicide layer 13 can have a C54 crystalline structure. Since the crystallization temperature of the second silicide layer 13 is lowered, the negative impact of high temperature on other layers during the process of manufacturing / fabricating semiconductor device 10 can be reduced, and semiconductor device 10 can have high conductivity. Alternatively or additionally, even when the thickness of the second silicide layer 13 is reduced, the first silicide layer 12 induces and promotes the crystallization of the second silicide layer 13 at a relatively low temperature, and thus, the second silicide layer 13 can have a C54 crystalline structure. In this way, the Schottky barrier height of the second silicide layer 13 can be reduced. For example, the second silicide layer 13 can have a Schottky barrier height of 0.7 eV or less. Alternatively or additionally, the second silicide layer 13 can have a Schottky barrier height in the range of 0.3 eV to 0.7 eV. Furthermore, the first silicide layer 12 can have a crystalline structure instead of an amorphous structure.

[0069] Hereinafter, an example in which the second silicide layer 13 includes titanium silicide (TiSi2) is described in more detail.

[0070] Titanium silicide may have, for example, a C49 crystal structure or a C54 crystal structure during the crystallization process.

[0071] Figure 2 Shows the change in resistivity according to temperature for cases where the thickness of the titanium silicide (TiSi x ) layer is 25 nm, 40 nm, and 60 nm. Figure 2 Shows an example in which a titanium silicide layer is crystallized without using the first silicide layer 12. Line A represents the process limit temperature of a semiconductor device including the titanium silicide layer. As the thickness of the titanium silicide layer decreases, the resistivity increases. When the thickness of the titanium silicide layer is 40 nm or 60 nm, the resistivity is relatively low even when in the amorphous state. Additionally, when the thickness of the titanium silicide layer is 25 nm, a C49 crystal structure is formed at a temperature in the range of 500 °C to 720 °C, and the resistivity is high, i.e., about 20 ohms / square or greater. A C54 crystal structure is formed at a temperature of about 720 °C or higher, and in this case, the resistivity decreases to 20 ohms / square or lower. In the case of titanium silicide, a C49 crystal structure is formed at a relatively low temperature such as about 500 °C, but a C54 crystal structure having a resistivity lower than that of the C49 structure is formed at a high temperature of about 720 °C. Since the C49 crystal structure has an activation energy lower than that of the C54 crystal structure, in the crystallization of titanium silicide, nucleation may proceed to have a C49 crystal structure rather than a C54 crystal structure. Thus, the packing density of the C54 crystal structure of titanium silicide becomes smaller than that of the C49 crystal structure, and due to the low packing density, volume shrinkage problems may occur during post-treatment operations such as annealing and / or other heat treatments such as low-pressure chemical vapor deposition (LPCVD) steps. Because it is difficult to crystallize due to the high crystallization temperature of the C54 crystal structure, and as the thickness decreases, the crystallization temperature of the C54 structure increases significantly, the titanium silicide layer has been used in the amorphous form all the time, even though the resistance in the amorphous state is higher than that of the C54 crystal structure. Alternatively or additionally, a C54 crystal structure has been formed at a relatively low temperature by adding a small amount of Mo, Ta, Nb, etc. to titanium silicide (TiSi x ) to lower the crystallization temperature, but the resistivity increases, and moreover, crystallization does not occur at a thin thickness.

[0072] As described above, titanium silicide has better resistance characteristics in the C54 crystal structure or phase compared to the C49 crystal structure or phase. However, due to the high activation energy of the C54 crystal structure, when the silicon semiconductor layer 11 and the second silicide layer 13 including titanium are bonded to each other, crystallization may not proceed sufficiently. At a relatively low temperature such as about 500 °C, the C49 crystal structure can be obtained, but when bonded to the silicon semiconductor layer 11, the C49 crystal structure exhibits high resistivity characteristics and high contact resistance. In contrast, titanium silicide (TiSi x ) in the C54 crystal structure has resistance characteristics better than those of the C49 crystal structure. However, since the crystallization temperature of the C54 crystal structure is higher than that of the C49 crystal structure, other layers are negatively affected during the crystallization process and the overall performance of the semiconductor device deteriorates.

[0073] Therefore, according to some example embodiments, a first silicide layer 12 including a crystallization driving intermediate (medium) material is provided between the silicon semiconductor layer 11 and the second silicide layer 13, and thus, crystallization of the second silicide layer 13 can proceed sufficiently even for a reduced thickness. Since the first silicide layer 12 has a high reactivity with silicon in the semiconductor layer 11, the crystallization activation energy of the second silicide layer 13 is greatly reduced, and the crystallization stability can be improved.

[0074] The first silicide layer 12 can be a silicide including a metal and silicon. The first silicide layer 12 can include a metal different from titanium. The metal layer 14 can be or can include a nitride-based metal layer such as TiN, WN, MoN, etc. Alternatively or additionally, the metal layer 14 can include at least one of Mo, Ru, Co, Ti, and W.

[0075] Figure 3 is a diagram showing the crystallization state of titanium silicide (TiSi x ) without the first silicide layer 12 according to the comparative example at about 400 °C based on X-ray diffraction (XRD) and reflection high energy electron diffraction (RHEED) analyses. Figure 3 The diagram of shows the light intensity according to 2θ as the crystallization specified angle. The crystal structure of the corresponding material can be confirmed based on the peak at a certain angle. Referring to Figure 3 , the titanium silicide layer of the comparative example shows amorphous characteristics. This indicates that due to the high activation energy, titanium silicide (TiSi x ) does not crystallize at a low temperature of about 400 °C. Figure 4 is a diagram showing the crystallization state of titanium silicide (TiSi x ) without the first silicide layer 12 according to the comparative example at a temperature of about 500 °C based on XRD and RHEED analyses. At a relatively high temperature of 500 °C, titanium silicide (TiSi x) Crystallization, but according to XRD analysis, it is confirmed that a C49 crystal structure with high resistance is formed.

[0076] Figure 5 FIG. is a diagram showing the crystallization state in the case where a first silicide layer 12 is disposed between a semiconductor layer 11 and a second silicide layer 13 according to some exemplary embodiments. Here, the first silicide layer 12 includes ZrSi2. The second silicide layer 13 includes titanium silicide (TiSi2). Examples are shown in which the thickness of the first silicide layer 12 is 5 Å, 10 Å, and 20 Å. In Figure 5 In order to facilitate description, the curves are shown spaced apart from each other regardless of intensity to show the embodiments in which the thickness of the first silicide layer 12 is 5 Å, 10 Å, and 20 Å together. When the first silicide layer 12 has thicknesses of 5 Å, 10 Å, and 20 Å, titanium silicide has a C54 crystal structure. When the first silicide layer 12 is very small in thickness, titanium silicide (TiSi2) can have a C54 crystal structure. The first silicide layer 12 can have a thickness of, for example, 3 Å to 30 Å. For example, the first silicide layer 12 can have a thickness of 3 Å to 20 Å. For example, the first silicide layer 12 can have a thickness of 5 Å to 20 Å.

[0077] Refer to Figure 5 , when the second silicide layer 13 is grown at a temperature of about 400 °C, it is confirmed by RHEED that titanium silicide (TiSi x ) crystallizes. According to XRD analysis, the crystal phase of titanium silicide (TiSi x ) has a low-resistance C54 crystal structure. The thickness of titanium silicide (TiSi x ) can be 70 Å or less. For example, the thickness of titanium silicide (TiSi x ) is 5 nm. In the semiconductor device 10 according to some exemplary embodiments, the second silicide layer 13 can have a single crystal phase. For example, the second silicide layer 13 can have a C54 crystal structure.

[0078] Figure 6 FIG. is a transmission electron microscope (TEM) image of a semiconductor device when the first silicide layer 12 includes ZrSi with a thickness of 20 Å x . The TEM image shows that the Si semiconductor layer 11, the ZrSi2 first silicide layer 12, and the TiSi2 second silicide layer 13 are stacked, and a crystal structure is formed. The TiSiO x layer represents an oxide layer generated when exposed to the atmosphere after stacking the semiconductor device. The TiSiO x layer is not a component in the semiconductor device according to some exemplary embodiments. Here, the total thickness of the ZrSi2 first silicide layer 12, the TiSi2 second silicide layer 13, and the TiSiO x layer can be about 90 Å.

[0079] Figure 7 is a TEM image of a semiconductor device when the first silicide layer 12 includes ZrSi having a thickness of 5 Å x The TEM image shows that the Si semiconductor layer 11, the first silicide layer 12 including ZrSi x (ZrSi2), and the second silicide layer 13 including TiSi x (TiSi2) are stacked, and a crystalline structure is formed. Here, the first silicide layer 12 including ZrSi x , the second silicide layer 13 including TiSi x , and the total thickness of the TiSiO x layer can be about 30 Å. As described above, when the first silicide layer 12 is very small in thickness, the second silicide layer 13 including TiSi x can crystallize.

[0080] Figure 8 is a diagram showing the C49-TiSi2 crystal structure and the C54-TiSi2 crystal structure in a semiconductor device formed by stacking a TiSi2 layer on an Si layer. C54-TiSi2 has a peak at a crystallization angle of about 40° 2θ.

[0081] Next, a comparative example in which zirconium silicide (ZrSi x ) is stacked on titanium silicide is described. That is, the ZrSi x layer is not provided between the Si layer and the TiSi x layer, but is disposed on the TiSi x . Figure 9 shows the crystallization state when a structure in which a TiSi x layer having a thickness of 2 nm, a ZrSi x layer having a thickness of 0.5 nm, and a TiSi x layer having a thickness of 5 nm are sequentially stacked on an Si layer at a temperature of 200 °C or lower is annealed at a temperature of 400 °C for 30 minutes. In Figure 9 , no crystal structure of titanium silicide is shown, but an amorphous state is shown. In other words, when the position of the ZrSi x layer corresponding to the first silicide layer 12 is changed to be on the second silicide layer 13, the TiSi x layer does not crystallize at a temperature of about 400 °C.

[0082] Figure 10 shows having Si / TiSi x / ZrSi xTEM image and EDS line scan of a comparative example of a stacked structure and atomic % according to the distance of the stacked structure. ZrSi x Has a thickness of 2 nm. TiSi x Has a thickness of about 2 nm. Here, TiSiO x Represents an oxide layer that is oxidized when the stacked structure crystallizes. Referring to the TEM image, TiSi x layer is not crystallized.

[0083] Figure 11 Showing a TEM image and EDS line scan of a comparative example of a stacked structure having Si / TiSi x / ZrSi x / TiSi x stacked structure and atomic % according to the distance of the stacked structure. ZrSi x Has a thickness of 0.5 nm. TiSi x Has a thickness of about 0.5 nm. Referring to the TEM image, TiSi x layer is not crystallized.

[0084] Referring to Figure 10 and 11 , when the ZrSi x layer corresponding to the first silicide layer is located on the TiSi x layer, or when the ZrSi x layer is located between two TiSi x layers and its thickness decreases, the TiSi x layer is not crystallized. When a thin ZrSi x layer is provided between two TiSi x layers, an effect similar to that obtained from a TiSi x layer doped with Zr can be obtained. Even when the TiSi x layer is doped with a dopant such as Zr, it may be difficult to crystallize the TiSi x layer.

[0085] In the semiconductor device 10 according to some example embodiments, the first silicide layer 12 may be an undoped layer. In addition, the second silicide layer 13 may be an undoped layer. When the second silicide layer 13 is an undoped layer, compared with a doped silicide layer, the second silicide layer 13 may have a lower specific resistance and a lower Schottky barrier. At the same time, the first silicide layer 12 may have a C54 crystal structure at a relatively low temperature. However, the first silicide layer 12 and the second silicide layer 13 are not limited thereto, and a dopant may be used when necessary or desired.

[0086] The semiconductor device 10 according to some example embodiments includes a first silicide layer 12 between a semiconductor layer 11 and a second silicide layer 13, and thus, crystallization of the second silicide layer 13 may be possible even with a very thin thickness and at a relatively low temperature. Since there is a first silicide layer 12 between the semiconductor layer 11 and the second silicide layer 13, the titanium silicide layer of the semiconductor device 10 according to some example embodiments may have a C54 crystal structure with the same thickness within the temperature range in which the titanium silicide layer in a conventional device without the first silicide layer 12 has a C49 crystal structure. In this way, the contact resistance of the miniaturized Si-based semiconductor device 10 can be reduced, and the negative impact on other layers of the semiconductor device 10 during the crystallization process can be reduced, thereby improving the performance of the semiconductor device 10.

[0087] Figure 12 is a diagram for describing a method of manufacturing a semiconductor device according to some example embodiments.

[0088] Referring to Figure 12 and 1 the method of manufacturing the semiconductor device includes forming a semiconductor layer 11 including silicon (S10). Additionally, a first silicide layer 12 is formed on the semiconductor layer 11 (S20). The first silicide layer 12 may include a metal different from titanium. An amorphous second silicide layer including titanium is formed on the first silicide layer 12 (S30). The amorphous second silicide layer is crystallized to obtain a second silicide layer 13 including TiSi2 having a C54 crystal structure (S40). The amorphous second silicide layer can be crystallized by a thermal process. The first silicide layer 12 promotes crystallization of the amorphous second silicide layer at a relatively low temperature such that the obtained second silicide layer 13 may have a C54 crystal structure. Crystallization of the amorphous second silicide layer can be performed at a temperature in the range of 200 °C to 400 °C. In the thermal process, the heating rate can be greater than >10 o °C / minute, the heating time can be greater than 10 seconds, and the thermal process can be performed under a vacuum with a pressure less than 10 -3 Torr. The first silicide layer 12 may have a thickness in the range of 3 Å to 30 Å. The second silicide layer 13 may have a thickness ranging from 5 Å to 70 Å.

[0089] The semiconductor device 10 manufactured by the manufacturing method according to some example embodiments may have a reduced contact resistance and can be applied to next-generation semiconductor memory devices and / or logic devices.

[0090] The logic device is responsible for operation and control, and the storage device is responsible for storing information. The logic device can be applied to one or more of micro-components, analog integrated circuits (ICs), logic ICs, etc. The analog IC can include one or more of power semiconductors, image sensors, touch controllers, etc. The logic IC can include a display driver IC (DDI), a timing controller (T-CON), a media IC, an application processor (AP), semiconductors for vehicles, etc. The storage device can include one or more of DRAM, SRAM, NAND memory, etc.

[0091] The semiconductor device 10 described above can be applied to various devices such as field effect transistors (FETs), etc. For example, Figure 13 is a cross-sectional view schematically showing an FET 100 according to some example embodiments. Referring to Figure 13 , the FET 100 can include a well region 101 doped with a first conduction type, a source region 102a doped with a second conduction type electrically opposite to the first conduction type, a drain region 102b doped with the second conduction type, a 1-1 silicide layer 103a provided on the source region 102a, a 1-2 silicide layer 103b provided on the drain region 102b, a 2-1 silicide layer 104a provided on the 1-1 silicide layer 103a, a 2-2 silicide layer 104b provided on the 1-2 silicide layer 103b, a source electrode 105a provided on the 2-1 silicide layer 104a, a drain electrode 105b provided on the 2-2 silicide layer 104b, a gate insulating layer 108 provided on the well region 101, and a gate electrode 109 provided on the gate insulating layer 108.

[0092] Compared with Figure 1 , the source region 102a and the drain region 102b can correspond to a semiconductor layer including silicon. The 2-1 silicide layer 104a and the 2-2 silicide layer 104b can include a metal and silicon. The 2-1 silicide layer 104a and the 2-2 silicide layer 104b can include titanium silicide (TiSi x ). The 1-1 silicide layer 103a and the 1-2 silicide layer 103b can each include at least one of HfSi x , ZrSi x , NiSi x , and CoSi x . The 1-1 silicide layer 103a and the 1-2 silicide layer 103b can include at least one of ZrSi, ZrSi2, Zr5Si3, or Zr3Si2.

[0093] In Figure 13In [the figure], the well region 101 is doped to be p-type, and the source region 102a and the drain region 102b are doped to be n-type. However, in some exemplary embodiments, it is not limited thereto, and the well region 101 may be doped to be n-type, and the source region 102a and the drain region 102b may be doped to be p-type. Additionally, in some exemplary embodiments, other impurities, such as, but not limited to, one or more of Group IV impurities such as carbon, silicon, or germanium, may be doped and introduced into either or both of the source region 102a and the drain region 102b. Alternatively, the source region 102a and the drain region 102b may be undoped. The well region 101 may be doped to a relatively low concentration of about 10 14 ~10 18 / cm 3 , and the source region 102a and the drain region 102b may be doped to a relatively high concentration of about 10 19 / cm 3 to reduce the depletion width. In some exemplary embodiments, a halo / pocket region (not shown) may be included in or near the source region 102a and / or the drain region 102b; however, the exemplary embodiments are not limited thereto.

[0094] The source region 102a and the drain region 102b may be disposed on opposite (relative) side surfaces of the upper portion of the well region 101. For example, after forming the well region 101 by doping a semiconductor substrate to be p-type, the opposite sides on the upper surface of the semiconductor substrate are doped to be n-type to form the source region 102a and the drain region 102b. The well region 101 may include a channel region 101a between the source region 102a and the drain region 102b. Like the well region 101, the channel region 101a may be doped to the first conduction type. The source region 102a and the drain region 102b may be disposed spaced apart from each other, and the channel region 101a is therebetween. Here, the source region 102a and the drain region 102b may correspond to Figure 1 the semiconductor layer 11. In other words, when Figure 13 the FET 100 corresponds to Figure 1 the semiconductor device 10, the semiconductor layer 11 may include the source region 102a and the drain region 102b.

[0095] The 1-1 silicide layer 103a and the 1-2 silicide layer 103b may be disposed spaced apart from each other, and the gate insulating layer 108 is therebetween.

[0096] The 2-1 silicide layer 104a and the 2-2 silicide layer 104b may reduce (e.g., further reduce) the contact resistance. The 2-1 silicide layer 104a and the 2-2 silicide layer 104b may be disposed spaced apart from each other, and the gate insulating layer 108 is therebetween. The 2-1 silicide layer 104a and the 2-2 silicide layer 104b may correspond to Figure 1The second silicide layer 13. In other words, when Figure 13 the FET 100 corresponds to Figure 1 the semiconductor device 10, the second silicide layer 13 may include a 2-1 silicide layer 104a and a 2-2 silicide layer 104b.

[0097] The 1-1 silicide layer 103a can induce and accelerate the crystallization of the 2-1 silicide layer 104a, and the 1-2 silicide layer 103b can induce and accelerate the crystallization of the 2-2 silicide layer 104b. The 1-1 silicide layer 103a and the 1-2 silicide layer 103b may correspond to Figure 1 the first silicide layer 12. In other words, when Figure 13 the FET 100 corresponds to Figure 1 the semiconductor device 10, the first silicide layer 12 may include a 1-1 silicide layer 103a and a 1-2 silicide layer 103b. The lower surface of the 1-1 silicide layer 103a may be in direct contact with the source region 102a, and the upper surface of the 1-1 silicide layer 103a may be in direct contact with the 2-1 silicide layer 104a. In addition, the lower surface of the 1-2 silicide layer 103b may be in direct contact with the drain region 102b, and the upper surface of the 1-2 silicide layer 103a may be in direct contact with the 2-2 silicide layer 104b.

[0098] The source electrode 105a on the 2-1 silicide layer 104a and the drain electrode 105b on the 2-2 silicide layer 104b may correspond to Figure 1 the metal layer 14. In other words, when Figure 13 the FET 100 corresponds to Figure 1 the semiconductor device 10, the metal layer 14 may include a source electrode 105a and a drain electrode 105b. The source electrode 105a and the drain electrode 105b may be arranged spaced apart from each other, and the gate electrode 109 is therebetween.

[0099] The gate insulating layer 108 may be disposed on the upper surface of the well region 101, and particularly on the upper surface of the channel region 101a. The gate insulating layer 108 may include at least one dielectric material from SiO2, SiN x , HfO2 and Al2O3. The gate electrode 109 disposed on the gate insulating layer 108 may include polysilicon such as doped polysilicon and / or the same metal material as the metal material included in the source electrode 105a and the drain electrode 105b.

[0100] The FET 100 may further include a spacer 110 surrounding the sidewalls of the gate insulating layer 108 and the gate electrode 109. The spacer 110 can prevent the gate insulating layer 108 and the gate electrode 109 from directly contacting the source electrode 105a and the drain electrode 105b. The spacer 110 may include an insulating material such as SiO2, SiN xetc.

[0101] Figure 14 is a cross-sectional view schematically showing the FET 100a according to some example embodiments. In Figure 13 the FET 100, the upper surfaces of the well region 101, the source region 102a, and the drain region 102b are located in the same plane, and the 2-1 and 2-2 silicide layers 104a and 104b can extend to contact the sidewalls of the spacer 110. In contrast, in Figure 14 the FET 100a, the 2-1 and 2-2 silicide layers 104a and 104b can extend to contact the lower surface of the spacer 110. For this purpose, the upper surface of the well region 101 can be formed higher than the upper surfaces of the source region 102a and the drain region 102b. The 2-1 and 2-2 silicide layers 104a and 104b can extend along the lower surface of the spacer 110 to the interface between the spacer 110 and the gate insulating layer 108. In this case, the 1-1 silicide layer 103a and the 1-2 silicide layer 103b can also extend to the interface between the spacer 110 and the gate insulating layer 108 to contact the side surface of the channel region 101a.

[0102] The FET 100 or 100a can be used in an image sensor (however, the example embodiments are not limited thereto). Figure 15 is a diagram schematically showing the image sensor 150. The image sensor 150 includes an optical sensor array 160 in which optical sensors 161 for sensing light are arranged, a color filter array 180 in which color filters 181 for filtering light according to color are arranged, a microlens array 190 in which microlenses 191 for focusing light according to pixels are arranged, and a driving layer 170 including a field effect transistor (FET) 100 or 100a. The image sensor 150 can generate an electrical image signal based on the intensity of incident light. The image sensor 150 can be applied to various multimedia devices having an image capturing function. The image sensor 150 can be applied to cameras in mobile phones, smart phones, tablet computers, smart tablet computers, laptop computers, etc.

[0103] Figure 16 is a cross-sectional view schematically showing the FET 200 according to some example embodiments. Refer to Figure 16, the FET 200 may include a gate electrode 201, a gate insulating layer 202 disposed on the gate electrode 201, a channel layer 203 disposed on the gate insulating layer 202, a source electrode 206a disposed on one side of the channel layer 203 in electrical contact with the channel layer 203, a drain electrode 206b disposed on the other side of the channel layer 203 in electrical contact with the channel layer 203, a 2-1 silicide layer 205a disposed between the channel layer 203 and the source electrode 206a, a 2-2 silicide layer 205b disposed between the channel layer 203 and the drain electrode 206b, a 1-1 silicide layer 204a disposed between the 2-1 silicide layer 205a and the channel layer 203, and a 1-2 silicide layer 204b disposed between the 2-2 silicide layer 205b and the channel layer 203.

[0104] The channel layer 203 may correspond to Figure 1 the semiconductor layer 11. For example, when Figure 16 the FET 200 corresponds to Figure 1 the semiconductor device 10, the semiconductor layer 11 may include the channel layer 203 disposed on the gate insulating layer 202. The channel layer 203 may include undoped silicon.

[0105] The source electrode 206a and the drain electrode 206b may correspond to Figure 1 the metal layer 14. For example, when Figure 16 the FET 200 corresponds to Figure 1 the semiconductor device 10, the metal layer 14 may include the source electrode 206a and the drain electrode 206b.

[0106] The 2-1 silicide layer 205a and the 2-2 silicide layer 205b may correspond to Figure 1 the second silicide layer 13. In other words, when Figure 16 the FET 200 corresponds to Figure 1 the semiconductor device 10, the second silicide layer 13 may include the 2-1 silicide layer 205a and the 2-2 silicide layer 205b. The 2-1 silicide layer 205a may extend from one side surface of the channel layer 203 to a part of its upper surface. In some exemplary embodiments, the 2-2 silicide layer 205b may extend from the other side surface of the channel layer 203 to another part of its upper surface without contacting the 2-1 silicide layer 205a. Thus, the 2-1 and 2-2 silicide layers 205a and 205b may bend by about 90° between the side surface and the upper surface of the channel layer 203.

[0107] The 1-1 silicide layer 204a and the 1-2 silicide layer 204b may correspond to Figure 1 the first silicide layer 12. In other words, when Figure 16 the FET 200 corresponds to Figure 1When manufacturing the semiconductor device 10, the first silicide layer 12 may include a 1-1 silicide layer 204a and a 1-2 silicide layer 204b. The 1-1 silicide layer 204a may extend from one side surface of the channel layer 203 to a part of the upper surface. In some exemplary embodiments, the 1-2 silicide layer 204b may extend from the other side surface of the channel layer 203 to another part of the upper surface, so as not to contact the 1-1 silicide layer 204a. Therefore, the 1-1 silicide layer 204a and the 1-2 silicide layer 204b may bend by approximately 90° between the side surface and the upper surface of the channel layer 203.

[0108] Figure 17 is a cross-sectional view schematically showing the FET 200a according to some exemplary embodiments. Figure 16 The FET200 has a bottom gate structure in which the gate electrode 201 is disposed under the channel layer 203, but Figure 17 the FET 200a is different from the FET 200 in that the FET 200a has a top gate structure. Referring to Figure 17 , the FET 200a may include a substrate 221, an insulating layer 222 disposed on the upper surface of the substrate 221, a channel layer 223 disposed on the upper surface of the insulating layer 222, a gate insulating layer 227 disposed in a part of the upper surface of the channel layer 223, a gate electrode 228 disposed on the upper surface of the gate insulating layer 227, a 1-1 silicide layer and a 1-2 silicide layer 224a and 224b respectively disposed on different regions of the upper surface of the channel layer 223, a 2-1 silicide layer 225a disposed on the upper surface of the 1-1 silicide layer 224a, a 2-2 silicide layer 225b disposed on the upper surface of the 1-2 silicide layer 224b, a source electrode 226a disposed on the upper surface of the 2-1 silicide layer 225a, and a drain electrode 226b disposed on the upper surface of the 2-2 silicide layer 225b.

[0109] The channel layer 223 may correspond to Figure 1 the semiconductor layer 11. In other words, when Figure 17 the FET 200a corresponds to Figure 1 the semiconductor device 10, the semiconductor layer 11 may include the channel layer 223 disposed on the insulating layer 222. The channel layer 223 may include undoped silicon.

[0110] The 1-1 silicide layer 224a and the 1-2 silicide layer 224b may correspond to Figure 1 the first silicide layer 12. In other words, when Figure 17 the FET 200a corresponds to Figure 1When referring to the semiconductor device 10, the first silicide layer 12 may include a 1-1 silicide layer 224a and a 1-2 silicide layer 224b. The 1-1 silicide layer 224a and the 1-2 silicide layer 224b may be arranged spaced apart from each other, and the gate insulating layer 227 is therebetween. The lower surface of the 1-1 silicide layer 224a may be in direct contact with the channel layer 223, and the upper surface of the 1-1 silicide layer 224a may be in direct contact with a 2-1 silicide layer 225a. In addition, the lower surface of the 1-2 silicide layer 224b may be in direct contact with the channel layer 223, and the upper surface of the 1-2 silicide layer 224b may be in direct contact with a 2-2 silicide layer 225b.

[0111] The 2-1 silicide layer 225a and the 2-2 silicide layer 225 may correspond to Figure 1 the second silicide layer 13. In other words, when Figure 17 the FET 200a corresponds to Figure 1 the semiconductor device 10, the second silicide layer 13 may include a 2-1 silicide layer 225a disposed on the 1-1 silicide layer 224a and a 2-2 silicide layer 225b disposed on the 1-2 silicide layer 224b. The 2-1 silicide layer 225a and the 2-2 silicide layer 225b may be arranged spaced apart from each other, and the gate insulating layer 227 is therebetween.

[0112] The source electrode 226a and the drain electrode 226b may correspond to Figure 1 the metal layer 14. In other words, when Figure 17 the FET 200a corresponds to Figure 1 the semiconductor device 10, the metal layer 14 may include a source electrode 226a disposed on the 2-1 silicide layer 225a and a drain electrode 226b disposed on the 2-2 silicide layer 225. The source electrode 226a and the drain electrode 226b may be arranged spaced apart from each other, and the gate electrode 228 is therebetween.

[0113] Figure 18 is a perspective view schematically showing an FET 300 according to some example embodiments. Referring to Figure 18 , the FET 300 may include a substrate 301, a source structure 310 protruding in the Z direction from the upper surface of the substrate 301, a drain structure 340 protruding in the Z direction from the upper surface of the substrate 301, a channel 320 protruding in the Z direction from the upper surface of the substrate 301 and having a strip shape extending in the Y direction, and a gate structure 330 covering the channel 320 to surround the channel 320. The FET 300 may further include an insulating layer 302 for electrically insulating from another adjacent FET not shown in the figure. The insulating layer 302 includes an insulating dielectric material and may be arranged to extend in the Y direction along opposite side surfaces of the source structure 310, the channel 320, the gate structure 330, and the drain structure 340 on the upper surface of the substrate 301.Figure 18 The FET 300 may include, for example, a fin field effect transistor (FinFET).

[0114] The channel 320 may extend in the Y direction and may then be connected between the source structure 310 and the drain structure 340. In other words, a first end of the channel 320 may be in contact with the source structure 310, and a second end of the channel 320 may be in contact with the drain structure 340. The channel 320 may include a P-type silicon semiconductor doped to a relatively low concentration or an N-type silicon semiconductor doped to a relatively low concentration.

[0115] The gate structure 330 may include a gate insulating layer 331 covering the channel 320 between the source structure 310 and the drain structure 340, and a gate electrode 332 covering the gate insulating layer 331. The gate insulating layer 331 may protrude from the upper surface of the substrate 301 to cover three surfaces of the channel 320, that is, opposite side surfaces and the upper surface of the channel 320. In addition, the gate electrode 332 may protrude from the upper surface of the substrate 301 to cover three surfaces of the gate insulating layer 331, that is, opposite side surfaces and the upper surface of the gate insulating layer 311.

[0116] The source structure 310 may include a semiconductor layer 311, a source electrode 314 disposed in the semiconductor layer 311, a second silicide layer 313 disposed in the semiconductor layer 311 to surround the source electrode 314, and a first silicide layer 312 including a first silicide disposed in the semiconductor layer 311 to surround the second silicide layer 313. Similarly, the drain structure 340 may include a semiconductor layer 341, a drain electrode 344 disposed in the semiconductor layer 341, a second silicide layer 343 disposed in the semiconductor layer 341 to surround the drain electrode 344, and a first silicide layer 342 including a first silicide disposed in the semiconductor layer 341 to surround the second silicide layer 343.

[0117] The semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340 may be disposed to protrude in the Z direction from the upper surface of the substrate 301. The semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340 may include an N-type semiconductor doped to a relatively high concentration or a P-type semiconductor doped to a relatively high concentration. The semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340 may extend locally in the Y direction and may be connected to the channel 320. A part of the semiconductor layer 311 in the source structure 310 and a part of the semiconductor layer 341 in the drain structure 340 (the parts connected to the channel 320) may have the same width as the channel 320 in the X direction. In addition, another part of the semiconductor layer 311 in the source structure 310 and another part of the semiconductor layer 341 in the drain structure 340 (these parts opposite to the channel 320) may have a width greater than the width of the channel 320.

[0118] Figure 19 is a cross-sectional view schematically showing Figure 18 source structure 310 and showing a cross-section of source structure 310 taken along line A-A' Figure 18 thereof. Referring to Figure 19 , source electrode 314 may have a strip shape extending in the Z direction, which is different from the direction in which channel 320 extends. Source electrode 314 may include a first portion 314a located in semiconductor layer 311 and a second portion 314b protruding in the Z direction from the upper surface of semiconductor layer 311. Second silicide layer 313 may be arranged to surround the first portion 314a of source electrode 314 between semiconductor layer 311 and the first portion 314a of source electrode 314. In some example embodiments, first silicide layer 312 may be arranged to surround second silicide layer 313 between semiconductor layer 311 and second silicide layer 313. On the upper surface of semiconductor layer 311, the second portion 314b of source electrode 314 may cover at least a portion of second silicide layer 313. To this end, the diameter of the second portion 314b in source electrode 314 may be greater than the diameter of the first portion 314a. The above structure of source structure 310 may be applied to drain structure 340 in the same manner.

[0119] When Figure 18 and 19 the FET 300 corresponds to Figure 1 semiconductor device 10, semiconductor layer 11 may include semiconductor layer 311 of source structure 310 and semiconductor layer 341 of drain structure 340, first silicide layer 12 may include first silicide layer 312 of source structure 310 and first silicide layer 342 of drain structure 340, second silicide layer 13 may include second silicide layer 313 of source structure 310 and second silicide layer 343 of drain structure 340, and metal layer 14 may include source electrode 314 of source structure 310 and drain electrode 344 of drain structure 340.

[0120] Referring to Figure 18 and 19 illustrates an example of a FinFET, but Figure 18 and 19 the source structure 310 and drain structure 340 thereof may be applied to devices different from FinFETs, such as fully-depleted surround-gate FETs (GAAFETs) or multi-bridge-channel FETs (MBCFET™).

[0121] In addition, semiconductor devices according to some example embodiments may be applied to semiconductor devices of a vertical structure type in which a metal layer is bonded (coupled) to a side surface of a silicon semiconductor layer.

[0122] The semiconductor device or FET described above can be used in, for example, a driving integrated circuit for a display, a complementary metal oxide semiconductor (CMOS) inverter, a CMOS SRAM device, a CMOS NAND circuit, and / or various other electronic devices.

[0123] Figure 20 FIG. 4 is a schematic block diagram of a display driver integrated circuit (IC) (DDI) 500 and a display device 520 including the DDI 500 according to some example embodiments. Referring to Figure 20 , the DDI 500 may include a controller 502, a power circuit 504, a driver block 506, and a memory block 508. The controller 502 receives and decodes commands applied from a main processing unit (MPU) 522, and controls each block in the DDI 500 to perform operations according to the commands. The power circuit 504 generates a driving voltage in response to control from the controller 502. The driver block 506 drives a display panel 524 by using the driving voltage generated by the power circuit 504 in response to control from the controller 502. The display panel 524 may include, for example, a liquid crystal display panel, an organic light emitting device (OLED) panel, or a plasma display panel. The memory block 508 is a block for temporarily storing commands input to the controller 502 or control signals output from the controller 502, or for storing required data, and may include memories such as RAM, ROM, etc. The power circuit 504 and the driver block 506 may each include the semiconductor device or FET according to some example embodiments described above with reference to Figures 1 to 19 .

[0124] Figure 21 FIG. 5 is a circuit diagram of a CMOS inverter 600 according to some example embodiments. Referring to Figure 21 , the CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a PMOS transistor 620 and an NMOS transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 may include the semiconductor device or FET according to some example embodiments described above with reference to Figures 1 to 19 . For example, either or both of the PMOS transistor 620 and the NMOS transistor 630 may be or correspond to the FET according to one or more embodiments described with reference to Figures 1 to 19 .

[0125] Figure 22 FIG. 6 is a circuit diagram of a CMOS SRAM device 700 according to some example embodiments. Referring to Figure 22, The CMOS SRAM device 700 includes a pair of drive transistors 710. Each of the pair of transistors 710 includes a PMOS transistor 720 and an NMOS transistor 730 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 700 may further include a pair of transfer transistors 740. The source electrodes of the transfer transistors 740 may be cross-connected to a common node of the PMOS transistor 720 and the NMOS transistor 730 forming the drive transistors 710. The power supply terminal Vdd is connected to the source electrode of the PMOS transistor 720, and the ground terminal is connected to the source electrode of the NMOS transistor 730. The word line WL may be connected to the gate electrodes of the pair of transfer transistors 740, and the bit line BL and the inverted bit line may be respectively connected to the drain electrodes of the pair of transfer transistors 740. At least one of the drive transistors 710 and the transfer transistors 740 of the CMOS SRAM device 700 may include the semiconductor device or FET according to some example embodiments described above with reference to Figures 1 to 19 a semiconductor device or FET according to some example embodiments described above.

[0126] Figure 23 is a circuit diagram of a CMOS NAND circuit 800 according to some example embodiments. Referring to Figure 23 , the CMOS NAND circuit 800 may include a pair of CMOS transistors to which different input signals are transmitted. At least one CMOS transistor of the pair of CMOS transistors of the CMOS NAND circuit 800 may include the semiconductor device or FET according to some example embodiments described above with reference to Figures 1 to 19 a semiconductor device or FET according to some example embodiments described above.

[0127] Figure 24 is a block diagram of an electronic device 900 according to some example embodiments. Referring to Figure 24 , the electronic device 900 includes a memory 910 and a memory controller 920. The memory controller 920 may control the memory 910 in response to a request from a host 930 to read data from and / or write data to the memory 910. At least one of the memory 910 and the memory controller 920 may include the semiconductor device or FET according to some example embodiments described above with reference to Figures 1 to 19 a semiconductor device or FET according to some example embodiments described above.

[0128] Figure 25 is a block diagram of an electronic device 1000 according to some example embodiments. Referring to Figure 25 , the electronic device 1000 may be configured as a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic device 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and a wireless interface 1040 connected to each other via a bus 1050.

[0129] The controller 1010 may include at least one of a microprocessor, a digital signal processor, or a similar processing device. The I / O 1020 may include at least one of a keypad, a keyboard, and a display. The memory 1030 may be used to store commands executed by the controller 1010. For example, the memory 1030 may be used to store user data. The electronic device 1000 may use the wireless interface 1040 to send / receive data via a wireless communication network. The wireless interface 1040 may include an antenna and / or a wireless transceiver. In some example embodiments, the electronic device 1000 may be used for communication interface protocols of third-generation communication systems, such as one or more of the following: Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Extended Time Division Multiple Access (E-TDMA), and / or Wideband Code Division Multiple Access (WCDMA). The electronic device 1000 may include a semiconductor device or a FET according to some example embodiments as described above with reference to Figures 1 to 18 a semiconductor device or a FET according to some example embodiments.

[0130] A semiconductor device or a FET according to some example embodiments may exhibit excellent electrical properties in an ultra-small size structure, and may be applied to integrated circuit devices, and may achieve one or more of miniaturization, low power consumption, and high performance.

[0131] A semiconductor device according to some example embodiments includes a first silicide layer between a silicon semiconductor layer and a second silicide layer, and thus may promote crystallization of the second silicide layer with a reduced thickness and a low temperature. In this way, the contact resistance of the miniaturized semiconductor device is reduced to improve electrical characteristics, and the example embodiments may be applied to various semiconductor devices.

[0132] Any of the elements and / or functional blocks disclosed above may include or be implemented as processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuitry may include at least one of electronic components such as transistors, resistors, capacitors, etc. The processing circuitry may include electronic components such as logic gates, which include at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0133] It should be understood that the various example embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of a feature or aspect in an embodiment should typically be considered available for other similar features or aspects in other embodiments; example embodiments are not necessarily mutually exclusive. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Semiconductor devices, including: a semiconductor layer comprising silicon; a first silicide layer on the semiconductor layer; and a second silicide layer including titanium and having a crystalline structure on the first silicide layer, The first silicide layer includes a metal other than titanium, and the second silicide layer includes TiSi2 having a C54 crystal structure. 2 . The semiconductor device according to claim 1 , wherein the first silicide layer comprises at least one of hafnium silicide, zirconium silicide, nickel silicide, and cobalt silicide.

3. The semiconductor device of claim 1, wherein the first silicide layer has a thickness in the range of 3Å to 30Å.

4. The semiconductor device according to claim 1, wherein the first silicide layer has a crystalline structure.

5. The semiconductor device of claim 1, wherein the second silicide layer has a thickness of 5Å to 70Å.

6. The semiconductor device of claim 1, wherein the first silicide layer comprises at least one of ZrSi, ZrSi2, Zr5Si3 or Zr3Si2. 7 . The semiconductor device according to claim 1 , wherein the second silicide layer has a Schottky barrier height of 0.7 eV or less.

8. The semiconductor device according to claim 1, further comprising: A metal layer is on the second silicide layer.

9. The semiconductor device of claim 8, wherein the metal layer comprises at least one of magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pb), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), and bismuth (Bi).

10. The semiconductor device according to claim 8, wherein The semiconductor layer includes a channel layer, The metal layer includes a source electrode on one side surface of the channel layer and a drain electrode on the other side surface of the channel layer, The second silicide layer includes a 2-1 silicide layer between the source electrode and the channel layer and a 2-2 silicide layer between the drain electrode and the channel layer, and The first silicide layer includes a 1-1 silicide layer between the 2-1 silicide layer and the channel layer and a 1-2 silicide layer between the 2-2 silicide layer and the channel layer.

11. The semiconductor device of claim 1, wherein the semiconductor layer comprises at least one of a single crystal or a polycrystalline structure.

12. The semiconductor device according to claim 1, wherein the first silicide layer is undoped.

13. The semiconductor device according to claim 1, wherein the second silicide layer is undoped.

14. The semiconductor device according to claim 1, wherein the first silicide layer is in direct contact with the semiconductor layer.

15. The semiconductor device according to claim 1, wherein the first silicide layer is in direct contact with the second silicide layer. 16 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises a well region doped to a first conductivity type, and a source region and a drain region doped to a second conductivity type electrically opposite to the first conductivity type.

17. The semiconductor device according to claim 1, further comprising: a gate electrode; and a gate insulating layer on the gate electrode, The semiconductor layer includes a channel layer on the gate insulating layer.

18. The semiconductor device according to claim 1, wherein The semiconductor layer includes a channel layer, and The semiconductor device further comprises: a gate insulating layer on an upper surface of the channel layer, and A gate electrode is on the gate insulating layer.

19. A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor layer including silicon; forming a first silicide layer on the semiconductor layer; forming an amorphous second silicide layer including titanium on the first silicide layer; and crystallizing the amorphous second silicide layer to obtain a second silicide layer, The first silicide layer includes a metal other than titanium, and the second silicide layer includes TiSi2 having a C54 crystal structure.

20. The method of claim 19, wherein the first silicide layer comprises ZrSi, ZrSi2, Zr5Si3 or Zr3Si2.

21. The method of claim 19, wherein crystallizing the amorphous second silicide layer is performed at a temperature ranging from 200°C to 400°C.

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