Field effect transistor

Abstract

The invention discloses a field effect transistor, which comprises a drain electrode positioned on a bottom layer; the substrate is located on the drain electrode; the first conductive type semiconductor layer is located on the substrate; the gate electrode structure comprises a gate electrode and a gate insulating film, the gate electrode extends downwards from a first area of the upper surface of the first conductive type semiconductor layer, and the gate insulating film wraps the whole outer surface of the gate electrode; a Schottky source electrode located in a second region on the upper surface of the first conductive type semiconductor layer; the field plate structure comprises a field plate electrode and a dielectric layer, the field plate electrode is in contact with the lower surface of the Schottky source electrode and extends downwards, the dielectric layer wraps the remaining outer surface of the field plate electrode, and the work function of the material of the field plate electrode is larger than that of the material of the first conductive type semiconductor layer; an ohmic source electrode on the third region of the upper surface of the first conductive type semiconductor layer; the first and second regions of the upper surface of the first conductive type semiconductor layer are not connected. According to the invention, the conduction loss of the field effect transistor can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a field effect transistor. Background Art

[0002] The Schottky source-drain MOSFET structure was proposed in the 1960s. It uses metal source and drain to replace the semiconductor doped source and drain of the traditional pn-junction MOSFET, and a Schottky contact barrier is formed between the metal source and drain and the semiconductor. For the Schottky source-drain MOSFET, when a positive voltage is applied between the drain and source, the Schottky barrier formed between the source and the semiconductor material is reverse-biased, and the depletion layer is widened to achieve turn-off. Accordingly, the Schottky source-drain MOSFET is a normally-off device; the conduction of the Schottky source-drain MOSFET is achieved by forming a conductive channel under the action of a positive gate bias, and the carriers at the source end directly tunnel through the barrier into the channel.

[0003] Compared with the traditional pn-junction MOSFET, the Schottky source-drain MOSFET has four advantages: First, the metal Schottky contact has the characteristic of ultra-shallow junction, which can effectively suppress the short-channel effect and source-drain punch-through problems that plague the conventional MOSFET when the device size is greatly reduced, providing the possibility for the MOSFET to continue to reduce the size; Second, the high conductivity of the metal-semiconductor contact can further reduce the source-drain resistance; Third, in the Schottky source-drain MOSFET, there is no parasitic bipolar effect, the response speed is faster, and it can be more high-frequency; Fourth, there is no need for ion implantation to form the n+ or P+ source and drain regions, and the high-temperature annealing is also cancelled. The process is simple, and at the same time, the lattice damage problems caused by ion implantation and annealing are avoided, which helps to obtain a high interface quality, thereby obtaining a high-quality dielectric layer, and the breakdown voltage and reliability will also be better.

[0004] However, since the birth of the Schottky source-drain MOSFET, there have been two significant disadvantages: First, the on-state current is small. The on-state current of the conventional pn-junction MOSFET can reach the order of dozens of amperes to hundreds of amperes, while the on-state current of the Schottky source-drain MOSFET under the same conditions can only reach the order of milliamperes or even lower; Second, the off-state leakage current is large. The leakage current includes the thermionic emission current transmitted through the substrate from the source junction and the tunneling current from the source junction.

[0005] Other Schottky source-drain field effect transistors also have the same problems, including but not limited to MOSFET, IGBT, various types of thyristors, etc. Summary of the Invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a field effect transistor that can at least reduce the off-state leakage current of the Schottky source-drain field effect transistor to a certain extent.

[0007] To solve the above technical problems, the technical solution of the embodiment of the field effect transistor provided by the present invention is as follows:

[0008] A field effect transistor, comprising:

[0009] A drain electrode, located at the bottom layer of the field effect transistor;

[0010] A substrate, located above the drain electrode;

[0011] A first conductive type semiconductor layer, located above the substrate;

[0012] A gate electrode structure, including a gate electrode and a gate insulating film, the gate electrode extends downward from a first region on the upper surface of the first conductive type semiconductor layer, and the gate insulating film wraps around the entire outer surface of the gate electrode;

[0013] A Schottky source electrode, located in a second region on the upper surface of the first conductive type semiconductor layer, and forms a Schottky contact with the first conductive type semiconductor layer;

[0014] A field plate structure, including a field plate electrode and a dielectric layer, the field plate electrode contacts the lower surface of the Schottky source electrode and extends downward, the dielectric layer wraps around the remaining outer surface of the field plate electrode, and the work function of the field plate electrode material is greater than the work function of the first conductive type semiconductor layer material;

[0015] An ohmic source electrode, located above a third region on the upper surface of the first conductive type semiconductor layer, and forms an ohmic contact with the first conductive type semiconductor layer;

[0016] The first region and the second region on the upper surface of the first conductive type semiconductor layer are not connected.

[0017] Preferably, the material of the first conductive type semiconductor layer is n-type.

[0018] Preferably, the width range of the first conductive type semiconductor layer between the Schottky source electrode and the gate electrode is in the interval of 3 nm to 200 nm.

[0019] Preferably, the Schottky source electrode and the ohmic source electrode correspond to different metals or alloys.

[0020] Preferably, the gate electrode includes a shielding gate electrode located at the lower part and a groove gate electrode located at the upper part, and there is a dielectric layer between the groove gate electrode and the shielding gate electrode.

[0021] Preferably, the depth of the field plate structure extending into the first conductive type semiconductor layer does not exceed the depth of the gate electrode structure extending into the first conductive type semiconductor layer.

[0022] Preferably, the field-effect transistor is composed of field-effect transistor units configured with strip-shaped cells; or the field-effect transistor is composed of field-effect transistor units configured with closed cells.

[0023] Preferably, the field plate electrode material is metal, alloy or electrode material of the second conductivity type, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type.

[0024] Preferably, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, the conductivity type of the substrate is also the first conductivity type, and the field-effect transistor is a MSOFET.

[0025] Preferably, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, the conductivity type of the substrate is the second conductivity type, the first conductivity type is opposite to the second conductivity type, and the field-effect transistor is an IGBT.

[0026] Regarding the above-mentioned invention content, the present invention has the following beneficial effects:

[0027] (1) The field-effect transistor of the embodiment of the present invention adjusts the pure Schottky source to a combined design of an ohmic source and a Schottky source. While maintaining the normally-off design of the device, it can solve the problem of small on-state current of the Schottky source-drain field-effect transistor, improve the current-carrying capacity of the Schottky source-drain field-effect transistor, reduce the on-resistance of the channel region, and thus reduce the conduction loss of the device.

[0028] (2) The field-effect transistor of the embodiment of the present invention adds a field plate structure connected thereto below the first part of the source electrode. The introduction of the field plate structure can increase the lateral depletion effect on the carriers in the drift region. Thus, when the carrier concentration in the drift region is increased, due to the lateral depletion effect of the field plate structure, the breakdown voltage of the device can be maintained unchanged, and increasing the carrier concentration in the drift region can reduce the on-resistance of the drift region, thereby further reducing the conduction loss of the device. Description of the Drawings

[0029] Figure 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET;

[0030] Figure 2 is a vertical cross-sectional view of an embodiment of a MOSFET proposed by the applicant in the patent with Chinese patent application number 202310325051.0;

[0031] Figure 3 is a vertical cross-sectional view of a specific embodiment of the field-effect transistor of the present invention.

[0032] The technical features corresponding to the markings in the figure are as follows:

[0033] 11 Leakage electrode

[0034] 12a Ohmic source electrode

[0035] 12b Schottky source electrode

[0036] 12c Surface layer source electrode

[0037] 13 Gate electrode

[0038] 13a Grooved gate electrode

[0039] 13b Shielded gate electrode

[0040] 14 p-type polysilicon electrode

[0041] 21a n+-type semiconductor layer

[0042] 21b n--type semiconductor layer

[0043] 51a Gate insulating film

[0044] 51b Dielectric layer Detailed implementation manners

[0045] To more clearly illustrate the technical solutions of the present invention, the following will be briefly introduced through examples or descriptions of the prior art. Obviously, the following drawings are only illustrations of some embodiments of the present invention, and the scope of protection required by the present invention is not limited to the embodiments. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0046] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0047] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0048] Unless otherwise specified, all technical and scientific terms used in this application have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0049] In the present invention, unless otherwise specified, directional terms such as "upper, lower, left, right", etc. generally refer to the directions shown in the drawings, or to the directions of the components themselves in the vertical, perpendicular or gravitational aspects; similarly, for the convenience of understanding and description, "inner, outer" refer to the inner and outer of the contours of the respective components themselves, but the above directional terms are not used to limit the present invention.

[0050] It should be noted that the field effect transistor structure of the present invention is universal, including MOSFET, IGBT, various types of thyristors, etc. The technical solutions provided in the following when introducing the R & D background of the field effect transistor of the present invention are described with MOSFET as an example. It should be understood that these solutions can also be extended and applied to other types of field effect transistors, such as including IGBT, various types of thyristors, etc.

[0051] Figure 1 It is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET. This MOSFET has: a drain electrode 11; an n+-type semiconductor layer 21a; an n−-type semiconductor layer 21b; a gate trench extending into the n−-type semiconductor layer 21b; a gate electrode 13 located in the trench and wrapped by a gate insulating film 51a; a Schottky source electrode 12b forming a Schottky contact with the n−-type semiconductor layer 21b; and a surface source electrode 12c.

[0052] Figure 1 For the shown conventional Schottky source-drain MOSFET, due to the existence of the Schottky junction formed between the Schottky source electrode 12b and the n−-type semiconductor layer 21b, when a positive voltage is applied only between the drain electrode 11 and the surface source electrode 12c, the Schottky junction is reverse-biased, causing the depletion region to widen, so that a complete electron conduction channel cannot be formed between the drain electrode 11 and the surface source electrode 12c, and no current passes between the drain and source. Based on this principle, Figure 2 the shown Schottky junction type MOSFET is a normally-off device; when a positive voltage is applied between the gate electrode 13 and the source electrode 12c, due to the existence of the Schottky barrier between the Schottky source electrode 12b and the n−-type semiconductor layer 21b, a complete and high-concentration electron conduction channel cannot be formed between the drain electrode 11 and the surface source electrode 12c. At this time, even when a positive voltage is applied between the drain electrode 11 and the surface source electrode 12c, due to the widening of the reverse-biased depletion layer formed by the Schottky barrier between the Schottky source electrode 12b and the n−-type semiconductor layer 21b, this inhibits the transport of electron carriers, so that only a small part of the electron carriers form a current through the tunneling effect between the drain electrode 11 and the Schottky source electrode 12b. This results in very poor on-state current-carrying capacity of the conventional Schottky junction type MOSFET and cannot meet the application requirements for currents above the ampere level.

[0053] Therefore, the applicant of this application has conducted research and development, and proposed a shielded-gate MOSFET with a large on-state current-carrying capacity in the patent application document with Chinese Application No. 202310325051.0. Figure 2 FIG. Figure 2 is a vertical cross-sectional view of an embodiment of the MOSFET in the patent application document with Chinese Application No. 202310325051.0. This MOSFET has: a drain electrode 11, located at the bottom layer of the field-effect transistor; an n+-type semiconductor layer 21a, located above the drain electrode 11; an n−-type semiconductor layer 21b, located above the n+-type semiconductor layer 21a; a gate electrode, extending downward from the upper surface of the n−-type semiconductor layer 21b. Further, the gate electrode includes a shielded-gate electrode 13a located at the lower part and a grooved gate electrode 13b located at the upper part, and there is a dielectric between the grooved gate electrode and the shielded-gate electrode; a gate insulating film 51a, wrapped around the outer surface of the gate electrode; a Schottky source electrode 12b, recessed into the n−-type semiconductor layer 21b and forming a Schottky contact with the n−-type semiconductor layer 21b; an ohmic source electrode 12a, located above the n−-type semiconductor layer 21b and forming an ohmic contact with the n−-type semiconductor layer 21b; a surface source electrode 12c, located at the top layer of the field-effect transistor and having the same potential as the shielded-gate electrode 13a.

[0054] It should be noted that when this application was submitted, the patent application document with Chinese Application No. 202310325051.0 had not been published. The content disclosed in this patent document and the content introduced in this application about this patent application document cannot be used to evaluate the novelty and inventiveness of this application.

[0055] Figure 2 For the MOSFET shown, the source electrode is designed and optimized, and the pure Schottky source electrode 12b in the traditional Schottky source-drain MOSFET is adjusted to a combined design of an ohmic source electrode 12a and a Schottky source electrode 12b. When the voltage V applied between the gate electrode 13 and the surface source electrode 12c GS is greater than the threshold voltage V GS(th) , in the region of the n−-type semiconductor layer 21b adjacent to the gate insulating film 51a, electron carriers will accumulate to form a high-concentration electron channel. Since there is no potential barrier between the ohmic source electrode 12a and the n−-type semiconductor layer 21b, when a positive voltage is applied between the drain electrode 11 and the surface source electrode 12c at this time, a complete and high-concentration electron channel will be formed between the drain electrode 11 and the surface source electrode 12c, and current will flow between the drain electrode 11 and the surface source electrode 12c; when the voltage V applied between the gate electrode 13 and the surface source electrode 12c GSWhen VGS = 0, the Schottky barrier formed by the Schottky source electrode 12b and the n-type semiconductor layer 21b will have a longitudinal and transverse depletion effect on electron carriers. In addition, when there is a work function difference between the material of the gate electrode 13 and the material of the n-type semiconductor layer 21b (that is, the work function of the material of the gate electrode 13 is greater than the work function of the material of the n-type semiconductor layer 21b), the gate electrode 13 will also have a transverse depletion effect on the electron carriers in the n-type semiconductor layer 21b. Thus, under the combined action of the Schottky source electrode 12b and the gate electrode 13, the electron carriers in the n-type semiconductor layer 21b located between the Schottky source electrode 12b and the gate electrode 13 can be completely depleted, which blocks the electron conduction channel between the drain electrode 11 and the surface source electrode 12c. Therefore Figure 2 the MOSFET shown in Figure 2 can be a normally-off device, and can be a normally-off device with a large on-state current-carrying capacity. Figure 2 Compared with Figure 1 optimizing the gate electrode 13 into a combination of a lower shielding gate electrode 13a and an upper groove gate electrode 13b aims to introduce the shielding gate electrode 13a. When the device is in the off state, the shielding gate electrode 13a has a transverse depletion effect on the carriers in the n-type semiconductor layer 21b. Thus, the off-state leakage of the device can be reduced and the breakdown voltage of the device can be increased.

[0056] In summary, the patent application with the application number 202310325051.0 adjusts the pure Schottky source electrode in the Schottky source-drain MOSFET to a combined design of an ohmic source electrode and a Schottky source electrode. While maintaining the normally-off design of the device, it can solve the problem of small on-state current in the Schottky source-drain MOSFET, improve the current-carrying capacity of the Schottky source-drain MOSFET, and reduce the on-resistance. However, in this patent application, the on-resistance is reduced by reducing the resistance of the channel region, and the optimization of the on-resistance of the drift region is not mentioned. In power devices with high breakdown voltage requirements, the on-resistance of the drift region has a greater impact on the conduction loss. Therefore, seeking to reduce the on-resistance of the drift region is the key to further reducing the conduction loss of the device.

[0057] The applicant of this application further studied and proposed an embodiment of the field-effect transistor structure of this application, including:

[0058] A drain electrode, located at the bottom layer of the field-effect transistor;

[0059] A substrate, located above the drain electrode;

[0060] A first-conductivity-type semiconductor layer, located above the substrate;

[0061] A gate electrode structure, including a gate electrode and a gate insulating film. The gate electrode extends downward from a first region on the upper surface of the first-conductivity-type semiconductor layer, and the gate insulating film wraps around the entire outer surface of the gate electrode;

[0062] The Schottky source electrode is located above the second region on the upper surface of the first-conductivity-type semiconductor layer and forms a Schottky contact with the first-conductivity-type semiconductor layer;

[0063] The field plate structure includes a field plate electrode and a dielectric layer. The field plate electrode contacts the lower surface of the Schottky source electrode and extends downward, and the dielectric layer wraps around the remaining outer surface of the field plate electrode. The work function of the field plate electrode material is greater than that of the first-conductivity-type semiconductor layer material;

[0064] The ohmic source electrode is located above the third region on the upper surface of the first-conductivity-type semiconductor layer and forms an ohmic contact with the first-conductivity-type semiconductor layer;

[0065] The first region and the second region on the upper surface of the first-conductivity-type semiconductor layer are not connected.

[0066] The above field effect transistor structure has the following beneficial effects:

[0067] (1) Adjust the pure Schottky source to a combined design of an ohmic source and a Schottky source. While maintaining the normally-off design of the device, it can solve the problem of small on-state current of the Schottky source-drain field effect transistor, improve the current-carrying capacity of the Schottky source-drain field effect transistor, reduce the on-resistance of the channel region, and thus reduce the conduction loss of the device;

[0068] (2) Add a connected field plate structure below the first part of the source electrode. The introduction of the field plate structure can increase the lateral depletion effect on the carriers in the drift region. In this way, when the carrier concentration in the drift region is increased, due to the lateral depletion effect of the field plate structure, the breakdown voltage of the device can be maintained unchanged, and increasing the carrier concentration in the drift region can reduce the on-resistance of the drift region, thereby further reducing the conduction loss of the device.

[0069] The material of the first-conductivity-type semiconductor layer is n-type.

[0070] Preferably, the width range of the first-conductivity-type semiconductor layer between the Schottky source electrode and the gate electrode is in the interval of 3 nm to 200 nm. In this way, it can ensure that the device realizes the normally-off function and has small off-state leakage current.

[0071] Preferably, the Schottky source electrode and the ohmic source electrode correspond to different metals or alloys. For example, when the first-conductivity-type semiconductor layer is a lightly doped single-crystalline silicon layer, the material of the Schottky source electrode is Pt, so as to form a higher Schottky barrier contact with the single-crystalline silicon layer, which can reduce the off-state leakage current of the device; the material of the ohmic source electrode can be Ti or TiN, so as to form a good ohmic contact with the single-crystalline silicon layer, which can reduce the on-state loss of the device.

[0072] Preferably, the gate electrode includes a lower shielding gate electrode and an upper grooved gate electrode, and there is a dielectric layer between the grooved gate electrode and the shielding gate electrode. The purpose is to make the Schottky barrier formed by the Schottky source electrode and the first-conductivity-type semiconductor layer reverse-biased when the field-effect transistor device is in the off state, which will form a longitudinal depletion effect on the carriers in the first-conductivity-type semiconductor layer. The introduction of the shielding gate electrode will simultaneously form a lateral depletion effect on the carriers in the first-conductivity-type semiconductor layer. In this way, the off-state leakage is reduced and the breakdown voltage of the device is increased.

[0073] Preferably, the depth to which the field plate structure extends into the first-conductivity-type semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first-conductivity-type semiconductor layer. The reason is that the field plate structure and the Schottky source electrode are at the same potential. When the device is in the off state, both the Schottky source electrode and the field plate structure will have a lateral depletion effect on the carriers in the first n-type conductivity semiconductor layer. If the depth to which the field plate structure extends into the first-conductivity-type semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first-conductivity-type semiconductor layer, under the action of a positive gate bias, the depth of the accumulation channel formed in the first-conductivity-type semiconductor layer controlled by the gate electrode will not be sufficient to cover the depth to which the field plate structure extends into the first-conductivity-type semiconductor layer. In this case, the device may not be able to achieve good turn-on.

[0074] Preferably, the field-effect transistor is composed of field-effect transistor units configured in strip cells; or the field-effect transistor is composed of field-effect transistor units configured in closed cells.

[0075] Preferably, the field plate electrode material is metal, alloy or the electrode material of the second conductivity type. The conductivity type of the first-conductivity-type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type. For example, when the conductivity type of the first-conductivity-type semiconductor layer is n-type conductivity, the electrode material of the second conductivity type is p-type conductivity. When the device is in the off state, the lateral depletion effect of the p-type field plate electrode on the carriers in the first-conductivity-type semiconductor layer can reduce the off-state leakage.

[0076] Preferably, the conductivity type of the first-conductivity-type semiconductor layer is the first conductivity type, and the conductivity type of the substrate is also the first conductivity type, and the field-effect transistor is a MSOFET.

[0077] Preferably, the conductivity type of the first-conductivity-type semiconductor layer is the first conductivity type, and the conductivity type of the substrate is the second conductivity type, and the first conductivity type is opposite to the second conductivity type, and the field-effect transistor is an IGBT.

[0078] Figure 3 is a vertical cross-sectional view of a specific embodiment of the field-effect transistor of the present invention. Figure 3 What is shown is also a shielded-gate MOSFET, which includes:

[0079] A drain electrode 11, located at the bottom layer of the field effect transistor;

[0080] A substrate, located above the drain electrode, i.e., Figure 3 the n+-type semiconductor layer 21a in

[0081] A first-conductivity-type semiconductor layer, located above the substrate 21a, i.e., Figure 3 the n--type semiconductor layer 21b in

[0082] A gate electrode structure, including a gate electrode and a gate insulating film. The gate electrode extends downward from a first region on the upper surface of the first-conductivity-type semiconductor layer, and the gate insulating film 51a wraps around the entire outer surface of the gate electrode. Please refer to Figure 3 , specifically, the gate electrode includes: a shielding gate electrode 13b located at the lower part and a groove gate electrode 13a located at the upper part. There is a dielectric layer between the groove gate electrode 13a and the shielding gate electrode 13b;

[0083] A Schottky source electrode 12b, located above a second region on the upper surface of the first-conductivity-type semiconductor layer, and forming a Schottky contact with the first-conductivity-type semiconductor layer;

[0084] A field plate structure, including a field plate electrode and a dielectric layer 51b. The field plate electrode is Figure 3 the p-type polysilicon electrode 14 in . The field plate electrode contacts the lower surface of the Schottky source electrode and extends downward. The dielectric layer 51b wraps around the remaining outer surface of the field plate electrode. The work function of the field plate electrode material is greater than the work function of the first-conductivity-type semiconductor layer material;

[0085] An ohmic source electrode 12a, located above a third region on the upper surface of the first-conductivity-type semiconductor layer, and forming an ohmic contact with the first-conductivity-type semiconductor layer;

[0086] The first region and the second region on the upper surface of the first-conductivity-type semiconductor layer are not connected.

[0087] The above Figure 3 The MOSFET field effect transistor in Figure 2 is further improved based on the structure shown in . Specifically, a field plate structure connected thereto is added below the Schottky source electrode 12b. The field plate structure includes a p-type polysilicon electrode 14 and a dielectric layer 51b surrounding the p-type polysilicon electrode 14, and the work function of the p-type polysilicon electrode 14 is greater than the work function of the corresponding material of the semiconductor layer of the n--type semiconductor layer 21b.

[0088] Figure 3The p-type polysilicon electrode 14, the dielectric layer 51b, and the n-type semiconductor layer 21b in contact with the dielectric layer 51b can form a MIS junction (i.e., an electrode-insulator-semiconductor junction). Since the work function of the p-type polysilicon electrode 14 is greater than that of the n-type semiconductor layer 21b, a lateral depletion effect on the electron carriers in the region of the dielectric layer 51b adjacent to the n-type semiconductor layer 21b will occur. Compared with Figure 2 the MSOFET shown, Figure 3 due to the introduction of the field plate structure connected to the Schottky source electrode 12b in the MOSFET shown, the lateral depletion of the carriers in the n-type semiconductor layer 21b is strengthened. Thus, when achieving the same breakdown voltage capability, Figure 3 in the MOSFET shown, the doping concentration of its n-type semiconductor layer 21b can be relatively higher, and the higher doping concentration helps to reduce the on-resistance of the drift region, thereby reducing the conduction loss of the device.

[0089] Regarding Figure 3 the MOSFET field-effect transistor in, further, to reduce the off-state leakage current, the width range of the n-type semiconductor layer 21b between the Schottky source electrode 12b and the gate insulating film 51a is set in the interval of 30 nm to 120 nm.

[0090] Regarding Figure 3 the MOSFET field-effect transistor in, further, the electrode material of the field plate structure can also be a metal or an alloy, and the work function of the metal or alloy should be greater than that of the n-type semiconductor layer 21b.

[0091] Figure 3 In the MOSFET field-effect transistor in, when a positive voltage V GS is applied between the gate electrode 13 and the surface source electrode 12c, electrons will gradually accumulate in the region of the n-type semiconductor layer 21b adjacent to the gate insulating film 51a. When the voltage applied to the gate electrode 13 is greater than the threshold voltage, a high-concentration electron accumulation channel will be formed in the region of the n-type semiconductor layer 21b adjacent to the gate insulating film 51a. Since this channel is formed in the n-type semiconductor layer 21b, it is equivalent to accumulating electrons to form an accumulation-type electron channel. Therefore, the MOSFET of the present invention is an accumulation-type channel field-effect transistor.

[0092] In the embodiment shown in the appendix Figure 3 , the substrate corresponds to the n+-type semiconductor layer 21a, and the formed device is an accumulation-type MOSFET; when the substrate uses a p-type conductive semiconductor layer, that is, when the n+-type semiconductor layer 21a is replaced with a p-type conductive semiconductor layer, an accumulation-type IGBT can be formed.

[0093] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention and should all be included in the protection scope of the present invention.

Claims

1. A field effect transistor, characterized in that, Comprising: A drain electrode, located at the bottom layer of the field effect transistor; A substrate, located above the drain electrode; A first conductivity type semiconductor layer, located above the substrate; A gate electrode structure, including a gate electrode and a gate insulating film, the gate electrode extending downward from a first region on the upper surface of the first conductivity type semiconductor layer, and the gate insulating film wrapping around the entire outer surface of the gate electrode; A Schottky source electrode, located in a second region on the upper surface of the first conductivity type semiconductor layer, and forming a Schottky contact with the first conductivity type semiconductor layer; A field plate structure, including a field plate electrode and a dielectric layer, the field plate electrode contacting and extending downward from the lower surface of the Schottky source electrode, the dielectric layer wrapping around the remaining outer surface of the field plate electrode, and the work function of the field plate electrode material being greater than the work function of the first conductivity type semiconductor layer material; An ohmic source electrode, located above a third region on the upper surface of the first conductivity type semiconductor layer, and forming an ohmic contact with the first conductivity type semiconductor layer; The first region and the second region on the upper surface of the first conductivity type semiconductor layer are not connected.

2. The field effect transistor according to claim 1, wherein: The material of the first conductivity type semiconductor layer is n-type.

3. The field effect transistor according to claim 1, characterized in that: The width range of the first conductivity type semiconductor layer between the Schottky source electrode and the gate electrode is in the interval of 3nm to 200nm.

4. The field effect transistor according to claim 1, characterized in that: The Schottky source electrode and the ohmic source electrode correspond to different metals or alloys.

5. The field effect transistor according to claim 1, wherein: The gate electrode includes: a shielding gate electrode located at the lower part and a groove gate electrode located at the upper part, and there is a dielectric layer between the groove gate electrode and the shielding gate electrode.

6. The field effect transistor according to claim 1, characterized in that: The depth to which the field plate structure extends into the first conductivity type semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first conductivity type semiconductor layer.

7. The field effect transistor according to claim 1, wherein: The field effect transistor is composed of field effect transistor units configured in a strip cell; or the field effect transistor is composed of field effect transistor units configured in a closed cell.

8. The field effect transistor according to claim 1, characterized in that: The field plate electrode material is a metal, an alloy or an electrode material of a second conductivity type, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type.

9. The field effect transistor according to claim 1, wherein: The conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the conductivity type of the substrate is also the first conductivity type, and the field effect transistor is a MSOFET.

10. The field effect transistor according to claim 1, characterized in that: The conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the conductivity type of the substrate is the second conductivity type, and the first conductivity type is opposite to the second conductivity type, and the field effect transistor is an IGBT.

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