950V super-junction MOS device with deep groove filling structure and manufacturing method of 950V super-junction MOS device

Abstract

The invention discloses a 950V super-junction MOS device with a deep groove filling structure and a manufacturing method of the 950V super-junction MOS device. The 950V super-junction MOS device is provided with polycrystalline silicon deposition with a discontinuous structure and additionally provided with an independent gate source ESD protection area, the whole device is subjected to secondary epitaxy through an N-type substrate, and a plurality of functional layers are expanded according to the optimal condition. According to the invention, charge imbalance caused by unequal groove width due to an etching angle is relieved through the N-type substrate which is subjected to two times of epitaxy; polycrystalline silicon of cells is separated through etching, one half of the polycrystalline silicon is connected with gate metal, the other half of the polycrystalline silicon is connected with source metal, a Dummy structure is formed, the ratio of true cells to false cells is 1: 1, the problem that input capacitance is too large is effectively solved, and the dynamic characteristic of a device is effectively optimized on the premise that voltage resistance and dynamic on resistance are not affected; by arranging ESD protection between the gate electrode and the source electrode, the device is prevented from being damaged under the condition of transient high voltage and large current.

Description

Technical Field

[0001] The present invention relates to the field of electronic science and technology, and more specifically, to a 950V superjunction MOS device with a deep trench filling structure and a manufacturing method thereof. Background Art

[0002] Power devices with a 950V voltage level are widely used in fields such as industrial frequency conversion drives, solar inverters, and uninterruptible power supplies (UPS). Due to the limitations of its physical structure, there is a difficult-to-break 2.5-power relationship between the on-resistance and the breakdown voltage in traditional power MOSFETs. That is, as the breakdown voltage increases, the on-resistance will increase sharply, resulting in an increase in the on-state loss of the device and a decrease in efficiency. To alleviate this contradiction to a certain extent, the superjunction (SuperJunction) structure has been developed. Its principle is to introduce alternating P-type and N-type columnar structures in the drift region to achieve an optimized distribution of the electric field, thereby reducing the on-resistance while increasing the breakdown voltage. The manufacturing of the superjunction structure is mainly divided into two types: multiple epitaxial processes and deep trench filling processes. Most of the 950V superjunction MOSs on the market currently use multiple epitaxial processes, and the number of epitaxial times is between 6 and 7.

[0003] For the convenience of explanation in combination with the accompanying drawings of the specification Figure 3 for illustration, Figure 3 is a schematic cross-sectional view of the structure of a conventional deep trench filling high-voltage superjunction MOS device, including an N+ substrate 301, a first N-type epitaxy 302, a JFET implantation region 303, a deep trench filling P-column region 304, a Pbody implantation region 305, a gate oxide layer 306, a polysilicon deposition 307, an N+ source implantation region 308, a dielectric layer 309, a front metal electrode 310, and a back metal electrode 311, where the polysilicon deposition 307 is a continuous integral structure. In high voltage levels above 950V for deep trench filling, there will be some problems. For example, due to the high voltage level of 950V, the thickness of the epitaxial wafer basically reaches about 75 µm, and the depth of the P-column formed by deep trench etching also reaches 65 µm. Such a deep P-column trench etching will surely cause a huge width difference between the surface and the bottom of the trench due to the etching angle, resulting in the inability to precisely control the doping concentration and size of the columnar bodies of different conductive types in the superjunction structure, which will lead to the inability to continue increasing the breakdown voltage of the device and it is also difficult to achieve an ideal balance with the on-resistance. In addition, the existing manufacturing process may introduce more defects, affecting the reliability and stability of the device. At the same time, due to the limitation of the cell size under 950V withstand voltage, the loss during the switching process is still large, restricting its performance in high-frequency applications. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a 950V superjunction MOS device with a deep trench filling structure and a manufacturing method thereof, so as to solve one or more of the above problems.

[0005] To achieve the above purpose, the present invention provides the following technical solutions: A 950V superjunction MOS device with a deep trench filling structure includes an N+ substrate. On the front side of the N+ substrate, a continuous first N-type epitaxy and a second N-type epitaxy are successively provided. A recessed JFET implantation region is provided on the second N-type epitaxy. Deep trench filling P-column regions are respectively provided on both sides of the first N-type epitaxy and the second N-type epitaxy. A Pbody implantation region is provided on the surface of the deep trench filling P-column region. A gate oxide layer is provided on the surfaces of the Pbody implantation region and the second N-type epitaxy. A polysilicon deposition is provided on the gate oxide layer, and the polysilicon deposition is a discontinuous structure. A recessed N+ source implantation region is also provided on the gate oxide layer. The N+ source implantation region contacts the Pbody implantation region. A dielectric layer is also provided on the gate oxide layer. The dielectric layer covers the polysilicon deposition and contacts the N+ source implantation region and the JFET implantation region; A back metal electrode is provided on the back side of the N+ substrate, and a front metal electrode is provided on the front side of the gate oxide layer. The front metal electrode covers the dielectric layer and contacts the N+ source implantation region.

[0006] Further, a gate-source ESD protection region is provided on the gate oxide layer. The peripheral edge at the top of the gate-source ESD protection region is the source metal, and the center at the top of the gate-source ESD protection region is the gate metal. The source metal corresponds to the front metal electrode. An ESD diode string N-type region is provided in the gate-source ESD protection region, and the back metal electrode corresponds to the drain metal.

[0007] Further, the other parts of the gate-source ESD protection region except the ESD diode string N-type region are all P-type regions, and the ESD diode string N-type region is coplanar with the N+ source implantation region.

[0008] Further, the JFET implantation region on the second N-type epitaxy is an N-type region, and the polysilicon deposition is in the active region.

[0009] A manufacturing method of a 950V superjunction MOS device with a deep trench filling structure is as follows: S1. Prepare an N+ substrate, and successively grow a first N-type epitaxy and a second N-type epitaxy on the N+ substrate; S2. Grow a thin pre-oxide layer on the second N-type epitaxy, perform N-type JFET implantation to form a JFET implantation region, and remove the thin pre-oxide layer; S3. Perform deep trench etching and P-type epitaxial filling on the first N-type epitaxy and the second N-type epitaxy to form P-columns, grow a sacrificial oxide layer on the surface and remove all of it to keep the surface flat; S4. Grow a thin pre-oxide layer on the flat surface, and perform P-type body region implantation with high dose and low energy. Then, perform high-temperature drive-in diffusion to form the Pbody implantation region. S5. Thermally deposit a field oxide layer on the surface, and perform active region etching. Grow a gate oxide layer in the active region, deposit gate polysilicon to form polysilicon deposition, and etch and separate the gates. Deposit an oxide layer. After deposition, perform blanket implantation and etching to form the gate PAD region ESD polysilicon, thereby forming the ESD protection of the device. S6. Etch the oxide layer, and implant to form the N+ source region implantation. Activate the source and the ESD protection region. Deposit and reflow the ILD, open holes and complete metal deposition and etching. Deposit and etch the surface dielectric and organic matter to form the front metal electrode, and metallize the back of the N+ substrate to form the back metal electrode.

[0010] Further, the resistivity of the first N-type epitaxy and the second N-type epitaxy in step S1 is different. The thickness of the thin pre-oxide layer in step S2 is 200 Å, and the implantation condition of the JFET implantation region is 2e12 cm -2 / 60 keV.

[0011] Further, the deep trench etching method in step S3 is wet etching. The trench depth of the etching region is 65 μm, the trench width is 5 μm, the etching angle is 88.8°, and the P-type epitaxial filling concentration is 4.2e15 cm -2 。

[0012] Further, the thickness of the thin pre-oxide layer in step S4 is 200 Å, and the implantation condition of the P-type body region is 6e13 cm -2 / 60 keV, and the annealing condition is 1100 °C with an annealing time of 180 min.

[0013] Further, the ambient temperature of the surface thermal deposition in step S5 is 980 °C, and the thickness of the field oxide layer is 8000 Å; the growth temperature of the gate oxide layer is 1050 °C, the growth thickness is 1000 Å, and the growth time is 90 min; the autodoping concentration of the polysilicon deposition is 4.3e20 cm -3 , and the thickness is 4000 Å; etch 1.6 μm of the polysilicon gate region in the middle of each cell in the gate region for Dummy design; the thickness of the oxide layer deposited before blanket implantation is 2000 Å to facilitate isolation of the gate PAD region ESD polysilicon; the thickness of the gate PAD region ESD polysilicon is 6000 Å, and the blanket implantation condition is 1e14 cm -2 / 80 keV.

[0014] Further, the remaining thickness of the oxide layer after etching in step S6 is 200 Å; the implantation activation conditions for the source region and the ESD protection region are 5e15 cm of arsenic ions -2 / 50 keV, the annealing temperature is 950 °C, and the annealing time is 30 min; the thickness of the ILD interlayer dielectric is 11200 Å, the temperature of the dense reflow is 900 °C, and the time of the dense reflow is 30 min; the size of the opening before metal deposition and etching is 3 μm, and the pore injection condition is 1.25e15 cm of boron difluoride -2 / 40 keV, 3.5e15 cm of boron -2 / 80 keV, and rapid annealing is carried out for 15 s; deposit 4-μm aluminum-copper alloy front and back metal electrodes.

[0015] In summary, the present invention has the following beneficial effects: The top groove width of the entire superjunction structure is 5 μm, the depth is 65 μm, and the etching angle is 88.8°. Due to the high voltage level, the groove depth is large, and due to the existence of the etching angle, the groove width of the lower part will be narrower. It is difficult to ensure the breakdown voltage with a single outer edge, and double epitaxy must be carried out to alleviate this situation. The charge imbalance caused by the unequal groove widths due to the etching angle is alleviated by the N-type substrate with two epitaxies; By etching the polysilicon of the separated cells, half is connected to the gate metal and the other half is connected to the source metal to form a Dummy structure, and the ratio of true to false cells is 1:1, effectively solving the problem of excessive input capacitance and effectively optimizing the dynamic characteristics of the device without affecting the breakdown voltage and dynamic on-resistance; By setting the ESD protection between the gate and source electrodes, the device is prevented from being damaged under transient high voltage and large current conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic cross-sectional view of a structure of an embodiment provided by the present invention; Figure 2 It is a top view schematic diagram of the gate-source ESD protection area in an embodiment provided by the present invention; Figure 3 It is a schematic cross-sectional view of the structure of a conventional deep trench filled high-voltage superjunction MOS device provided by the present invention; Figure 4 It is an I-V comparison curve graph provided by the present invention and the prior art; Figure 5 It is a Ciss-V comparison curve graph provided by the present invention and the prior art; Figure 6 It is a structure diagram of the implementation of step S1 of the manufacturing method of an embodiment provided by the present invention; Figure 7 It is a structure diagram of the implementation of step S2 of the manufacturing method of an embodiment provided by the present invention; Figure 8 It is a structure diagram of the implementation of step S3 of the manufacturing method of an embodiment provided by the present invention; Figure 9 Structural diagram of the implementation of step S4 in the manufacturing method of an embodiment provided by the present invention; Figure 10 Structural diagram of the implementation of step S5 in the manufacturing method of an embodiment provided by the present invention; Figure 11 Structural diagram of the implementation of step S6 in the manufacturing method of an embodiment provided by the present invention.

[0017] In the figure: 101, N+ substrate; 102, primary N-type epitaxy; 103, secondary N-type epitaxy; 104, JFET implantation region; 105, deep trench filled P pillar region; 106, Pbody implantation region; 107, gate oxide layer; 108, polysilicon deposition; 109, N+ source implantation region; 110, dielectric layer; 111, front metal electrode; 112, back metal electrode; 201, gate PAD region ESD polysilicon; 202, ESD diode string N-type region; 203, source metal; 204, gate metal; 301, N+ substrate; 302, primary N-type epitaxy; 303, JFET implantation region; 304, deep trench filled P pillar region; 305, Pbody implantation region; 306, gate oxide layer; 307, polysilicon deposition; 308, N+ source implantation region; 309, dielectric layer; 310, front metal electrode; 311, back metal electrode. Specific implementation manner

[0018] Example: The following is a further detailed description of the present invention in conjunction with the attached Figure 1-11 drawings.

[0019] A manufacturing method of a 950V superjunction MOS device with a deep trench filling structure mainly includes six steps: S1. Prepare an N-type doped substrate, form an N+ substrate 101, clean the original wafer and grow the first layer of N-type epitaxial layer and the second layer of N-type epitaxial layer to form a primary N-type epitaxy 102 and a secondary N-type epitaxy 103; the primary N-type epitaxy 102 and the secondary N-type epitaxy 103 are designed as two epitaxial layers with different resistivities, and the resistivity of the primary N-type epitaxy 102 is higher than that of the secondary N-type epitaxy 103. Since there is an etching angle in the subsequent deep trench etching based on the two epitaxial layers, the trench width is narrower in the deeper area, and the total charge of the corresponding P pillar is lower, so the resistivity of the primary N-type epitaxy 102 is slightly higher. Relatively, the resistivity of the secondary N-type epitaxy 103 is lower because the total charge of the P pillar in the upper half of the etching area where it is located is higher, obtaining a device with the structure as shown in Figure 6 the figure.

[0020] Among them, an arsenic-doped N-type substrate wafer with a resistivity of 0.002 - 0.003 Ω·cm is preferably selected, and the first N-type epitaxial layer 102 is grown at a temperature of 1000 °C. The doping element of the first N-type epitaxial layer 102 is phosphorus, with a thickness of 42 μm and a resistivity of 3.4 Ω·cm. Then, the second N-type epitaxial layer is grown at a temperature of 1000 °C. The doping element of the second N-type epitaxial layer 103 is phosphorus, with a thickness of 33 μm and a resistivity of 2.0 Ω·cm.

[0021] S2. On the basis of the second N-type epitaxial layer 103, a thin pre-oxide layer with a thickness of 200 Å is grown, and the N-type JFET injection region 104 is defined by photolithography. High-energy injection of N-type impurities is carried out to form the JFET injection region 104 of the N-type planar gate mos. The injection angle is 7°, the injection energy is 60 keV, and the injection dose is 2e12 cm -2 , and after the injection is completed, the surface oxide layer is removed to obtain a device with the structure as shown in Figure 7 the figure.

[0022] S3. Continue to carry out deep trench etching on the chip by wet etching. The etching angle is 88.8°, the etching depth is 65 μm, and the etching width is 5 μm. After the etching is completed, P-column epitaxial filling is carried out to form the deep trench filled P-column region 105. The impurity for epitaxial filling is boron, the filling thickness is 65 μm, and the filling concentration is 4.2e15 cm -2 . The trench depth, trench width, and the concentration of the P-column directly affect the breakdown voltage performance of the superjunction mosfet.

[0023] Continue to grow a sacrificial oxide layer on the surface. The growth temperature is 900 °C, and the thickness of the sacrificial oxide layer is 1265 Å. The oxide layer is completely removed by CMP process to keep the surface flat, and a device with the structure as shown in Figure 8 the figure is obtained.

[0024] S4. Continue to grow a thin pre-oxide layer with a thickness of about 200 Å on the flat surface. The growth temperature is 950 °C, and high-dose and low-energy P-type body region injection is carried out. The injected impurity is boron, the injection angle is 7°, the injection dose is 6e13 cm -2 , the injection energy is 60 keV, and high-temperature drive-in is carried out to form the Pbody injection region 106. The drive-in temperature is 1100 °C, and the drive-in time is 180 min. This is actually the active region as a whole, and a device with the structure as shown in Figure 9 the figure is obtained.

[0025] S5. After the drive-in injection in the active region is completed, a field oxide layer is thermally deposited on the chip surface. The thermal deposition temperature is 980 °C, and the thickness of the field oxide layer is 8000 Å, and active region etching is carried out.

[0026] Grow the gate oxide layer 107 in the active region at a growth temperature of 1050 °C, a growth thickness of 1000 Å, and a growth time of 90 min; deposit gate polysilicon to form polysilicon deposition 108, and the autodoping concentration of the polysilicon deposition 108 is 4.3e20 cm -3 , with a thickness of 4000 Å; Etch the polysilicon gate region in the middle of each cell in the gate region by 1.6 μm for Dummy design. Half of the polysilicon of a single cell is connected to the source, and half is connected to the gate. The number of true and false cells in the Dummy structure is 1:1. The breakdown voltage of the device remains unchanged, and the resistance increases slightly. The increased value of the resistance is the resistance value of the accumulation layer in the JFET region, but the input capacitance and reverse transfer capacitance can be reduced to half of the original; Etch and separate the gate; As Figure 2 shown, deposit an oxide layer with a thickness of 2000 Å. The purpose of this operation is to facilitate the isolation of the gate PAD area ESD polysilicon 201; deposit undoped ESD polysilicon 108 with a deposition thickness of 6000 Å; then perform general implantation and etching to form the gate PAD area ESD polysilicon 201 to form the ESD protection of the device. The thickness of the gate PAD area ESD polysilicon 201 is 6000 Å. The impurity for general implantation is boron, the implantation angle is 7°, the implantation dose is 1e14 cm -2 , the implantation energy is 80 keV, and the remaining thickness after etching is 200 Å; the dotted part is the built-in ESD diode string N-type region 202. The other regions of the ESD polysilicon are P-type regions. The N-type region, the active region, and the subsequent N+ source implantation region 109 share one mask. The bottom periphery of the region is the gate metal 204, and the center is the source metal 203, obtaining the device with the structure as Figure 10 shown.

[0027] S6. Photolithographically define and implant the etched oxide layer to form the N+ source implantation region 109, activate the source and the ESD protection region. The implantation target is arsenic ions, the implantation energy is 50 keV, and the implantation dose is 5e15 cm -2 , and the temperature condition for annealing and activation is 950 °C, and the time for annealing and activation is 30 min; Use plasma-enhanced chemical vapor deposition to deposit and reflux the ILD. The thickness of the ILD interlayer dielectric is 11200 Å, the temperature for dense reflux is 900 °C, and the time for dense reflux is 30 min; Photolithographically define and use a wet plus dry process to etch openings, complete metal deposition and etching, and photolithographically pattern the lead area again after depositing the passivation layer. The opening size before metal deposition and etching is 3 μm, and the hole implantation conditions are 1.25e15 cm of boron difluoride -2 / 40 keV, 3.5e15 cm of boron -2 / 80 keV, and perform rapid annealing for 15 s; Deposit and etch the surface dielectric and organic matter to form the front metal electrode 111. Metallize the back of the N+ substrate 101 to form the back metal electrode 112. Deposit the front metal electrode 111 and the back thinned metal electrode of 4μm aluminum-copper alloy to obtain a device with the structure as Figure 11 shown.

[0028] The 950V superjunction MOS device with a deep trench filling structure obtained based on the above process, as Figure 1 shown, successively has a continuous first N-type epitaxy 102 and a second N-type epitaxy 103 on the front of the N+ substrate 101. There is a recessed JFET implantation region 104 on the second N-type epitaxy 103. Deep trench filling P pillar regions 105 are respectively arranged on both sides of the first N-type epitaxy 102 and the second N-type epitaxy 103. A Pbody implantation region 106 is arranged on the surface of the deep trench filling P pillar region 105. A gate oxide layer 107 is arranged on the surfaces of the Pbody implantation region 106 and the second N-type epitaxy 103. A polysilicon deposition 108 is arranged on the gate oxide layer 107. The polysilicon deposition 108 has a discontinuous structure. A recessed N+ source implantation region 109 is also arranged on the gate oxide layer 107. The N+ source implantation region 109 contacts the Pbody implantation region 106. A dielectric layer 110 is also arranged on the gate oxide layer 107. The dielectric layer 110 covers the polysilicon deposition 108 and contacts the N+ source implantation region 109 and the JFET implantation region 104; a back metal electrode 112 is arranged on the back of the N+ substrate 101. A front metal electrode 111 is arranged on the front of the gate oxide layer 107. The front metal electrode 111 covers the dielectric layer 110 and contacts the N+ source implantation region 109. That is, a first N-type epitaxy 102 and a second N-type epitaxy 103 are grown on the N+ substrate 101. The JFET implantation region 104 is implanted and formed after the second epitaxy. The deep trench filling P pillar region 105 is formed through deep trench etching and P-type epitaxial filling. After the sacrificial oxygen treatment, the Pbody implantation region 106 is implanted and activated on the flat device surface. A layer of gate oxide layer 107 is continuously grown. The polysilicon deposition 108 is deposited on the gate oxide layer 107. The N+ source implantation region 109 is implanted and formed after the oxide layer etching. The ILD is deposited and densely reflowed to form the dielectric layer 110. The front metal electrode 111 is deposited after the via etching and via implantation. The back is thinned and metallized to form the back metal electrode 112.

[0029] A gate-source ESD protection area is provided on the gate oxide layer 107 to protect the gate from the large transient voltage and current between the gate and the source. The peripheral edge of the top of the gate-source ESD protection area is the source metal 204, and the center of the top of the gate-source ESD protection area is the gate metal 203. The gate metal 203 corresponds to the front metal electrode 111. An ESD diode string N-type region 202 is provided in the gate-source ESD protection area, and the back metal electrode 112 corresponds to the drain metal. The source metal 203 is the metal deposited on the device surface and part of the polysilicon source electrode. The drain metal is formed under the N+ substrate 101, and the gate metal 204 is formed on another part of the polysilicon deposition 108.

[0030] As Figure 4 shown, the figure is the I-V comparison curve of the present application and the existing structure. The curve is a two-dimensional simulation line current. The breakdown voltage of the device of the present application is much higher than that of the conventional superjunction MOSFET. The voltage levels of the two structures are very different. The breakdown voltage of the conventional superjunction MOSFET can only reach 980V and cannot reach the required 1100V voltage level. This is mainly because of the single epitaxial superjunction MOS structure. Due to the deep trench etching angle problem, charge imbalance occurs, and the device cannot achieve charge balance as in the case of 90° etching.

[0031] As Figure 5 shown, the figure is the Ciss-V characteristic comparison curve of the present application and the existing structure. Limited by the deep trench etching superjunction process, the cells of the existing structure are generally small, which will result in larger dynamic parameters such as capacitive charge under the same area. The structure of the present application has a double epitaxial Dummy feature, which can optimize the internal charge imbalance situation and optimize the electric field distribution at the bottom and top of the P-column and N-column, similar to the double superjunction MOS structure. In addition, by etching the polysilicon gate and connecting the source and the gate respectively to form a Dummy structure, the dynamic parameters such as the input capacitance and reverse transfer capacitance of the device are effectively optimized.

[0032] The total charge of the entire first N-type epitaxy 102 is basically equal to the total positive and negative charges of the P-columns in the lower half of the deep trench filled P-column region 105. The total charge of the second N-type epitaxy 103 is basically equal to the total positive and negative charges of the P-columns in the upper half of the deep trench filled P-column region 105. The purpose of the two N-type epitaxies is to alleviate the charge imbalance problem caused by the etching angle of the P-column trench. By adjusting the resistivity of the two epitaxies and the epitaxial concentration of the P-column, the breakdown voltage performance of the superjunction MOSFET can be adjusted. As long as the concentrations of the first N-type epitaxy 102 and the second N-type epitaxy 103 are adjusted to balance the charge of the P-column, a deep trench filled high-voltage superjunction MOS device with a controllable breakdown voltage higher than 950V and up to 1150V can be manufactured. The implantation dose and implantation energy of the Pbody implantation region 106 can adjust the threshold voltage of the superjunction MOSFET. By separating and etching the polysilicon deposition 108, one side of the cell is connected to the source electrode and the other side is connected to the gate electrode to form a Dummy structure. Without affecting the breakdown voltage and on-resistance, a nearly two-fold reduction in the input capacitance and Miller capacitance can be achieved, realizing low dynamic characteristics.

[0033] After optimizing the structural design and manufacturing process of this application, the on-resistance is effectively reduced, the breakdown voltage level and related stability are improved, and at the same time, the switching loss is reduced, and the overall performance is significantly improved.

[0034] It should be noted that this specific embodiment is only an interpretation of the present invention and does not limit the present invention. After reading this specification, those skilled in the art can make modifications to this embodiment that do not contribute creatively according to needs, but as long as it is within the scope of the claims of the present invention, it is protected by the patent law.

Claims

1. A 950V super junction MOS device with a deep trench filling structure, characterized in that: It includes an N+ substrate. On the front side of the N+ substrate, a continuous first N-type epitaxy and a second N-type epitaxy are successively provided. A recessed JFET implantation region is provided on the second N-type epitaxy. Deep trench filled P pillar regions are respectively provided on both sides of the first N-type epitaxy and the second N-type epitaxy. A Pbody implantation region is provided on the surface of the deep trench filled P pillar region. A gate oxide layer is provided on the surfaces of the Pbody implantation region and the second N-type epitaxy. Polysilicon deposition is provided on the gate oxide layer, and the polysilicon deposition is a discontinuous structure. A recessed N+ source implantation region is also provided on the gate oxide layer. The N+ source implantation region contacts the Pbody implantation region. A dielectric layer is also provided on the gate oxide layer. The dielectric layer coats the polysilicon deposition and contacts the N+ source implantation region and the JFET implantation region; A back metal electrode is provided on the back side of the N+ substrate. A front metal electrode is provided on the front side of the gate oxide layer. The front metal electrode coats the dielectric layer and contacts the N+ source implantation region.

2. The 950V superjunction MOS device with a deep trench filling structure according to claim 1, characterized in that: A gate-source ESD protection region is provided on the gate oxide layer. The peripheral edge at the top of the gate-source ESD protection region is source metal, and the center at the top of the gate-source ESD protection region is gate metal. The source metal corresponds to the front metal electrode. An ESD diode string N-type region is provided inside the gate-source ESD protection region. The back metal electrode corresponds to the drain metal.

3. The 950V super junction MOS device with a deep trench filling structure according to claim 2, characterized in that: Other parts of the gate-source ESD protection region except the ESD diode string N-type region are all P-type regions. The ESD diode string N-type region and the N+ source implantation region are on the same plate.

4. The 950V super junction MOS device with a deep trench filling structure according to claim 3, characterized in that: The JFET implantation region on the second N-type epitaxy is an N-type region. The polysilicon deposition is in the active region.

5. A manufacturing method of a 950V superjunction MOS device with a deep trench filling structure, characterized in that: The steps are as follows: S1. Prepare an N+ substrate, and successively grow a first N-type epitaxy and a second N-type epitaxy on the N+ substrate; S2. Grow a thin pre-oxide layer on the second N-type epitaxy, perform N-type JFET implantation to form a JFET implantation region, and remove the thin pre-oxide layer; S3. Perform deep trench etching and P-type epitaxial filling on the first N-type epitaxy and the second N-type epitaxy to form P pillars, grow a sacrificial oxide layer on the surface and remove it all to keep the surface flat; S4. Grow a thin pre-oxide layer on the flat surface, perform high-dose and low-energy P-type body region implantation, and perform high-temperature drive-in to form a Pbody implantation region; S5. Thermally deposit a field oxide layer on the surface, perform active region etching, grow a gate oxide layer in the active region, deposit gate polysilicon to form polysilicon deposition, and etch and separate the gate; Deposit an oxide layer, perform general implantation and etching after deposition to form a gate PAD region ESD polysilicon, and form the ESD protection of the device; S6. Etch the oxide layer, and implant to form an N+ source implantation region, activate the source and the ESD protection region, perform ILD deposition and reflow, open holes to complete metal deposition and etching, deposit and etch the surface dielectric and organic matter to form a front metal electrode, and metallize the back side of the N+ substrate to form a back metal electrode.

6. The manufacturing method of the MOS device according to claim 5, wherein: In step S1, the resistivity of the first N-type epitaxy and the second N-type epitaxy is different. In step S2, the thickness of the thin pre-oxide layer is 200 Å, and the implantation conditions for the JFET implantation region are 2e12 cm -2 / 60 keV.

7. The manufacturing method of the MOS device according to claim 5, characterized in that: In step S3, the deep groove etching is carried out by wet etching. The groove depth of the etched area is 65 μm, the groove width is 5 μm, the etching angle is 88.8°, and the P-type epitaxial filling concentration is 4.2e15 cm -2 .

8. The manufacturing method of the MOS device according to claim 5, wherein: In step S4, the thickness of the thin pre-oxidation layer is 200 Å, and the implantation conditions for the P-shaped body region are 6e13 cm -2 / 60 keV, the annealing conditions are 1100 °C, and the annealing time is 180 min.

9. The manufacturing method of the MOS device according to claim 5, characterized in that: In step S5, the ambient temperature for surface thermal deposition is 980 °C, and the thickness of the field oxide layer is 8000 Å; the growth temperature of the gate oxide layer is 1050 °C, the growth thickness is 1000 Å, and the growth time is 90 min; the self-doping concentration of polysilicon deposition is 4.3e20 cm -3 , and the thickness is 4000 Å; the polysilicon gate region in the middle of each cell in the gate region is etched by 1.6 μm for Dummy design; the deposition thickness of the oxide layer before general implantation is 2000 Å to facilitate isolation of the ESD polysilicon in the gate PAD region; the thickness of the ESD polysilicon in the gate PAD region is 6000 Å, and the general implantation condition is 1e14 cm -2 / 80 keV.

10. The manufacturing method of the MOS device according to claim 5, characterized in that: The remaining thickness of the oxide layer after etching in step S6 is 200 Å; the implantation activation conditions for the source region and the ESD protection region are 5e15 cm -2 / 50 keV for arsenic ions, the annealing temperature is 950 °C, and the annealing time is 30 min; the thickness of the ILD interlayer dielectric is 11200 Å, the temperature of the dense reflow is 900 °C, and the time of the dense reflow is 30 min; the opening size before metal deposition and etching is 3 μm, and the hole implantation conditions are 1.25e15 cm -2 / 40 keV for boron difluoride and 3.5e15 cm -2 / 80 keV for boron, and a rapid annealing for 15 s is performed; a 4-μm-thick front metal electrode and a back metal electrode of aluminum copper alloy are deposited.

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