Groove type IGBT device

Abstract

An embodiment of the invention discloses a groove type IGBT (insulated gate bipolar transistor) device which comprises a cellular structure unit and a Miller capacitor well structure arranged on the periphery of the cellular structure, the cellular structure unit comprises at least one IGBT cellular, the Miller capacitor well structure comprises a plurality of Miller capacitor wells, and the Miller capacitor wells are arranged on the periphery of the cellular structure unit. The Miller capacitor well comprises a collector metal layer, a first conductive type region, an oxide layer and a gate metal layer, a plurality of first grooves are arranged in the first conductive type region, the first grooves are filled with polycrystalline silicon and the oxide layer surrounding the polycrystalline silicon, and the first grooves are connected with the gate metal layer. By means of the mode, the proportion of the CGC / CGE can be obviously changed, the switching speed of the IGBT is effectively regulated and controlled, expected switching performance parameters are achieved, the method can be merged with a conventional technological process, and comprehensive benefits of performance and cost can be achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular, to a trench IGBT device. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) chips combine the advantages of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Bipolar Junction Transistor (BJT), and have characteristics such as high input impedance, low voltage-controlled power consumption, simple control circuit, high voltage resistance, and large current-carrying capacity. With the upgrading of technology, its gate structure has been upgraded from a planar structure to a trench gate structure. The trench gate structure eliminates the JFET effect compared with the planar structure, increases the surface carrier concentration, and improves the channel density, which is the subsequent development trend of IGBTs. Among them, the arrangement structure of the trench gates directly affects the current density and turn-on speed of the IGBT. By reasonably designing the arrangement structure of the trench gates, the conduction characteristics and switching characteristics of the IGBT chip can be effectively adjusted. The existing IGBT trench gate arrangement structures have problems such as small input capacitance and Miller capacitance, and uneven channel current distribution. When reflected in IGBT devices, it shows the phenomenon of gate oscillation during the small-current turn-on process.

[0003] As a gate-controlled switching device, capacitance plays a very important regulatory role during dynamic switching. The trench gate IGBT structure includes three different electrodes G, E, and C. When designing the IGBT structure, in order to increase the C GC capacitance, usually a trench connected to the G electrode needs to be added, but this structure will also increase the C GE capacitance, which results in that it is difficult to significantly adjust the ratio of C GC / C GE Although structures such as split gates can also adjust the C GC / C GE ratio, it requires additional process steps and higher requirements for trench process control, and it is difficult to compromise between performance and cost. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present invention provide a trench IGBT device, which overcomes the above problems or at least partially solves the above problems.

[0005] According to one aspect of an embodiment of the present invention, a trench IGBT device is provided, including: a cell structure unit and a Miller capacitance trap structure disposed around the cell structure. The cell structure unit includes at least one IGBT cell. The Miller capacitance trap structure includes a plurality of Miller capacitance traps. The Miller capacitance trap includes: a collector metal layer, a first conductivity type region, an oxide layer, and a gate metal layer. A plurality of first trenches are provided in the first conductivity type region. The first trenches are filled with polysilicon and an oxide layer surrounding the polysilicon. The first trenches are connected to the gate metal layer.

[0006] Optionally, the IGBT cell sequentially includes, from bottom to top: a collector metal layer, a first conductivity type region, a second conductivity type region, a first conductivity type enhancement region, and a source metal layer. A plurality of second trenches are provided between the first conductivity type enhancement regions. The second trenches are filled with polysilicon and an oxide layer surrounding the polysilicon. An oxide layer is provided between the second trenches and the source metal layer.

[0007] Optionally, the second trenches serve as polysilicon gates or polysilicon sources, wherein the polysilicon gates and polysilicon sources are arranged at intervals.

[0008] Optionally, the Miller capacitance trap structure is in a matrix structure of multiple rows and multiple columns, and the cell structure unit is provided between any adjacent two rows and any adjacent two columns.

[0009] Optionally, the Miller capacitance trap structure is in a matrix structure of multiple rows and multiple columns, and the cell structure unit is provided between some rows and columns.

[0010] Optionally, the Miller capacitance trap structure is arranged in multiple rows and multiple columns, and each column is provided with an irregularly arranged branch structure.

[0011] Optionally, the branch structure includes a plurality of the Miller capacitance traps.

[0012] Optionally, any row and any column in the Miller capacitance trap structure include a plurality of the Miller capacitance traps.

[0013] Optionally, the first trenches in a plurality of the Miller capacitance traps are arranged in multiple columns, and multiple rows are arranged in parallel between adjacent two columns.

[0014] Optionally, the first trenches in adjacent two rows in a direction perpendicular to the column are arranged in a staggered manner.

[0015] The trench IGBT device according to an embodiment of the present invention includes a cell structure unit and a Miller capacitance trap structure disposed around the cell structure. The cell structure unit includes at least one IGBT cell. The Miller capacitance trap structure includes a plurality of Miller capacitance traps. Each Miller capacitance trap includes: a collector metal layer, a first conductivity type region, an oxide layer, and a gate metal layer. A plurality of first trenches are provided in the first conductivity type region. The first trenches are filled with polysilicon and an oxide layer surrounding the polysilicon. The first trenches are connected to the gate metal layer. By adjusting the number / area of the Miller capacitance traps, the ratio of C GC / C GE can be significantly changed, thereby effectively regulating the switching speed of the IGBT, achieving the expected switching performance parameters, being compatible with the conventional process flow, and realizing the comprehensive benefits of performance and cost.

[0016] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to be able to understand the technical means of the embodiment of the present invention more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features and advantages of the embodiment of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0018] Figure 1 shows a schematic structural diagram of a trench IGBT device provided by an embodiment of the present invention;

[0019] Figure 2 shows a schematic structural diagram of a Miller capacitance trap in the trench IGBT device provided by an embodiment of the present invention;

[0020] Figure 3 shows a schematic structural diagram of an IGBT cell in the trench IGBT device provided by an embodiment of the present invention;

[0021] Figure 4 shows a comparison schematic diagram of the C GC / C GE ratio between the Miller capacitance trap and the IGBT cell in the trench IGBT device provided by an embodiment of the present invention;

[0022] Figure 5 shows a schematic structural diagram of another trench IGBT device provided by an embodiment of the present invention;

[0023] Figure 6 shows Figure 2 a schematic structural diagram of another trench IGBT device in

[0024] Figure 7 shows Figure 1 a top view of the internal Miller capacitance trap layout within the dashed box in Detailed implementation manners

[0025] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0026] Figure 1 shows a schematic structural diagram of a trench IGBT device provided by an embodiment of the present invention. As Figure 1 shown, the trench IGBT device includes: a cell structure unit 1 and a Miller capacitance trap structure 2 disposed around the cell structure. The cell structure unit 1 includes at least one IGBT cell 3, and the Miller capacitance trap structure 2 includes a plurality of Miller capacitance traps 4. Refer to Figure 2 , the Miller capacitance trap 4 includes: a collector metal layer 41, a first conductivity type region 42, an oxide layer 43, and a gate metal layer 44. A plurality of first trenches 45 are disposed in the first conductivity type region 42. The first trenches 45 are filled with polysilicon 46 and an oxide layer 47 surrounding the polysilicon 46. The first trenches 45 are connected to the gate metal layer 44.

[0027] In an embodiment of the present invention, refer to Figure 3 , the IGBT cell 3 sequentially includes, from bottom to top: a collector metal layer 31, a first conductivity type region 32, a second conductivity type region 33, a first conductivity type enhancement region 34, and a source metal layer 35. A plurality of second trenches 36 are disposed between the first conductivity type enhancement regions 34. The second trenches 36 are filled with polysilicon 37 and an oxide layer 38 surrounding the polysilicon 37. An oxide layer 39 is disposed between the second trenches 36 and the source metal layer 35. The second trenches 36 serve as polysilicon gates or polysilicon sources, wherein the polysilicon gates and polysilicon sources are arranged at intervals. The first trenches 45 and the second trenches 36 are prepared in the same process, the source metal layer 35 and the gate metal layer 44 are prepared in the same process, and the collector metal layer 41 and the collector metal layer 31 are an integral structure.

[0028] From Figures 1 - 3As can be seen, when the trench-type IGBT device is an N-type IGBT device, the first conductivity type region 42 and the first conductivity type region 32 are N-type regions, the second conductivity type region 33 is a P-type region, and the first conductivity type enhancement region 34 is a heavily doped N+ region. Figure 3 In it, the capacitance C between the gate G and the emitter E GE is composed of the parallel connection of the C1 capacitance and the C2 capacitance, and the capacitance C between the gate G and the collector C GC is composed of C3. Figure 2 In it, C GC The capacitance is composed of the parallel connection of the C3, C4, and C5 capacitances. Figure 4 is Figure 2 the IGBT cell in Figure 3 and the C of the Miller capacitance trap in GC / C GE ratio comparison schematic diagram. It can be seen that Figure 3 the C of the GC / C GE is Figure 2 several times that of the Figure 2 structure, and when the number of trenches in GC / C GE ratio will further increase.

[0029] Thus, several Miller capacitance traps are arranged inside the trench-type IGBT device. The Miller capacitance trap has the following typical characteristics: it includes several trench structures connected to the G electrode under the oxide layer; the electrode on the oxide layer is connected to the G electrode; the trench is directly connected to the first conductivity type region through the oxide layer without a P-type doped region. By adjusting the number / area of the Miller capacitance traps in the embodiments of the present invention, the ratio of C GC / C GE can be significantly changed, thereby effectively regulating the switching speed of the IGBT and achieving the expected switching performance parameters; at the same time, the process of the Miller capacitance trap can be merged with the conventional process flow, without increasing additional process costs, so as to achieve the comprehensive benefits of performance and cost.

[0030] Since the metal electrode on the Miller capacitance trap is connected to the G electrode, it needs to be distributed along the gate bus during the layout inside the device.

[0031] Continue to refer to Figure 1 , the Miller capacitance trap structure 2 can be in a matrix structure of multiple rows and multiple columns, and the cell structure unit 1 is arranged between any adjacent two rows and any adjacent two columns. Refer to Figure 5 , the Miller capacitance trap structure 2 is in a matrix structure of multiple rows and multiple columns, and the cell structure unit 1 is arranged between some rows and columns. Figure 5 On the Figure 1 basis, further increase the C GC / C GE ratio.Figure 6 For a distributed Miller capacitance trap distribution, the structural layout within the device is made more uniform to improve the current sharing performance. As Figure 6 shown, the Miller capacitance trap structure is arranged in multiple rows and columns, and each column is provided with a branch structure 5 arranged irregularly. The branch structure 5 includes a plurality of the Miller capacitance traps. Any row and any column in the Miller capacitance trap structure 2 include a plurality of the Miller capacitance traps.

[0032] Since the area of the Miller capacitance trap is smaller than that of the normal cell structure, in order to expand the effect of the Miller capacitance trap, the layout of the Miller capacitance trap structure is also different from Figure 2 the cell structure. As Figure 7 shown is a top view of the internal Miller capacitance trap layout within the dashed box in Figure 1 , which includes grooves in two directions (xz direction), and the contact area between the grooves and the substrate N-sub is increased to further increase C GC , and its cross-sectional views in the AB and CD directions are the same as those of Figure 2 the structure. As Figure 7 shown, within any column or any row of the Miller capacitance trap structure, the first grooves among the plurality of the Miller capacitance traps are arranged in multiple columns, and there are multiple rows arranged in parallel between adjacent two columns. The first grooves in adjacent two rows along the direction perpendicular to the column are arranged staggeredly. For example, there is a position difference in the z-axis direction between the first grooves in the rows located between the first column and the second column and the first grooves in the rows located between the second column and the third column in the figure.

[0033] In the trench-type IGBT device in the embodiment of the present invention, a number of Miller capacitance traps are arranged within the device. By adjusting the number / area of the Miller capacitance traps, the ratio of C GC / C GE can be significantly changed, so as to effectively regulate the switching speed of the IGBT and achieve the expected switching performance parameters; meanwhile, the process of the Miller capacitance trap can be combined with the conventional process flow, with stronger process compatibility, without the need to develop a new process and degenerate with the conventional process flow. Only by changing the layout can different C GC / C GE ratios be achieved, without increasing additional process costs, thus realizing the comprehensive benefits of performance and cost.

[0034] Those of ordinary skill in the art should understand that: the discussion of any above embodiment is only exemplary, and is not intended to imply that the scope of the present disclosure is limited to these examples; under the idea of the present disclosure, the technical features between the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present invention as described above, and they are not provided in detail for the sake of brevity.

[0035] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of all embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention shall be included within the scope of protection of this disclosure.

Claims

1. A trench IGBT device, characterized in that, The trench IGBT device includes: a cell structure unit and a Miller capacitance trap structure arranged around the cell structure. The cell structure unit includes at least one IGBT cell. The Miller capacitance trap structure includes a plurality of Miller capacitance traps. Each Miller capacitance trap includes: a collector metal layer, a first conductivity type region, an oxide layer, and a gate metal layer. A plurality of first trenches are arranged in the first conductivity type region. The first trenches are filled with polysilicon and an oxide layer surrounding the polysilicon. The first trenches are connected to the gate metal layer.

2. The trench IGBT device according to claim 1, wherein The IGBT cell sequentially includes, from bottom to top: a collector metal layer, a first conductivity type region, a second conductivity type region, a first conductivity type enhanced region, and a source metal layer. A plurality of second trenches are arranged between the first conductivity type enhanced regions. The second trenches are filled with polysilicon and an oxide layer surrounding the polysilicon. An oxide layer is arranged between the second trenches and the source metal layer.

3. The trench IGBT device according to claim 2, characterized in that, The second trenches serve as polysilicon gates or polysilicon sources, wherein the polysilicon gates and the polysilicon sources are arranged at intervals.

4. The trench IGBT device according to claim 1, wherein The Miller capacitance trap structure is in a multi-row and multi-column matrix structure, and the cell structure unit is arranged between any adjacent two rows and any adjacent two columns.

5. The trench IGBT device according to claim 1, characterized in that, The Miller capacitance trap structure is in a multi-row and multi-column matrix structure, and the cell structure unit is arranged between some rows and columns.

6. The trench IGBT device according to claim 1, wherein, The Miller capacitance trap structure is arranged in multiple rows and multiple columns, and an irregularly arranged branch structure is provided in each column.

7. The trench IGBT device according to claim 6, characterized in that, The branch structure includes a plurality of the Miller capacitance traps.

8. The trench IGBT device according to any one of claims 4-6, characterized in that, Any row and any column in the Miller capacitance trap structure include a plurality of the Miller capacitance traps.

9. The trench IGBT device according to claim 8, wherein The first trenches in a plurality of the Miller capacitance traps are arranged in multiple columns, and multiple rows are arranged in parallel between adjacent two columns.

10. The trench IGBT device according to claim 9, wherein, The first trenches in adjacent two rows along the direction perpendicular to the columns are arranged in a staggered manner.

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