Integrated circuit device

Abstract

The invention provides an integrated circuit device. The integrated circuit device includes: a plurality of device isolation films; a plurality of gate lines disposed on the plurality of device isolation films; a first source / drain region and a second source / drain region disposed between the plurality of gate lines, respectively, in which each of the first source / drain region and the second source / drain region includes a source / drain barrier layer, a source / drain body layer on the source / drain barrier layer, and a source / drain cap layer on the source / drain body layer, in which the source / drain cap layer is disposed between the plurality of gate lines, a doping concentration of the source / drain cap layer is greater than a doping concentration of the source / drain body layer, a doping concentration of the source / drain body layer is greater than a doping concentration of the source / drain barrier layer, and the source / drain cap layer includes a tip.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0186303, filed with the Korean Intellectual Property Office on December 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including source / drain regions. Background Art

[0003] Due to the development of electronic technology, the scaling of integrated circuit devices has been rapidly progressing. Since semiconductor devices require high operating speeds and operating accuracies, various studies have been conducted to optimize the structure of transistors included in semiconductor devices. Summary of the Invention

[0004] The inventive concept provides an integrated circuit device having improved electrical characteristics.

[0005] The problems to be solved by the technical spirit of the present inventive concept are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] According to an aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and longitudinally extending in the second horizontal direction; a first source / drain region and a second source / drain region respectively disposed between the plurality of gate lines; and at least one source / drain contact over the first source / drain region and the second source / drain region, wherein each of the first source / drain region and the second source / drain region includes a source / drain blocking layer, a source / drain body layer on the source / drain blocking layer, and a source / drain capping layer on the source / drain body layer, wherein the doping concentration of the source / drain capping layer is greater than that of the source / drain body layer, the doping concentration of the source / drain body layer is greater than that of the source / drain blocking layer, and the source / drain capping layer includes a pointed portion.

[0007] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and longitudinally extending in the second horizontal direction; a first source / drain region and a second source / drain region respectively disposed between the plurality of gate lines; and a plurality of source / drain contacts above the first source / drain region and the second source / drain region, wherein each of the first source / drain region and the second source / drain region includes a source / drain barrier layer and a source / drain body layer on the source / drain barrier layer, and wherein the first source / drain region further includes a source / drain recess recessed inward from an upper surface of the first source / drain region and a source / drain capping layer disposed in the source / drain recess.

[0008] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and longitudinally extending in the second horizontal direction; a first source / drain region and a second source / drain region respectively disposed between the plurality of gate lines; a source / drain contact on the first source / drain region; and a backside source / drain contact below the second source / drain region, wherein each of the first source / drain region and the second source / drain region includes a source / drain barrier layer and a source / drain body layer on the source / drain barrier layer, and wherein the second source / drain region further includes a backside source / drain recess recessed inward from a lower surface of the second source / drain region and a backside source / drain capping layer disposed in the backside source / drain recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram showing a planar layout of a unit block of an integrated circuit device according to an exemplary embodiment;

[0011] Figure 2 is a diagram for explaining a planar layout of an integrated circuit device according to an exemplary embodiment;

[0012] Figure 3A is a cross-sectional view taken along line X1-X1' of Figure 2 ;

[0013] Figure 3B is a cross-sectional view taken along Figure 2A cross-sectional view taken along the line Y1 - Y1';

[0014] Figure 4 is Figure 3A An enlarged view of the area indicated by "EX2" in;

[0015] Figure 5 A diagram for explaining the layout of an integrated circuit device according to other exemplary embodiments;

[0016] Fig. 6A is along Figure 5 A cross-sectional view taken along the line X1 - X1';

[0017] Figure 6B is along Figure 5 A cross-sectional view taken along the line Y1 - Y1';

[0018] Figure 6C is along Figure 5 A cross-sectional view taken along the line Y2 - Y2';

[0019] Figure 7 is Fig. 6A An enlarged view of the area indicated by "EX3" in;

[0020] Figure 8 A diagram for explaining an integrated circuit device according to other exemplary embodiments;

[0021] Fig. 9 A diagram for explaining an integrated circuit device according to other exemplary embodiments;

[0022] Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A and Fig. 22B are diagrams showing the process sequence of a method for manufacturing an integrated circuit device according to an exemplary embodiment; and

[0023] Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.35A and Fig.35B are diagrams showing the process sequence of a method of manufacturing an integrated circuit device according to other example embodiments. Detailed Description

[0024] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same components in the drawings, and their description will not be repeated.

[0025] It will be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, or is referred to as "contacting" another element or "in contact with" another element (or using any form of the word "contact"), there are no intervening elements at the point of contact.

[0026] When referring to orientation, layout, position, shape, size, quantity, or other measurements, terms such as "same", "equal", "planar", or "coplanar" as used herein need not mean exactly the same orientation, layout, position, shape, size, quantity, or other measurements, but are intended to cover almost the same orientation, layout, position, shape, size, quantity, or other measurements within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0027] In this specification, the horizontal direction may include a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction) that cross each other. A direction that crosses the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction) may be referred to as the vertical direction (e.g., the Z direction). In this specification, the vertical level may be referred to as the height level in the vertical direction (e.g., the Z direction) of any configuration.

[0028] Figure 1 is a diagram showing a planar layout of a unit block 12 of an integrated circuit device 10 according to an exemplary embodiment.

[0029] Referring to Figure 1 , the unit block 12 of the integrated circuit device 10 may include a plurality of logic units LC, and the logic units LC include circuit patterns for constructing various circuits. The plurality of logic units LC may be arranged in a matrix form in the unit block 12 in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction).

[0030] Each of the plurality of logic units LC may include a circuit pattern having a layout designed according to placement and routing (PnR) technology to perform at least one logic function. The plurality of logic units LC may have functions of performing various logic functions. In an exemplary embodiment, the plurality of logic units LC may include a plurality of standard cells. In an exemplary embodiment, at least some of the plurality of logic units LC may perform the same logic function. In other exemplary embodiments, at least some of the plurality of logic units LC may perform different logic functions.

[0031] The plurality of logic units LC may include various types of logic units including a plurality of circuit elements. For example, each of the plurality of logic units LC may include AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MXT / MXIT, OAI, AO, AOI, D flip-flop, reset flip-flop, master-slave flip-flop, latch, or any combination thereof, but not limited thereto.

[0032] In the cell block 12, at least some of the multiple logic cells LC forming a row (row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6) in the first horizontal direction (e.g., the X direction) may have the same width. Additionally, at least some of the multiple logic cells LC forming a row (row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6) may each have the same height. However, the inventive concept is not limited to Figure 1 the embodiment shown in, and at least some of the multiple logic cells LC forming a row (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6) may have different widths and heights.

[0033] The area of each of the multiple logic cells LC included in the cell block 12 of the integrated circuit device 10 may be limited by the cell boundary CBD. The cell boundary contact portion CBC where each cell boundary CBD intersects may be included between two logic cells LC adjacent to each other in the first horizontal direction (e.g., the X direction) or the second horizontal direction (e.g., the Y direction) among the multiple logic cells LC.

[0034] In an example embodiment, among the multiple logic cells LC forming a row (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6), two logic cells LC adjacent to each other in the first horizontal direction (e.g., the X direction) may be in contact with each other at the cell boundary contact portion CBC without an intervening distance therebetween. In other example embodiments, among the multiple logic cells LC forming a row (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6), two logic cells LC adjacent to each other in the first horizontal direction (e.g., the X direction) may be spaced apart from each other by a predetermined distance therebetween.

[0035] In an example embodiment, among the multiple logic cells LC forming a row (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6), two adjacent logic cells LC may perform the same function. In this case, the two adjacent logic cells LC may have the same structure. In other example embodiments, among the multiple logic cells LC forming a row (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, or row RO6), two adjacent logic cells LC may perform different functions.

[0036] In an example embodiment, one logic cell LC selected from among the multiple logic cells LC included in the cell block 12 of the integrated circuit device 10 and in the second horizontal direction ( Figure 1Another logic unit LC adjacent to the selected logic unit LC on Y in [ ] may have a structure symmetric with respect to the cell boundary contact portion CBC therebetween. For example, the reference logic unit LC_R in the third row RO3 and the lower logic unit LC_L in the second row RO2 have a structure symmetric with respect to the cell boundary contact portion CBC therebetween. In addition, the reference logic unit LC_R in the third row RO3 and the upper logic unit LC_H in the fourth row RO4 may have a structure symmetric with respect to the cell boundary contact portion CBC therebetween.

[0037] Figure 1 The cell block 12 including six rows (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, and row RO6) is shown, but this is merely an example, and the cell block 12 may include a variable number of rows selected as needed, and one row may include a variable number of logic units selected as needed.

[0038] One selected from a plurality of ground lines VSS and a plurality of power lines VDD may be provided between each of a plurality of rows (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, and row RO6), and each of the plurality of rows (e.g., row RO1, row RO2, row RO3, row RO4, row RO5, and row RO6) includes a plurality of logic units LC arranged in a row in the first horizontal direction (e.g., X direction). The plurality of ground lines VSS and the plurality of power lines VDD may extend longitudinally in the first horizontal direction (e.g., X direction), may be spaced apart from each other in the second horizontal direction (e.g., Y direction), and may be arranged alternately. Accordingly, the plurality of ground lines VSS and the plurality of power lines VDD may be arranged to overlap with the cell boundary CBD of the logic unit LC in the second horizontal direction (e.g., Y direction).

[0039] Figure 2 is a diagram for explaining the layout of the integrated circuit device 10 according to an embodiment. Specifically, Figure 2 is Figure 1 an enlarged view of the region EX1 in [ ]. Figure 3A is along Figure 2 a cross-sectional view taken along the line X1-X1' of [ ]. Figure 3B is along Figure 2 a cross-sectional view taken along the line Y1-Y1' of [ ]. Figure 4 is Figure 3A an enlarged view of the region EX2 in [ ].

[0040] Referring to Figure 2 、 Figure 3A 、 Figure 3B and Figure 4, an integrated circuit device 10 including a field effect transistor (FET) will be described. The field effect transistor has a gate-all-around structure including an active region having a nanowire or nanosheet shape and a gate surrounding the active region. For example, the integrated circuit device 10 may include a multi-bridge channel FET (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 10 may include a planar FET device, a fin FET device, etc. The integrated circuit device 10 may be formed Figure 1 as a part of a plurality of logic units LC shown in .

[0041] The integrated circuit device 10 may include a substrate 102 having a back surface 102B and a fin-shaped active region F1 protruding from the substrate 102 to define a trench region T1 in the substrate 102 on the opposite side of the back surface 102B. The fin-shaped active region F1 may extend longitudinally on the substrate 102 in a first horizontal direction (e.g., the X direction) and may extend parallel to each other.

[0042] The substrate 102 may include a semiconductor (such as Si or Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, InGaAs, or InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", "InP" used in this specification refer to materials composed of the elements included in each term and do not represent chemical formulae indicating stoichiometric relationships. The substrate 102 may include a conductive region (e.g., a well doped with impurities or a structure doped with impurities).

[0043] A device isolation film 112 may be disposed in the trench region T1 defining the fin-shaped active region F1. The device isolation film 112 may cover a part of the sidewall of the fin-shaped active region F1 in the trench region T1 and may be stacked with a part of the sidewall of the fin-shaped active region F1, and may extend away from the substrate 102 in a vertical direction (e.g., the Z direction). For example, the device isolation film 112 may contact the sidewall of the fin-shaped active region F1 in the trench region T1. The device isolation film 112 may include a silicon oxide film.

[0044] A plurality of gate lines 160 may be disposed on the fin-type active region F1. Each of the plurality of gate lines 160 may extend longitudinally in the second horizontal direction (e.g., the Y direction). In the region where the fin-type active region F1 and the plurality of gate lines 160 intersect, a plurality of nanosheet stacks NSS may be disposed on the fin upper surface FT of the fin-type active region F1. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet that faces the fin upper surface FT at a position spaced apart from the fin upper surface FT of the fin-type active region F1 in the vertical direction (e.g., the Z direction). The term "nanosheet" used herein refers to a conductive structure having a cross-section substantially perpendicular to the current flow direction. The term "nanosheet" should be understood to include nanowires.

[0045] The plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that are stacked on top of each other in the vertical direction (e.g., the Z direction) in the fin-type active region F1. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (distances in the vertical direction) from the fin upper surface FT of the fin-type active region F1. The plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 that are stacked on top of each other in the vertical direction (e.g., the Z direction) and included in the nanosheet stack NSS.

[0046] Although Figure 2 the case where the planar shape of the nanosheet stack NSS is approximately square is shown, it is not limited thereto. Depending on the planar shapes of each of the fin-type active region F1 and the gate lines 160, the nanosheet stack NSS may have various planar shapes. In this example, a configuration in which a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are disposed in one fin-type active region F1, and the plurality of nanosheet stacks NSS are arranged in a row in the first horizontal direction (e.g., the X direction) in one fin-type active region F1 is taken as an example. However, the number of nanosheet stacks NSS and gate lines 160 disposed in one fin-type active region F1 is not particularly limited.

[0047] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS can each be used as a channel region. In an exemplary embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can each have a thickness selected in the range from about 4 nm to about 6 nm, but the thickness range is not limited thereto. Here, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 refers to the thickness or length in the vertical direction (e.g., the Z direction). In an exemplary embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can have substantially the same thickness in the vertical direction (e.g., the Z direction). In other exemplary embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can have different thicknesses in the vertical direction (e.g., the Z direction). In an exemplary embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS can each include an Si layer, an SiGe layer, or any combination thereof.

[0048] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS have the same or similar dimensions to each other in the first horizontal direction (e.g., the X direction). In other exemplary embodiments, different from that shown in Figure 3A , the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS can have different dimensions in the first horizontal direction (e.g., the X direction). In this example, a case where a plurality of nanosheet stacks NSS each include three nanosheets is shown, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS can include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0049] Each of the plurality of gate lines 160 can include a main gate portion 160M and a plurality of sub - gate portions 160S. The main gate portion 160M covers the upper surface of the nanosheet stack NSS and is stacked on the upper surface of the nanosheet stack NSS, and can extend longitudinally in the second horizontal direction (e.g., the Y direction). The plurality of sub - gate portions 160S are integrally connected to the main gate portion 160M, and one sub - gate portion 160S can be disposed between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 (e.g., between the first nanosheet N1 and the second nanosheet N2, and between the second nanosheet N2 and the third nanosheet N3) and between the first nanosheet N1 and the fin - type active region F1. In the vertical direction (e.g., the Z direction), the thickness of each of the plurality of sub - gate portions 160S can be less than the thickness of the main gate portion 160M.

[0050] A plurality of active region recesses R1 may be formed in the fin-type active region F1. The vertical level of the bottommost surface of each of the plurality of active region recesses R1 may be less than the vertical level of the fin upper surface FT of the fin-type active region F1.

[0051] A plurality of source / drain regions SD may be respectively disposed in the plurality of active region recesses R1. The plurality of source / drain regions SD may each be disposed adjacent to at least one gate line 160 selected from among the plurality of gate lines 160. The plurality of source / drain regions SD may have surfaces respectively facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS. For example, the plurality of source / drain regions SD may be stacked with the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in a first horizontal direction (e.g., the X direction).

[0052] Each of the plurality of gate lines 160 may include a metal, a metal nitride, a metal carbide, or any combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the material constituting the plurality of gate lines 160 is not limited to the above examples.

[0053] A gate dielectric film 152 may be disposed between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may contact the nanosheet stack NSS and the gate line 160. In an exemplary embodiment, the gate dielectric film 152 may have a stacked structure of an interfacial dielectric film and a high-k dielectric film. The interfacial dielectric film may include a low dielectric material film having a dielectric constant of about 9 or less (e.g., a silicon oxide film, a silicon oxynitride film, or any combination thereof). In an exemplary embodiment, the interfacial dielectric film may be omitted. The high-k dielectric film may include a material having a dielectric constant greater than that of the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant in the range from about 10 to about 25. The high-k dielectric layer may include hafnium oxide, but is not limited thereto.

[0054] According to an exemplary embodiment, each of the gate dielectric film 152 and the gate line 160 may include a portion stacked with the plurality of nanosheet stacks NSS in a vertical direction (e.g., the Z direction).

[0055] According to an example embodiment, a plurality of transistors may be formed in a region where a plurality of nanosheet stacks NSS are stacked with a gate line 160 and a gate dielectric film 152. The plurality of transistors may include nanosheet transistors. According to an example embodiment, the plurality of transistors may include PMOS transistors and NMOS transistors. For example, each of the plurality of transistors may be composed of at least one nanosheet stack NSS, a gate dielectric film 152 surrounding the at least one nanosheet stack NSS, a gate line 160, and a plurality of source / drain regions SD facing the at least one nanosheet stack NSS in a first horizontal direction (e.g., the X direction).

[0056] In some embodiments, each of the plurality of nanosheet stacks NSS may include an undoped Si layer. In some other embodiments, each of the plurality of nanosheet stacks NSS may include a doped Si layer. For example, if the plurality of nanosheet stacks NSS constitute PMOS transistors, each of the plurality of nanosheet stacks NSS may each include a Si layer doped with a p-type dopant, and if the plurality of nanosheet stacks NSS constitute NMOS transistors, each of the plurality of nanosheet stacks NSS may each include a Si layer doped with an n-type dopant, but is not limited thereto. The p-type dopant may be selected from B (boron) and Ga (gallium). The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0057] In an example embodiment, each of the plurality of source / drain regions SD may have a multi-layer structure. Each of the plurality of source / drain regions SD may include a source / drain barrier layer 132 and a source / drain body layer 134 on the source / drain barrier layer 132. The source / drain body layer 134 may contact the source / drain barrier layer 132. For example, in one source / drain region SD selected from the plurality of source / drain regions SD, the source / drain barrier layer 132 may conformally extend on the upper surface of the active region recess R1, the sidewalls of the plurality of nanosheet stacks NSS adjacent to the source / drain barrier layer 132, and the sidewalls of the gate dielectric film 152. The source / drain barrier layer 132 may contact the fin-type active region F1. The source / drain body layer 134 on the source / drain barrier layer 132 may fill the active region recess R1.

[0058] In an exemplary embodiment, each of the plurality of source / drain regions SD may include a source / drain blocking layer 132, a source / drain body layer 134, and a source / drain capping layer 136 on the source / drain body layer 134. The source / drain capping layer 136 may be disposed in a source / drain recess R2 that is recessed inward from the upper surface of each of the plurality of source / drain regions SD. In some embodiments, the source / drain capping layer 136 may be disposed in a source / drain recess R2 formed by recessing a portion of the source / drain body layer 134. The source / drain capping layer 136 may be stacked with a portion of the source / drain blocking layer 132 (e.g., a portion of the source / drain blocking layer 132 that covers the lower surface of the source / drain body layer 134 and is stacked with the lower surface of the source / drain body layer 134) in a vertical direction (e.g., the Z direction), and may be stacked with the source / drain body layer 134 in a vertical direction (e.g., the Z direction). In some other embodiments, the source / drain capping layer 136 may be disposed in a source / drain recess R2 formed by recessing a portion of the source / drain blocking layer 132 and a portion of the source / drain body layer 134. The source / drain capping layer 136 may be stacked with the source / drain blocking layer 132 and the source / drain body layer 134 in a vertical direction (e.g., the Z direction).

[0059] The source / drain recess R2 formed by recessing a portion of the source / drain blocking layer 132 and / or a portion of the source / drain body layer 134 may be stacked with at least one of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in a first horizontal direction (e.g., the X direction). In other words, the source / drain capping layer 136 may be stacked with at least one of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in a first horizontal direction (e.g., the X direction). For example, the lowermost surface of the source / drain capping layer 136 may be at a vertical level lower than the upper surface of at least one of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3.

[0060] In some embodiments, the source / drain capping layer 136 may include a pointed portion PT1, and the pointed portion PT1 may include a vertex VT1. The pointed portion PT1 may be a lower region of the source / drain capping layer 136, and the vertex VT1 may be a portion of the pointed portion PT1 having the lowest vertical level in the vertical direction (e.g., the Z direction). However, this is an example, and the pointed portion PT1 may include at least one vertex. In the process of manufacturing the integrated circuit device 10, after forming the source / drain barrier layer 132 and the source / drain body layer 134, a source / drain recess R2 having an angular shape may be formed by etching a portion of the source / drain barrier layer 132 and the source / drain body layer 134. Since the source / drain capping layer 136 epitaxially grows on the source / drain recess R2 having an angular shape, the source / drain capping layer 136 may include the pointed portion PT1. The source / drain capping layer 136 including the pointed portion PT1 may have relatively few defects in the film that may occur due to epitaxial growth. For example, the epitaxial growth of the source / drain capping layer 136 is described below in the description of the method of manufacturing the integrated circuit device 10. The source / drain capping layer 136 may include a crystalline material.

[0061] In an exemplary embodiment, a first group of source / drain regions SD among the plurality of source / drain regions SD may be configured as PMOS transistors. In this case, the plurality of source / drain regions SD may include Si 1-x Ge x layers (or, Si 1-x Ge x films) (here, 0.0 < x ≤ 0.6).

[0062] In some embodiments, in the source / drain region SD, the Ge content ratio in the source / drain body layer 134 may be greater than the Ge content ratio in the source / drain barrier layer 132, and the Ge content ratio in the source / drain capping layer 136 may be greater than the Ge content ratio in the source / drain body layer 134. In some embodiments, the Ge content ratio in the source / drain barrier layer 132 may be greater than about 0.0 atomic % (at%) and less than or equal to about 20 atomic % (e.g., greater than or equal to about 10 atomic % and less than or equal to about 20 atomic %). The Ge content ratio in the source / drain body layer 134 may be in the range from about 30 atomic % to about 45 atomic % (e.g., in the range from about 30 atomic % to about 40 atomic %). The Ge content ratio in the source / drain capping layer 136 may be greater than about 40 atomic % and less than or equal to about 70 atomic % (e.g., greater than or equal to about 45 atomic % and less than or equal to about 55 atomic %). However, the inventive concept is not limited to the above examples.

[0063] In some embodiments, in the source / drain region SD, the ratio of the p-type dopant content in the source / drain bulk layer 134 may be greater than the ratio of the p-type dopant content in the source / drain barrier layer 132, and the ratio of the p-type dopant content in the source / drain capping layer 136 may be greater than the ratio of the p-type dopant content in the source / drain bulk layer 134. For example, the concentration of the p-type dopant in the source / drain capping layer 136 may be in the range from about 5×10 20 at / cm 3 to about 2×10 21 at / cm 3 . In some embodiments, the p-type dopant may be at least one selected from boron (B) and gallium (Ga), but is not limited thereto.

[0064] In other exemplary embodiments, a second group of source / drain regions SD of the plurality of source / drain regions SD may be configured as NMOS transistors. In this case, the source / drain region SD may include a Si layer (or, Si film) doped with an n-type dopant, an undoped Si layer, or any combination thereof.

[0065] In some embodiments, in the source / drain region SD, the source / drain barrier layer 132 may include an undoped Si layer, and the source / drain bulk layer 134 and the source / drain capping layer 136 may include a Si layer doped with an n-type dopant. In some other embodiments, in the source / drain region SD, the source / drain barrier layer 132, the source / drain bulk layer 134, and the source / drain capping layer 136 may be doped with an n-type dopant, but the ratio of the n-type dopant content in the source / drain bulk layer 134 may be greater than the ratio of the n-type dopant content in the source / drain barrier layer 132, and the ratio of the n-type dopant content in the source / drain capping layer 136 may be greater than the ratio of the n-type dopant content in the source / drain bulk layer 134. For example, the concentration of the n-type dopant in the source / drain capping layer 136 may be in the range from about 5×10 20 at / cm 3 to about 2×10 21 at / cm 3 . The n-type dopant may be at least one selected from P (phosphorus), As (arsenic), and Sb (antimony), but is not limited thereto.

[0066] In some embodiments, in the first group of source / drain regions SD that constitute a PMOS transistor among the plurality of source / drain regions SD, the tip PT1 of the source / drain capping layer 136 may overlap with the sub-gate part 160S that surrounds the lower surface of the third nanosheet N3 at the top among the plurality of sub-gate parts 160S in the first horizontal direction (e.g., X direction).

[0067] In some other embodiments, in a second group of source / drain regions SD that constitute NMOS transistors among the plurality of source / drain regions SD, the tip PT1 of the source / drain capping layer 136 may be superimposed on a sub-gate portion 160S that surrounds the lower surface of the first nanosheet N1 located at the bottom among the plurality of sub-gate portions 160S in a first horizontal direction (e.g., the X direction).

[0068] In an exemplary embodiment, a first group of source / drain regions SD that constitute PMOS transistors among the plurality of source / drain regions SD are electrically connected to a plurality of power supply lines VDD (see Figure 1 ), and thus can receive a voltage of a positive potential, and a second group of source / drain regions SD that constitute NMOS transistors among the plurality of source / drain regions SD are electrically connected to a plurality of ground lines VSS (see Figure 1 ), and thus can receive a ground voltage or a voltage of a negative potential.

[0069] A metal silicide film 172 may be disposed on the upper surfaces of the plurality of source / drain regions SD. The metal silicide film 172 may include a metal composed of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide, but is not limited thereto. The metal silicide film 172 may contact the source / drain capping layer 136. The metal silicide film 172 may be superimposed on the source / drain body layer 134 and the source / drain capping layer 136 in a first horizontal direction (e.g., the X direction).

[0070] A capping insulating pattern 168 may be disposed on the gate dielectric film 152 and the gate line 160. For example, the capping insulating pattern 168 may cover the upper surface of the main gate portion 160M and the upper surfaces of portions of the gate dielectric film 152 that surround the main gate portion 160M and may be superimposed on the upper surface of the main gate portion 160M and the upper surfaces of portions of the gate dielectric film 152 that surround the main gate portion 160M. The capping insulating pattern 168 may contact the upper surface of the main gate portion 160M and the upper surfaces of portions of the gate dielectric film 152 that surround the main gate portion 160M. The capping insulating pattern 168 may include a silicon nitride film or a silicon oxide film.

[0071] Two sidewalls of each of the gate line 160 and the capping insulating pattern 168 may be covered by and superimposed on an outer insulating spacer 118. Specifically, the outer insulating spacer 118 may cover two sidewalls of the main gate portion 160M on the upper surface of the plurality of nanosheet stacks NSS and may be superimposed on the two sidewalls of the main gate portion 160M. The outer insulating spacer 118 may be spaced apart from the gate line 160, and the gate dielectric film 152 is disposed between the outer insulating spacer 118 and the gate line 160. For example, the outer insulating spacer 118 may contact the side surfaces of the gate dielectric film 152 and the capping insulating pattern 168.

[0072] The plurality of recess side insulating spacers 119 may respectively cover one sidewall of the source / drain region SD and the other sidewall facing the one sidewall, and may be stacked with one sidewall of the source / drain region SD and the other sidewall facing the one sidewall, and may be disposed on the upper surface of the device isolation film 112. For example, the plurality of recess side insulating spacers 119 may contact the sidewalls of the source / drain body layer 134 of the source / drain region SD and the upper surface of the device isolation film 112. In an exemplary embodiment, each of the plurality of recess side insulating spacers 119 may be integrally connected to the adjacent outer insulating spacer 118.

[0073] The plurality of outer insulating spacers 118 and the plurality of recess side insulating spacers 119 may each include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or any combination thereof. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used in this specification refer to materials composed of the elements included in each term, and are not chemical formulas representing stoichiometric relationships.

[0074] The plurality of source / drain regions SD, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered by and stacked with the insulating layer 142. The insulating layer 142 may contact the upper surface of the device isolation film 112, the side surfaces of the recess side insulating spacers 119, the surface of the source / drain body layer 134, the surface of the source / drain capping layer 136, the upper surfaces of the plurality of metal silicide films 172, and the side surfaces of the plurality of outer insulating spacers 118. In an exemplary embodiment, the insulating layer 142 may be omitted. The inter-gate insulating film 144 may be disposed on the insulating layer 142. The inter-gate insulating film 144 may contact the insulating layer 142. If the insulating layer 142 is omitted, the inter-gate insulating film 144 may contact the plurality of source / drain regions SD.

[0075] The insulating layer 142 and the inter-gate insulating film 144 may be sequentially disposed on the plurality of source / drain regions SD and the plurality of metal silicide films 172. The insulating layer 142 and the inter-gate insulating film 144 may form an insulating structure. In an exemplary embodiment, the insulating layer 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or any combination thereof, but is not limited thereto. The inter-gate insulating film 144 may include a silicon oxide film, but is not limited thereto.

[0076] Two sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be spaced apart from the source / drain regions SD, and a gate dielectric film 152 is disposed between the two sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 and the source / drain regions SD. The gate dielectric film 152 may be disposed between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portion 160S included in the gate line 160 and the source / drain regions SD.

[0077] In addition, two sidewalls of each of the plurality of main-gate portions 160M included in the plurality of gate lines 160 may be spaced apart from the source / drain regions SD, and the gate dielectric film 152 and the outer insulating spacer 118 are disposed between the two sidewalls of each of the plurality of main-gate portions 160M included in the plurality of gate lines 160 and the source / drain regions SD. The gate dielectric film 152 may be disposed between the main-gate portion 160M included in the gate line 160 and the outer insulating spacer 118, and between the main-gate portion 160M and the uppermost third nanosheet N3.

[0078] A plurality of source / drain contact members CA may be respectively disposed on the plurality of source / drain regions SD. The plurality of source / drain contact members CA may each penetrate a part of the inter-gate insulating film 144 and the insulating layer 142 in the vertical direction (e.g., the Z direction) and contact the metal silicide film 172. The inter-gate insulating film 144 and the insulating layer 142 may contact the side surfaces of the plurality of source / drain contact members CA. Each of the plurality of source / drain contact members CA may be electrically connected to the source / drain region SD through the metal silicide film 172. The plurality of source / drain contact members CA are spaced apart from the main-gate portion 160M in the first horizontal direction (e.g., the X direction), and the outer insulating spacer 118, the insulating layer 142, and the inter-gate insulating film 144 are disposed between the plurality of source / drain contact members CA and the main-gate portion 160M. The upper surfaces of the plurality of source / drain contact members CA, the plurality of covering insulating patterns 168, the outer insulating spacer 118, the insulating layer 142, and the inter-gate insulating film 144 may be coplanar.

[0079] The multiple source / drain contacts CA may include a conduction barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region SD. In an exemplary embodiment, a source / drain capping layer 136 of the source / drain region SD may surround a lower portion of each of the multiple source / drain contacts CA. The conduction barrier pattern 174 may surround a lower surface and sidewalls of the contact plug 176 and may be in contact with the lower surface and sidewalls of the contact plug 176. The conduction barrier pattern 174 may be disposed between the metal silicide film 172 and the contact plug 176. The conduction barrier pattern 174 may contact an upper surface of the metal silicide film 172. In an exemplary embodiment, the conduction barrier pattern 174 may include a metal or a metal nitride. For example, the conduction barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or any combination thereof, but is not limited thereto. The contact plug 176 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), and aluminum (Al), combinations thereof, or any alloy thereof, but is not limited thereto.

[0080] An upper surface of each of the multiple source / drain contacts CA, each of the multiple capping insulating patterns 168, the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144 may be covered by and stacked with an upper insulating structure 180. The upper insulating structure 180 may contact the upper surfaces of the multiple source / drain contacts CA, the multiple capping insulating patterns 168, the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144. The upper insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184 sequentially stacked on each of the multiple source / drain contacts CA, the multiple capping insulating patterns 168, and the inter-gate insulating film 144. The etch stop film 182 may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or any combination thereof. The interlayer insulating film 184 may include an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant K in a range from about 2.2 to about 2.4, or any combination thereof. For example, the interlayer insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or any combination thereof, but is not limited thereto.

[0081] Multiple source / drain via contacts VA can be respectively disposed on multiple source / drain contacts CA. Each of the multiple source / drain via contacts VA can penetrate the upper insulating structure 180 and contact the source / drain contact CA. The upper insulating structure 180 can contact side surfaces of the multiple source / drain via contacts VA. The upper surface of the upper insulating structure 180 and the upper surfaces of the multiple source / drain via contacts VA can be coplanar. Multiple source / drain regions SD can be configured to be electrically connected to the multiple source / drain via contacts VA respectively through the metal silicide film 172 and the source / drain contacts CA. The lower surface of each of the multiple source / drain via contacts VA can contact the upper surface of the source / drain contact CA. Each of the multiple source / drain via contacts VA can be formed of or include molybdenum (Mo) or tungsten (W), but is not limited thereto.

[0082] The upper surface of the upper insulating structure 180 can be covered by and stacked with the upper insulating film 192. The upper insulating film 192 can contact the upper surface of the upper insulating structure 180. The constituent material of the upper insulating film 192 can be substantially the same as the constituent material described above with respect to the interlayer insulating film 184.

[0083] Multiple upper wiring layers M1 can be provided to penetrate the upper insulating film 192. Each of the multiple upper wiring layers M1 can be electrically connected to one source / drain via contact VA selected from among the multiple source / drain via contacts VA located below the multiple upper wiring layers M1. For example, each of the multiple upper wiring layers M1 can be connected to the upper surface of the corresponding source / drain via contact VA. The multiple upper wiring layers M1 can be formed of or include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), any combination thereof, or any alloy thereof, but is not limited thereto.

[0084] According to an embodiment of the inventive concept, since the source / drain contact CA is electrically connected to the source / drain barrier layer 132 and the source / drain body layer 134 through the relatively highly doped source / drain capping layer 136, the resistance (e.g., contact resistivity) between the source / drain contact CA and the source / drain region SD can be reduced, thereby reducing the voltage drop.

[0085] In addition, since the source / drain capping layer 136 is formed in a shape including the tip PT1, defects in the source / drain capping layer 136 can be relatively reduced during epitaxial growth of the source / drain capping layer 136. Accordingly, an integrated circuit device 10 having improved reliability can be provided.

[0086] Figure 5 is a view for explaining the layout of the integrated circuit device 20 according to other exemplary embodiments. Fig. 6A is along Figure 5 a cross-sectional view taken along the line X1-X1'. Figure 6B is along Figure 5 a cross-sectional view taken along the line Y1-Y1'. Figure 6C is along Figure 5 a cross-sectional view taken along the line Y2-Y2'. Figure 7 is Fig. 6A an enlarged view of the region EX3 in

[0087] Referring to Figure 5 , Fig. 6A , Figure 6B , Figure 6C and Figure 7 , an integrated circuit device 20 including a field effect transistor having a gate-all-around structure is described, the gate-all-around structure including an active region having a nanowire or nanosheet shape and a gate surrounding the active region. For example, the integrated circuit device 20 may include a multi-bridge channel FET (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 20 may include a planar FET (FET) device, a fin-shaped FET device, etc. The integrated circuit device 20 may form Figure 1 a part of the plurality of logic units LC shown in

[0088] Since the integrated circuit device 20 is constructed substantially and similarly to the integrated circuit device 10 described with reference to Figure 2 , Figure 3A , Figure 3B and Figure 4 , hereinafter, the differences from the integrated circuit device 10 will be mainly described. Redundant descriptions will not be repeated.

[0089] The integrated circuit device 20 may include a gap-fill insulating film 202, and the gap-fill insulating film 202 may include a gap-fill insulating region G1 defining a trench region T1' in the gap-fill insulating film 202. The gap-fill insulating region G1 may extend longitudinally in a first horizontal direction (e.g., the X direction) and may extend parallel to each other.

[0090] In an exemplary embodiment, the gap-fill insulating film 202 may be formed of or include silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or any combination thereof, but is not limited thereto. The terms "SiN", "SiO", "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", "SiOC" used in this specification refer to materials composed of the elements included in each term and are not chemical formulas indicating stoichiometric relationships. In other exemplary embodiments, the gap-fill insulating film 202 may include a low-k dielectric film. The low-k dielectric film may include fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon oxide, porous organosilicate glass, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or any combination thereof, but is not limited to the above examples.

[0091] The device isolation film 112 may be disposed on the trench region T1' of the gap-fill insulating film 202. For example, the device isolation film 112 may contact the sidewalls of the gap-fill insulating region G1 in the trench region T1'. The device isolation film 112 may be configured to be substantially the same as the configuration described above in the description of the integrated circuit device 10.

[0092] A plurality of gate lines 160 may be disposed on the gap-fill insulating region G1. Each of the plurality of gate lines 160 may extend longitudinally in a second horizontal direction (e.g., the Y direction). On the gap-fill insulating region G1, a plurality of nanosheet stacks NSS may be disposed in a region where the gap-fill insulating region G1 intersects with the plurality of gate lines 160. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the upper surface GT of the gap-fill insulating region G1 at a position spaced apart from the upper surface GT of the gap-fill insulating region G1 in a vertical direction (e.g., the Z direction).

[0093] The plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 stacked on top of each other in a vertical direction (e.g., the Z direction). The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (distances in the Z direction) from the upper surface GT of the gap-fill insulating region G1.

[0094] Figure 5The case where the planar shape of the nanosheet stack NSS is approximately square is shown, but is not limited thereto. In addition, this example shows a configuration in which a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are provided on the gap-fill insulating film 202, and the plurality of nanosheet stacks NSS are arranged in a row on the gap-fill insulating film 202 in a first horizontal direction (e.g., the X direction). However, the number of nanosheet stacks NSS and gate lines 160 provided on the gap-fill insulating film 202 is not particularly limited.

[0095] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS can each be used as a channel region. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can each be configured to be substantially the same as the configuration described above in the description of the integrated circuit device 10.

[0096] Each of the plurality of gate lines 160 can include a main gate portion 160M and a plurality of sub-gate portions 160S. The plurality of gate lines 160, the main gate portion 160M and the plurality of sub-gate portions 160S constituting the plurality of gate lines 160 can be respectively configured to be substantially the same as those described above in the description of the integrated circuit device 10.

[0097] The placeholder PH can be provided on the gap-fill insulating region G1. In the example embodiment, the placeholder PH can include a SiGe film. For example, the placeholder PH can include a single-crystalline SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or any combination thereof. The upper surface of the placeholder PH can be coplanar with the upper surface of the gap-fill insulating region G1.

[0098] The vertical level of the lower surface PB of the placeholder PH can be lower than the vertical level of the upper surface GT of the gap-fill insulating region G1. Referring together Fig.23A and Fig. 23B , the lower surface PB of the placeholder PH can correspond to the lower surfaces of the plurality of active region recesses R1' of the integrated circuit device 20. Referring together Figure 3A and Figure 3B , the vertical level of the lower surface PB of the placeholder PH of the integrated circuit device 20 can be relatively lower compared to the vertical level of the plurality of active region recesses R1 of the integrated circuit device 10.

[0099] In the example embodiment, the Ge content in the placeholder PH can be constant. The SiGe film constituting the placeholder PH can have a constant Ge content selected in the range from about 5 atomic % to about 60 atomic % (e.g., in the range from about 10 atomic % to about 40 atomic %). However, the Ge content in the SiGe film constituting the placeholder PH can be variably selected within a range such that the placeholder PH and the fin-type active region F1 (see Fig.24A) have different etching selectivities between them.

[0100] Multiple source / drain regions SD may be disposed between multiple gate lines 160. The multiple source / drain regions SD may each be disposed adjacent to at least one gate line 160 selected from the multiple gate lines 160. The multiple source / drain regions SD may have surfaces facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS, respectively. For example, the multiple source / drain regions SD may be stacked with the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in a first horizontal direction (e.g., the X direction).

[0101] The gate dielectric film 152 may be disposed between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may contact the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 may be configured to be substantially the same as the configuration described above in the description of the integrated circuit device 10.

[0102] According to an example embodiment, each of the gate dielectric film 152 and the gate line 160 may include a portion stacked with the multiple nanosheet stacks NSS in a vertical direction (e.g., the Z direction).

[0103] According to an example embodiment, multiple transistors may be formed in a region where the multiple nanosheet stacks NSS, the gate line 160, and the gate dielectric film 152 are stacked with each other. The multiple transistors may include nanosheet transistors. According to an example embodiment, the multiple transistors may include PMOS transistors and NMOS transistors. For example, each of the multiple transistors may be composed of at least one nanosheet stack NSS, a gate dielectric film 152 surrounding the at least one nanosheet stack NSS and the gate line 160, and multiple source / drain regions SD facing the at least one nanosheet stack NSS in a first horizontal direction (e.g., the X direction).

[0104] In an example embodiment, the multiple source / drain regions SD may include a first source / drain region SDa and a second source / drain region SDb. The first source / drain region SDa may be connected to the source / drain contact CA through a metal silicide film 172, and the second source / drain region SDb may be connected to the backside source / drain contact BCA through a backside metal silicide film 222.

[0105] In some embodiments, the first source / drain region SDa and the second source / drain region SDb may be spaced apart from each other in a first horizontal direction (e.g., the X direction), and a nanosheet stack NSS is disposed between the first source / drain region SDa and the second source / drain region SDb. For example, the first source / drain region SDa may be used as a drain region, and the second source / drain region SDb may be used as a source region. In some embodiments, the first source / drain region SDa and the second source / drain region SDb may have the same shape, but the shape is not limited thereto and may be different shapes. For example, the first source / drain region SDa and the second source / drain region SDb may have different horizontal widths or different vertical thicknesses.

[0106] In an exemplary embodiment, each of the plurality of source / drain regions SD may have a multi-layer structure. In some embodiments, the plurality of source / drain regions SD may each include a source / drain barrier layer 132 and a source / drain body layer 134 on the source / drain barrier layer 132. For example, in a selected source / drain region SD among the plurality of source / drain regions SD, the source / drain barrier layer 132 may conformally extend on the upper surface of the placeholder PH, the sidewalls of the plurality of nanosheet stacks NSS adjacent to the source / drain barrier layer 132, and the sidewalls of the gate dielectric film 152. For example, the source / drain barrier layer 132 may contact the upper surface of the placeholder PH, the sidewalls of the plurality of nanosheet stacks NSS adjacent to the source / drain barrier layer 132, and the sidewalls of the gate dielectric film 152. The source / drain body layer 134 may partially fill the space between the plurality of gate lines 160 on the source / drain barrier layer 132.

[0107] In an exemplary embodiment, the first source / drain region SDa may include a source / drain barrier layer 132 and a source / drain capping layer 136 on the source / drain body layer 134. The lower surface of the source / drain barrier layer 132 may be coplanar with the lower surface of the gate dielectric film 152 under the first nanosheet N1 adjacent to the first source / drain region SDa. The source / drain capping layer 136 may be disposed in a source / drain recess R2 that is recessed inward from the upper surface of the first source / drain region SDa. The source / drain capping layer 136 and the source / drain recess R2 may be configured to be substantially the same as the configuration described above in the description of the integrated circuit device 10.

[0108] In an exemplary embodiment, the second source / drain region SDb may include a source / drain blocking layer 132, a source / drain body layer 134, and a backside source / drain covering layer 212 under the source / drain body layer 134. The backside source / drain covering layer 212 may be disposed in a backside source / drain recess R3 that is recessed inward from the lower surface of the second source / drain region SDb. In some embodiments, the backside source / drain covering layer 212 may be disposed in the backside source / drain recess R3, and the backside source / drain recess R3 is formed by recessing a part of the source / drain blocking layer 132 (e.g., a part of the source / drain blocking layer 132 that covers the lower surface of the source / drain body layer 134 and is stacked with the lower surface of the source / drain body layer 134) and a part of the source / drain body layer 134. The backside source / drain covering layer 212 may penetrate through the source / drain blocking layer 132 and a part of the source / drain body layer 134. The backside source / drain covering layer 212 may contact the source / drain blocking layer 132 and the source / drain body layer 134. In the exemplary embodiment, the backside source / drain covering layer 212 may be surrounded by the source / drain blocking layer 132 and the source / drain body layer 134.

[0109] The backside source / drain recess R3 formed by recessing a part of the source / drain blocking layer 132 and a part of the source / drain body layer 134 may overlap with at least one nanosheet (e.g., the first nanosheet N1, the second nanosheet N2, or the third nanosheet N3) in a first horizontal direction (e.g., the X direction). In other words, the backside source / drain covering layer 212 may overlap with at least one nanosheet (e.g., the first nanosheet N1, the second nanosheet N2, or the third nanosheet N3) in the first horizontal direction (e.g., the X direction).

[0110] In some embodiments, the backside source / drain covering layer 212 may include a tip PT2 (or at least one tip PT2), and the tip PT2 may include a vertex VT2. The tip PT2 may be an upper region of the backside source / drain covering layer 212, and the vertex VT2 may be a part of the tip PT2 that has the highest vertical level in the vertical direction (e.g., the Z direction). However, this is an example, and the tip PT2 may include at least one vertex.

[0111] In the process of manufacturing the integrated circuit device 20, after forming the source / drain barrier layer 132 and the source / drain body layer 134, a backside source / drain recess R3 including an angular shape may be formed by etching a part of the source / drain barrier layer 132 and the source / drain body layer 134. Since the backside source / drain capping layer 212 epitaxially grows on the backside source / drain recess R3 having an angular shape, the backside source / drain capping layer 212 may include a tip PT2. The backside source / drain capping layer 212 including the tip PT2 may have relatively few defects in the film that may occur due to epitaxial growth. For example, the epitaxial growth of the backside source / drain capping layer 212 is described below in the description of the method of manufacturing the integrated circuit device 20. The backside source / drain capping layer 212 may include a crystalline material.

[0112] In an exemplary embodiment, a first group of source / drain regions SD of the plurality of source / drain regions SD may be configured as PMOS transistors. In this case, the plurality of source / drain regions SD may include Si doped with a p-type dopant 1-x Ge x layer (here, 0.0 < x ≤ 0.6).

[0113] In some embodiments, the Ge content ratio in the source / drain body layer 134 may be greater than the Ge content ratio in the source / drain barrier layer 132, and the Ge content ratios in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be greater than the Ge content ratio in the source / drain body layer 134. In some embodiments, the Ge content ratio in the source / drain barrier layer 132 may be greater than about 0.0 atomic % and less than or equal to about 20 atomic % (for example, in the range from about 10 atomic % to about 20 atomic %). The Ge content ratio in the source / drain body layer 134 may be in the range from about 30 atomic % to about 45 atomic % (for example, in the range from about 30 atomic % to about 40 atomic %). The Ge content ratios in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be greater than about 40 atomic % and less than or equal to about 70 atomic % (for example, in the range from about 45 atomic % to about 55 atomic %). However, the inventive concept is not limited to the above examples.

[0114] In some embodiments, in the source / drain region SD, the p-type dopant content ratio in the source / drain body layer 134 may be greater than the p-type dopant content ratio in the source / drain barrier layer 132, and the p-type dopant content ratios in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be greater than the p-type dopant content ratio in the source / drain body layer 134. For example, the concentrations of the p-type dopant in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be in the range from about 5×10 20 at / cm3 to about 2×10 21 at / cm 3 In some embodiments, the p-type dopant may be at least one selected from boron (B) and gallium (Ga), but is not limited thereto.

[0115] In other exemplary embodiments, a second set of source / drain regions SD of the plurality of source / drain regions SD may be configured as NMOS transistors. In this case, the source / drain regions SD may include an Si layer doped with an n-type dopant, an undoped Si layer, or any combination thereof.

[0116] In some embodiments, the source / drain blocking layer 132 may include an undoped Si layer, and the source / drain body layer 134, the source / drain capping layer 136, and the backside source / drain capping layer 212 may include an Si layer doped with an n-type dopant. In some other embodiments, in the source / drain regions SD, the source / drain blocking layer 132, the source / drain body layer 134, the source / drain capping layer 136, and the backside source / drain capping layer 212 may include an Si layer doped with an n-type dopant. The n-type dopant content ratio in the source / drain body layer 134 may be greater than the n-type dopant content ratio in the source / drain blocking layer 132, and the n-type dopant content ratio in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be greater than the n-type dopant content ratio in the source / drain body layer 134. For example, the concentration of the n-type dopant in the source / drain capping layer 136 and the backside source / drain capping layer 212 may be in the range from about 5×10 20 at / cm 3 to about 2×10 21 at / cm 3 In some embodiments, the n-type dopant may be at least one selected from P (phosphorus), As (arsenic), and Sb (antimony), but is not limited thereto.

[0117] In some embodiments, in a first set of source / drain regions SD that constitute PMOS transistors among the plurality of source / drain regions SD, the tip PT1 of the source / drain capping layer 136 may be superimposed in a first horizontal direction (e.g., the X direction) on the sub-gate portions 160S among the plurality of sub-gate portions 160S that surround the lower surface of the third nanosheet N3 located at the top.

[0118] In some other embodiments, in a second set of source / drain regions SD that constitute NMOS transistors among the plurality of source / drain regions SD, the tip PT1 of the source / drain capping layer 136 may be superimposed in a first horizontal direction (e.g., the X direction) on the sub-gate portions 160S among the plurality of sub-gate portions 160S that surround the lower surface of the first nanosheet N1 located at the bottom.

[0119] In an exemplary embodiment, a first group of source / drain regions SD that constitute PMOS transistors among the plurality of source / drain regions SD are electrically connected to a plurality of power supply lines VDD (see Figure 1 ), and thus can receive a voltage of a positive potential, and a second group of source / drain regions SD that constitute NMOS transistors among the plurality of source / drain regions SD are electrically connected to a plurality of ground lines VSS (see Figure 1 ), and thus can receive a ground voltage or a voltage of a negative potential.

[0120] A metal silicide film 172 may be provided on the upper surface of the first source / drain region SDa. The metal silicide film 172 may include a metal composed of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide, but is not limited thereto.

[0121] A cover insulating pattern 168 may be provided on the gate dielectric film 152 and the gate line 160. Two sidewalls of each of the gate line 160 and the cover insulating pattern 168 may be covered by and stacked with an outer insulating spacer 118. A plurality of recessed side insulating spacers 119 may respectively cover one sidewall of the source / drain region SD and another sidewall facing the one sidewall and be stacked with the one sidewall of the source / drain region SD and the another sidewall facing the one sidewall, and may be provided on the upper surface of the device isolation film 112. The plurality of recessed side insulating spacers 119 may contact the sidewalls of the source / drain region SD and the upper surface of the device isolation film 112. The plurality of source / drain regions SD, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered by and stacked with an insulating liner 142. The insulating liner 142 and the inter-gate insulating film 144 may be sequentially provided on the plurality of source / drain regions SD and the plurality of metal silicide films 172. The cover insulating pattern 168, the outer insulating spacer 118, the plurality of recessed side insulating spacers 119, the insulating liner 142, and the inter-gate insulating film 144 may be substantially the same as those described above in the description of the integrated circuit device 10.

[0122] The source / drain contact CA can be disposed on the first source / drain region SDa. The source / drain contact CA can penetrate a part of the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (e.g., the Z direction), and can contact the metal silicide film 172. The inter-gate insulating film 144 and the insulating liner 142 can contact the side surfaces of a plurality of source / drain contacts CA. The source / drain contact CA can be electrically connected to the first source / drain region SDa through the metal silicide film 172. The source / drain contact CA can include a conduction blocking pattern 174 and a contact plug 176 that are sequentially stacked on the first source / drain region SDa. The upper surfaces of the plurality of source / drain contacts CA, the plurality of covering insulating patterns 168, the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144 can be coplanar.

[0123] The upper surface of each of the source / drain contact CA, the plurality of covering insulating patterns 168, the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144 can be covered by and stacked with the upper insulating structure 180. The upper insulating structure 180 can contact the upper surfaces of the plurality of source / drain contacts CA, the plurality of covering insulating patterns 168, the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144. The source / drain via contact VA can be disposed on the source / drain contact CA. The source / drain via contacts VA can each penetrate the upper insulating structure 180 and contact the source / drain contact CA. The upper insulating structure 180 can contact the side surfaces of the plurality of source / drain via contacts VA. The upper surfaces of the upper insulating structure 180 and the plurality of source / drain via contacts VA can be coplanar. The upper surface of the upper insulating structure 180 can be covered by and stacked with the upper insulating film 192. The upper insulating film 192 can contact the upper surface of the upper insulating structure 180. The upper wiring layer M1 can be disposed to penetrate the upper insulating film 192. For example, a plurality of upper wiring layers M1 can contact the upper surfaces of the source / drain via contacts VA. The source / drain contact CA, the upper insulating structure 180, the source / drain via contact VA, the upper insulating film 192, and the upper wiring layer M1 can be constructed to be substantially the same as the construction described above in the description of the integrated circuit device 10.

[0124] The backside metal silicide film 222 can be disposed on the lower surface of the second source / drain region SDb. The backside metal silicide film 222 can include a metal composed of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the backside metal silicide film 222 can include titanium silicide, but is not limited thereto.

[0125] In an exemplary embodiment, the dorsal source / drain capping layer 212 may cover a portion of the upper surface of the dorsal metal silicide film 222 and overlap with a portion of the upper surface of the dorsal metal silicide film 222, and the source / drain barrier layer 132 or the source / drain body layer 134 may cover the remaining portion of the upper surface of the dorsal metal silicide film 222 and overlap with the remaining portion of the upper surface of the dorsal metal silicide film 222. The dorsal metal silicide film 222 may contact the lower surface of the dorsal source / drain capping layer 212, the lower surface of the source / drain barrier layer 132, and the side surface of the gap-fill insulating film 202. In other exemplary embodiments, the dorsal source / drain capping layer 212 may cover the upper surface of the dorsal metal silicide film 222 and overlap with the upper surface of the dorsal metal silicide film 222.

[0126] The dorsal source / drain contact BCA may be disposed on the second source / drain region SDb. The dorsal source / drain contact BCA may penetrate the gap-fill insulating region G1 in a vertical direction (e.g., the Z direction) and contact the dorsal metal silicide film 222. The dorsal source / drain contact BCA may be electrically connected to the second source / drain region SDb through the dorsal metal silicide film 222. The dorsal source / drain contact BCA may include a conduction barrier pattern 224 and a contact plug 226 sequentially stacked on the second source / drain region SDb. The conduction barrier pattern 224 may surround the upper surface and sidewalls of the contact plug 226 and may contact the upper surface and sidewalls of the contact plug 226. The conduction barrier pattern 224 may be disposed between the dorsal metal silicide film 222 and the contact plug 226. The conduction barrier pattern 224 may contact the lower surface of the dorsal metal silicide film 222. The upper surfaces of each of the dorsal metal silicide film 222, the conduction barrier pattern 224, and the contact plug 226 may have a convex shape in a vertical direction (e.g., the Z direction). For example, the upper surfaces of the dorsal metal silicide film 222 and the conduction barrier pattern 224 may overlap with the dorsal source / drain capping layer 212 in a first horizontal direction (e.g., the X direction), and the upper surface of the contact plug 226 may overlap with the dorsal metal silicide film 222 in a first horizontal direction (e.g., the X direction). In an exemplary embodiment, the conduction barrier pattern 224 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or any combination thereof, but is not limited thereto. The contact plug 226 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), and aluminum (Al), any combination thereof, or any alloy thereof, but is not limited thereto.

[0127] According to an embodiment of the inventive concept, since the relatively highly doped back source / drain overlay 212 is connected to the back source / drain contact BCA through the back metal silicide film 222, the resistance (e.g., contact resistivity) between the back source / drain contact BCA and the source / drain region SD is reduced, thereby reducing the voltage drop of the integrated circuit device 20.

[0128] In addition, since the back source / drain overlay 212 is formed in a shape including a tip PT2, defects in the back source / drain overlay 212 can be relatively reduced during the epitaxial growth of the back source / drain overlay 212. Accordingly, the integrated circuit device 20 with improved reliability can be provided.

[0129] Figure 8 is a view for explaining an integrated circuit device 20a according to other exemplary embodiments. Figure 8 shows a portion corresponding to the region EX3 in Fig. 6A .

[0130] Since the integrated circuit device 20a is substantially and similarly configured to the integrated circuit device 20 described with reference to Figure 5 , Fig. 6A , Figure 6B , Figure 6C and Figure 7 , differences from the integrated circuit device 20 will be mainly described below. Redundant descriptions will not be repeated.

[0131] In an exemplary embodiment, the plurality of source / drain regions SD may include a first source / drain region SDa (see Fig. 6A ) and a second source / drain region SDb. The first source / drain region SDa may be connected to the source / drain contact CA through the metal silicide film 172, and the second source / drain region SDb may be connected to the back source / drain contact BCA through the back metal silicide film 222.

[0132] In an exemplary embodiment, the second source / drain region SDb may include a source / drain barrier layer 132, a source / drain body layer 134, and a back source / drain overlay 212a on the source / drain body layer 134. The back source / drain overlay 212a may be disposed in a back source / drain recess R3 that is recessed inward from the lower surface of the second source / drain region SDb. The back source / drain overlay 212a may penetrate through the source / drain barrier layer 132 and a part of the source / drain body layer 134.

[0133] The dorsal source / drain capping layer 212a may include a first capping portion 212a_1 and a second capping portion 212a_2. The first capping portion 212a_1 is stacked with the source / drain blocking layer 132 and the source / drain body layer 134 in a first horizontal direction (e.g., the X direction), and the second capping portion 212a_2 is not stacked with the source / drain blocking layer 132 and the source / drain body layer 134 in the first horizontal direction (e.g., the X direction). The first capping portion 212a_1 may include a tip PT2.

[0134] The sidewalls of the first capping portion 212a_1 may be surrounded by the source / drain blocking layer 132 and the source / drain body layer 134, and the sidewalls of the second capping portion 212a_2 may be surrounded by the gap-fill insulating region G1 of the gap-fill insulating film 202. For example, the sidewalls of the first capping portion 212a_1 may contact the source / drain blocking layer 132 and the source / drain body layer 134, the sidewalls of the second capping portion 212a_2 may contact the gap-fill insulating region G1 of the gap-fill insulating film 202, and the upper surface of the second capping portion 212a_2 may contact the lower surface of the source / drain blocking layer 132. The first capping portion 212a_1 may be a portion protruding from the second capping portion 212a_2 toward the source / drain body layer 134. The upper surface of the second capping portion 212a_2 may be covered by and stacked with the first capping portion 212a_1 and the source / drain blocking layer 132, and the lower surface of the second capping portion 212a_2 may be covered and stacked with the dorsal metal silicide film 222. The upper surfaces of each of the dorsal metal silicide film 222, the conduction blocking pattern 224, and the contact plug 226 may have a planar shape.

[0135] Fig. 9 is a diagram for explaining an integrated circuit device 20b according to other exemplary embodiments. Fig. 9 shows the part corresponding to the region EX3 in Fig. 6A

[0136] Since the integrated circuit device 20b is constructed substantially and similarly to the integrated circuit device 20 described with reference to Figure 5 , Fig. 6A , Figure 6B , Figure 6C and Figure 7 , the differences from the integrated circuit device 20 will be mainly described below. Redundant descriptions will not be repeated.

[0137] In an exemplary embodiment, the multiple source / drain regions SD may include a first source / drain region SDa (see Fig. 6A) and a second source / drain region SDb. The first source / drain region SDa can be connected to the source / drain contact CA through the metal silicide film 172, and the second source / drain region SDb can be connected to the backside source / drain contact BCA through the backside metal silicide film 222.

[0138] In an exemplary embodiment, the second source / drain region SDb may include a source / drain barrier layer 132, a source / drain body layer 134, and a backside source / drain capping layer 212b on the source / drain body layer 134. The backside source / drain capping layer 212b may be disposed in a backside source / drain recess R3 that is recessed inward from the lower surface of the second source / drain region SDb. The backside source / drain capping layer 212b may penetrate the source / drain barrier layer 132 and a portion of the source / drain body layer 134.

[0139] The backside source / drain capping layer 212b may include a first capping portion 212b_1 and a second capping portion 212b_2. The first capping portion 212b_1 overlaps with the source / drain barrier layer 132 and the source / drain body layer 134 in a first horizontal direction (e.g., the X direction), and the second capping portion 212b_2 does not overlap with the source / drain barrier layer 132 and the source / drain body layer 134 in the first horizontal direction (e.g., the X direction). The first capping portion 212b_1 may include a tip PT2.

[0140] The sidewalls of the first capping portion 212b_1 may be surrounded by the source / drain barrier layer 132 and the source / drain body layer 134, and the sidewalls of the second capping portion 212b_2 may be surrounded by a gap-fill insulating region G1 of the gap-fill insulating film 202. For example, the sidewalls of the first capping portion 212b_1 may contact the source / drain barrier layer 132 and the source / drain body layer 134, the sidewalls of the second capping portion 212b_2 may contact the gap-fill insulating region G1 of the gap-fill insulating film 202, and the upper surface of the second capping portion 212b_2 may contact the lower surface of the source / drain barrier layer 132. The first capping portion 212b_1 may be a portion protruding from the second capping portion 212b_2 toward the source / drain body layer 134, and the upper surface of the second capping portion 212b_2 may be covered by and overlap with the first capping portion 212b_1 and the source / drain barrier layer 132.

[0141] The second covering portion 212b_2 may include a groove GR1 recessed from the lower surface of the second covering portion 212b_2 to the inside of the second covering portion 212b_2. The back metal silicide film 222 may be disposed on the groove GR1. In some embodiments, the second covering portion 212b_2 may overlap with the back metal silicide film 222 in the first horizontal direction (e.g., the X direction). In addition, in some embodiments, the second covering portion 212b_2 may overlap with a portion of the back source / drain contact BCA disposed in the back metal silicide film 222 in the first horizontal direction (e.g., the X direction). Due to the groove GR1, the contact area between the back source / drain covering layer 212b and the back metal silicide film 222 may be relatively increased.

[0142] The back insulating liner 214 may be disposed on the back source / drain capping layer 212 b and the back metal silicide film 222. For example, an upper surface of the back insulating liner 214 may contact lower surfaces of the back source / drain capping layer 212 b and the back metal silicide film 222. The back insulating liner 214 may be disposed between the back source / drain contacts BCA and the gap-filling insulating region G1 of the gap-filling insulating film 202. In example embodiments, the back insulating liner 214 may include an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant K in a range from about 2.2 to about 2.4, or any combination thereof. For example, the back insulating liner 214 may include a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or any combination thereof, but is not limited thereto.

[0143] Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A , Fig. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A and Fig. 22B 1 is a diagram illustrating a process sequence of a method of manufacturing an integrated circuit device 10 according to example embodiments.

[0144] Specifically, Fig.10 , Fig.11 , Fig. 12B , Fig.13 , Fig. 14B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B is a view corresponding to a cross-section along the Y1 - Y1' line in Figure 2 . Fig. 12A , Fig.14A , Fig.15 , Fig.16 , Fig.17 , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A is a view corresponding to a cross-section along the X1 - X1' line in Figure 2 .

[0145] Figure 2 , Figure 3A , Figure 3B and Figure 4 in the same reference numerals in

[0146] Refer to Fig.10 , multiple sacrificial semiconductor layers 103 and multiple nanosheet semiconductor layers NS can be alternately stacked one layer at a time on a substrate 102. The substrate 102 can include a semiconductor (such as Si or Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, InGaAs, or InP). The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", "InP" used in this specification refer to materials composed of the elements included in each term and do not represent chemical formulas indicating stoichiometric relationships. For example, the substrate 102 can include a bulk Si substrate.

[0147] The multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS can include semiconductor materials having different etching selectivities from each other. In an exemplary embodiment, the multiple nanosheet semiconductor layers NS can include Si layers, and the multiple sacrificial semiconductor layers 103 can include SiGe films. In an example embodiment, the Ge content within the multiple sacrificial semiconductor layers 103 can be constant. The SiGe films constituting the multiple sacrificial semiconductor layers 103 can have a constant Ge content selected in the range of about 5 atomic % to about 60 atomic % (e.g., about 10 atomic % to about 40 atomic %). The Ge content in the SiGe films constituting the multiple sacrificial semiconductor layers 103 can be selected in various ways as needed.

[0148] Refer to Fig.11 , in Fig.10 After forming a mask pattern MP1 on the obtained product, a fin-shaped active region F1 can be formed on the substrate 102 by etching a plurality of sacrificial semiconductor layers 103, a plurality of nanosheet semiconductor layers NS, and a part of the substrate 102 using the mask pattern MP1 as an etching mask. A plurality of trench regions T1 can be defined on the substrate 102 through the fin-shaped active region F1. In an exemplary embodiment, the mask pattern MP1 can have a stacked structure of an oxide film pattern and a silicon nitride film pattern. The mask patterns MP1 can extend parallel to each other in a first horizontal direction (e.g., the X direction) on the substrate 102. The stacked structures of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS can remain on the upper surface of each fin of the fin-shaped active region F1.

[0149] A device isolation insulating film (or referred to as "device isolation insulating layer") P112 can be formed on the obtained product. The device isolation insulating film P112 can be formed to a thickness sufficient to fill the remaining space of the plurality of trench regions T1 on the top of the substrate 102. The device isolation insulating film P112 can include a silicon oxide film.

[0150] To form the device isolation insulating film P112, processes such as plasma enhanced chemical vapor deposition (PECVD), high density plasma CVD (HDP CVD), inductively coupled plasma CVD (ICP CVD), capacitively coupled plasma CVD (CCP CVD), flowable chemical vapor deposition (FCVD), spin coating, etc. can be used.

[0151] Referring to Fig. 12A and Fig. 12B After planarizing the obtained product such that the upper surface of the mask pattern MP1 is exposed, the exposed mask pattern MP1 is removed, and then a device isolation film 112 can be formed by performing a recess process for removing a part of the device isolation insulating film P112. As a result, the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS (see Fig.11 ) can protrude onto the upper surface of the device isolation film 112. Fig.11 )

[0152] To perform the recess process of the device isolation insulating layer P112, dry etching, wet etching, or a combination of dry and wet etching processes can be used. At this time, a wet etching process using NH4OH, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), etc. as an etchant, or a dry etching process (such as inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), reactive ion etching (RIE)) can be used. If a dry etching process is used to perform the recess process of the device isolation insulating film P112, a gas containing fluorine (such as CF4), a gas containing chlorine (such as Cl2), HBr, etc. can be used as an etching gas.

[0153] A plurality of dummy gate structures DGS can be formed on the stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. Each of the plurality of dummy gate structures DGS can be formed to longitudinally extend in the second horizontal direction (e.g., the Y direction). Each of the plurality of dummy gate structures DGS can have a structure in which an oxide film D122, a dummy gate layer D124, and a cover layer D126 are sequentially stacked. In an exemplary embodiment, the oxide film D122 can be a film obtained by oxidizing the surface of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS (see Fig. 12A ). The dummy gate layer D124 can include polysilicon, and the cover layer D126 can include a silicon nitride film.

[0154] After forming a plurality of outer insulating spacers 118 that cover two sidewalls of each of the plurality of dummy gate structures DGS and are stacked with the two sidewalls of each of the plurality of dummy gate structures DGS, a part of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS is etched using the plurality of dummy gate structures DGS and the plurality of outer insulating spacers 118 as an etching mask to divide the plurality of nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS each including a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. To etch a part of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS, dry etching, wet etching, or any combination thereof can be used.

[0155] Thereafter, a plurality of active region recesses R1 can be formed by etching a part of the exposed fin-type active region F1 that is exposed by etching a part of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. To form the plurality of active region recesses R1, etching can be performed by using dry etching, wet etching, or any combination thereof. After forming the plurality of active region recesses R1, a plurality of recess side insulating spacers 119 adjacent to the plurality of active region recesses R1 can be formed on the device isolation film 112.

[0156] Referring to Fig.13 , a plurality of source / drain regions SD can be formed on a plurality of active region recesses R1.

[0157] To form the plurality of source / drain regions SD, a source / drain blocking layer 132 and a source / drain body layer 134 can be formed sequentially. The source / drain blocking layer 132 can be formed by epitaxially growing a semiconductor material from a surface of the fin-type active region F1 exposed from the bottom of the plurality of active region recesses R1 and sidewalls of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS, and the source / drain body layer 134 can be formed by epitaxially growing a semiconductor material from the source / drain blocking layer 132.

[0158] Referring to Fig.14A and Fig. 14B , after forming an insulating liner 142 covering the Fig.13 resulting product and stacking it with the Fig.13 resulting product and forming an inter-gate insulating film 144 on the insulating liner 142, a portion of each of the insulating liner 142 and the inter-gate insulating film 144 can be etched to expose the upper surfaces of the plurality of capping layers D126. Thereafter, the plurality of capping layers D126 are removed to expose the dummy gate layer D124, and a portion of each of the insulating liner 142 and the inter-gate insulating film 144 can be removed such that the upper surface of the inter-gate insulating film 144 and the upper surface of the dummy gate layer D124 are at substantially the same level.

[0159] Referring to Fig.15 , a gate space GS can be prepared by removing the dummy gate layer D124 and the oxide film D122 below the dummy gate layer D124 from the Fig.14A and Fig. 14B resulting product, and the plurality of nanosheet stacks NSS can be exposed through the gate space GS. Thereafter, the plurality of sacrificial semiconductor layers 103 remaining on the fin-type active region F1 are removed through the gate space GS, and the gate space GS can extend into the spaces between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 (e.g., the space between the first nanosheet N1 and the second nanosheet N2 and the space between the second nanosheet N2 and the third nanosheet N3) and the space between the first nanosheet N1 and the fin upper surface FT. In an exemplary embodiment, to selectively remove the plurality of sacrificial semiconductor layers 103, the difference in etching selectivity between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the plurality of sacrificial semiconductor layers 103 can be used.

[0160] A liquid or gas-phase etchant may be used to selectively remove the plurality of sacrificial semiconductor layers 103. In an exemplary embodiment, a CH3COOH-based etchant (e.g., an etchant including a mixture of CH3COOH, HNO3, and HF or an etchant including a mixture of CH3COOH, H2O2, and HF) may be used to selectively remove the plurality of sacrificial semiconductor layers 103, but the etchant is not limited to the above examples.

[0161] Referring to Fig.16 , in Fig.15 the resulting product of

[0162] Referring to Fig.17 , a gate line 160 that fills the gate space GS (see Fig.16 ) and covers the upper surface of the inter-gate insulating film 144 and is stacked with the upper surface of the inter-gate insulating film 144, and a covering insulating pattern 168 that covers the upper surfaces of each of the gate line 160 in the gate space GS and the gate dielectric film 152 and is stacked with the upper surfaces of each of the gate line 160 in the gate space GS and the gate dielectric film 152 may be formed on the gate dielectric film 152.

[0163] Referring to Fig.18A and Fig.18B , in Fig.17 the resulting product of

[0164] Referring to Fig.19A and 19B , a plurality of source / drain contact holes CAH may be formed to expose the plurality of source / drain regions SD through an insulating structure including the insulating liner 142 and the inter-gate insulating film 144. Some regions of the plurality of source / drain regions SD may be removed through the source / drain contact holes CAH by using an anisotropic etching process such that the plurality of source / drain contact holes CAH may extend longer toward the substrate 102.

[0164] Referring to Fig.19A and 19B , the source / drain regions SD that pass through Fig.18A and Fig.18BSome regions exposed by multiple source / drain contact holes CAH. For example, the etching process may include a dry etching process, or may include a reactive ion etching (RIE) process or an atomic layer etching (ALE) process. The etching process may use a gas including chlorine (such as Cl2) as the etching gas. Before and after the etching process, a cleaning process may be performed using a gas including carbon (C) or a gas including oxygen (O). Through the etching process, source / drain recesses R2 having a pointed shape toward the substrate 102 may be formed.

[0165] Referring Fig. 20A and Fig. 20B , a preliminary source / drain capping layer P136 may be formed on the source / drain recesses R2 of Fig.19A and Fig.19B . The preliminary source / drain capping layer P136 is formed by epitaxially growing a semiconductor material on the source / drain barrier layer 132 and / or the source / drain body layer 134 exposed through the source / drain recesses R2. Since the source / drain recesses R2 include a pointed shape, at the interface between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary source / drain capping layer P136, weakening of adhesion due to lattice constant mismatch between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary source / drain capping layer P136 may be reduced.

[0166] Referring Fig.21A and Fig. 21B , a part of the preliminary source / drain capping layer P136 of Fig. 20A and Fig. 20B may be consumed to form a metal silicide film 172. In an exemplary embodiment, to form the metal silicide film 172, a process of forming a metal liner (not shown) that conformally covers the exposed surface of the preliminary source / drain capping layer P136 and is stacked on the exposed surface of the preliminary source / drain capping layer P136 and a process of initiating a reaction between the preliminary source / drain capping layer P136 and the metal constituting the metal liner by heat-treating the metal liner may be included. After forming the metal silicide film 172, the remaining portion of the metal liner may be removed. In an exemplary embodiment, if the metal silicide film 172 includes a titanium silicide film, the metal liner may include a Ti film.

[0167] Thereafter, a source / drain contact CA including a conduction barrier pattern 174 and a contact plug 176 may be formed on the metal silicide film 172.

[0168] Referring Fig.22A and Fig. 22B , in Fig.21A and Fig. 21BIn the resulting product, an upper insulating structure 180 can be formed by sequentially forming an etch stop film 182 and an interlayer insulating film 184 that cover the upper surfaces of each of the gate insulating film 144, the plurality of source / drain contact members CA, and the plurality of covering insulating patterns 168 and are stacked on the upper surfaces of each of the gate insulating film 144, the plurality of source / drain contact members CA, and the plurality of covering insulating patterns 168, and a plurality of source / drain via contact members VA can be formed through the upper insulating structure 180 in the vertical direction (e.g., the Z direction) to connect to the plurality of source / drain contact members CA.

[0169] Thereafter, an upper insulating film 192 that covers the upper surface of the upper insulating structure 180 and is stacked on the upper surface of the upper insulating structure 180 can be formed, and a plurality of upper wiring layers M1 can be formed through the upper insulating film 192 in the vertical direction (e.g., the Z direction) to connect to the plurality of source / drain via contact members VA.

[0170] Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A , Fig.33B , Fig.34A , Fig.34B , Fig.35A and Fig.35B are diagrams showing the process sequence of a method for manufacturing an integrated circuit device 20 according to other exemplary embodiments.

[0171] Specifically, Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A , Fig.33A , Fig.34A and Fig.35A are related to along Figure 5The view corresponding to the cross-section of the line X1-X1' in Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B and Fig.29B are views corresponding to the cross-section of the line Y1-Y1' along Figure 5 in Fig.25C , Fig.29C , Fig. 30B , Fig.31B , Fig.32B , Fig.33B , Fig.34B and Fig.35B are views corresponding to the cross-section of the line Y2-Y2' along Figure 5 in

[0172] In Figure 5 , Fig. 6A , Figure 6B , Figure 6C and Figure 7 the same reference numerals indicate the same components and their detailed description will not be repeated.

[0173] Referring to Fig.23A and Fig. 23B , after performing the process described above with reference to Fig.10 and Fig.11 , the resulting product of Fig.11 is planarized such that the upper surface of the mask pattern MP1 is exposed and the exposed mask pattern MP1 is removed, and then, a device isolation film 112 can be formed by performing a recess process for removing a part of the device isolation insulating film P112. As a result, a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS (see Fig.11 ) can protrude onto the upper surface of the device isolation film 112.

[0174] To perform the recess process for removing the device isolation insulating layer P112, dry etching, wet etching, or a combination thereof can be used. At this time, a wet etching process using NH4OH, TMAH, KOH, etc. as an etchant, or a dry etching process (such as ICP, TCP, ECR, RIE) can be used. If a dry etching process is used to perform the recess process of the device isolation insulating film P112, a gas containing fluorine (such as CF4), a gas containing chlorine (such as Cl2), HBr, etc. can be used as an etching gas.

[0175] A plurality of dummy gate structures DGS may be formed on a stacked structure of a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS. Each of the plurality of dummy gate structures DGS may be formed to extend longitudinally in a second horizontal direction (e.g., the Y direction). Each of the plurality of dummy gate structures DGS may have a structure in which an oxide film D122, a dummy gate layer D124, and a capping layer D126 are stacked in sequence. In an exemplary embodiment, the oxide film D122 may be a film obtained by oxidizing the surface of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS (see Fig. 12A ). The dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride film.

[0176] After forming a plurality of outer insulating spacers 118 that cover two sidewalls of each of the plurality of dummy gate structures DGS and are stacked with the two sidewalls of each of the plurality of dummy gate structures DGS, a portion of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS is etched using the plurality of dummy gate structures DGS and the plurality of outer insulating spacers 118 as an etch mask to divide the plurality of nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS each including a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. To etch a portion of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS, dry etching, wet etching, or any combination thereof may be used.

[0177] Thereafter, a plurality of active region recesses R1 (or a plurality of active region recesses R1') may be formed by etching a portion of the fin-shaped active region F1 exposed by etching a portion of each of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS. To form the plurality of active region recesses R1, etching may be performed by using dry etching, wet etching, or any combination thereof. After forming the plurality of active region recesses R1, a plurality of recess side insulating spacers 119 adjacent to the plurality of active region recesses R1 may be formed on the device isolation film 112.

[0178] Referring to Fig.24A and Fig. 24B , a plurality of placeholders PH may be formed on the plurality of active region recesses R1. In an exemplary embodiment, the plurality of placeholders PH may include a SiGe film. For example, the plurality of placeholders PH may include a single crystal SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or any combination thereof.

[0179] In an exemplary embodiment, to form a plurality of placeholder bodies PH, various deposition processes (such as PECVD process, HDP CVD process, ICP CVD process, CCP CVD process, FCVD process, etc.) may be performed using a raw material including an element precursor. In other exemplary embodiments, to form a plurality of placeholder bodies PH, an LPCVD process, a SEG process, or a CDE process may be performed using a raw material including an elemental semiconductor precursor. The elemental semiconductor precursor may include a Si source containing element Si. As the Si source, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), etc. may be used, but the Si source is not limited thereto. Additionally, the elemental semiconductor precursor may include a Ge source containing element Ge. As the Ge source, germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H 10 ), dichlorogermane (Ge2H2Cl2), etc. may be used, but the Ge source is not limited thereto. For example, a plurality of placeholder bodies PH may be formed by epitaxially growing a SiGe film from the surfaces of the fin-shaped active region F1 exposed at the sidewalls and bottom of the active region recess R1. In this case, the plurality of placeholder bodies PH may include a single-crystalline SiGe film.

[0180] In an exemplary embodiment, the Ge content in the plurality of placeholder bodies PH may be constant. The SiGe film constituting the plurality of placeholder bodies PH may have a constant Ge content selected in the range of about 5 atomic % to about 60 atomic % (e.g., in the range of about 10 atomic % to about 40 atomic %). However, the Ge content in the SiGe film constituting the plurality of placeholder bodies PH may be variably selected within a range such that the etching selectivity between the plurality of placeholder bodies PH and the fin-shaped active region F1 is different.

[0181] Referring to Fig.25A and Fig.25B , a plurality of source / drain regions SD may be formed on the plurality of placeholder bodies PH.

[0182] To form a plurality of source / drain regions SD, a source / drain barrier layer 132 and a source / drain body layer 134 may be sequentially formed. The source / drain barrier layer 132 may be formed by epitaxially growing a semiconductor material from the surface of the plurality of placeholder bodies PH and the sidewalls of each of the first nanosheet N1, second nanosheet N2, and third nanosheet N3 included in the nanosheet stack NSS, and the source / drain body layer 134 may be formed by epitaxially growing a semiconductor material from the source / drain barrier layer 132.

[0183] Thereafter, by performing the reference Fig.14A and Fig. 14B , Fig.15 , Fig.16 and Fig.17 The described process is used to sequentially form the insulating liner 142, the inter-gate insulating film 144, the gate dielectric film 152, the gate line 160, and the covering insulating pattern 168.

[0184] Referring Figure 25A to Figure 25B and Figure 25C , in the resulting product of Figure 24A and Figure 24B , source / drain contact holes CAH can be formed, and the source / drain contact holes CAH expose selected source / drain regions SD among a plurality of source / drain regions SD through an insulating structure including the insulating liner 142 and the inter-gate insulating film 144. The source / drain contact holes CAH can be formed to extend toward the substrate 102 by removing a part of the source / drain regions SD using an anisotropic etching process passing through the source / drain contact holes CAH.

[0185] Referring Figure 26A to Figure 26B , the part of the source / drain regions SD exposed by the source / drain contact holes CAH of Figure 25A and Figure 25B can be removed by using an anisotropic etching process. For example, the etching process can include a dry etching process, or can include an RIE process or an ALE process. The etching process can use a gas including chlorine (such as, Cl2) as the etching gas. Before and after the etching process, a cleaning process can be performed using a gas including carbon (C) or a gas including oxygen (O). Through the etching process, source / drain recesses R2 having a tapered shape toward the substrate 102 can be formed.

[0186] Referring Figure 27A to Figure 27B , a preliminary source / drain covering layer P136 can be formed on the source / drain recesses R2 of Figure 26A and Figure 26B . The preliminary source / drain covering layer P136 is formed by epitaxially growing a semiconductor material on the source / drain barrier layer 132 and / or the source / drain body layer 134 exposed through the source / drain recesses R2. Since the source / drain recesses R2 include a tapered shape, the reduction in adhesion due to the lattice constant mismatch between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary source / drain covering layer P136 can be reduced at the interface between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary source / drain covering layer P136.

[0187] Referring Figure 28A to Figure 28B , Figure 27A and Figure 27BA portion of the preliminary source / drain capping layer P136 is used to form the metal silicide film 172. In an exemplary embodiment, to form the metal silicide film 172, a process may include forming a metal liner (not shown) that conformally covers the exposed surface of the preliminary source / drain capping layer P136 and is stacked with the exposed surface of the preliminary source / drain capping layer P136, and a process of initiating a reaction between the preliminary source / drain capping layer P136 and the metal constituting the metal liner by heat-treating the metal liner. After forming the metal silicide film 172, the remaining portion of the metal liner may be removed.

[0188] Thereafter, a source / drain contact CA including a conduction blocking pattern 174 and a contact plug 176 may be formed on the metal silicide film 172.

[0189] Referring to Figure 29A 、 Figure 29B and Figure 29C ,in Figure 28A and Figure 28B In the resulting product, an upper insulating structure 180 may be formed by sequentially forming an etch stop film 182 and an interlayer insulating film 184 that cover the upper surfaces of each of the gate insulating film 144, the plurality of source / drain contacts CA, and the plurality of capping insulating patterns 168 and are stacked with the upper surfaces of each of the gate insulating film 144, the plurality of source / drain contacts CA, and the plurality of capping insulating patterns 168, and a plurality of source / drain via contacts VA may be formed in the vertical direction through the upper insulating structure 180 to connect to the plurality of source / drain contacts CA (e.g., the Z direction).

[0190] Thereafter, an upper insulating film 192 may be formed to cover the upper surface of the upper insulating structure 180 and be stacked with the upper surface of the upper insulating structure 180, and a plurality of upper wiring layers M1 may be formed in the vertical direction (e.g., the Z direction) through the upper insulating film 192 to connect to the plurality of source / drain via contacts VA.

[0191] Referring to Figure 30A and Figure 30B ,the Figure 29A 、 Figure 29B and Figure 29C The resulting product may be inverted such that the back surface 102B of the substrate 102 is on the upper side. Thereafter, a chemical mechanical polishing process may be performed on the back surface 102B of the substrate 102 to expose the plurality of placeholders PH.

[0192] Thereafter, the fin-type active regions F1 surrounding the plurality of placeholder PHs can be selectively removed. In order to selectively remove the fin-type active regions F1 surrounding the plurality of placeholder PHs, the difference in etching selectivity between the fin-type active regions F1 and the placeholder PHs can be used. For example, in order to selectively remove the fin-type active regions F1 surrounding the exposed placeholder PHs, an RIE process, a thermal etching process, or a wet etching process using a liquid-phase etchant or a gas-phase etchant can be performed. For example, an etchant including TMAH can be used, but is not limited thereto.

[0193] Referring to Figure 31A and Figure 31B , a gap-fill insulating film 202 can be formed in the space formed by selectively removing the fin-type active regions F1 (see Figure 30A and Figure 30B ) from the obtained product of Figure 29A , Figure 29B and Figure 29C ). In order to form the gap-fill insulating film 202, various methods such as a PVD process, a CVD process, or an ALD process can be used. Thereafter, a chemical mechanical polishing process can be performed on the upper surface of the gap-fill insulating film 202 to planarize the upper surface of the gap-fill insulating film 202.

[0194] Referring to Figure 32A and Figure 32B , a backside source / drain contact hole BCH can be formed by etching a part of the gap-fill insulating region G1 of the gap-fill insulating film 202 on the obtained product of Figure 31A and Figure 31B . A selected placeholder PH among the plurality of placeholder PHs can be exposed through the backside source / drain contact hole BCH, and then, an etching process for removing the placeholder PH can be performed through the backside source / drain contact hole BCH. The etching process for removing the placeholder PH can include a selective etching process utilizing the fact that the placeholder PH includes a material different from the material of the gap-fill insulating film 202. For example, an RIE process can be performed to remove the placeholder PH.

[0195] Referring to Figure 33A and Figure 33B , a part of the source / drain region SD exposed by removing the placeholder PH through the backside source / drain contact hole BCH can be removed by an anisotropic etching process. For example, the etching process can include a dry etching process, or can include methods such as RIE or ALE. The etching process can use a gas including chlorine (such as Cl2) as an etching gas. Before and after the etching process, a cleaning process can be performed using a gas including carbon (C) or a gas including oxygen (O). Through the etching process, a backside source / drain recess R3 having a pointed shape toward the gate insulating film 144 can be formed.

[0196] Referring to Figure 34A and Figure 34B , a preliminary back-side source / drain covering layer P212 can be formed on the back-side source / drain recess R3 of Figure 33A and Figure 33B . The preliminary back-side source / drain covering layer P212 can be formed by epitaxially growing a semiconductor material on the source / drain barrier layer 132 and / or the source / drain body layer 134 exposed through the back-side source / drain recess R3. Since the source / drain recess R3 has a tapered shape, at the interface between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary back-side source / drain covering layer P212, weakening of adhesion due to lattice constant mismatch between the source / drain barrier layer 132 and / or the source / drain body layer 134 and the preliminary back-side source / drain covering layer P212 can be reduced.

[0197] In some other embodiments, the preliminary back-side source / drain covering layer P212 can be formed relatively thick by epitaxially growing a semiconductor material until it covers and overlaps with the upper surface of the source / drain barrier layer 132 exposed through the back-side source / drain contact hole BC. In this case, similar to the integrated circuit device 20a described with reference to Figure 8 , the back-side source / drain covering layer P212 can include a portion that overlaps with the gap-fill insulating region G1 of the gap-fill insulating film 202 in the first horizontal direction (e.g., the X direction).

[0198] In some other embodiments, after forming a relatively thick preliminary back-side source / drain covering layer P212 by epitaxially growing a semiconductor material until it covers and overlaps with the upper surface of the source / drain barrier layer 132 exposed through the back-side source / drain contact hole BC, a back-side insulating liner 214 can be conformally formed along the sidewalls of the back-side source / drain contact hole BCH (see Figure 9 ), and a portion of the central region of the preliminary back-side source / drain covering layer P212 can be etched. In this case, similar to the integrated circuit device 20b described with reference to Figure 9 , the back-side source / drain covering layer P212 can include a portion that overlaps with the gap-fill insulating region G1 of the gap-fill insulating film 202 in the first horizontal direction (e.g., the X direction).

[0199] Referring to Figure 35A and Figure 35B , Figure 34A and Figure 34BA portion of the preliminary backside source / drain capping layer P212 is covered to form a backside metal silicide film 222. In an exemplary embodiment, to form the backside metal silicide film 222, a process of forming a metal liner (not shown) that conformally covers the exposed surface of the preliminary backside source / drain capping layer P212 and is stacked with the exposed surface of the preliminary backside source / drain capping layer P212, and a process of inducing a reaction between the preliminary backside source / drain capping layer P212 and the metal constituting the metal liner may be included. After forming the backside metal silicide film 222, the remaining portion of the metal liner may be removed. In an exemplary embodiment, if the backside metal silicide film 222 includes a titanium silicide film, the metal liner may include a Ti film.

[0200] Thereafter, a backside source / drain contact BCA including a conduction blocking pattern 224 and a contact plug 226 may be formed on the backside metal silicide film 222.

[0201] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and extending longitudinally in a second horizontal direction; A first source / drain region and a second source / drain region are respectively disposed between the plurality of gate lines; as well as at least one source / drain contact over the first source / drain region and the second source / drain region, Each of the first source / drain region and the second source / drain region includes: a source / drain blocking layer; a source / drain body layer on the source / drain blocking layer; and a source / drain capping layer on the source / drain body layer. The doping concentration of the source / drain cap layer is greater than the doping concentration of the source / drain body layer. Wherein, the doping concentration of the source / drain body layer is greater than the doping concentration of the source / drain barrier layer, and The source / drain capping layer includes a tip portion.

2. The integrated circuit device according to claim 1, wherein: The at least one source / drain contact is configured in plural to be electrically connected to the first source / drain region and the second source / drain region, respectively.

3. The integrated circuit device according to claim 1, wherein: The source / drain capping layer is surrounded by the source / drain blocking layer and the source / drain body layer.

4. The integrated circuit device according to claim 1, wherein: The tip of the source / drain capping layer includes a vertex.

5. The integrated circuit device according to claim 1, further comprising: a plurality of backside source / drain contacts beneath at least one of the first source / drain region and the second source / drain region, wherein the first source / drain region is electrically connected to one of the at least one source / drain contact, and Wherein, the second source / drain region is electrically connected to one of the plurality of back side source / drain contacts.

6. The integrated circuit device according to claim 5, wherein: The second source / drain region further includes a backside source / drain capping layer disposed between the backside source / drain contact and the source / drain body layer.

7. The integrated circuit device according to claim 6, wherein: The backside source / drain capping layer is surrounded by the source / drain barrier layer and the source / drain body layer.

8. The integrated circuit device according to claim 6, wherein: The back side source / drain capping layer includes at least one tip portion.

9. The integrated circuit device according to claim 1, in, The source / drain capping layer includes a SiGe film containing a p-type dopant, and The concentration of p-type dopant ranges from 5×10 20 at / cm 3 Up to 2×10 21 at / cm 3 within the range.

10. The integrated circuit device according to claim 1, in, The source / drain capping layer includes a Si film containing an n-type dopant, and The concentration of n-type dopant ranges from 5×10 20 at / cm 3 Up to 2×10 21 at / cm 3 within the range.

11. The integrated circuit device according to claim 1 , further comprising: A plurality of fin-type active regions are respectively arranged between the plurality of device isolation films, Wherein, the plurality of fin-type active regions include compound semiconductors.

12. The integrated circuit device according to claim 1, further comprising: a plurality of gap-filling insulating films, respectively disposed between the plurality of device isolation films; The plurality of gap-filling insulating films include silicon oxide films, silicon nitride films or silicon oxynitride films.

13. An integrated circuit device comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and extending longitudinally in a second horizontal direction; A first source / drain region and a second source / drain region are respectively disposed between the plurality of gate lines; as well as a plurality of source / drain contacts over the first source / drain region and the second source / drain region, Each of the first source / drain region and the second source / drain region comprises: a source / drain barrier layer; and a source / drain body layer on the source / drain barrier layer, and The first source / drain region further includes: a source / drain recess, which is recessed inward from the upper surface of the first source / drain region; and a source / drain capping layer, which is arranged in the source / drain recess.

14. The integrated circuit device according to claim 13, further comprising: an insulating liner disposed between the plurality of source / drain contacts and gate lines adjacent to the plurality of source / drain contacts among the plurality of gate lines, Wherein, at least a portion of the upper surface of the source / drain capping layer overlaps with the insulating liner.

15. The integrated circuit device according to claim 13, further comprising: at least one nanosheet surrounded by the plurality of gate lines, The source / drain capping layer overlaps with the at least one nanosheet in a first horizontal direction.

16. The integrated circuit device according to claim 13, wherein: A source / drain capping layer surrounds a lower portion of each of the plurality of source / drain contacts.

17. An integrated circuit device comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a plurality of gate lines disposed on the plurality of device isolation films and extending longitudinally in a second horizontal direction; A first source / drain region and a second source / drain region are respectively disposed between the plurality of gate lines; a source / drain contact on the first source / drain region; as well as a back side source / drain contact, beneath the second source / drain region, Each of the first source / drain region and the second source / drain region includes: a source / drain barrier layer; and a source / drain body layer on the source / drain barrier layer, and The second source / drain region further includes: a back source / drain recess, which is recessed inward from the lower surface of the second source / drain region; and a back source / drain capping layer, which is arranged in the back source / drain recess.

18. The integrated circuit device according to claim 17, in, The sidewalls of the back source / drain capping layer overlap with the source / drain barrier layer and the source / drain body layer, and The lower surface of the back source / drain cover layer overlaps with the back source / drain contact.

19. The integrated circuit device according to claim 17, further comprising: at least one nanosheet surrounded by the plurality of gate lines, The back side source / drain capping layer overlaps with the at least one nanosheet in a first horizontal direction.

20. The integrated circuit device according to claim 17, wherein: The backside source / drain cap layer overlaps at least a portion of the upper surface of the backside source / drain contact.

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