Glass packaging substrate and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a glass packaging substrate and a preparation method thereof, and the method comprises the steps: providing a glass substrate, forming a through glass through hole in the glass substrate, and filling the glass through hole with a first conductive column; the metal layers located on the upper surface and the lower surface of the glass substrate are electrically connected through first conductive columns. Applying an ABF dielectric layer on the upper surface and the lower surface of the glass substrate by adopting a pressing process, so that the ABF dielectric layer coats the metal layer and is leveled to form a layer of wiring structure; a groove is formed in the ABF dielectric layer, the width of the groove is smaller than that of the metal layer, part of the surface of the metal layer is exposed through the groove, and the groove is filled with a second conductive column; the multiple layers of wiring structures are sequentially formed on the formed wiring structure through repeated lamination, the metal layers in the two adjacent layers of wiring structures are electrically connected through the second conductive columns, and the technical problem that in the related technology, the surface flatness of the metal layers is poor is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a glass encapsulation substrate and a preparation method thereof. Background Art

[0002] The future development of mobile communication requires spectrum resources in different frequency bands, including high, medium, and low frequency bands, to meet the needs of different scenarios and applications. Future communication technologies such as 6G will use higher frequency bands, which means higher requirements for communication devices and materials, and they need to have better high-frequency performance and signal transmission capabilities. However, due to the limitations of the material physical properties and manufacturing processes of traditional resin substrates, they can no longer meet the needs of the current development of mobile communication. Glass substrates have become the preferred materials for the future communication industry due to their excellent physical properties and extremely low manufacturing costs. During the manufacturing process of glass substrates, a metal layer (i.e., a metal wiring layer) and a dielectric layer need to be formed to achieve circuit interconnection and insulation. Among them, the metal layer is used to transmit electrical signals, and the dielectric layer is used to isolate different metal layers to prevent short circuits and crosstalk. In related technologies, polyimide (PI) is usually used as the dielectric layer, and the PI dielectric layer is prepared by spin coating deposition. As Figure 1 shown, PI will form an uneven surface in different regions with and without a metal layer. This uneven surface will cause the surface of the upper metal layer to be uneven, thus affecting the performance and reliability of the device. Summary of the Invention

[0003] This application provides a glass encapsulation substrate and a preparation method thereof, which solve the technical problem of poor surface flatness of the metal layer in related technologies and achieve the technical effect of improving the encapsulation reliability.

[0004] To achieve the above object, the main technical solutions adopted in this application include:

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a glass encapsulated substrate. The method includes: providing a glass substrate, forming through glass vias on the upper and lower surfaces of the glass substrate, and filling first conductive pillars in the glass vias; disposing metal layers on both the upper and lower surfaces of the glass substrate, and electrically connecting the metal layers on the upper and lower surfaces of the glass substrate through the first conductive pillars; laminating ABF dielectric layers on the upper and lower surfaces of the glass substrate respectively through a lamination process, such that the ABF dielectric layers cover the metal layers and are flattened, so as to form a wiring structure on each of the upper and lower surfaces of the glass substrate; forming trenches on the ABF dielectric layers, the trenches being aligned with the metal layers, the width of the trenches being smaller than the width of the metal layers, exposing a partial surface of the metal layers through the trenches, and filling second conductive pillars in the trenches; forming multiple layers of the wiring structures in sequence by repeating lamination on the formed wiring structure, and electrically connecting the metal layers in two adjacent layers of the wiring structures through the second conductive pillars.

[0006] The method for manufacturing a glass encapsulated substrate proposed by an embodiment of the present application includes: providing a glass substrate, forming through glass vias on the upper and lower surfaces of the glass substrate, and filling first conductive pillars in the glass vias; disposing metal layers on both the upper and lower surfaces of the glass substrate, and electrically connecting the metal layers on the upper and lower surfaces of the glass substrate through the first conductive pillars; laminating ABF dielectric layers on the upper and lower surfaces of the glass substrate respectively through a lamination process, such that the ABF dielectric layers cover the metal layers and are flattened, so as to form a wiring structure on each of the upper and lower surfaces of the glass substrate; forming trenches on the ABF dielectric layers, the trenches being aligned with the metal layers, the width of the trenches being smaller than the width of the metal layers, exposing a partial surface of the metal layers through the trenches, and filling second conductive pillars in the trenches; forming multiple layers of the wiring structures in sequence by repeating lamination on the formed wiring structure, and electrically connecting the metal layers in two adjacent layers of the wiring structures through the second conductive pillars, which solves the technical problem of poor surface flatness of the metal layer in the related art and achieves the technical effect of improving the encapsulation reliability.

[0007] Optionally, the method further includes: magnetron sputtering a seed layer of titanium or copper on the inner walls of the glass vias or the trenches, and filling dense copper pillars on the seed layer by using an electrochemical deposition process, the porosity of the dense copper pillars being less than 2%, to form the first conductive pillars and the second conductive pillars respectively.

[0008] Optionally, the metal layer is a copper line with a line width and a pitch of 5 μm.

[0009] Optionally, the method further includes: forming the tapered glass through-hole by laser-induced etching, the diameter of the glass through-hole being 55 um, the material of the glass substrate being borosilicate glass, and the thickness of the glass substrate being 200 um.

[0010] Optionally, the method further includes: providing a solder mask layer on the surfaces of the outermost wiring structures at the top and bottom of the glass packaging substrate, the solder mask layer being green oil with a thickness set to 10-15 um.

[0011] Optionally, open windows in the solder mask layer at the top to expose a first region of the metal layer of the outermost wiring structure at the top, perform OSP surface treatment on the first region to obtain a chip flip-chip bonding region; open windows in the solder mask layer at the bottom to expose a second region of the metal layer of the outermost wiring structure at the bottom, perform ENEPIG surface treatment on the second region to obtain an LGA pad array region.

[0012] Optionally, the minimum pad size of the LGA pad array region is 60 um, and the minimum pad pitch is 150 um.

[0013] Optionally, the method further includes: forming a dielectric thin film on the surface of the metal layer; forming a metal thin film on the dielectric thin film such that the metal layer, the dielectric thin film, and the metal thin film form a capacitor structure; applying the ABF dielectric layer using a lamination process such that the ABF dielectric layer covers the capacitor structure and levels it.

[0014] Optionally, the metal thin film is a copper-gold thin film with a thickness of 0.2 um sputtered by PVD, and the dielectric thin film is a silicon nitride thin film with a thickness of 150 nm deposited by PE-CVD.

[0015] In a second aspect, an embodiment of the present application further provides a glass packaging substrate, which includes a glass substrate and a wiring structure. Among them, multiple layers of the wiring structure are respectively provided on the upper surface and the lower surface of the glass substrate, through glass through-holes are provided on the upper surface and the lower surface of the glass substrate, and the glass through-holes are filled with first conductive posts; the wiring structure includes a metal layer and an ABF dielectric layer, metal layers are provided on both the upper surface and the lower surface of the glass substrate, and the metal layers on the upper surface and the lower surface of the glass substrate are electrically connected through the first conductive posts; ABF dielectric layers are laminated on the upper surface and the lower surface of the glass substrate using a lamination process, the ABF dielectric layer covers the metal layer and levels it, grooves are provided in the ABF dielectric layer, the width of the grooves is smaller than the width of the metal layer, a partial surface of the metal layer is exposed through the grooves, and second conductive posts are filled in the grooves; the metal layers in two adjacent layers of the wiring structure are electrically connected through the second conductive posts.

[0016] Optionally, the glass encapsulation substrate further includes a solder mask layer disposed on the surfaces of the outermost wiring structures at the top and bottom of the glass encapsulation substrate.

[0017] Optionally, a capacitor structure is provided in the wiring structure, and the electrode plates of the capacitor structure reuse metal layers. Description of the Drawings

[0018] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 Schematic diagram of a glass encapsulation substrate in the related art;

[0020] Figure 2 Flowchart of a method for manufacturing a glass encapsulation substrate provided by an embodiment of the present application;

[0021] Figure 3 Schematic diagram of the structure of a glass encapsulation substrate provided by an embodiment of the present application;

[0022] Figure 4 Schematic diagram of the capacitor structure provided by an embodiment of the present application.

[0023] Reference numerals: 100 - glass substrate; 200 - wiring structure; 210 - capacitor structure; 201 - metal layer; 202 - ABF dielectric layer; 300 - solder mask layer; 310a - chip flip - chip bonding area; 310b - LGA pad array area; V1 - first conductive post; V2 - second conductive post. Detailed Embodiments

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0025] The future development of mobile communications requires spectrum resources in different frequency bands, including high, medium, and low frequency bands, to meet the needs of different scenarios and applications. Future communication technologies such as 6G will use higher frequency bands, which means higher requirements for communication devices and materials, and they need to have better high-frequency performance and signal transmission capabilities. However, due to the limitations of the physical properties of traditional resin substrates and manufacturing processes, they can no longer meet the needs of the current development of mobile communications. For example, in the high-frequency band, the node constant and dielectric loss of resin substrates are relatively high, which will cause signal transmission attenuation and distortion, affecting communication quality. Glass substrate 100 has become the preferred material for the future communication industry due to its excellent physical properties and extremely low manufacturing cost. During the manufacturing process of glass substrate 100, a metal layer 201 (i.e., a metal wiring layer) and a dielectric layer need to be formed to achieve circuit interconnection and insulation. Among them, the metal layer 201 is used to transmit electrical signals, and the dielectric layer is used to isolate different metal layers 201 to prevent short circuits and crosstalk. The coating materials involved in related technologies still have some deficiencies in terms of high temperature resistance, chemical corrosion resistance, optical properties, etc., which limit their application in high-end fields. In related technologies, polyimide (PI) is usually used as the dielectric layer of the RDL wiring structure 200, and PI is prepared by spin coating deposition. However, as Figure 1 shown, in different regions with and without the metal layer 201, PI will form an uneven surface. This uneven surface will cause the surface of the upper metal layer 201 to be uneven, thus affecting the performance and reliability of the device. In addition, in related technologies, the preparation process of glass packaging substrates requires complex process flows and a large number of equipment, which not only increases production costs but also prolongs the production cycle. How to improve the surface flatness of the metal layer 201 efficiently and at low cost has become a technical problem to be solved urgently.

[0026] The glass packaging substrate provided by the embodiments of the present application, as the substrate layer of the radio frequency front-end module, constitutes a key interconnection carrier between the semiconductor die (DIE) and the printed circuit board (PCB) in the system-level packaging (SiP) architecture. In terms of functions, the glass packaging substrate can achieve interconnection and impedance matching between dies, internal and external signal transmission and interaction, passive integration and electromagnetic shielding, mechanical support, and three-dimensional heat dissipation channels.

[0027] The preparation method of the glass packaging substrate provided by the embodiments of the present application laminates a multi-layer wiring structure 200 on the glass substrate 100 by using the ABF process, solves the technical problem of poor surface flatness of the metal layer 201 in related technologies, achieves the technical effect of improving packaging reliability, is easy to process fine lines, has good mechanical properties and strong durability, greatly improves production efficiency, and reduces production costs.

[0028] An embodiment of the present application provides a method for preparing a glass encapsulation substrate. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0029] Figure 2 is a flowchart of the method for preparing a glass encapsulation substrate provided by an embodiment of the present application. As Figure 2 shown, the process includes the following steps:

[0030] Step S1, provide a glass substrate 100, form a through glass via hole on the upper surface and the lower surface of the glass substrate 100, and fill a first conductive pillar V1 in the glass via hole.

[0031] Among them, the glass substrate 100 serves as the core layer of the glass encapsulation substrate. Rerouting is performed on the glass substrate 100 to form a wiring structure 200 (i.e., RDL). The glass substrate 100 can be made very flat, which is beneficial to obtaining a high surface flatness. The wiring structure 200 can be formed on both the upper and lower surfaces of the glass substrate 100. The wiring structures 200 located on the upper and lower surfaces of the glass substrate 100 can be electrically connected through the first conductive pillar V1, replacing the traditional through-silicon via (TSV), which is beneficial to reducing losses and supporting high-frequency signal transmission.

[0032] Step S3, set a metal layer 201 on both the upper surface and the lower surface of the glass substrate 100, and the metal layers 201 on the upper surface and the lower surface of the glass substrate 100 are electrically connected through the first conductive pillar V1.

[0033] The method for forming the metal layer 201 on the surface of the glass substrate 100 includes one or a combination of electroplating, reflow soldering, and bonding. The metal layer 201 can be formed on both the upper and lower surfaces of the glass substrate 100. The metal layer 201 is a fine metal circuit for transmitting electrical signals.

[0034] Step S5, laminate an ABF dielectric layer 202 on the upper surface and the lower surface of the glass substrate 100 respectively through a lamination process, so that the ABF dielectric layer 202 covers the metal layer 201 and levels it, so as to form a wiring structure 200 on the upper surface and the lower surface of the glass substrate 100 respectively.

[0035] ABF is a build-up film material used for semiconductor packaging. The ABF material is mainly composed of epoxy resin, hardener, and inorganic particulate fillers, and has high insulation, high hardness, low coefficient of thermal expansion, and good processability. The lamination process refers to the ABF film being adhered to the surface of the glass substrate 100 by heating and pressing, covering the metal layer 201. The ABF material fills the gap around the metal layer 201 during the lamination process, forming a dielectric layer that wraps the sidewalls of the metal layer 201, and only exposing the top of the metal layer 201 for subsequent electrical connection. The ABF process has the characteristics of low coefficient of thermal expansion and low dielectric loss, is easy to process fine circuits, has good mechanical properties, and high durability. Compared with the physical and chemical treatment methods in the related technology, the ABF process has a simpler process flow and fewer equipment requirements, greatly improving the production efficiency and reducing the production cost.

[0036] The wiring structure 200 includes a metal layer 201 and an ABF dielectric layer 202. The wiring structures 200 located on the upper and lower surfaces of the glass substrate 100 are electrically connected through the first conductive pillar V1. The ABF dielectric layer 202 is prepared by using the ABF lamination process, so that the metal layer 201 in each layer of the wiring structure 200 has a high surface flatness.

[0037] Step S7, forming a trench on the ABF dielectric layer 202, the trench being aligned with the metal layer 201, the width of the trench being smaller than the width of the metal layer 201, exposing a partial surface of the metal layer 201 through the trench, and filling a second conductive pillar V2 in the trench.

[0038] Among them, photolithography technology can be used to define the trench pattern on the ABF dielectric layer 202, and the trench with a width smaller than the width of the metal layer 201 is etched. By controlling the trench width, only a partial area at the top of the metal layer 201 is exposed, and the sidewalls of the metal layer 201 are still wrapped by the ABF dielectric layer 202, avoiding the risk of short circuit. The top of the metal layer 201 is exposed at the bottom of the trench, and titanium or copper seed layer is sputtered in the trench. On the basis of the seed layer, dense metal is filled in the trench to achieve the electrical connection between the wiring structures 200.

[0039] Step S9, forming multiple layers of the wiring structure 200 by repeating lamination on the formed wiring structure 200; the metal layers 201 in the adjacent wiring structures 200 are electrically connected through the second conductive pillar V2.

[0040] The adjacent two wiring structures 200 are electrically connected through the second conductive posts V2. On the upper surface and the lower surface of the glass substrate 100, a plurality of wiring structures 200 are laminated by the ABF process to form a hierarchical architecture. Multi-layer laminated wiring structures 200 can be formed on both the upper surface and the lower surface of the glass substrate 100. For example, on the ABF dielectric layer 202 of the wiring structure 200 in the lower layer, the metal layer 201 of the wiring structure 200 in the upper layer is formed by electroplating. The metal layers 201 in two adjacent laminated wiring structures 200 are electrically connected through the second conductive posts V2.

[0041] The method for preparing the glass encapsulation substrate provided in this embodiment includes: providing a glass substrate 100, forming through glass vias on the upper surface and the lower surface of the glass substrate 100, and filling the first conductive posts V1 in the glass vias; providing metal layers 201 on both the upper surface and the lower surface of the glass substrate 100, and electrically connecting the metal layers 201 on the upper surface and the lower surface of the glass substrate 100 through the first conductive posts V1; respectively laminating ABF dielectric layers 202 on the upper surface and the lower surface of the glass substrate 100 through a lamination process, so that the ABF dielectric layers 202 cover the metal layers 201 and are flattened, to respectively form a layer of wiring structure 200 on the upper surface and the lower surface of the glass substrate 100; forming trenches on the ABF dielectric layers 202, the trenches being aligned with the metal layers 201, the width of the trenches being smaller than the width of the metal layers 201, exposing a partial surface of the metal layers 201 through the trenches, and filling the second conductive posts V2 in the trenches; sequentially forming multiple layers of the wiring structures 200 by repeating lamination on the formed wiring structures 200; and electrically connecting the metal layers 201 in the adjacent wiring structures 200 through the second conductive posts V2, solving the technical problem of poor surface flatness of the metal layer 201 in the related art, and achieving the technical effect of improving the encapsulation reliability.

[0042] In some embodiments, the method for preparing the glass encapsulation substrate further includes: magnetron sputtering a seed layer of titanium or copper on the inner wall of the glass via or the trench, and filling a dense copper post on the seed layer by an electrochemical deposition process (ECD), the porosity of the dense copper post being less than 2%, to respectively form the first conductive post V1 and the second conductive post V2.

[0043] Among them, the first conductive pillar V1 is used to electrically connect the wiring structures 200 on the upper and lower surfaces of the glass substrate 100, replacing the traditional through-silicon via (TSV), which is beneficial to reducing losses and supporting high-frequency signal transmission. The second conductive pillar V2 is used to electrically connect adjacent laminated wiring structures 200 to transmit electrical signals. The purpose of sputtering the seed layer is to provide a conductive substrate for subsequent electrodeposition, ensuring that the filled metal can be evenly deposited on the inner wall of the glass via or trench. A higher porosity may lead to a decrease in conductivity, and a dense copper pillar can provide better conductivity and lower resistance, reducing energy loss in signal transmission and improving the overall electrical performance.

[0044] In some embodiments, the metal layer 201 is a copper line with a line width and pitch of 5 μm.

[0045] Among them, based on the current process limit, the thickness of the metal layer 201, that is, the line width of the copper line, can be made 5 μm.

[0046] In some embodiments, the tapered glass via is formed by laser-induced etching. The diameter of the glass via is 55 μm, the material of the glass substrate 100 is borosilicate glass, and the thickness of the glass substrate 100 is 200 μm.

[0047] Among them, a tapered glass via (i.e., TGV) is formed in the glass substrate 100 by laser-induced etching (i.e., LIDE). Based on the current process conditions, the entrance diameter of the glass via can be made 55 μm. The glass via penetrates the upper and lower surfaces of the glass substrate 100, and the first conductive pillar V1 is filled in the glass via. Wiring structures 200 are provided on both the upper and lower surfaces of the glass substrate 100.

[0048] The metal layer 201 covers the glass via at the surface of the glass substrate 100, so that the metal layers 201 on the upper and lower surfaces of the glass substrate 100 are electrically connected through the first conductive pillar V1.

[0049] In some embodiments, a solder mask layer 300 is provided on the surfaces of the outermost wiring structures 200 at the top and bottom of the glass packaging substrate. The solder mask layer 300 is green oil with a thickness set to 10 - 15 μm.

[0050] Among them, the outermost wiring structure 200 is used to realize the electrical connection between the glass packaging substrate and the internal chip or the external PCB. The solder mask layer 300 is used to cover the outside of the outermost wiring structure 200 to prevent oxidation, corrosion and mechanical damage. The solder mask has good insulation performance and chemical stability. According to the IPC-A-600F standard, the thickness of the solder mask layer should be greater than or equal to 10 microns to ensure the basic protection function of the solder mask layer. Setting the thickness of the solder mask layer to 10-15 microns can effectively prevent solder bridging during the soldering process and avoid problems such as poor heat dissipation and stress concentration caused by excessive thickness.

[0051] In some embodiments, the solder mask layer 300 on the top is opened to expose the first region of the metal layer 201 of the outermost wiring structure 200 on the top, and the OSP surface treatment is performed on the first region to obtain the chip flip-chip bonding area 310a; the solder mask layer 300 on the bottom is opened to expose the second region of the metal layer 201 of the outermost wiring structure 200 on the bottom, and the ENEPIG surface treatment is performed on the second region to obtain the LGA pad array area 310b.

[0052] Figure 3 The structural schematic diagram of a glass packaging substrate provided by an embodiment of the present application is as Figure 3 shown. The wiring structures 200 on the top and bottom of the glass packaging substrate are the outermost wiring structures 200. Opening the solder mask layer 300 means forming a specific opening on the solder mask layer 300 through photolithography and development processes to expose the area that needs to be surface-treated. This area is called a pad, which is the interface for realizing electrical connection with the chip or PCB. The outermost wiring structure 200 is provided with a solder mask layer 300. By opening the solder mask layer 300, some areas of the metal layer 201 in the wiring structures 200 on the top and bottom are exposed, and the exposed area is used as a pad. The packaging interfaces of the glass packaging substrate are divided into the chip flip-chip bonding area 310a on the top and the LGA pad array area 310b on the bottom. Among them, the chip flip-chip bonding area 310a refers to the area where the chip is connected to the pads on the substrate. The flip-chip bonding technology can achieve high-density electrical connection and is suitable for high-performance chip packaging. The LGA pad array area 310b refers to the area where the pads on the substrate are connected to the corresponding pads on the printed circuit board (PCB) in the LGA packaging. OSP (Organic Solderability Preservative) is an organic solderability protection agent used to protect the copper surface. ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) is a high-performance PCB surface treatment technology with a three-layer structure of nickel, palladium, and gold, which can provide excellent solderability, corrosion resistance, and oxidation resistance.

[0053] In some embodiments, the minimum pad size of the LGA pad array region 310b is 60 um, and the minimum pad pitch is 150 um.

[0054] Among them, the minimum pad size and the minimum pad pitch can meet the current LGA standard.

[0055] In some embodiments, the method for preparing the glass encapsulation substrate further includes: forming a dielectric film on the surface of the metal layer 201; forming a metal film on the dielectric film so that the metal layer 201, the dielectric film and the metal film form a capacitor structure 210; applying the ABF dielectric layer 202 by a lamination process so that the ABF dielectric layer 202 covers the capacitor structure 210 and levels it.

[0056] In some embodiments, the metal film is a copper-gold film with a thickness of 0.2 um sputtered by PVD, and the dielectric film is a silicon nitride film with a thickness of 150 nm deposited by the PE-CVD process.

[0057] Figure 4 It is a schematic diagram of the capacitor structure 210 provided by the embodiment of the present application. As Figure 4 shown, the wiring structure 200 further includes a capacitor structure 210. The upper electrode plate in the capacitor structure 210 is prepared by sputtering a copper-gold film with a thickness of 0.2 um by PCD. The intermediate dielectric film of the capacitor structure 210 is a SiN x dielectric film with a thickness of 150 nm deposited by the PE-CVD process. The lower electrode plate of the capacitor structure 210 multiplexes the metal layer 201 in the wiring structure 200.

[0058] Among them, through the above parameter selection, the capacitance density of the capacitor structure can reach 400 pF / um^ 2 , and the breakdown voltage is greater than 100V.

[0059] After the capacitor structure 210 is prepared, the ABF dielectric layer 202 is laminated again so that the ABF dielectric layer 202 covers the capacitor structure 210.

[0060] For example, grooves are formed on the ABF dielectric layer 202, and conductive posts are filled in the grooves so that the metal layer 201 in the upper layer is electrically connected to the upper electrode plate of the capacitor structure 210 in the lower layer.

[0061] Among them, PCD sputtering refers to using a PCD sputtering device, selecting a copper-gold target, bombarding the target with high-energy ions, so that copper-gold atoms are sputtered out and deposited on the substrate to form a 0.2-μm copper-gold thin film. The PE-CVD process refers to using a PE-CVD device to generate a silicon nitride thin film through a plasma reaction and deposit it on the substrate to form a silicon nitride dielectric thin film with a thickness of 150 nm.

[0062] In some embodiments, as Figure 3 shown, three layers of the wiring structure 200 are provided on the upper surface of the glass substrate 100, and two layers of the wiring structure 200 are provided on the lower surface of the glass substrate 100.

[0063] On the other hand, an embodiment of the present application further provides a glass package substrate, as Figure 3 shown, the glass package substrate includes a glass substrate 100 and a wiring structure 200. Among them, multiple layers of the wiring structure 200 are respectively provided on the upper surface and the lower surface of the glass substrate 100. Through glass vias are provided on the upper surface and the lower surface of the glass substrate 100, and a first conductive column V1 is filled in the glass vias; the wiring structure 200 includes a metal layer 201 and an ABF dielectric layer 202. Metal layers 201 are provided on both the upper surface and the lower surface of the glass substrate 100, and the metal layers 201 on the upper surface and the lower surface of the glass substrate 100 are electrically connected through the first conductive column V1; ABF dielectric layers 202 are laminated on the upper surface and the lower surface of the glass substrate 100 by a lamination process. The ABF dielectric layer 202 covers the metal layer 201 and levels it. Grooves are provided in the ABF dielectric layer 202, and the width of the grooves is smaller than the width of the metal layer 201. Part of the surface of the metal layer 201 is exposed through the grooves, and a second conductive column V2 is filled in the grooves; the metal layers 201 in two adjacent layers of the wiring structure 200 are electrically connected through the second conductive column V2.

[0064] In some embodiments, the glass package substrate further includes a solder mask layer 300, and the solder mask layer 300 is provided on the surfaces of the outermost wiring structures 200 at the top and the bottom of the glass package substrate. Among them, the solder mask layer 300 is green oil, and the thickness is set to 10-15 μm.

[0065] In some embodiments, the package interface of the glass package substrate includes a chip flip-chip bonding area 310a at the top and an LGA pad array area 310b at the bottom.

[0066] In some embodiments, a capacitor structure 210 is provided in the wiring structure 200. The capacitor structure 210 includes a metal layer 201 - dielectric thin film - metal thin film. Among them, the metal layer 201 serves as one of the electrodes of the capacitor structure 210.

[0067] Although the embodiments of the present application are described with reference to the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

[0068] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, commodity or device comprising the said element.

[0069] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiment of the glass encapsulation substrate, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the embodiment of the preparation method of the glass encapsulation substrate.

[0070] The above description is only for the embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0071] Although the embodiments of the present application are described with reference to the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for preparing a glass packaging substrate, characterized in that: The method comprises: Providing a glass substrate, forming through-glass holes on the upper surface and the lower surface of the glass substrate, and filling the through-glass holes with first conductive pillars; A metal layer is disposed on both the upper surface and the lower surface of the glass substrate, and the metal layers on the upper surface and the lower surface of the glass substrate are electrically connected through the first conductive column; laminating ABF dielectric layers on the upper surface and the lower surface of the glass substrate respectively through a lamination process, so that the ABF dielectric layer covers the metal layer and is flattened, so as to form a wiring structure on the upper surface and the lower surface of the glass substrate respectively, wherein the wiring structure includes the metal layer and the ABF dielectric layer; Forming a groove on the ABF dielectric layer, wherein the groove is aligned with the metal layer, the width of the groove is smaller than the width of the metal layer, a portion of the surface of the metal layer is exposed through the groove, and a second conductive column is filled in the groove; Multiple layers of the wiring structure are sequentially formed on the formed wiring structure by repeated lamination, and the metal layers in two adjacent layers of the wiring structure are electrically connected through the second conductive pillars.

2. The preparation method according to claim 1, characterized in that: The method also includes: magnetron sputtering a titanium or copper seed layer on the inner wall of the glass through hole or the groove, and filling dense copper columns on the seed layer using an electrochemical deposition process, wherein the porosity of the dense copper columns is less than 2%, so as to form the first conductive column and the second conductive column respectively.

3. The preparation method according to claim 1, characterized in that: The metal layer is a copper circuit with a line width and a spacing of 5um.

4. The preparation method according to claim 1, characterized in that: The method further includes: forming the tapered through-glass hole by laser induced etching, the diameter of the through-glass hole is 55 um, the material of the glass substrate is borosilicate glass, and the thickness of the glass substrate is 200 um.

5. The preparation method according to claim 1, characterized in that: The method further comprises: arranging a solder resist layer on the surface of the outermost wiring structure at the top and bottom of the glass packaging substrate, wherein the solder resist layer is green oil and has a thickness of 10-15 um.

6. The preparation method according to claim 5, characterized in that: Opening a window in the solder resist layer at the top to expose a first area of ​​the metal layer of the outermost wiring structure at the top, and performing OSP surface treatment on the first area to obtain a chip flip-chip bonding area; A window is opened in the solder resist layer at the bottom to expose the second area of ​​the metal layer of the outermost wiring structure at the bottom, and the second area is subjected to ENEPIG surface treatment to obtain an LGA pad array area.

7. The preparation method according to claim 6, characterized in that: The minimum pad size of the LGA pad array area is 60um, and the minimum pad spacing is 150um.

8. The preparation method according to claim 1, characterized in that: The method further comprises: forming a dielectric film on the surface of the metal layer; forming a metal film on the dielectric film so that the metal layer, the dielectric film and the metal film form a capacitor structure; The ABF dielectric layer is applied by a lamination process, so that the ABF dielectric layer covers the capacitor structure and is flattened.

9. The preparation method according to claim 8, characterized in that: The metal film is a 0.2um thick copper-gold film sputtered by PVD, and the dielectric film is a 150nm thick silicon nitride deposited by PE-CVD process.

10. A glass packaging substrate, characterized in that: The glass packaging substrate comprises a glass substrate and a wiring structure, wherein the upper surface and the lower surface of the glass substrate are respectively provided with multiple layers of the wiring structure, the upper surface and the lower surface of the glass substrate are provided with penetrating glass through holes, and the glass through holes are filled with first conductive pillars; the wiring structure comprises a metal layer and an ABF dielectric layer, the upper surface and the lower surface of the glass substrate are both provided with metal layers, and the metal layers on the upper surface and the lower surface of the glass substrate are electrically connected through the first conductive pillars; The upper and lower surfaces of the glass substrate are laminated with ABF dielectric layers by a lamination process, the ABF dielectric layer covers the metal layer and is flattened, a groove is provided in the ABF dielectric layer, the groove is aligned with the metal layer, the width of the groove is smaller than the width of the metal layer, a portion of the surface of the metal layer is exposed through the groove, and a second conductive column is filled in the groove; the metal layers in two adjacent layers of the wiring structure are electrically connected through the second conductive column.

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