Semiconductor element

Abstract

A semiconductor device includes a first type semiconductor structure having a first lattice constant and including a first side and a second side opposite to the first side; the active structure is located on the first side of the first type semiconductor structure and emits radiation, and the peak wavelength of the radiation is between 1000 nanometers and 2000 nanometers; and a contact layer on the second side of the first type semiconductor structure and having a second lattice constant. Wherein a difference between the second lattice constant and the first lattice constant is at least 0.5%, and the contact layer comprises a Group III-V semiconductor material.

Description

[0001] This application is a divisional application of a Chinese invention patent application (Application No.: 201911334812.9, Application Date: December 23, 2019, Invention Title: Semiconductor Element). Technical Field

[0002] The present invention relates to semiconductor elements, and particularly to a semiconductor element having a lattice constant difference. Background Art

[0003] With the rapid development of technology, semiconductor elements play a very important role in fields such as information transmission and energy conversion, and the research and development of related materials continue. For example, semiconductor materials can be applied to various optoelectronic elements such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, power devices, acoustic wave sensors, etc., and can also be applied to fields such as lighting, display, communication, sensing, and power systems.

[0004] The principle of light emission of a light emitting diode is to apply a current to combine electrons in the N-type semiconductor layer and holes in the P-type semiconductor layer to convert electrical energy into light energy. The light emitting diode has advantages such as low power consumption and long life, and has thus gradually replaced traditional light sources and been widely used in traffic signals, backlight modules, various lighting, and medical devices. Light emitting diodes that emit infrared rays also have a considerable application market and potential in sensing systems, identification systems, surveillance systems, and vehicle light sources. Summary of the Invention

[0005] According to some embodiments of the present invention, there is provided a semiconductor element, which includes a first-type semiconductor structure having a first lattice constant and including a first side and a second side opposite to the first side; an active structure located on the first side of the first-type semiconductor structure and emitting a radiation, and a peak wavelength of the radiation is between 1000 nanometers and 2000 nanometers; and a contact layer located on the second side of the first-type semiconductor structure and having a second lattice constant. Wherein the difference between the second lattice constant and the first lattice constant is at least 0.5%, and the contact layer includes a III-V group semiconductor material. Brief Description of the Drawings

[0006] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0007] Figure 1FIG. 0 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0008] Figure 2 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure;

[0009] Figure 3 FIG. 8 is a top view of a semiconductor device according to an embodiment of the present disclosure;

[0010] Figures 4A to 4B FIGS. 12 to 17 are cross-sectional schematic diagrams of different stages in the manufacturing of a semiconductor device according to some embodiments; Figure 2 ;

[0011] Figure 5 FIG. 18 is a graph showing the relationship between the concentration and depth of elements in a partial range of a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 6 FIG. 22 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure;

[0013] Figure 7 FIG. 26 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present disclosure;

[0014] Figure 8 FIG. 30 is a schematic diagram of a package structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Symbol Description

[0016] 100, 200, 300, 400 - Semiconductor device

[0017] 101 - Growth substrate

[0018] 102 - Substrate

[0019] 103 - Sacrificial layer

[0020] 104 - First contact layer

[0021] 106 - First window layer

[0022] 108 - Buffer layer

[0023] 110 - First type semiconductor structure

[0024] 112 - Active structure

[0025] 114 - Second type semiconductor structure

[0026] 116 - Second window layer

[0027] 118 - Second contact layer

[0028] 122 - First electrode

[0029] 120 - Second electrode

[0030] 124 - Bonding layer

[0031] 130 - Reflective structure

[0032] 132 - Third contact layer

[0033] 134 - Barrier layer

[0034] 136 - Reflective bonding layer

[0035] 138 - Reflective layer

[0036] 140 - Conductive structure

[0037] 141 - Pore

[0038] 142 - First conductive layer

[0039] 144 - Second conductive layer

[0040] 146 - Insulating layer

[0041] 302 - First dopant

[0042] 304 - Second dopant

[0043] 306 - First element

[0044] 308 - Second element

[0045] 310 - Third element

[0046] 500 - Encapsulation structure

[0047] 51 - Encapsulation board

[0048] 52 - Through - hole

[0049] 53 - Carrier

[0050] 53a - First part

[0051] 53b - Second part

[0052] 55 - Bonding wire

[0053] 56 - Contact structure

[0054] 56a, 56b - Contact pad

[0055] 58 - Encapsulation material

[0056] S - Semiconductor stack

[0057] S1 - First side

[0058] S2 - Second side Detailed implementation manners

[0059] The following outlines some embodiments to make it easier for those with ordinary knowledge in the technical field to which the present invention pertains to understand the present invention. However, these embodiments are merely examples and are not used to limit the present invention. It can be understood that those with ordinary knowledge in the technical field to which the present invention pertains can adjust the embodiments described below according to requirements, such as changing the manufacturing process sequence and / or including more or fewer steps than those described herein.

[0060] In addition, other elements or steps can be added based on the embodiments described below. For example, the description of "forming a second layer / structure on the first layer / structure" may include embodiments where the first layer / structure is in direct contact with the second layer / structure, and may also include embodiments where there are other elements between the first layer / structure and the second layer / structure, such that the first layer / structure and the second layer / structure are not in direct contact, and the spatial relative relationship between the first layer / structure and the second layer / structure may change as the device operates or is used in different orientations. Additionally, the present invention may repeat reference numerals and / or letters in different embodiments, and this repetition is for simplicity and clarity, rather than to indicate the relationship between the different embodiments discussed. Furthermore, in this disclosure, the description of a layer "substantially composed of X material" means that the main component of the layer is X material, but does not exclude the inclusion of dopants or inevitable impurities.

[0061] In the embodiments of the present invention, unless otherwise specified, chemical formulas may include "stoichiometric compounds" and "non-stoichiometric compounds", where "stoichiometric compounds" are, for example, the total elemental dose of group III elements being the same as the total elemental dose of group V elements, and "non-stoichiometric compounds" are, for example, the total elemental dose of group III elements being different from the total elemental dose of group V elements. For example, the chemical formula AlGaAs represents the inclusion of group III elements aluminum (Al) and / or gallium (Ga), and the inclusion of group V element arsenic (As), where the total elemental dose of group III elements (aluminum and / or gallium) may be the same as or different from the total elemental dose of group V element (arsenic).

[0062] In addition, when each compound represented by the chemical formula is a stoichiometric compound, AlGaAs represents Al x1 Ga (1-x1) As, where 0 < x1 < 1; AlInP represents Al x2 In (1-x2) P, where 0 < x2 < 1; AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3P, where 0 < x3 < 1 and 0 < y1 < 1; AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x4 In x4 As, where 0 < x4 < 1 and 0 < y2 < 1; AlGaN represents Al x5 Ga (1 - x5) N, where 0 < x5 < 1; AlAsSb represents AlAs x6 Sb (1-x6) , where 0 < x6 < 1; InGaP represents In x7 Ga 1-x7 P, where 0 < x7 < 1; InGaAsP represents In x8 Ga 1-x8 As 1-y3 P y3 , where 0 < x8 < 1 and 0 < y3 < 1; InGaAsN represents In x9 Ga 1-x9 As 1-y4 N y4 , where 0 < x9 < 1 and 0 < y4 < 1; AlGaAsP represents Al x10 Ga 1-x10 As 1-y5 P y5 , where 0 < x10 < 1 and 0 < y5 < 1; InGaAs represents In x11 Ga 1-x11 As, where 0 < x11 < 1.

[0063] For the sake of convenience of description, the present invention will be described below by taking a quaternary light-emitting diode as an example, but the present invention is not limited thereto. The present invention can also be applied to other types of semiconductor devices, such as binary, ternary light-emitting diodes or other semiconductor devices, and the two electrodes of the semiconductor device can be located on both sides of the semiconductor device or on the same side of the semiconductor device respectively. The "quaternary", "ternary", and "binary" respectively refer to compounds composed of four, three, and two elements in the semiconductor stack of the light-emitting diode.

[0064] The following describes a semiconductor device according to some embodiments of the present invention, and is particularly applicable to a light-emitting device that emits near-infrared rays (NIR). In this embodiment, a semiconductor device is proposed. When the semiconductor device is a light-emitting diode, a non-light-absorbing material is selected for the contact layer and / or the window layer near the light-emitting surface. The absorption wavelength of this non-light-absorbing material is different from the light-emitting wavelength of the active structure, so it will not absorb the light emitted by the active structure, which can improve the light-emitting efficiency. In addition, since there is no need to remove the contact layer through an additional manufacturing process later, the manufacturing process steps can be reduced. In addition, a roughening manufacturing process can be performed on the contact layer and / or the window layer to further improve the brightness of the semiconductor device. In some embodiments, the material of the active structure includes a quaternary compound semiconductor, such as AlInGaAs or InGaAsP, and the non-light-absorbing material can include a binary compound semiconductor, such as GaAs or InP. In another embodiment, the active structure is AlInGaAs or substantially composed of AlInGaAs, and the non-light-absorbing material is substantially composed of GaAs or InP; in still another embodiment, the active structure is InGaAsP or substantially composed of InGaAsP, and the non-light-absorbing material is substantially composed of GaAs or InP.

[0065] Figure 1 FIG. 4 is a cross-sectional schematic view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a substrate 102 and a semiconductor stack S located on the substrate 102. The semiconductor stack S includes a first contact layer 104, a first window layer 106, a buffer layer 108, a first-type semiconductor structure 110, an active structure 112, a second-type semiconductor structure 114, a second window layer 116, and a second contact layer 118.

[0066] In some embodiments, the semiconductor stack S can be grown on or bonded to the substrate 102 by an epitaxial method, that is, the substrate 102 can be a growth substrate or a non-growth substrate. The substrate 102 can be used to support the semiconductor stack S and other layers or structures located thereon. The substrate 102 can be transparent, translucent or opaque to the light emitted by the active structure 112, and can also be conductive, semiconductive or insulating. In this embodiment, the semiconductor device 100 is in a vertical type. Therefore, the substrate 102 is a conductive material and includes a metal material, a metal alloy material, a metal oxide material, a semiconductor material or a carbon-containing material. The metal materials include copper (Cu), aluminum (Al), chromium (Cr), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb) or cobalt (Co); the metal alloy materials are alloys containing the above metal materials; the semiconductor materials can include but are not limited to group-IV semiconductors or group-III-V semiconductors, such as: silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), gallium arsenide phosphide (AsGaP) or indium phosphide (InP), etc.; the metal oxide materials can include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO); the carbon-containing materials can include but are not limited to diamond-like carbon (DLC) or graphene. In another embodiment, when the semiconductor device 100 is in a non-vertical type, the substrate 102 can include an insulating material, such as sapphire, glass, insulating nitride (such as SiN) or insulating oxide (such as SiO2), etc. In this embodiment, the semiconductor device is a near-field infrared light-emitting device, and the material of the substrate 102 includes indium phosphide (InP) or gallium arsenide (GaAs), for example, the material of the substrate 102 is InP or GaAs or is substantially composed of InP or GaAs.

[0067] In some embodiments, the second contact layer 118, the second window layer 116, the second type semiconductor structure 114, the active structure 112, the first type semiconductor structure 110, the buffer layer 108, the first window layer 106, and the first contact layer 104 may be formed by epitaxial methods to grow successively on the substrate 102 or a growth substrate (not shown in the figure). The epitaxial methods include Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), similar methods, or combinations of the foregoing.

[0068] In some embodiments, the materials of the first contact layer 104, the first window layer 106, the first type semiconductor structure 110, the active structure 112, the second type semiconductor structure 114, the second window layer 116, and the second contact layer 118 may independently include ternary and quaternary compound semiconductor materials. For example, they may include AlGaInAs, AlGaAs, AlInAs, GaInAs, AlAs, GaAs, InAs, AlGaInP, AlGaP, AlInP, GaInP, AlP, GaP, InP, AlInGaN, AlInN, AlGaN, InGaN, AlAsSb, AlSb, AsSb, InGaAsP, InAsP, GaAsP, InGaAsN, InAsN, GaAsN, InN, AlGaAsP, AlAsP, or similar ternary and quaternary compound semiconductor materials.

[0069] As Figure 1 shown, the active structure 112 is located between the first type semiconductor structure 110 and the second type semiconductor structure 114. When the semiconductor device 100 of the present disclosure is a light-emitting device, the first type semiconductor structure 110 and the second type semiconductor structure 114 are, for example, cladding layers and / or confinement layers, which can respectively provide electrons and holes and have a bandgap greater than that of the active layer, thereby increasing the probability of electrons and holes combining in the active structure 112 to emit light. The active structure 112 can emit a radiation. For example, for a near-infrared light-emitting device, this radiation has a peak wavelength between 1000 nanometers and 2000 nanometers, preferably between 1200 nanometers and 1800 nanometers, such as between 1250 nanometers and 1650 nanometers.

[0070] The semiconductor element 100 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. In some embodiments, the active structure 112 is a multiple quantum wells structure, which includes a plurality of barrier layers and a plurality of well layers stacked alternately, and the barrier layer has a higher energy gap than the well layer. In some embodiments, the barrier layer and the well layer may independently include a quaternary material or a ternary material. According to some embodiments, the active structure 112 may include aluminum (Al), gallium (Ga), indium (In), phosphorus (P), or arsenic (As), and preferably does not include a quaternary compound containing nitrogen (N), such as: AlGaInAs, InGaAsP.

[0071] As Figure 1 shown, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 are respectively located on both sides of the active structure 112. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 may be single-layer or multi-layer, and have an energy gap greater than that of the active structure 112, so as to confine carriers in the active structure 112 and effectively prevent the overflow of carriers in the active structure 112, and / or respectively provide electrons and holes into the active structure 112. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 may include a III-V semiconductor material, and the examples are as described above, so they will not be elaborated here. According to some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 preferably include aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), indium (In), or a combination of the foregoing, and preferably do not include a ternary or binary compound containing nitrogen (N), such as: InAlAs or InP.

[0072] In some embodiments, the first-type semiconductor structure 110 has a first conduction type, and the second-type semiconductor structure 114 has a second conduction type, where the first conduction type is different from the second conduction type. For example, the first conduction type and the second conduction type can be P-type and N-type respectively, or N-type and P-type respectively. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 have different conduction types by adding different dopants, for example, the first-type semiconductor structure 110 contains a dopant, and the second-type semiconductor structure 114 has another dopant different from the dopant of the first-type semiconductor structure 110. Specifically, the above dopants can include magnesium (Mg), zinc (Zn), silicon (Si), tellurium (Te), etc. In some embodiments, the doping of the first-type semiconductor structure 110 and the second-type semiconductor structure 114 can be performed by in-situ doping during epitaxial growth and / or by implanting using P-type or N-type dopants after epitaxial growth. For example, in this embodiment, the dopant of the first-type semiconductor structure 110 is zinc and the dopant of the second-type semiconductor structure 114 is silicon.

[0073] In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 and the doping concentration of the dopant in the second-type semiconductor structure 114 can each independently be in the range of 1×10 16 / cm 3 to 5×10 18 / cm 3 . In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 can be greater than the doping concentration of the dopant in the second-type semiconductor structure 114. For example, the doping concentration of the dopant in the first-type semiconductor structure 110 is 1×10 17 / cm 3 to 1×10 18 / cm 3 , preferably 3×10 17 / cm 3 to 8×10 17 / cm 3 , and the doping concentration of the dopant in the second-type semiconductor structure 114 is 3×10 16 / cm 3 to 1×10 18 / cm 3 , preferably 5×10 16 / cm 3 to 9×10 17 / cm 3According to some embodiments, the thickness of the first-type semiconductor structure 110 and the thickness of the second-type semiconductor structure 114 can each independently be in the range of 100 nanometers to 1200 nanometers, for example, in the range of 200 nanometers to 1000 nanometers.

[0074] The description of the embodiments of the present disclosure will be given with the first contact layer 104 and the first window layer 106 including the same non-light-absorbing material, and the non-light-absorbing material being GaAs as an example, and the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 can each independently include any suitable material, but the present invention is not limited thereto. In another embodiment, the first contact layer 104 and the first window layer 106 can each independently include different non-light-absorbing materials, such as GaAs and InP respectively. In addition, the second contact layer 118 and the second window layer 116 can include the same or different non-light-absorbing materials, and the first contact layer 104 and the first window layer 106 can each independently include any suitable material. Or in another embodiment, the first contact layer 104, the first window layer 106, the second contact layer 118, and the second window layer 116 include non-light-absorbing materials, and these non-light-absorbing materials can be the same or different.

[0075] As Figure 1 shown, the semiconductor element 100 includes a first contact layer 104 located above the first-type semiconductor structure 110, such that the first-type semiconductor structure 110 is located between the first contact layer 104 and the substrate 102. Specifically, the first-type semiconductor structure 110 includes a first side S1 and a second side S2 relative to the first side S1, and the second side S2 is farther from the substrate 102 than the first side S1. The active structure 112 is disposed on the first side S1 and the first contact layer 104 is disposed on the second side S2. The energy gap of the first contact layer 104 is greater than the energy gaps of the active structure 112 and the first-type semiconductor structure 110, so as to prevent the first contact layer 104 from absorbing light and causing a reduction in the efficiency of the semiconductor element 100. In one embodiment, the difference between the energy gap of the first contact layer 104 and the energy gap of the active structure 112 is 0.3 eV to 0.8 eV, preferably 0.4 eV to 0.7 eV.

[0076] In addition, the first-type semiconductor structure 110 has a first lattice constant and the first contact layer 104 has a second lattice constant, where the first lattice constant is different from the second lattice constant, that is, the first-type semiconductor structure 110 and the first contact layer 104 have a lattice mismatch. When the first-type semiconductor structure 11 is composed of a single layer, the lattice constant of the single layer is defined as the first lattice constant. When the first-type semiconductor structure 11 is composed of multiple layers, the average value (arithmetic mean) of the lattice constants of the multiple layers is defined as the first lattice constant. In some embodiments, the difference between the second lattice constant and the first lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, more preferably 3% to 4.5%. The above difference D1 between the second lattice constant and the first lattice constant is calculated by the following formula (1), where d1 represents the first lattice constant and d2 represents the second lattice constant:

[0077]

[0078] In this embodiment, the material of the first-type semiconductor structure 110 is In 0.53 Al 0.47 As or is substantially composed of In 0.53 Al 0.47 As, and the first lattice constant is 5.848. The material of the first contact layer 104 is GaAs or is substantially composed of GaAs, and the second lattice constant is 5.653. The difference between the second lattice constant and the first lattice constant is 3.45%. In addition, the lattice constant can be obtained by any suitable method. For example, a diffraction pattern can be made by transmission electron microscopy (TEM) to analyze the lattice constants of the first-type semiconductor structure 110 and the first contact layer 104, or the lattice constant information can be obtained through XRD (X-ray diffraction). In the present disclosure, the "lattice constant" is defined as the lattice constant a0 of a substantially unstrained layer.

[0079] In one embodiment, the thickness of the first contact layer 104 can be in the range of 5 nanometers to 100 nanometers, for example, 50 nanometers. In addition, the surface of the first contact layer 104 can be selected to have a roughened structure, thereby reducing the probability of total internal reflection of the light emitted by the active structure 112 in the semiconductor stack S, so as to improve the light extraction efficiency, thereby further enhancing the brightness of the semiconductor device 100.

[0080] Such as Figure 1As shown, the first window layer 106 is disposed between the first contact layer 104 and the first-type semiconductor structure 110. The first window layer 106 can be used to increase the light extraction efficiency of the semiconductor element 100 and / or to evenly distribute current in the semiconductor stack S. In one embodiment, the first window layer 106 and the first contact layer 104 are of the same material, that is, the first window layer 106 and the first contact layer 104 have the same lattice constant (both have the second lattice constant), and the difference from the first lattice constant of the first-type semiconductor structure 110 is at least 0.5%. For example, the materials of the first contact layer 104 and the first window layer 106 are both GaAs or are substantially composed of GaAs. In another embodiment, the first contact layer 104 can have a different material from the first window layer 106, and the first window layer 106 has a lattice constant with a difference from the first lattice constant of less than 0.5%. In another embodiment, the material of the first window layer 106 can also be the same as the material of the substrate 102. For example, the first contact layer 104 is GaAs or is substantially composed of GaAs, and the first window layer 106 and the substrate 102 are both InP or are substantially composed of InP.

[0081] In addition, the conduction types of the first contact layer 104 and the first window layer 106 can be the same as the conduction type of the first-type semiconductor structure 110. For example, the conduction types of the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 are all P-type, and the same dopant, such as zinc, is present in the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110. The doping of the first contact layer 104 and the first window layer 106 can be achieved by in-situ doping during epitaxial growth and / or by implantation using a dopant after epitaxial growth. The doping concentration of the dopant in the first contact layer 104 is greater than the doping concentration of the first-type semiconductor structure 110 and greater than 1×10 18 / cm 3 , thereby resulting in a lower resistance value between the first contact layer 104 and the first electrode 122 of the electrode structure formed thereon. Preferably, the doping concentration of the dopant in the first contact layer 104 is, for example, in the range of 2×10 18 / cm 3 to 5×10 19 / cm 3 . The first window layer 106 has a thickness thicker than that of the first-type semiconductor structure 110 and / or a lower doping concentration, which can be used to increase the light extraction rate or improve the lateral current distribution ability.

[0082] The doping concentration of the dopant in the first contact layer 104 is different from the doping concentration of the dopant in the first window layer 106. According to some embodiments, the doping concentration of the dopant in the first window layer 106 is less than the doping concentration of the dopant in the first contact layer 104. In one embodiment, the doping concentration of the dopant in the first window layer 106 can be in the range of 2×10 16 / cm 3 to 1×10 19 / cm 3 , for example, 4×10 16 / cm 3 to 8×10 18 / cm 3 .

[0083] According to some embodiments, the thickness of the first window layer 106 can be greater than the thickness of the first contact layer 104. In one embodiment, the thickness of the first window layer 106 can be in the range of 300 nanometers to 10,000 nanometers, preferably in the range of 500 nanometers to 8,000 nanometers. In this embodiment, for example, 7,000 nanometers.

[0084] Such as Figure 1As shown, a buffer layer 108 is disposed between the first window layer 106 and the first type semiconductor structure 110 to alleviate the energy level difference between the first type semiconductor structure 110 and the first window layer 106. Specifically, there is a valence band energy gap (valence band energy, Ev) difference between the valence band energy levels of the first window layer 106 and the first type semiconductor structure 110, and there is a conduction band energy gap (conduction band energy, Ec) difference between the conduction band energy levels of the first window layer 106 and the first type semiconductor structure 110. When the valence band energy gap difference and / or the conduction band energy gap difference is too large, an additional voltage difference is required to transport carriers, which may cause the semiconductor device to easily generate a large forward voltage (forward voltage, Vf), resulting in problems such as a reduction in the saturation current of the semiconductor device or premature failure. Therefore, a buffer layer 108 can be disposed between the first window layer 106 and the first type semiconductor structure 110 to avoid the above problems. The buffer layer 108 has a valence band energy level between the valence band energy levels of the first type semiconductor structure 110 and the first window layer 106, and the buffer layer 108 has a conduction band energy level between the conduction band energy levels of the first type semiconductor structure 110 and the first contact layer 104 to alleviate the energy level difference between the first type semiconductor structure 110 and the first window layer 106, thereby improving the reliability of the semiconductor device 100. In another embodiment, the first window layer 106 can be selectively disposed, and when the semiconductor device 100 does not include the first window layer 106, the buffer layer 108 can be disposed between the first contact layer 104 and the first type semiconductor structure 110 and be in direct contact with the first contact layer 104 and the first type semiconductor structure 110. As described above, the buffer layer 108 can alleviate the energy level difference between the first contact layer 104 and the first type semiconductor structure 110.

[0085] In some embodiments, the material of the buffer layer 108 can include a quaternary semiconductor compound, such as: AlGaInAs or InGaAsP. When the first contact layer 104 is GaAs or substantially composed of GaAs and the first type semiconductor layer is InAlAs or substantially composed of InAlAs, the material of the buffer layer 108 is (Al x Ga 1-x ) 0.47 In 0.53 As, 0 < x < 1 or substantially composed of (Al x Ga 1-x ) 0.47 In 0.53As, it is composed of 0 < x < 1. In another embodiment, when the first contact layer 104 is GaAs or substantially composed of GaAs and the first-type semiconductor layer is InP or substantially composed of InP, the material of the buffer layer 108 is InGaAsP or substantially composed of InGaAsP.

[0086] When the buffer layer 108 is located between the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), the buffer layer 108 has the same conductivity type as the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), and the three may contain the same dopant. In one embodiment, the doping concentration of the dopant in the buffer layer 108 can be in the range of 5×10 16 / cm 3 to 2×10 18 / cm 3 For example, 5×10 17 / cm 3 to 1×10 18 / cm 3 . In addition, the thickness of the buffer layer 108 can be in the range of 10 nm to 200 nm, such as 100 nm.

[0087] The buffer layer 108 is optional. In some embodiments, the buffer layer 108 may not be provided, such that the first window layer 106 directly contacts the first-type semiconductor structure 110. In addition, the position and number of the buffer layer 108 can be adjusted according to the characteristics of the actual product. In other embodiments, more than two buffer layers can be provided, and these buffer layers can have the same or different materials and / or doping concentrations. For example, in some embodiments, an additional buffer layer (not shown in the figure) can be provided between the second-type semiconductor structure 114 and the second window layer 116.

[0088] Such as Figure 1As shown, the second window layer 116 is disposed between the second-type semiconductor structure 114 and the substrate 102, and the second window layer 116 is away from the second side S2 of the first-type semiconductor structure 110. In some embodiments, the material of the second window layer 116 may include a III-V semiconductor material. In some embodiments, the material of the second window layer 116 may include a transparent conductive material. For example, the material of the second window layer 116 may include, but is not limited to, a metal oxide material or a semiconductor material. The metal oxide may include, but is not limited to, indium tin oxide (ITO), indium oxide, tin oxide, chromium titanium oxide (CTO), antimony tin oxide (ATO), aluminum-doped zinc oxide (AZO), zinc tin oxide (ZTO), gallium doped zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), magnesium oxide (MgO), or indium zinc oxide (IZO). The semiconductor material may include, but is not limited to, indium phosphide (InP), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or gallium phosphide (GaP), etc. The material of the first window layer 106 may refer to the material of the second window layer 116. In one embodiment, the material of the second window layer 116 is the same as the material of the first window layer 106, for example, both are InP or are substantially composed of InP. In other embodiments, the material of the second window layer 116 is different from the material of the first window layer 106, and are InP and GaAs respectively or are substantially composed of InP and GaAs respectively.

[0089] The second window layer 116 has a third lattice constant different from the second lattice constant of the first contact layer 104. In some embodiments, the difference between the third lattice constant and the second lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, more preferably 3% to 4.5%. As described above, any suitable method can be used to analyze the third lattice constant of the second window layer 116. In some embodiments, the difference between the third lattice constant and the first lattice constant is not greater than 0.5%, and in another embodiment, the difference between the third lattice constant and the first lattice constant is less than 0.2% and greater than 0. The above difference D2 between the third lattice constant and the first lattice constant is calculated by the following formula (2), where d1 represents the first lattice constant and d3 represents the third lattice constant:

[0090]

[0091] In one embodiment, the doping concentration of the dopant in the second window layer 116 can be greater than 1×10 16 / cm 3 , for example, in the range of 2×10 16 / cm 3 to 1×10 18 / cm 3 . In some embodiments, the thickness of the second window layer 116 can be less than the thickness of the first window layer 106. In another embodiment, the thickness of the second window layer 116 is greater than the thickness of the second-type semiconductor structure 114 or the second window layer 116 has a lower doping concentration than the second-type semiconductor structure 114, which can be used to increase the light extraction rate or improve the lateral current spreading ability. According to some embodiments, the thickness of the second window layer 116 can be in the range of 100 nanometers to 1000 nanometers, such as 500 nanometers.

[0092] As Figure 1 shown, a second contact layer 118 can be selectively disposed between the second window layer 116 and the substrate 102, and the second contact layer 118 is away from the second side S2 of the first-type semiconductor structure 110. The material of the second contact layer 118 can include a III-V semiconductor material. For example, as described above, it will not be elaborated here. The conduction types of the second contact layer 118 and the second window layer 116 are the same as the conduction type of the second-type semiconductor structure 114. For example, the conduction types of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 are all N-type, and the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 all contain the same dopant, such as silicon. The doping concentration of the dopant in the second contact layer 118 is different from the doping concentration of the dopant in the second window layer 116. According to some embodiments, the doping concentration of the dopant in the second contact layer 118 is greater than the doping concentration of the dopant in the second window layer 116. In one embodiment, the doping concentration of the dopant in the second contact layer 118 can be greater than 5×10 17 / cm 3 , thereby making the resistance value between the second contact layer 118 and the substrate 102 relatively low. The doping concentration of the dopant in the second contact layer 118 is, for example, in the range of 1×10 18 / cm 3 to 1×10 20 / cm 3 .

[0093] The semiconductor device 100 includes a first electrode 122 and a second electrode 120 located on opposite sides of the semiconductor device 100 respectively. For example, in this embodiment, a first contact layer 104 is located between the first-type semiconductor structure 110 and the first electrode 122, and a substrate 102 is located between the second electrode 120 and the second-type semiconductor structure 114 to form a vertical semiconductor device 100. However, the present invention is not limited thereto. In some other embodiments, the first electrode 122 and the second electrode 120 may be located on the same side of the substrate 102 to form a horizontal semiconductor device. In one embodiment, the first contact layer 104 is formed between the first-type semiconductor structure 110 and the first electrode 122 and only corresponds to the position of the first electrode 122.

[0094] Both the first electrode 122 and the second electrode 120 can be used to connect to an external power supply and conduct current into the semiconductor device 100. In some embodiments, the materials of the first electrode 122 and the second electrode 120 may independently include a metal material, an alloy material, a metal oxide material, or a carbon-containing material. For example, the metal material may include, but is not limited to, aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb), zinc (Zn), cadmium (Cd), antimony (Sb), or cobalt (Co). The alloy material includes alloys of the above metal combinations, and the metal oxide material may include, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). The carbon-containing material may include, but is not limited to, diamond-like carbon film (DLC) or graphene.

[0095] Figure 2 is a cross-sectional schematic diagram of a semiconductor device 200 according to an embodiment of the present disclosure, Figure 3 is a top view of a semiconductor device 200 according to an embodiment of the present disclosure, Figure 2 corresponds to Figure 3 a cross-sectional schematic diagram of line AA'. Figure 2 and Figure 1 the same elements are described with the same reference numerals, and the materials and characteristics of these elements are as described above, so they will not be repeated. The semiconductor device 200 of this embodiment compared to Figure 1 the semiconductor device 100 shown, has undergone a single chip bonding manufacturing process. Therefore, the order of the semiconductor stack S is the same as that of Figure 1On the contrary, the first-type semiconductor structure 110 is located between the substrate 102 and the active structure 112. Moreover, after the bonding manufacturing process, the second contact layer 118 and the second window layer 116 are located on the light-emitting traveling path of the active structure 112. Therefore, the second contact layer 118 and the second window layer 116 can also be made of non-light-absorbing materials, so that the energy gaps of the second contact layer 118 and the second window layer 116 are respectively greater than the energy gap of the active structure 112. For example, InP is selected as the non-light-absorbing material. Regarding the chip bonding manufacturing process, it will be described later.

[0096] Compared with Figure 1 the semiconductor device 100, the semiconductor device 200 further includes a reflective structure 130, a conductive structure 140, and an adhesive layer 124 located between the substrate 102 and the semiconductor stack S in addition to the substrate 102, the semiconductor stack S, the first electrode 122, and the second electrode 120. In addition, in this embodiment, the first contact layer 104 can be selectively omitted, and the characteristics such as the lattice constant, energy gap difference, doping concentration, or thickness of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 can also refer to the relationship of Figure 1 the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 described above. In this embodiment, as Figures 2 to 3 shown, the second electrode 122 includes an electrode pad 1221 substantially located at the center of an upper surface of the semiconductor stack S, and a plurality of extended electrodes 1222 connected to the electrode pad 1221 and extending away from the electrode pad 1221. The extended electrodes 1222 are used to evenly diffuse current into the semiconductor stack S.

[0097] Specifically, the semiconductor element 200 includes an adhesive layer 124 disposed between the reflective structure 130 and the substrate 102 to bond the reflective structure 130 and the substrate 102. In some embodiments, the adhesive layer 124 may include a plurality of sub-layers (not shown), and the material of the adhesive layer 124 may include a conductive material, such as a metal oxide material, a semiconductor material, a metal material, a metal alloy material, or a carbon-containing material. For example, the metal oxide may include, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium and aluminum codoped zinc oxide (GAZO). The semiconductor material may include, but is not limited to, gallium phosphide (GaP). The metal material may include, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), or tungsten (W). The metal alloy material is an alloy containing the above metal materials. The carbon-containing material may include, but is not limited to, graphene.

[0098] The reflective structure 130 is disposed between the substrate 102 and the semiconductor stack S and is configured to reflect the light emitted by the active structure 112 to increase the light extraction efficiency (LEE) of the semiconductor element 200. In some embodiments, the material of the reflective structure 130 may include, but is not limited to, a metal material or a metal alloy material. The metal material may include, but is not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), platinum (Pt), tungsten (W); the metal alloy material is an alloy containing the above metal materials.

[0099] In some embodiments, as Figure 2As shown, the reflective structure 130 may include a third contact layer 132, a barrier layer 134 on the third contact layer 132, a reflective adhesive layer 136 on the barrier layer 134, and a reflective layer 138 on the reflective adhesive layer 136. The third contact layer 132 may form a low-resistance contact with the underlying adhesive layer 124. The barrier layer 134 can be used to prevent the material of the adhesive layer 124 from diffusing into the reflective layer 138 during the manufacturing process and damaging the structure of the reflective layer 138, thereby maintaining the reflectivity of the reflective layer 138. The reflective adhesive layer 136 can be used to connect the reflective layer 138 and the barrier layer 134. The reflective layer 138 can be used to reflect the light emitted by the active structure 112. However, the present invention is not limited thereto. For example, the reflective structure 130 may include more structures, and the materials of the third contact layer 132, the barrier layer 134, the reflective adhesive layer 136, and the reflective layer 138 may each independently include the same or different metal materials or metal alloy materials. The metal materials may include, but are not limited to, copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W); the metal alloy materials are alloys containing the above metal materials.

[0100] A conductive structure 140 is located between the reflective structure 130 and the first contact layer 104. The conductive structure 140 is transparent to the light emitted by the active structure 112 and can be used to increase the current conduction and diffusion between the first contact layer 104 and the reflective structure 130. In some embodiments, the conductive structure 140 and the reflective structure 130 may jointly form an Omni-Directional Reflector (ODR) to further increase the light extraction efficiency (LEE) of the semiconductor device 200. In some embodiments, the material of the conductive structure 140 may include metal oxide materials, carbon-containing materials, or a combination of the above materials. The metal oxide materials may include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), or gallium aluminum zinc oxide (GAZO). The carbon-containing materials may include, but are not limited to, graphene.

[0101] In some embodiments, such as Figure 2As shown, the conductive structure 140 includes a first conductive layer 142 located above the reflective structure 130, and a second conductive layer 144 located between the semiconductor stack S and the first conductive layer 142. According to some embodiments, the materials of the first conductive layer 142 and the second conductive layer 144 may be different. Specifically, at least one element of the materials of the first conductive layer 142 and the second conductive layer 144 is different. For example, the material of the first conductive layer 142 is indium zinc oxide (IZO) and the material of the second conductive layer 144 is indium tin oxide (ITO).

[0102] According to some embodiments, as Figure 2 As shown, an insulating layer 146 is disposed between the second conductive layer 144 and the first contact layer 104, and the insulating layer 146 is in direct contact with the second transparent conductive layer 144. In some embodiments, the material of the insulating layer 146 may be selected to have a light transmittance greater than 90% for the light emitted by the active structure 112, and the material of the insulating layer 146 may include an oxide insulating material or a non-oxide insulating material. For example, the oxide insulating material may include silicon oxide (SiOx) or similar materials; the non-oxide insulating material may include silicon nitride (SiNx), benzocyclobutene (BCB), cyclo olefin copolymer (COC), or fluorocarbon polymer. In other embodiments, the material of the insulating layer 146 may include a halide or a compound of Group IIA and Group VII, such as calcium fluoride (CaF2) or magnesium fluoride (MgF2). In one embodiment, the material of the insulating layer 146 has a refractive index less than 1.6.

[0103] In some embodiments, the insulating layer 146 may include a plurality of pores 141 passing through the insulating layer 146, such that the conductive structure 140 is in direct contact with and electrically connected to the semiconductor stack S via these pores 141.

[0104] According to some embodiments, as Figure 2 As shown, a roughening process may be performed on the top surface of the second contact layer 118 and / or the second window layer 116 to make it have a rough surface, so as to scatter the light emitted by the active structure 112 and improve the light extraction efficiency of the semiconductor element 200.

[0105] Figures 4A to 4B is a cross-sectional schematic diagram showing various stages in the manufacture of a semiconductor element according to some embodiments, and is used to illustrate the chip bonding process. In this embodiment, the substrate 102 is a non-growing substrate. As Figure 4AAs shown, a semiconductor stack S is epitaxially grown on a growth substrate 101, and a sacrificial layer 103 may be selectively provided between the semiconductor stack S and the growth substrate 101, and the sacrificial layer 103 may be removed in subsequent manufacturing processes as shown in Figure 4B to separate the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 from the growth substrate 101. In some embodiments, the sacrificial layer 103 may be formed on the growth substrate 101 before the second contact layer 118 is formed. In some embodiments, the semiconductor device does not have the sacrificial layer 103, and the second contact layer 118 is directly formed on the growth substrate 101. In other embodiments, a buffer structure (not shown) is further provided between the second contact layer 118 and the growth substrate 101 to reduce the lattice defects of the second contact layer 118 and the layers thereon, and improve the epitaxial quality of the semiconductor stack S. In other embodiments, the semiconductor device does not have the sacrificial layer 103 but includes an etch stop layer (not shown) between the growth substrate 101 and the second contact layer 118. When the growth substrate 101 is etched and removed subsequently, the etch stop layer has the effect of protecting the semiconductor stack S and preventing the semiconductor stack S from being damaged in the etching manufacturing process. The material of the etch stop layer may be, for example, InGaAs or InGaP or substantially composed of InGaAs or InGaP.

[0106] In addition, according to some embodiments, the sacrificial layer 103 includes a material that has a different etch selectivity from the material of the second contact layer 118, such as aluminum arsenide (AlAs). In some embodiments, the removal of the sacrificial layer 103 may use a wet etching manufacturing process, a dry etching manufacturing process, a laser lift-off (LLO) manufacturing process, or a combination of the foregoing.

[0107] Figure 4BA cross-sectional schematic view of one stage in the manufacture of a semiconductor device according to some embodiments is shown. Through a substrate transfer technique, a first contact layer 104, a first window layer 106, a buffer layer 108, a first-type semiconductor structure 110, an active structure 112, a second-type semiconductor structure 114, a second window layer 116, and a second contact layer 118 are bonded to a non-growing substrate (substrate 102) via an adhesive layer (not shown in the figure). The adhesive layer is located between the first contact layer 104 and the non-growing substrate. Then, the sacrificial layer 103 is removed, causing the second contact layer 118 to be detached from the growth substrate 101, but the present invention is not limited thereto. Due to the up-and-down flipping, the arrangement of the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 on the non-growing substrate is opposite to that on the growth substrate 101 in Figure 4A Specifically, as shown in Figure 4A before the up-and-down flipping, the active structure 112 is located between the first-type semiconductor structure 110 and the growth substrate 101; as shown in Figure 4B after the up-and-down flipping, the first-type semiconductor structure 110 is located between the non-growing substrate and the active structure 112.

[0108] In addition, the growth substrate 101 may include a semiconductor material, such as but not limited to silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), indium phosphide (InP), etc. In some embodiments, the material of the growth substrate 101 may include but not limited to sapphire. The material of the non-growing substrate and the material of the growth substrate 101 may be the same or different. In most embodiments, the non-growing substrate has different characteristics from the growth substrate 101. For example, compared with the growth substrate 101, the non-growing substrate has higher thermal conductivity, electrical conductivity, transparency, or mechanical strength.

[0109] Figure 5 is a graph showing the relationship between the concentration and depth of elements and the concentration and depth of dopants in a partial range of a semiconductor device according to an embodiment of the present disclosure. Specifically, Figure 5 is based on Figure 1Secondary ion mass spectrometry (SIMS) mass spectrum of a partial structure of the semiconductor element 100. However, the present invention is not limited thereto, and a relationship diagram of the concentration and depth of elements in a partial range of the semiconductor element 100 can also be obtained using other techniques. The depth described herein refers to the depth in the direction from the side far from the substrate 102 to the side close to the substrate 102, that is, the closer to the substrate 102, the deeper the depth.

[0110] As Figure 5 shown, according to the depth and order of each layer in the semiconductor element 100, the mass spectrum can be roughly divided into seven regions A-G. Region A substantially corresponds to the position of the first contact layer 104, region B substantially corresponds to the position of the first window layer 106, region C substantially corresponds to the position of the buffer layer 108, region D substantially corresponds to the position of the first-type semiconductor structure 110, region E substantially corresponds to the position of the active structure 112, region F substantially corresponds to the position of the second-type semiconductor structure 114, and region G substantially corresponds to the position of the second window layer 116.

[0111] As Figure 5 shown, the mass spectrum includes a first dopant 302, a second dopant 304, a first element 306, a second element 308, and a third element 310. The first contact layer 104, the first window layer 106, the buffer layer 108, and the first-type semiconductor structure 110 have the first dopant 302, and the first dopant 302 makes the conduction type of the above layers P-type. The first dopant is zinc. The second-type semiconductor structure 114 and the second window layer 116 have the second dopant 304, and the second dopant 304 makes the conduction type of the above layers N-type. The second dopant is silicon. The first element, the second element, and the third element are elements that make up the host of each layer, and can be group III elements or group V elements. In Figure 5 it, the first element is indium, the second element is aluminum, and the third element is gallium. They are all group III elements, and the atomic weight of the first element is greater than that of the third element, and the atomic weight of the second element is less than that of the third element. The concentrations of the first dopant 302 and the second dopant 304 are shown on the left vertical axis, and the contents of the first element 306, the second element 308, and the third element 310 are shown on the right vertical axis. The element content on the right vertical axis represents the relative relationship of the content of a single element in each layer.

[0112] In region A, the first dopant 302 (zinc) has the highest concentration, and its concentration is greater than 1×10 18 / cm 3, and the concentration of the first dopant 302 decreases with increasing depth. Specifically, the zinc dopant in region A has a first doping concentration, and the zinc dopant in region C has a second doping concentration, and the second doping concentration is less than the first doping concentration. In addition, the zinc dopant in region E has a third doping concentration, and the second doping concentration is between the first doping concentration and the third doping concentration. The zinc dopant in region B also has a fourth doping concentration, and the fourth doping concentration is between the first doping concentration and the second doping concentration. In some embodiments, the ratio of the first doping concentration to the second doping concentration is from 10 to 100.

[0113] As Figure 5 shown, the second dopant 304 (silicon) in region G has the highest doping concentration, and its concentration is about 1×10 18 / cm 3 . Specifically, the silicon dopant in region G has a fifth doping concentration, and the silicon dopant in region F has a sixth doping concentration, and the fifth doping concentration is greater than the sixth doping concentration. In some embodiments, the ratio of the fifth doping concentration to the sixth doping concentration is from about 2 to about 100.

[0114] As Figure 5 shown, the first element 306 (indium) in region G has the largest content, and the content of the first element 306 increases with increasing depth. Specifically, regions C, D, E, and F contain substantially the same content of indium 306, and the ratios of the indium content in regions C, D, E, and F to the indium content in region A are all greater than 1000, so region A can be regarded as not containing indium. The above "not containing" means "not intentionally added".

[0115] As Figure 5 shown, the content of the second element 308 (aluminum) in regions D and F is greater than the content of the second element 308 in region E. Regions D and F contain substantially the same content of aluminum 308, and the ratios of the aluminum content in regions D and F to the aluminum content in region A are all greater than 1000, so region A can be regarded as not containing aluminum. Similarly, the ratios of the aluminum content in regions D and F to the aluminum content in region G are all greater than 1000, and region G can also be regarded as not containing aluminum.

[0116] The third element 310 (gallium) in regions A and B has the highest content, and the gallium content in region E is less than the gallium content in regions A and B. Moreover, compared with the gallium content in regions A and B, the gallium content in regions D, F, and G is extremely small. Specifically, the ratio of the gallium content in region A to the gallium content in regions D, F, and G is greater than about 1000, so regions D, F, and G can be regarded as not containing gallium.

[0117] Figure 6FIG. 0 is a cross-sectional schematic view of a semiconductor element 300 according to another embodiment. For simplicity, the same or similar structures will be described with the same reference numerals. The formation methods and materials of these structures are as described above, so they will not be elaborated here. In this embodiment, compared with the semiconductor element 100, the semiconductor element 300 does not include the second-type semiconductor structure 114, the second contact layer 118, and the buffer layer 108. In addition, the semiconductor element 300 is a double heterostructure (DH), and the material of the active structure 112 is a quaternary compound semiconductor, such as InGaAsP, and the material of the first contact layer 104 is a binary compound semiconductor, such as GaAs. In one embodiment, the material of the first window layer 106 can be the same as the material of the second window layer 116 and different from the material of the first-type semiconductor structure 110. For example, the materials of the first window layer 106 and the second window layer 116 are both InP or substantially composed of InP. In another embodiment, the first contact layer 104 and the first window layer 106 include the same material, such as GaAs, and are different from the material of the second window layer 116. The material of the second window layer is, for example, InP. Additionally, the doping concentration of the dopant in the second window layer 116 of the semiconductor element 300 can be less than 8×10 17 / cm 3 , for example, in the range of 1×10 16 / cm 3 to 5×10 17 / cm 3 .

[0118] Figure 7 FIG. 16 is a cross-sectional schematic view of a semiconductor element 400 according to another embodiment. For simplicity, the same or similar structures will be described with the same reference numerals. The formation methods and materials of these structures are as described above, so they will not be elaborated here. In this embodiment, the first electrode 122 and the second electrode 120 are located on the same side of the substrate 102 to form a horizontal semiconductor element 400. In another embodiment, a bonding layer 126 can be selectively provided between the semiconductor stack S and the substrate 102. The material of the bonding layer 126 can include insulating materials. For example, the insulating materials can include, but are not limited to, silicon oxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), or benzocyclobutene (BCB), etc. In these embodiments, the above-mentioned substrate 102 can be selected to be a material transparent to the light emitted by the active structure 112, so that the semiconductor element can emit light from the side of the substrate 102, and the semiconductor element can be in a flip manner, with the first electrode 122 and the second electrode 120 bonded downward to the circuit board.

[0119] Figure 8 FIG. 20 is a schematic diagram of a packaging structure of a semiconductor element according to an embodiment of the present disclosure. Please refer to Figure 8, the encapsulation structure 500 includes a semiconductor element 100, an encapsulation board 51, a carrier 53, bonding wires 55, a contact structure 56, and an encapsulation material 58. The encapsulation board 51 may include a ceramic or glass material. The encapsulation board 51 has a plurality of through holes 52. The through holes 52 may be filled with a conductive material such as metal to facilitate conduction of electricity and / or heat dissipation. The carrier 53 is located on the surface of one side of the encapsulation board 51 and also includes a conductive material, such as metal. The contact structure 56 is located on the surface of the other side of the encapsulation board 51. In this embodiment, the contact structure 56 includes a contact pad 56a and a contact pad 56b, and the contact pad 56a and the contact pad 56b can be electrically connected to the carrier 53 through the through holes 52. In one embodiment, the contact structure 56 may further include a thermal pad (not shown), for example, located between the contact pad 56a and the contact pad 56b. The semiconductor element 100 is located on the carrier 53 and can be the semiconductor element described in any embodiment of this disclosure. In this embodiment, the carrier 53 includes a first part 53a and a second part 53b, and the semiconductor element 100 is electrically connected to the second part 53b of the carrier 53 through the bonding wires 55. In another embodiment, the semiconductor element 100 can be directly disposed on the encapsulation board 51 without being disposed on the carrier 53 and forms an electrical connection with the contact structure 56.

[0120] The material of the bonding wires 55 may include metal, such as gold, silver, copper, aluminum, or an alloy containing at least any one of the above elements. The encapsulation material 58 covers the semiconductor element 100 and has the effect of protecting the semiconductor element 100. Specifically, the encapsulation material 58 may include a resin material such as epoxy resin, silicone resin, etc. The encapsulation material 58 may further include a plurality of wavelength conversion particles (not shown in the figure) to convert the first light emitted by the semiconductor element 50 into a second light. The wavelength of the second light is greater than the wavelength of the first light. In other embodiments, the semiconductor element 100 in the above encapsulation structure 500 may be the semiconductor element 200 or 300, or, in some embodiments, the encapsulation structure 500 includes a plurality of semiconductor elements 100, 200, and / or 300, and the plurality of semiconductor elements 100, 200, and / or 300 may be connected in series, parallel, or in series-parallel connection.

[0121] According to some embodiments, the present invention provides a semiconductor element. One or more contact layers and / or window layers in this semiconductor element are selected to use materials with absorption wavelengths different from the emission wavelength of the active structure, so as to avoid the light emitted by the active structure being absorbed by the contact layer and / or the window layer, improve the light emission efficiency, and the manufacturing process steps for removing the contact layer and / or the window layer that affect the brightness can be omitted. In addition, the contact layer can also be roughened to further improve the light emission efficiency.

[0122] In addition, according to some embodiments of the present invention, a buffer layer is provided between the contact layer and the type semiconductor layer in the semiconductor device to alleviate the valence band energy level and / or conduction band energy level difference between the contact layer and the first-type or second-type semiconductor layer, avoiding problems such as a reduction in the saturation current of the semiconductor device or premature failure, thereby improving the reliability of the semiconductor device.

[0123] The light-emitting device disclosed herein can be applied to products in fields such as lighting, display, communication, sensing, power systems, etc., such as lamps, monitors, mobile phones, tablet computers, vehicle instrument panels, televisions, sensors, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, etc.

[0124] Although the present invention is disclosed in combination with the above-mentioned multiple embodiments, these embodiments are not intended to limit the present invention. Those of ordinary skill in the art to which the present invention pertains should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same purposes and / or advantages as those described in the multiple embodiments herein. Those of ordinary skill in the art to which the present invention pertains can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor stack, comprising: A first-type semiconductor structure, comprising a first side and a second side opposite to the first side; An active structure, located on the first side, comprising a quaternary semiconductor compound and emitting a radiation, and a peak wavelength of the radiation is between 1000 nanometers and 2000 nanometers; A first contact layer, located on the second side, and comprising a III-V compound semiconductor material; A first window layer, located between the first contact layer and the first-type semiconductor structure; A second-type semiconductor structure, with the active structure located between the first-type semiconductor structure and the second-type semiconductor structure; And A second window layer, with the second-type semiconductor structure located between the active structure and the second window layer; A reflective structure, located under the semiconductor stack; A conductive structure, located between the reflective structure and the semiconductor stack; And An insulating layer, located between the conductive structure and the semiconductor stack; Wherein, a material of the second window layer is the same as a material of the first window layer.

2. The semiconductor device according to claim 1, wherein the semiconductor stack further comprises a buffer layer, located between the first contact layer and the first-type semiconductor structure.

3. The semiconductor device according to claim 1, wherein the quaternary semiconductor compound is AlGaInAs or InGaAsP.

4. The semiconductor device according to claim 1, wherein a bandgap of the first contact layer is greater than bandgaps of the active structure and the first-type semiconductor structure.

5. The semiconductor device according to claim 1, wherein the first-type semiconductor structure comprises a ternary or binary compound not containing nitrogen (N).

6. The semiconductor device according to claim 1, wherein the first contact layer and the first window layer have different materials.

7. The semiconductor device according to claim 1, wherein the first contact layer comprises GaAs, GaInAs or InGaAsP.

8. The semiconductor device according to claim 1, wherein the material of the second window layer and the material of the first window layer comprise InP.

9. The semiconductor device according to claim 1, further comprising a first electrode and a second electrode, and the first electrode and the second electrode are located on opposite sides of the semiconductor device.

10. The semiconductor device according to claim 1, wherein the reflective structure comprises a barrier layer, a reflective adhesive layer located on the barrier layer, and a reflective layer located on the reflective adhesive layer.

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