Display processing unit (DPU) pixel rate based on display region of interest (ROI) geometry

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as a CPU. The apparatus may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all content in the first frame, where the partial frame update for the first frame is associated with a panel ROI of the first frame. The apparatus may also calculate a margin time period between the first update time and a subsequent Vsync time. Further, the apparatus may send a first indication of a subsequent frame transfer interruption time based on the margin time period. The apparatus may also send a second indication to the DPU for delivering a set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame delivery interrupt time.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Patent Application Serial No. 18 / 057,750, entitled “DISPLAY PROCESSING UNIT (DPU) PIXEL RATE BASED ON DISPLAY REGION OF INTEREST (ROI) GEOMETRY,” filed on November 21, 2022, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to processing systems, and more particularly, the present disclosure relates to one or more techniques for display processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones (such as smartphones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of concurrently executing multiple applications, each of which may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values and can issue commands to the display panel to display visual content. Devices that provide content for visual presentation on a display may utilize the GPU and / or the display processor.

[0005] The GPU of a device can be configured to execute processes in the graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) can be configured to execute processes for display processing. However, with the emergence of wireless communication and smaller handheld devices, the demand for improved graphics or display processing has been increasing. Summary of the Invention

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or critical elements of all aspects nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device can be a central processing unit (CPU), a display processing unit (DPU), a graphics processing unit (GPU), or any device capable of performing display processing. The device can receive a frame indication for a first frame before a partial frame update for the first frame; and identify that the first frame is associated with the partial frame update. The device can also perform a partial frame update for the first frame at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame. Additionally, the device can calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time. The device can also switch to a compositor latch signaling model based on the partial frame update for the first frame, where the compositor latch signaling model is a software model associated with the immediate consumption of frames by the DPU. Further, the device can calculate a subsequent frame delivery interruption time based on the margin time period between the first update time and the subsequent Vsync time. The device can also send a first indication of the subsequent frame delivery interruption time based on the margin time period, where the subsequent frame delivery interruption time is associated with a start time of delivering a set of second frames before a subsequent Vsync time, and where the set of second frames is after the first frame. The device can also send a second indication to a display processing unit (DPU) for delivering the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame delivery interruption time. Additionally, the device can identify an adjustment to the panel ROI of the set of second frames; and send a third indication to the DPU for delivering the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames.

[0008] Details of one or more examples of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system.

[0010] Figure 2 illustrates an example graphics processing unit (GPU).

[0011] Figure 3 Illustrates an example display framework including a display processor and a display.

[0012] Figure 4 Is a diagram illustrating an example mask layer for display processing.

[0013] Figure 5 Is a diagram illustrating an example layer composition scheme for display processing.

[0014] Figure 6 Is a diagram illustrating an example of a frame.

[0015] Figure 7 Is a diagram illustrating examples of a content update timeline and a frame transfer timeline.

[0016] Figure 8 Is a diagram illustrating examples of a content update timeline and a frame transfer timeline.

[0017] Figure 9 Is a graph illustrating an example of a bandwidth distribution plotted against frequency.

[0018] Figure 10 Is a communication flow chart illustrating an example communication between a CPU, an application, and a DPU.

[0019] Figure 11 Is a flow chart of an example method of display processing.

[0020] Figure 12 Is a flow chart of an example method of display processing. Detailed Description

[0021] A display processing unit (DPU) can transfer pixel data to certain components (e.g., a display driver integrated circuit (DDIC)) at a constant rate. That is, each row in the display (i.e., a display row) can be transferred within a fixed time (e.g., transferred to the DDIC memory). Additionally, regardless of the time available before the pixel data is consumed by a certain display component (e.g., a display controller (DC)), each row in the display can be transferred. For example, during a video playback application, although a certain number of rows are updated (e.g., 608 out of 2520 rows are updated), the DPU may still need to transfer these rows within a certain amount of time (e.g., transfer 608 rows within 608 / 2520 time). Additionally, the display controller can have a certain number of static rows (e.g., 1912 static rows) to be refreshed from a previous frame before consuming these new rows. In some aspects, certain bandwidth for partial frame updates (i.e., updating the content of a part of the frame) can be equivalent to full frame updates (i.e., updating the content of the full frame). That is, due to partial frame composition algorithms, certain bandwidth for partial frame updates may need to be timed at the same level as the full frame (i.e., utilizing display clock resources). For example, DPU bandwidth, display serial interface (DSI) bandwidth, and / or double data rate (DDR) bandwidth may need to be timed at the same level as the full frame. Additionally, as the refresh rate of the display (e.g., 120Hz, 144Hz, 180Hz, 240Hz, etc.) increases, the amount of display power utilized correspondingly increases. In some instances, as indicated above, the DPU can transfer pixel data to components (e.g., a display driver integrated circuit (DDIC)) at a constant rate regardless of the time available before the pixel data is consumed. For example, the DPU can transfer pixel data to the DDIC at a constant rate regardless of the time available before the pixel data is consumed by a display controller (DC). For example, video playback can update a certain number of rows (e.g., 608 out of 2520 rows), yet the DC can still refresh 1912 static rows before consuming these new rows. Aspects of the present disclosure can optimize power at the DPU and / or the display for partial frame updates. In some instances, aspects of the present disclosure can refresh only the updated area of the display during partial frame updates. For example, aspects presented herein can avoid refreshing non-updated areas of the display during partial frame updates. By doing so, aspects presented herein can optimize the power utilized at the DPU during partial frame updates because only the necessary / updated part of the display is refreshed. Thus, aspects presented herein can prevent power waste by refreshing the static part of the frame (i.e., the non-updated part of the frame) during partial frame updates where the static part of the frame is not updated. That is, compared to the level of display resources used for full frame updates, aspects presented herein can utilize certain display resources at a reduced level during partial frame updates.For example, aspects presented herein may utilize some DPU or display resources (e.g., DPU clock, DSI clock, and / or DDR clock) at a reduced level during partial frame updates to save power. Aspects presented herein may also utilize idle regions of frame timing (e.g., due to partial frame updates) to transfer frames to the display panel at a lower clock speed. This can result in a reduction of visual artifacts (e.g., screen tearing) on the display screen and a reduction in the amount of power utilized at the DPU.

[0022] Aspects of the systems, apparatuses, computer program products, and methods will be described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of other aspects of the present disclosure or in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice a method. In addition, the scope of the present disclosure is intended to cover such apparatuses or methods implemented using other structures, functionality, or a combination of structures and functionality in addition to or different from the aspects of the present disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.

[0023] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of the aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses, or objectives. Rather, the aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The detailed description and the drawings merely illustrate the present disclosure and do not limit the present disclosure, and the scope of the present disclosure is defined by the appended claims and their equivalent technical solutions.

[0024] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the following detailed description and illustrated in the drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the particular application and design constraints imposed on the overall system.

[0025] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in the processing system may execute software. Software may be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, executing threads, procedures, functions, etc., regardless of whether it is expressed in terms of software, firmware, middleware, microcode, hardware description language, or other terms. The term "application" may refer to software. As described herein, one or more techniques may refer to an application configured to perform one or more functions, i.e., software. In such examples, the application may be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). The hardware (such as a processor) described herein may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more of the techniques described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more of the techniques described herein. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. Components may be separate components or sub-components of a single component.

[0026] Thus, in one or more examples described herein, the described functionality may be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality may be stored or encoded on a computer-readable medium as one or more instructions or code. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the above types of computer-readable media, or any other medium capable of storing computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0027] In general, the present disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve the rendering of graphical content and / or reduce the load on a processing unit (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a GPU). For example, the present disclosure describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout the present disclosure.

[0028] As used herein, instances of the term "content" can refer to "graphical content", "image", and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphical content" can refer to content generated by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphical content" can refer to content generated by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphical content" can refer to content generated by a graphics processing unit.

[0029] In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" can refer to content generated by a display processing unit. Graphical content can be processed to become display content. For example, a graphics processing unit can output graphical content (such as a frame) to a buffer (which can be referred to as a frame buffer). A display processing unit can read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, a display processing unit can be configured to perform composition on one or more rendering layers to generate a frame. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling on a frame, such as magnifying or reducing. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form the frame, i.e., the frame includes two or more layers, and the frame including two or more layers can subsequently be blended.

[0030] Figure 1FIG. 0 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of the device 104 may be components of a system-on-a-chip (SOC). The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frames for presentation thereon. In further examples, the results of graphics processing may not be displayed on the device, e.g., the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or the results of graphics processing may be passed to another device. In some aspects, this is referred to as split rendering.

[0031] The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. The content encoder / decoder 122 may include an internal memory 123. In some examples, the device 104 may include a display processor (such as the display processor 127) to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before being presented by the one or more displays 131. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present the frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0032] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0033] The content encoder / decoder 122 may be configured to receive graphical content from any source, such as system memory 124 and / or communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphical content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphical content, for example, in the form of encoded pixel data, from system memory 124 and / or communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphical content.

[0034] The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or the system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0035] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term "non-transitory" should not be construed to mean that the internal memory 121 or the system memory 124 is immovable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. Alternatively, the system memory 124 may not be removable from the device 104.

[0036] The processing unit 120 can be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 can be integrated into the motherboard of the device 104. In some examples, the processing unit 120 can be present on a graphics card in a port installed in the motherboard of the device 104, or can otherwise be incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 can include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is implemented partially in software, the processing unit 120 can store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121) and can execute the instructions in hardware using one or more processors to perform the techniques of the present disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered one or more processors.

[0037] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the motherboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is implemented partially in software, the content encoder / decoder 122 can store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123) and can execute the instructions in hardware using one or more processors to perform the techniques of the present disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered one or more processors.

[0038] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or location information. The transmitter 130 may be configured to perform any of the sending functions described herein with respect to device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any of the receiving functions and / or sending functions described herein with respect to device 104.

[0039] Referring again to Figure 1 , in certain aspects, the display processor 127 may include a composition component 198 that is configured to receive a frame indication for a first frame prior to a partial frame update for the first frame; and identify that the first frame is associated with the partial frame update. The composition component 198 may also be configured to perform the partial frame update for the first frame at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame. The composition component 198 may also be configured to calculate a margin time period between the first update time and a subsequent vertical sync (Vsync) time. The composition component 198 may also be configured to switch to a compositor latch signaling model based on the partial frame update for the first frame, where the compositor latch signaling model is a software model associated with immediate consumption of the frame by the DPU. The composition component 198 may also be configured to calculate a subsequent frame delivery interruption time based on the margin time period between the first update time and the subsequent Vsync time. The composition component 198 may also be configured to send a first indication of the subsequent frame delivery interruption time based on the margin time period, where the subsequent frame delivery interruption time is associated with a start time of delivering a set of second frames prior to the subsequent Vsync time, and where the set of second frames is after the first frame. The composition component 198 may also be configured to send a second indication to a display processing unit (DPU) to deliver the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame delivery interruption time. The composition component 198 may also be configured to identify an adjustment to the panel ROI of the set of second frames; and send a third indication to the DPU to deliver the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0040] As described herein, a device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, a device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, a device, a telephone, a smartphone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smartwatch, an augmented reality device, or a virtual reality device), a non-wearable device, a display or display device, a television, a set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. The processes herein can be described as being performed by specific components (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments can be used to perform them.

[0041] The GPU can process multiple types of data or data packets in a GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a collection of global state information, e.g., information about global registers, shader programs, or constant data, which can regulate how a graphics context will be processed. For example, a context register packet can include information about a color format. In some aspects of a context register packet, there may be bits indicating which workload belongs to the context register. Additionally, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a certain operation, e.g., a color mode or a color format. Thus, the context register can define multiple states of the GPU.

[0042] The context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) runs and / or in which mode the processing unit runs. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in the pipeline based on the context register definition of a mode or state. Certain processing units (e.g., a VFD) can use these states to determine certain functions, e.g., how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workloads corresponding to the mode or state can follow the changed mode or state.

[0043] Figure 2 An example GPU 200 illustrating one or more techniques of the present disclosure. As Figure 2 shown, the GPU 200 includes a command processor (CP) 210, a draw call packet 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, a secondary (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 it is shown that the GPU 200 includes processing units 220 to 238, the GPU 200 may include multiple additional processing units. Additionally, the processing units 220 to 238 are merely examples, and a GPU according to the present disclosure may use any combination or order of processing units. The GPU 200 also includes a command buffer 250, a context register packet 260, and a context state 261.

[0044] As Figure 2 shown, the GPU may utilize the CP (e.g., CP 210) or a hardware accelerator to parse the command buffer into a context register packet (e.g., context register packet 260) and / or a draw call data packet (e.g., draw call packet 212). Subsequently, the CP 210 may transmit the context register packet 260 or the draw call packet 212 to a processing unit or block in the GPU via separate paths. Additionally, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed as follows: context registers of context N, draw calls of context N, context registers of context N + 1, and draw calls of context N + 1.

[0045] The GPU may render images in a variety of different ways. In some instances, the GPU may use rendering and / or tiled rendering to render images. In a tiled rendering GPU, an image may be divided or segmented into different parts or tiles. After dividing the image, each part or tile may be rendered separately. A tiled rendering GPU may divide a computer graphics image into a grid format such that each part of the grid (i.e., a tile) is rendered separately. In some aspects, during a binning process, the image may be divided into different bins or tiles. In some aspects, during the binning process, a visibility stream may be constructed where visible primitives or draw calls may be identified. In contrast to tiled rendering, direct rendering does not divide a frame into smaller bins or tiles. Instead, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tiled rendering and direct rendering.

[0046] Figure 3FIG. 300 is a block diagram illustrating an example display framework including a processing unit 120, a system memory 124, a display processor 127, and a display 131 as may be identified with device 104.

[0047] A GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smartphone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. Operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by a CPU 315. The CPU 315 may be configured to concurrently execute multiple applications. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 simultaneously. Processing techniques may be performed via the processing unit 120 outputting frames over a physical or wireless communication channel.

[0048] The system memory 124 executable by the processing unit 120 may include a user space 320 and a kernel space 325. The user space 320 (sometimes referred to as the “application space”) may include software applications and / or application frameworks. For example, software applications may include an operating system, media applications, graphics applications, workspace applications, etc. Application frameworks may include frameworks used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application programming interfaces (APIs), etc. The kernel space 325 may further include a display driver 330. The display driver 330 may be configured to control the display processor 127. For example, the display driver 330 may cause the display processor 127 to compose a frame and send data of the frame to the display.

[0049] The display processor 127 includes a display control block 335 and a display interface 340. The display processor 127 may be configured to manipulate the functions of the display 131 (e.g., based on inputs received from the display driver 330). The display control block 335 may be further configured to output an image frame to the display 131 via the display interface 340. In some examples, the display control block 335 may additionally or alternatively perform post-processing on image data provided based on execution of the system memory 124 by the processing unit 120.

[0050] The display interface 340 can be configured to cause the display 131 to display image frames. The display interface 340 can output image data to the display 131 according to an interface protocol (such as, for example, MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface)). That is, the display 131 can be configured according to the MIPI DSI standard. The MIPI DSI standard supports video mode and command mode. In an example where the display 131 operates in video mode, the display processor 127 can continuously refresh the graphical content of the display 131. For example, the entire graphical content can be refreshed in each refresh cycle (e.g., line by line). In an example where the display 131 operates in command mode, the display processor 127 can write the graphical content of a frame to the buffer 350.

[0051] In some such examples, the display processor 127 may not continuously refresh the graphical content of the display 131. Instead, the display processor 127 can use a vertical synchronization (Vsync) pulse to coordinate the rendering and consumption of the graphical content at the buffer 350. For example, when a Vsync pulse is generated, the display processor 127 can output new graphical content to the buffer 350. Thus, the generation of the Vsync pulse can indicate that the current graphical content has been rendered at the buffer 350.

[0052] Based on the display controller 345, the display client 355, and the buffer 350, a frame is displayed at the display 131. The display controller 345 can receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 can output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 can represent local memory to the display 131. In some examples, the display controller 345 can output the image data received from the display interface 340 directly to the display client 355.

[0053] The display client 355 can be associated with a touch panel that senses the interaction between the user and the display 131. When the user interacts with the display 131, one or more sensors in the touch panel can output signals to the display controller 345 that indicate which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 can use the sensor output to determine the way the user interacts with the display 131. The display 131 can further be associated with / include other devices (such as a camera, a microphone, and / or a speaker) that operate in conjunction with the display client 355.

[0054] Some processing techniques of device 104 may be performed in three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing techniques may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process the content buffer based on the execution of an application that generates content on a per-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to the physical display panel / subsystem (e.g., display 131) that displays the frame.

[0055] Instructions executed by the CPU (e.g., software instructions) or instructions executed by the display processor may cause the CPU or the display processor to search for and / or generate a composition strategy for composing a frame based on dynamic priorities and runtime statistics associated with one or more composition strategy groups. The frame to be displayed by a physical display device such as a display panel may include multiple layers. Additionally, the composition of the frame may be based on combining the multiple layers into a frame (e.g., based on a frame buffer). After combining the multiple layers into a frame, the frame may be provided to the display panel for display on the display panel. The process of combining each of the multiple layers into a frame may be referred to as composition, frame composition, composition procedure, composition process, etc.

[0056] The frame composition procedure or composition strategy may correspond to a technique for combining different layers among the multiple layers into a single frame. The multiple layers may be stored in a double data rate (DDR) memory. Each of the multiple layers may further correspond to a separate buffer. A compositor or a hardware compositor (HWC) associated with a block or function may determine the input for each layer / buffer and execute the frame composition procedure to generate an output indicating the composed frame. That is, the input may be a layer, and the output may be a frame composition procedure for composing a frame to be displayed on the display panel.

[0057] Some aspects of display processing may utilize different types of mask layers, e.g., a shape mask layer. A mask layer is a layer that may represent a part of a display or a display panel. For example, the area of the mask layer may correspond to the area of the display, but the entire mask layer may depict a part of what is actually displayed at the display or panel. For example, the mask layer may include a top portion and a bottom portion of the display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different parts of the display area. Additionally, for certain parts of the display area, the content of different mask layers may overlap each other. Thus, a mask layer may represent a part of the display area that may or may not overlap with other mask layers.

[0058] Figure 4FIG. 400 is an illustration of an example mask layer for display processing. More specifically, FIG. 400 depicts a type of mask layer that can represent portions of a display panel. As Figure 4 shown, FIG. 400 includes a mask layer 402 that includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. As Figure 4 depicted, the mask layer 402 can represent different regions displayed on the display panel.

[0059] Some types of displays can use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer can reshape the display frame to provide a more optimized visual shape (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.) at the display panel. These types of mask layers (e.g., shape mask layers) can be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). Additionally, these mask layers can be processed by other specific types of hardware logic modules (e.g., modules in a display driver integrated circuit (DDIC) or a bridge chip). In some aspects, these types of mask layers (e.g., shape mask layers) can be based on a certain unit, such as a pixel. That is, the shape generation basic unit of the shape mask layer can be a single pixel.

[0060] Some aspects of display processing can utilize a frame buffer to cache or store the composite output of the GPU. For example, after being composed at the GPU, the display layer can be cached or stored in the frame buffer. In some aspects, the composite hardware (HW) or software (SW) stack can use the frame buffer target to cache the composite output (e.g., GPU composite output or CPU composite output). The cached composite output can then be transmitted to another processor (e.g., DPU) as an input layer. The frame buffer can have multiple different color formats, such as red (R) green (G) blue (B) alpha (A) (RGBA) format (e.g., RGBA8888 format). Moreover, the frame buffer can have a specific size (e.g., a 32-bit triple buffer). For example, at the start of the display / graphics subsystem design, the frame buffer can be created as an RGBA8888 format and a 32-bit triple buffer. In some instances, if the frame layer does not use a specific composition (e.g., GPU or client composition), the frame buffer can be ignored. Moreover, the layer (e.g., a frame layer or a display layer associated with display processing) can be directly extracted and composed. For example, the DPU or a hardware compositor can directly extract the layer and then compose the layer.

[0061] Figure 5 FIG. 500 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, FIG. 500 depicts the layer composition of a display layer, where certain layers (e.g., specifically composed layers) are cached in a frame buffer, and some layers are directly extracted and composed by a DPU. As Figure 5 shown, FIG. 500 includes layer 510, layer 511, layer 512, layer 513, frame buffer 530 (e.g., an RGBA8888 format frame buffer), DPU 540, and display 550. Figure 5 It depicts that the layers composed at the GPU (i.e., the layers associated with GPU composition) can be cached or stored in the frame buffer. For example, layers 510, 511, and 512 can be composed at the GPU and then cached / stored at frame buffer 530. Alternatively, the layers not composed at the GPU (i.e., the layers associated with non-GPU composition) can be directly extracted and composed at the DPU. For example, layer 513 can be directly extracted and composed at DPU 540. That is, layers 510, 511, and 512 can be a specific type of composition (e.g., GPU composition), while layer 513 can be another type of composition (non-GPU composition). After being cached / stored in frame buffer 530, layers 510, 511, and 512 can be transferred to DPU 540. In addition, after the processing at DPU 540, layers 510 to 513 can be transferred to display 550.

[0062] Some types of display processing devices (e.g., mobile devices, computers, TVs, or other consumer devices) can utilize complex multiple content layouts in a single display processing layer or multiple display processing layers. That is, for the graphics or display stack in the operating system of the device, there can be a single display processing layer (i.e., the display layer or layers associated with display processing) or multiple display processing layers. For example, there can be at least one display layer that can be associated with the screen or frame of the display processing device, such that the display panel at the device can be divided among the display layers. Additionally, for the content or the end user, there can be multiple content entities in the display processing layer. This may be due to operating system limitations and / or application rendering / resource management limitations. Further, some types of applications can choose to use a single display processing layer for rendering. The color processing capability based on each region (i.e., for each region of interest (ROI) in the layer) can be utilized with certain types of display processing unit (DPU) architectures.

[0063] Current mobile consumer electronic devices can utilize different types of DPU image processing (e.g., DPU per-layer flexible image processing). Based on the content of different layers, providing accurate per-layer image processing may be important for the end-user's perception. There can be multiple different types of per-layer image processing, such as video high dynamic range (HDR) layer tone mapping and processing and / or video standard dynamic range (SDR) layer visual contrast enhancement. The type of per-layer image processing can also include appropriate tone mapping for photo image layers, game layer color processing and flexible visual control options provided to the end user, flexible visual control options for video layers provided to the end user, and flexible visual control options for text / user interface (UI) layers provided to the end user.

[0064] A display processing unit (DPU) can be included in multiple different display devices (e.g., smart phones or user equipment (UE)). In some aspects, the DPU can be utilized to determine a specific bandwidth (e.g., double data rate (DDR) bandwidth) as the DPU can mix and transfer data to a display panel for each row in a frame or a display. Additionally, this mixing and transfer of data can be performed within a fixed row time of the frame or the display. A display bandwidth request or selection (i.e., display bandwidth assessment) can account for the total number of pixels that may need to be fetched to produce a row in a frame or a display. Thus, the display bandwidth request or assessment can increase proportionally with the total number of overlapping layers in a frame or a display.

[0065] In some aspects, a display bandwidth assessment (i.e., display bandwidth request or selection) can be a request from the DPU for the amount of display bandwidth from display hardware. For example, a display bandwidth assessment can be a request to increase the bandwidth for a corresponding increase in voltage or power. For example, a display bandwidth assessment can be based on the number of overlaps, frame rate, vertical active amount, horizontal active amount, and bytes per pixel. As an equation, display bandwidth assessment = (number of overlaps) * (frame rate) * (vertical active amount) * (horizontal active amount) * (bytes per pixel). For example, a main screen display can include the following display bandwidth assessment: display bandwidth assessment = 4 * 60 * 1440 * 2560 * 4 = 3.3 gigabytes per second (Gbps), e.g., on a 1440x2560 display at 60 Hz.

[0066] A display processing unit (DPU) can transfer pixel data to certain components (e.g., a display driver integrated circuit (DDIC)) at a constant rate. That is, each row in the display (i.e., a display row) can be transferred within a fixed time (e.g., transferred to the DDIC memory). Additionally, regardless of the time available before the pixel data is consumed by a certain display component (e.g., a display controller (DC)), each row in the display can be transferred. For example, during a video playback application, although a certain number of rows are updated (e.g., 608 out of 2520 rows are updated), the DPU may still need to transfer these rows within a certain amount of time (e.g., transfer 608 rows within 608 / 2520 time). Additionally, the display controller can have a certain number of static rows (e.g., 1912 static rows) to refresh from a previous frame before consuming these new rows.

[0067] Figure 6 FIG. 600 illustrating an example of a frame at an exemplary display device. More specifically, FIG. 600 illustrates a frame 610 including an update region (e.g., region 612) and a static region (e.g., region 614). As Figure 6 shown, FIG. 600 includes a frame 610, a region 612 (i.e., the update region) having a certain amount of rows (e.g., 608 rows), and a region 614 (i.e., the static region) having a certain amount of rows (e.g., 1912 rows). As Figure 6 depicted, a portion of the frame 610 can be updated a certain amount of rows at a time (e.g., region 612 can be updated 608 rows at a time). Additionally, a portion of the frame 610 can include a certain amount of static or non-updated rows (e.g., region 614 can include 1912 static rows). Additionally, the display controller of the frame 610 can have a certain number of static rows corresponding to region 614 (e.g., 1912 static rows) to refresh from a previous frame before consuming these new rows. Region 612 and region 614 can be referred to as regions of interest (ROI) or display ROIs. Thus, Figure 6 is an example of updating display rows based on a display region of interest (ROI).

[0068] In some aspects, certain bandwidths used for partial frame updates (i.e., updates of the content of a portion of a frame) can be equivalent to full frame updates (i.e., updates of the content of a full frame). That is, due to partial frame composition algorithms, certain bandwidths used for partial frame updates may need to be timed at the same level as full frames (i.e., leveraging display clock resources). For example, DPU bandwidth, Display Serial Interface (DSI) bandwidth, and / or Double Data Rate (DDR) bandwidth may need to be timed at the same level as full frames. Additionally, as the refresh rate of the display (e.g., 120Hz, 144Hz, 180Hz, 240Hz, etc.) increases, the amount of display power utilized correspondingly increases. In some instances, as indicated above, the DPU can transfer pixel data to a component (e.g., a Display Driver Integrated Circuit (DDIC)) at a constant rate regardless of the time available before the pixel data is consumed. For example, the DPU can transfer pixel data to the DDIC at a constant rate regardless of the time available before the pixel data is consumed by a Display Controller (DC). For example, video playback may update a certain number of rows (e.g., 608 out of 2520 rows), yet the DC can still refresh 1912 static rows before consuming these new rows.

[0069] Based on the above, it may be beneficial to find ways to optimize power at the display for partial frame updates. For example, it may be beneficial to only refresh the updated region of the display during partial frame updates. Additionally, it may be beneficial to avoid refreshing non-updated regions of the display during partial frame updates. Furthermore, it may be beneficial to utilize certain display resources (e.g., DPU clock, DSI clock, and / or DDR clock) at a reduced level during partial frame updates compared to the level of display resources used for full frame updates.

[0070] Aspects of the present disclosure may optimize power at the DPU and / or the display for partial frame updates. In some instances, aspects of the present disclosure may refresh only the updated regions of the display during partial frame updates. For example, aspects presented herein may avoid refreshing non-updated regions of the display during partial frame updates. By doing so, aspects presented herein may optimize the power utilized at the DPU during partial frame updates, as only the necessary / updated portions of the display are refreshed. Thus, aspects presented herein may prevent wasted power by refreshing the static portions of a frame (i.e., the non-updated portions of the frame) during partial frame updates that do not update the static portions of the frame. That is, aspects presented herein may utilize certain display resources at a reduced level during partial frame updates as compared to the level for full frame updates. For example, aspects presented herein may utilize some DPU or display resources (e.g., DPU clock, DSI clock, and / or DDR clock) at a reduced level during partial frame updates, thereby saving power. Aspects presented herein may also utilize the idle regions of the frame timing (e.g., due to partial frame updates) to transfer the frame to the display panel at a lower clock speed. This may result in a reduction in visual artifacts (e.g., screen tearing) on the display screen and a reduction in the amount of power utilized at the DPU.

[0071] In some instances, aspects of the present disclosure may calculate the margin time between the frame update time and the next vertical sync (Vsync) time. Vsync timing is a means of synchronizing the frame rate of an application (e.g., a video game) with the refresh rate of a corresponding display or monitor. The application, GPU, and / or DPU may utilize Vsync timing to eliminate certain visual artifacts such as screen tearing (i.e., a split in a portion of the displayed frame where a portion of the frame lags behind the other portions). In some instances, aspects presented herein may utilize the software solution duration for frame submission and the margin available before the next Vsync time. Additionally, a specific timing structure (e.g., early frame transfer interrupt time) may be generated before the Vsync time based on the estimated margin and the panel ROI. After this specific timing structure, the frame may be transferred to the display at a reduced clock speed. By doing so, certain visual artifacts such as screen tearing (i.e., a split in a portion of the displayed frame where a portion of the frame lags behind the other portions) may be avoided.

[0072] Additionally, aspects presented herein may trigger an early frame transfer interrupt time that can be generated before the next Vsync time based on an estimated margin and panel ROI. In some instances, a previous frame update may be transferred to the display panel and may correspond to an update on the display screen. Static regions of the frame (i.e., non-updated regions) may not be transferred to the display panel as it may not need to be updated on the display screen. Aspects presented herein may utilize the static regions where the DPU may be idle. That is, aspects presented herein may utilize the idle regions of the frame timing and generate an interrupt time immediately after the frame transfer of the previous frame. Thus, at the interrupt time, the frame can be transferred to the display panel at a lower clock speed without causing any visual artifacts (e.g., screen tearing) on the display screen. Therefore, aspects presented herein may utilize the available additional margin time corresponding to the static regions of the frame where the DPU may not transfer data to the panel. Accordingly, aspects presented herein may utilize the static regions of the frame to transfer the next frame earlier (e.g., transfer the next frame at a slower rate). Thus, instead of transferring data during the updated regions of the frame (e.g., 25% of the time), aspects presented herein utilize the remaining time (e.g., 75% of the previous frame duration) to transfer the frame at a slower rate. By doing so, aspects presented herein may optimize the power utilized at the DPU and / or the display.

[0073] Aspects of the present disclosure may estimate the margin available between the frame update time and the next vertical sync (Vsync) time. For example, aspects presented herein may utilize a software model in which the duration of the frame submission (e.g., frame update time) and the margin available before the next vertical sync (Vsync) time are estimated. Aspects of the present disclosure may also utilize a model such as generating an early frame transfer interrupt before the next Vsync time based on the estimated margin and the region of interest (ROI) of the display panel. Additionally, aspects presented herein may transfer the frame to the display panel at a lower clock speed without experiencing visual artifacts (e.g., tearing screen). The frame may be transferred at a lower clock speed at a specific time (e.g., at the frame interrupt time).

[0074] In some aspects, the aspects presented herein may allow content to be ready before the next Vsync time. For example, in some ROI use cases and / or partial frame updates, the aspects presented herein may allow content to be ready before the next Vsync time. For example, this may apply to video playback during certain applications. Additionally, due to buffer flips (i.e., there may be a significant amount of idle time before the next Vsync time at which a frame will be delivered), the software duration may be reduced. Additionally, the DPU may use this idle time to spread pixel delivery over one Vsync duration. That is, since the aspects presented herein only deliver the updated portion of a frame during a partial frame update, the frame may be delivered at a slower clock speed by taking advantage of the idle margin time corresponding to the static portion of the frame (e.g., the non-updated portion of the frame).

[0075] Figure 7 Diagrams 700 and 750 including examples respectively illustrating a content update timeline and a frame delivery timeline. More specifically, diagram 700 illustrates a timeline for content updates (e.g., content update timeline 710), and diagram 750 illustrates frame delivery for display processing (e.g., frame delivery timeline 760). As Figure 7 shown, diagram 700 includes a content update timeline 710 that includes content updates for a plurality of frames (e.g., frame 711, frame 712, frame 713, frame 714, frame 715, frame 716, and frame 717), and a compositor frame scheduler 720. Diagram 750 depicts a frame delivery timeline 760 that includes the frame delivery times for a plurality of frames (e.g., frame 711, frame 712, frame 713, frame 714, frame 715, frame 716, and frame 717), and Vsync times 770. The Figure 7 diagram illustrates that each frame (e.g., frame 711, frame 712, frame 713, frame 714, frame 715, frame 716, and frame 717) is delivered at the start of the next Vsync time (e.g., Vsync time 770). Thus, for the static or non-updated portion of the frame, there may be a significant amount of idle time between frames.

[0076] Aspects of the present disclosure may utilize display software (e.g., software at a central processing unit (CPU) or display driver software) that constructs software duration heuristics and / or synthesizes a timeline for predicting ROI use cases. Additionally, aspects presented herein may utilize display software that calculates line pointer interrupt values and / or configures a tearing check block in a display system (e.g., a multimedia display subsystem (MDSS)) based on idle time prediction. Additionally, aspects presented herein may utilize display software that switches to a certain synthesizer model (e.g., a synthesizer "latch signaling" model) to ensure content availability at the DPU driver during interrupts. The synthesizer latch signaling model may be a software model associated with the immediate consumption of frames by the DPU. Additionally, aspects presented herein may utilize display software that switches to a lower DPU clock and DSI clock prior to frame ROI transfer. Aspects presented herein may also utilize display software that tunes the CPU frequency if latency is predicted on an occasional geometry change.

[0077] Figure 8 Diagrams 800 and 850 including examples respectively illustrating a content update timeline and a frame transfer timeline. More specifically, Diagram 800 illustrates a timeline for content update (e.g., content update timeline 810), and Diagram 850 illustrates frame transfer for display processing (e.g., frame transfer timeline 860). As Figure 8 shown, Diagram 800 includes a content update timeline 810 that includes content updates for a plurality of frames (e.g., frame 811, frame 812, frame 813, frame 814, frame 815, frame 816, and frame 817), and a synthesizer frame scheduler 820. Diagram 850 depicts a frame transfer timeline 860 that includes frame transfer times for a plurality of frames (e.g., frame 811, frame 812, frame 813, frame 814, frame 815, frame 816, and frame 817), and a Vsync time 870. Additionally, Diagram 850 includes a frame transfer interrupt time 880. The Figure 8 diagram illustrates that each frame (e.g., frame 811, frame 812, frame 813, frame 814, frame 815, frame 816, and frame 817) may be transferred at the start of the next Vsync time (e.g., Vsync time 870), or at the start of the frame transfer interrupt time 880. That is, if there is a large amount of idle time between frames for static or non-updated portions of the frame, the frame (e.g., frame 812, frame 813, and frame 817) may be transferred at the start of the frame transfer interrupt time 880. By doing so, aspects presented herein may transfer a set of frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from a subsequent frame transfer interrupt time.

[0078] AsFigure 8 As shown, aspects presented herein may perform a partial frame update for a first frame (e.g., frame 811) at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame. Additionally, aspects presented herein may compute a margin time period between the first update time and a subsequent Vsync time (e.g., Vsync time 870). Additionally, aspects presented herein may send a first indication of a subsequent frame delivery interruption time (e.g., frame delivery interruption time 880), where the subsequent frame delivery interruption time is associated with a start time of delivering a set of second frames (e.g., frames 812 and 813) before a subsequent Vsync time (e.g., Vsync time 870), and where the set of second frames (e.g., frames 812 and 813) is after the first frame (e.g., frame 811). Aspects presented herein may also send a second indication to the DPU for delivering the set of second frames (e.g., frames 812 and 813) at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame delivery interruption time (e.g., frame delivery interruption time 880).

[0079] Figure 9 A graph 900 including an example illustrating a bandwidth distribution plotted relative to frequency. More specifically, graph 900 illustrates a percentage of bandwidth distribution plotted relative to frequencies in MHz (e.g., frequencies of 451 MHz, 547 MHz, 768 MHz, 1017 MHz, 1555 MHz, 1804 MHz, or 2092 MHz). As Figure 9 shown, graph 900 includes a current display bandwidth request 910 (i.e., current display bandwidth assessment), a true compressed display bandwidth request 912 (i.e., true compressed display bandwidth assessment), and an optimal delivery time display bandwidth request 914 (i.e., optimal delivery time display bandwidth assessment). Figure 9 Illustrated for lower frequencies (e.g., frequency 451), aspects presented herein may have a higher percentage of distribution for the optimal delivery time display bandwidth request (e.g., optimal delivery time display bandwidth request 914). As the frequency increases, the percentage of distribution of the optimal delivery time display bandwidth request (e.g., optimal delivery time display bandwidth request 914) decreases. That is, aspects presented herein may include a power advantage for lower frequencies during partial frame updates, since frames with static or non-updated regions may be delivered at a reduced DPU clock frequency and a reduced bandwidth frequency.

[0080] ​Aspects of the present disclosure may include a number of benefits or advantages. For example, aspects presented herein may optimize power at the DPU and / or the display for partial frame updates. Aspects of the present disclosure may also refresh the updated region of the display during partial frame updates. That is, aspects presented herein may avoid refreshing the non-updated region of the display during partial frame updates. By doing so, aspects presented herein may optimize the power utilized at the DPU during partial frame updates, as only the necessary / updated portion of the display is refreshed. Thus, aspects presented herein may prevent power waste by refreshing the static portion of a frame (i.e., the non-updated portion of the frame) during partial frame updates where the static portion of the frame is not updated. Compared to the level of display resources used for full frame updates, aspects presented herein may utilize certain display resources at a reduced level during partial frame updates. For example, aspects presented herein may utilize some DPU or display resources (e.g., DPU clock, DSI clock, and / or DDR clock) at a reduced level during partial frame updates, thereby saving power. Additionally, aspects presented herein may utilize the idle region of the frame timing (e.g., due to partial frame updates) to transfer the frame to the display panel at a lower clock speed. This may result in a reduction in visual artifacts (e.g., screen tearing) on the display screen and a reduction in the amount of power utilized at the DPU.

[0081] Figure 10 is a communication flowchart 1000 of display processing according to one or more techniques of the present disclosure. As Figure 10 shown, according to one or more techniques of the present disclosure, illustration 1000 includes an example communication between a CPU 1002 (e.g., a DPU driver, other central processor, or display processor), an application / GPU 1004 (e.g., an application or GPU), and a DPU 1006.

[0082] At 1010, the CPU 1002 may receive a frame indication for a first frame (e.g., receive indication 1012 from the application / GPU 1004) prior to a partial frame update for the first frame.

[0083] Additionally, at 1010, the CPU 1002 may identify that the first frame is associated with a partial frame update.

[0084] At 1020, the CPU 1002 may perform a partial frame update for the first frame at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with the panel region of interest (ROI) of the first frame. In some aspects, the partial frame update for the first frame may be performed at the full DPU clock frequency and the full bandwidth frequency.

[0085] At 1030, the CPU 1002 may calculate a margin time period between a first update time and a subsequent vertical synchronization (Vsync) time. The subsequent Vsync time may be after the first update time. Additionally, the first update time may correspond to the frame transfer time of a first frame. In some aspects, calculating the margin time period between the first update time and the subsequent Vsync time may include: generating one or more software duration heuristics; and predicting one or more composite timelines for a panel ROI of a set of second frames. That is, the CPU may generate one or more software duration heuristics; and predict one or more composite timelines for a panel ROI of a set of second frames.

[0086] At 1040, the CPU 1002 may switch to a synthesizer latch signaling model based on a partial frame update for the first frame, where the synthesizer latch signaling model is a software model associated with the immediate consumption of frames by the DPU.

[0087] At 1050, the CPU 1002 may calculate a subsequent frame transfer interrupt time based on the margin time period between the first update time and the subsequent Vsync time.

[0088] At 1060, the CPU 1002 may send a first indication of the subsequent frame transfer interrupt time (e.g., send indication 1062 to the DPU 1006) based on the margin time period, where the subsequent frame transfer interrupt time is associated with the start time of transferring a set of second frames before the subsequent Vsync time, where the set of second frames is after the first frame. Additionally, a first indication of the subsequent frame transfer interrupt time may be sent to the DPU. In some aspects, sending the first indication of the subsequent frame transfer interrupt time may include: programming the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time. That is, the CPU may program the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time.

[0089] At 1070, the CPU 1002 may send a second indication to the Display Processing Unit (DPU) for transmitting a set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time (e.g., sending indication 1072 to the DPU 1006). The transmission of the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency may correspond to the amortization of the pixel transfer of the set of second frames. Additionally, the DPU may be programmed to transmit the set of second frames during the subsequent frame programming time. In some aspects, sending the second indication for transmitting the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency may include: programming the DPU to transmit the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency. That is, the CPU may program the DPU to transmit the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency. In some aspects, the second indication for transmitting the set of second frames may be generated by at least one of a Central Processing Unit (CPU) or DPU driver software. Additionally, the DPU may include at least one of the following: DPU hardware or at least one display processor. In some instances, the set of second frames may be transmitted at a reduced DPU clock frequency and a reduced bandwidth frequency until the adjustment of the panel ROI of the set of second frames.

[0090] At 1080, the CPU 1002 may identify the adjustment of the panel ROI of the set of second frames.

[0091] Additionally, at 1080, the CPU 1002 may send a third indication to the DPU for transmitting the set of second frames at the full DPU clock frequency and the full bandwidth frequency based on the adjustment of the panel ROI of the set of second frames (e.g., sending indication 1082 to the DPU 1006). The third indication may be sent to the DPU at the subsequent Vsync time. In some aspects, sending the third indication for transmitting the set of second frames at the full DPU clock frequency and the full bandwidth frequency may include: reprogramming the DPU to transmit the set of second frames at the full DPU clock frequency and the full bandwidth frequency. That is, the CPU may reprogram the DPU to transmit the set of second frames at the full DPU clock frequency and the full bandwidth frequency.

[0092] Figure 11 is a flowchart 1100 of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a CPU (or other central processor), DPU driver, DPU (or other display processor), GPU (or other graphics processor), DDIC, a device for display processing, a wireless communication device, and / or any device that can execute the display processing used in combination Figures 1 to 10 of the example use.

[0093] At 1104, the CPU may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1020 of Figure 10 , the CPU 1002 may perform a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame. Additionally, step 1104 may be performed by the Figure 1 processing unit 120 in. In some aspects, the partial frame update for the first frame may be performed at the full DPU clock frequency and the full bandwidth frequency.

[0094] At 1106, the CPU may calculate a margin time period between the first update time and a subsequent vertical sync (Vsync) time, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1030 of Figure 10 , the CPU 1002 may calculate a margin time period between the first update time and a subsequent vertical sync (Vsync) time. Additionally, step 1106 may be performed by the Figure 1 processing unit 120 in. In some aspects, calculating the margin time period between the first update time and a subsequent Vsync time may include: generating one or more software duration heuristics; and predicting one or more synthetic timelines for the panel ROI of a set of second frames. That is, the CPU may generate one or more software duration heuristics; and predict one or more synthetic timelines for the panel ROI of a set of second frames.

[0095] At 1112, the CPU may send a first indication of a subsequent frame transfer interrupt time based on the margin time period, where the subsequent frame transfer interrupt time is associated with a start time of transferring a set of second frames before a subsequent Vsync time, and where the set of second frames is after the first frame, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1060 of Figure 10 , the CPU 1002 may send a first indication of a subsequent frame transfer interrupt time based on the margin time period, where the subsequent frame transfer interrupt time is associated with a start time of transferring a set of second frames before a subsequent Vsync time, and where the set of second frames is after the first frame. Additionally, step 1112 may be performed by the Figure 1It is executed by the processing unit 120 in []. In addition, a first indication of the subsequent frame transfer interrupt time may be sent to the DPU. In some aspects, sending the first indication of the subsequent frame transfer interrupt time may include: programming the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time. That is, the CPU may program the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time.

[0096] At 1114, the CPU may send a second indication to the display processing unit (DPU), and this second indication is used to transfer a set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interrupt time, as described in the example in conjunction with Figures 1 to 10 []. For example, as described in 1070 of Figure 10 , the CPU 1002 may send a second indication to the display processing unit (DPU), and this second indication is used to transfer a set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interrupt time. In addition, step 1114 may be executed by the processing unit 120 in Figure 1 []. Transferring the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency may correspond to the amortization of pixel transfer of the set of second frames. In addition, the DPU may be programmed to transfer the set of second frames at the subsequent frame programming time. In some aspects, sending the second indication for transferring the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency may include: programming the DPU to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency. That is, the CPU may program the DPU to transfer the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency. In some aspects, the second indication for transferring the set of second frames may be generated by at least one of a central processing unit (CPU) or DPU driver software. In addition, the DPU may include at least one of the following: DPU hardware or at least one display processor. In some instances, the set of second frames may be transferred at a reduced DPU clock frequency and a reduced bandwidth frequency until the adjustment of the panel ROI of the set of second frames.

[0097] Figure 12 is a flowchart 1200 of an example method of display processing according to one or more techniques of the present disclosure. This method may be executed by a CPU (or other central processor), DPU driver, DPU (or other display processor), GPU (or other graphics processor), DDIC, a device for display processing, a wireless communication device, and / or any device that can execute the display processing used in the example in conjunction with Figures 1 to 10 [].

[0098] At 1202, the CPU may receive a frame indication for a first frame before a partial frame update for the first frame, as described in the example in conjunction with Figures 1 to 10 as described. For example, as Figure 10 described in 1010 of Figure 1 , the CPU 1002 may receive a frame indication for the first frame before a partial frame update for the first frame. Additionally, step 1202 may be performed by the

[0099] processing unit 120 in Figures 1 to 10 as described. For example, as Figure 10 described in 1010 of Figure 1 , the CPU 1002 may identify that the first frame is associated with a partial frame update. Additionally, step 1202 may be performed by the

[0100] processing unit 120 in Figures 1 to 10 as described. For example, as Figure 10 described in 1020 of Figure 1 , the CPU 1002 may perform a partial frame update for the first frame at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame, as described in the example in conjunction with

[0101] In some aspects, the partial frame update for the first frame may be performed at a full DPU clock frequency and a full bandwidth frequency. At 1206, the CPU may calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time, as described in the example in conjunction with Figures 1 to 10 as described. For example, as Figure 10 described in 1030 of Figure 1 , the CPU 1002 may calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time. Additionally, step 1206 may be performed by the

[0102] At 1208, the CPU may switch to a synthesizer latch signaling model based on a partial frame update for a first frame, where the synthesizer latch signaling model is a software model associated with immediate consumption of frames by the DPU, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1040 of Figure 10 , the CPU 1002 may switch to a synthesizer latch signaling model based on a partial frame update for a first frame, where the synthesizer latch signaling model is a software model associated with immediate consumption of frames by the DPU. Additionally, step 1208 may be performed by the processing unit 120 in Figure 1 .

[0103] At 1210, the CPU may calculate a subsequent frame transfer interrupt time based on a margin time period between a first update time and a subsequent Vsync time, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1050 of Figure 10 , the CPU 1002 may calculate a subsequent frame transfer interrupt time based on a margin time period between a first update time and a subsequent Vsync time. Additionally, step 1210 may be performed by the processing unit 120 in Figure 1 .

[0104] At 1212, the CPU may send a first indication of the subsequent frame transfer interrupt time based on the margin time period, where the subsequent frame transfer interrupt time is associated with a start time of transferring a set of second frames before a subsequent Vsync time, where the set of second frames is after the first frame, as described in the example in conjunction with Figures 1 to 10 as described. For example, as described in 1060 of Figure 10 , the CPU 1002 may send a first indication of the subsequent frame transfer interrupt time based on the margin time period, where the subsequent frame transfer interrupt time is associated with a start time of transferring a set of second frames before a subsequent Vsync time, where the set of second frames is after the first frame. Additionally, step 1212 may be performed by the processing unit 120 in Figure 1 . Additionally, a first indication of the subsequent frame transfer interrupt time may be sent to the DPU. In some aspects, sending the first indication of the subsequent frame transfer interrupt time may include: programming the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time. That is, the CPU may program the DPU to generate the subsequent frame transfer interrupt time before the subsequent Vsync time.

[0105] At 1214, the CPU may send a second indication to a display processing unit (DPU) for transferring the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interrupt time, as described in the example in conjunction with Figures 1 to 10as described in the example in Figure 10 As described in 1070 of Figure 10 , the CPU 1002 may send a second indication to the display processing unit (DPU), and the second indication is used to transfer a set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time. In addition, step 1214 may be performed by Figure 1 the processing unit 120 in

[0106] At 1216, the CPU may identify an adjustment to the panel ROI of the set of second frames, as described in connection with Figures 1 to 10 the example in Figure 10 As described in 1080 of Figure 10 , the CPU 1002 may identify an adjustment to the panel ROI of the set of second frames. In addition, step 1216 may be performed by Figure 1 the processing unit 120 in

[0107] In addition, at 1216, the CPU may send a third indication to the DPU, and the third indication is used to transfer the set of second frames at the full DPU clock frequency and the full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames, as described in connection with Figures 1 to 10 the example in Figure 10 As described in 1080 of Figure 10 , the CPU 1002 may send a third indication to the DPU, and the third indication is used to transfer the set of second frames at the full DPU clock frequency and the full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames. In addition, step 1216 may be performed by Figure 1It is executed by the processing unit 120 therein. A third indication can be sent to the DPU at a subsequent Vsync time. In some aspects, sending the third indication for transmitting the set of second frames at the full DPU clock frequency and the full bandwidth frequency can include: reprogramming the DPU to transmit the set of second frames at the full DPU clock frequency and the full bandwidth frequency. That is, the CPU can reprogram the DPU to transmit the set of second frames at the full DPU clock frequency and the full bandwidth frequency.

[0108] In various configurations, a method or apparatus for display processing is provided. The apparatus can be a CPU (or other central processing unit), DPU (or other display processing unit), GPU (or other graphics processing unit), DPU driver, DDIC, an apparatus for display processing, and / or some other processor capable of performing display processing. In various aspects, the apparatus can be the processing unit 120 within the device 104, or can be some other hardware within the device 104 or another device. The apparatus (e.g., the processing unit 120) can include components for performing a partial frame update for a first frame at a first update time, where the partial frame update corresponds to an update of less than all of the content in the first frame, and where the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame. The apparatus (e.g., the processing unit 120) can also include components for calculating a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time. The apparatus (e.g., the processing unit 120) can also include components for sending a first indication of a subsequent frame delivery interrupt time based on the margin time period, where the subsequent frame delivery interrupt time is associated with a start time for delivering a set of second frames before the subsequent Vsync time, and where the set of second frames is after the first frame. The apparatus (e.g., the processing unit 120) can also include components for sending a second indication to a display processing unit (DPU) for delivering the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame delivery interrupt time. The apparatus (e.g., the processing unit 120) can also include components for identifying an adjustment to the panel ROI of the set of second frames. The apparatus (e.g., the processing unit 120) can also include components for sending a third indication to the DPU for delivering the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames. The apparatus (e.g., the processing unit 120) can also include components for switching to a compositor latch signaling model based on the partial frame update for the first frame, where the compositor latch signaling model is a software model associated with the DPU's immediate consumption of frames. The apparatus (e.g., the processing unit 120) can also include components for calculating the subsequent frame delivery interrupt time based on the margin time period between the first update time and the subsequent Vsync time. The apparatus (e.g., the processing unit 120) can also include components for receiving a frame indication for the first frame before the partial frame update for the first frame. The apparatus (e.g., the processing unit 120) can also include components for identifying the first frame as being associated with the partial frame update.

[0109] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described display processing techniques can be used by a CPU, a central processing unit, a DPU driver, a DPU, a display processor, a GPU, or some other processor capable of performing display processing to implement the partial frame update techniques described herein. This can also be implemented at low cost compared to other display processing techniques. Additionally, the display processing techniques herein can improve or accelerate data processing or execution. Further, the display processing techniques herein can improve resource or data utilization and / or resource efficiency. Additionally, aspects of the present disclosure can utilize partial frame update techniques in order to improve memory bandwidth efficiency and / or increase the processing speed at the CPU, DPU, or GPU.

[0110] It should be understood that the particular order or hierarchy of the blocks in the disclosed process / flowchart is illustrative of example methods. It should be understood that based on design preferences, the particular order or hierarchy of the blocks in the process / flowchart can be rearranged. Further, some blocks can be combined or omitted. The appended method claims present the elements of the various blocks in a sample order, but are not meant to be limited to the particular order or hierarchy presented.

[0111] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, where the reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but rather "one or more". The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0112] Unless otherwise specifically stated, the term "some" refers to one or more, and the term "or" may be interpreted as "and / or" where the context does not otherwise dictate. Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof", including any combination of A, B, and / or C, can include multiple A's, multiple B's, or multiple C's. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combination can include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public, whether or not such disclosure is explicitly recited in the claims. The words "module", "mechanism", "element", "device", etc. are not intended to substitute for the word "component". Thus, no claim element will be construed as a functional component unless the element is expressly recited using the phrase "component for...".

[0113] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on or transmitted over a computer-readable medium as one or more instructions or code.

[0114] According to the present disclosure, the term "or" may be understood as "and / or" where the context does not otherwise dictate. Additionally, although phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for others, features for which such language is not used may be understood to have such an implicit meaning where the context does not otherwise dictate.

[0115] In one or more examples, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing units can be implemented in hardware, software, firmware, or any combination thereof. If any of the functions, processing units, techniques, or other modules described herein are implemented in software, the functions, processing units, techniques, or other modules described herein can be stored on or transmitted over a computer-readable medium as one or more instructions or code. A computer-readable medium can include computer data storage media and communication media, which include any medium that facilitates transfer of a computer program from one place to another. In this manner, a computer-readable medium generally can correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium can be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. As used herein, disk and optical disks include: compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks utilize lasers to reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media. A computer program product can include a computer-readable medium.

[0116] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, as used herein, the term "processor" can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Additionally, these techniques can be fully implemented in one or more circuits or logic elements.

[0117] The techniques of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs) or groups of ICs (e.g., chip sets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of the devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with suitable software and / or firmware. Thus, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Similarly, these techniques can be fully implemented in one or more circuits or logic elements.

[0118] The following aspects are merely illustrative and can be combined with other aspects or teachings described herein without limitation.

[0119] Aspect 1 is a device for display processing, the device comprising: a memory and at least one processor, the at least one processor being coupled to the memory and being configured to, at least in part based on information stored in the memory, perform a partial frame update for a first frame at a first update time, wherein the partial frame update corresponds to an update of less than all the content in the first frame, and wherein the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame; calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time; based on the margin time period, send a first indication of a subsequent frame transfer interruption time, wherein the subsequent frame transfer interruption time is associated with a start time of transferring a set of second frames before the subsequent Vsync time, wherein the set of second frames is after the first frame; and send a second indication to a display processing unit (DPU), the second indication being for transferring the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time.

[0120] Aspect 2 is the device according to aspect 1, wherein the at least one processor is further configured to: identify an adjustment of the panel ROI of the set of second frames; and send a third indication to the DPU, the third indication being for transferring the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment of the panel ROI of the set of second frames.

[0121] Aspect 3 is the apparatus according to aspect 2, wherein, to send the third indication for transmitting the set of second frames at the full DPU clock frequency and the full bandwidth frequency, the at least one processor is configured to: reprogram the DPU to transmit the set of second frames at the full DPU clock frequency and the full bandwidth frequency.

[0122] Aspect 4 is the apparatus according to any one of aspects 2 to 3, wherein, to send the third indication, the at least one processor is configured to: send the third indication to the DPU at the subsequent Vsync time.

[0123] Aspect 5 is the apparatus according to any one of aspects 1 to 4, wherein, to calculate the margin time period between the first update time and the subsequent Vsync time, the at least one processor is configured to: generate one or more software duration heuristics; and predict one or more synthetic timelines of the panel ROI of the set of second frames.

[0124] Aspect 6 is the apparatus according to any one of aspects 1 to 5, wherein the at least one processor is further configured to: switch to a synthesizer latch signaling model based on the partial frame update for the first frame, wherein the synthesizer latch signaling model is a software model associated with the immediate consumption of frames by the DPU.

[0125] Aspect 7 is the apparatus according to any one of aspects 1 to 6, wherein the at least one processor is further configured to: calculate the subsequent frame transfer interruption time based on the margin time period between the first update time and the subsequent Vsync time.

[0126] Aspect 8 is the apparatus according to any one of aspects 1 to 7, wherein, to send the first indication of the subsequent frame transfer interruption time, the at least one processor is configured to: program the DPU to generate the subsequent frame transfer interruption time before the subsequent Vsync time.

[0127] Aspect 9 is the apparatus according to any one of aspects 1 to 8, wherein the transfer of the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency corresponds to the amortization of the pixel transfer of the set of second frames.

[0128] Aspect 10 is the apparatus according to any one of aspects 1 to 9, wherein, to send the second indication for transmitting the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency, the at least one processor is configured to: program the DPU to transmit the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency.

[0129] Aspect 11 is the apparatus according to aspect 10, wherein the at least one processor is configured to program the DPU to deliver the set of the second frame at a subsequent frame programming time.

[0130] Aspect 12 is the apparatus according to any one of aspects 1 to 11, wherein the at least one processor is further configured to: receive a frame indication of the first frame before the partial frame update for the first frame; and identify that the first frame is associated with the partial frame update.

[0131] Aspect 13 is the apparatus according to any one of aspects 1 to 12, wherein, in order to send the first indication of the subsequent frame delivery interruption time, the at least one processor is configured to: send the first indication of the subsequent frame delivery interruption time to the DPU.

[0132] Aspect 14 is the apparatus according to any one of aspects 1 to 13, wherein the partial frame update for the first frame is configured to be performed at a full DPU clock frequency and a full bandwidth frequency.

[0133] Aspect 15 is the apparatus according to any one of aspects 1 to 14, wherein the second indication for delivering the set of the second frame is configured to be generated by at least one of the following: a central processing unit (CPU) or DPU driver software, and wherein the DPU includes at least one of the following: DPU hardware or at least one display processor.

[0134] Aspect 16 is the apparatus according to any one of aspects 1 to 15, the apparatus further including at least one of an antenna or a transceiver coupled to the at least one processor, wherein, in order to send the second indication, the at least one processor is configured to send the second indication via at least one of the antenna or the transceiver, and wherein the set of the second frame is configured to be delivered at the reduced DPU clock frequency and the reduced bandwidth frequency until adjustment of a panel ROI of the set of the second frame.

[0135] Aspect 17 is a method for implementing display processing according to any one of aspects 1 to 16.

[0136] Aspect 18 is a display processing apparatus, the apparatus including components for implementing any one of aspects 1 to 16.

[0137] Aspect 19 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer-executable code, the code causing the at least one processor to implement any one of aspects 1 to 16 when executed by the at least one processor.

Claims

1. An apparatus for display processing, the apparatus comprising: a memory; and at least one processor coupled to the memory, and at least partially based on information stored in the memory, the at least one processor being configured to: perform a partial frame update for a first frame at a first update time, wherein the partial frame update corresponds to an update of less than all content in the first frame, and wherein the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame; calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time; based on the margin time period, send a first indication of a subsequent frame transfer interruption time, wherein the subsequent frame transfer interruption time is associated with a start time of transferring a set of second frames before the subsequent Vsync time, and wherein the set of second frames is after the first frame; and send a second indication to a display processing unit (DPU), the second indication for transferring the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time.

2. The apparatus according to claim 1, wherein the at least one processor is further configured to: identify an adjustment to the panel ROI of the set of second frames; and send a third indication to the DPU, the third indication for transferring the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames.

3. The apparatus according to claim 2, wherein in order to send the third indication for transferring the set of second frames at the full DPU clock frequency and the full bandwidth frequency, the at least one processor is configured to: reprogram the DPU to transfer the set of second frames at the full DPU clock frequency and the full bandwidth frequency.

4. The apparatus according to claim 2, wherein in order to send the third indication, the at least one processor is configured to: send the third indication to the DPU at the subsequent Vsync time.

5. The apparatus according to claim 1, wherein in order to calculate the margin time period between the first update time and the subsequent Vsync time, the at least one processor is configured to: generate one or more software duration heuristics; and predict one or more synthetic timelines of the panel ROI of the set of second frames.

6. The apparatus according to claim 1, wherein the at least one processor is further configured to: switch to a synthesizer latch signaling model based on the partial frame update for the first frame, wherein the synthesizer latch signaling model is a software model associated with immediate consumption of frames by the DPU.

7. The apparatus according to claim 1, wherein the at least one processor is further configured to: calculate the subsequent frame transfer interruption time based on the margin time period between the first update time and the subsequent Vsync time.

8. The apparatus according to claim 1, wherein, in order to send the first indication of the subsequent frame transfer interruption time, the at least one processor is configured to: program the DPU to generate the subsequent frame transfer interruption time before the subsequent Vsync time.

9. The apparatus according to claim 1, wherein the transfer of the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency corresponds to the amortization of the pixel transfer of the set of second frames.

10. The apparatus according to claim 1, wherein, in order to send the second indication for transferring the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency, the at least one processor is configured to: program the DPU to transfer the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency.

11. The apparatus according to claim 10, wherein the at least one processor is configured to program the DPU to transfer the set of second frames at a subsequent frame programming time.

12. The apparatus according to claim 1, wherein the at least one processor is further configured to: receive a frame indication of the first frame before the partial frame update for the first frame; and identify that the first frame is associated with the partial frame update.

13. The apparatus according to claim 1, wherein, in order to send the first indication of the subsequent frame transfer interruption time, the at least one processor is configured to: send the first indication of the subsequent frame transfer interruption time to the DPU.

14. The apparatus according to claim 1, wherein the partial frame update for the first frame is configured to be performed at a full DPU clock frequency and a full bandwidth frequency.

15. The apparatus according to claim 1, wherein the second indication for transferring the set of second frames is configured to be generated by a central processing unit (CPU), and wherein the DPU includes DPU hardware.

16. The apparatus according to claim 1, the apparatus further includes a transceiver coupled to the at least one processor, wherein, in order to send the second indication, the at least one processor is configured to send the second indication via the transceiver, and wherein the set of second frames is configured to be transferred at the reduced DPU clock frequency and the reduced bandwidth frequency until the adjustment of the panel ROI of the set of second frames.

17. A method for display processing, the method includes: performing a partial frame update for a first frame at a first update time, wherein the partial frame update corresponds to an update of less than all the content in the first frame, and wherein the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame; calculating a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time; Based on the margin time period, send a first indication of a subsequent frame delivery interruption time, where the subsequent frame delivery interruption time is associated with a start time of delivering a set of second frames before the subsequent Vsync time, and the set of second frames is after the first frame; and Send a second indication to a Display Processing Unit (DPU), where the second indication is for delivering the set of second frames starting from the subsequent frame delivery interruption time at a reduced DPU clock frequency and a reduced bandwidth frequency.

18. The method according to claim 17, the method further comprising: Identify an adjustment to a panel ROI of the set of second frames; And Send a third indication to the DPU, where the third indication is for delivering the set of second frames at a full DPU clock frequency and a full bandwidth frequency based on the adjustment to the panel ROI of the set of second frames.

19. The method according to claim 18, wherein sending the third indication of the set for delivering the second frame at the full DPU clock frequency and the full bandwidth frequency comprises: Reprogram the DPU to deliver the set of second frames at the full DPU clock frequency and the full bandwidth frequency, and where the third indication is sent to the DPU at the subsequent Vsync time.

20. The method according to claim 17, wherein calculating the margin period between the first update time and the subsequent Vsync time comprises: Generate one or more software duration heuristics; And predict one or more synthetic timelines of a panel ROI of the set of second frames.

21. The method according to claim 17, the method further comprising: Based on the partial frame update for the first frame, switch to a synthesizer latch signaling model, where the synthesizer latch signaling model is a software model associated with immediate consumption of frames by the DPU.

22. The method according to claim 17, the method further comprising: Calculate the subsequent frame delivery interruption time based on the margin time period between the first update time and the subsequent Vsync time.

23. The method according to claim 17, wherein sending the first indication of the subsequent frame transfer interruption time includes: Program the DPU to generate the subsequent frame delivery interruption time before the subsequent Vsync time.

24. The method according to claim 17, where the delivery of the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency corresponds to amortization of pixel delivery of the set of second frames.

25. The method according to claim 17, wherein sending the second indication for transmitting the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency comprises: Program the DPU to deliver the set of second frames at the reduced DPU clock frequency and the reduced bandwidth frequency, and where the DPU is programmed to deliver the set of second frames at a subsequent frame programming time.

26. The method according to claim 17, the method further comprising: Receive a frame indication of the first frame before the partial frame update for the first frame; And Identify the first frame as being associated with the partial frame update.

27. The method according to claim 17, where the first indication of the subsequent frame delivery interruption time is sent to the DPU, and where the partial frame update for the first frame is performed at a full DPU clock frequency and a full bandwidth frequency.

28. The method according to claim 17, wherein the second indication for transmitting the set of second frames is generated by a central processing unit (CPU), and wherein the DPU includes DPU hardware, and wherein the set of second frames is transmitted at the reduced DPU clock frequency and the reduced bandwidth frequency until adjustment of the panel ROI of the set of second frames.

29. An apparatus for display processing, the apparatus comprising: means for performing a partial frame update for a first frame at a first update time, wherein the partial frame update corresponds to an update of less than all of the content in the first frame, and wherein the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame; means for calculating a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time; means for sending a first indication of a subsequent frame transfer interruption time based on the margin time period, wherein the subsequent frame transfer interruption time is associated with a start time of transmitting a set of second frames before the subsequent Vsync time, and wherein the set of second frames is after the first frame; and means for sending a second indication to a display processing unit (DPU), the second indication for transmitting the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time.

30. A computer-readable medium storing computer-executable code for display processing, the code causing the processor to: perform a partial frame update for a first frame at a first update time, wherein the partial frame update corresponds to an update of less than all of the content in the first frame, and wherein the partial frame update for the first frame is associated with a panel region of interest (ROI) of the first frame; calculate a margin time period between the first update time and a subsequent vertical synchronization (Vsync) time; send a first indication of a subsequent frame transfer interruption time based on the margin time period, wherein the subsequent frame transfer interruption time is associated with a start time of transmitting a set of second frames before the subsequent Vsync time, and wherein the set of second frames is after the first frame; and send a second indication to a display processing unit (DPU), the second indication for transmitting the set of second frames at a reduced DPU clock frequency and a reduced bandwidth frequency starting from the subsequent frame transfer interruption time.

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