Glass substrate device with embedded component

Abstract

An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and discrete passive components disposed in other cavities; a molding layer including a molding layer active component die disposed in the molding layer; and a build-up layer contacting a top surface of the glass core layer and a bottom surface of the molding layer. The build-up includes conductive interconnects connecting the glass core layer active component die, the discrete passive component, and the molded layer active component die. A top surface of the component die is electrically connected to the molded layer active component die.

Description

Claim for Priority

[0001] This application claims priority to U.S. Patent Application No. 18 / 086,293, filed on December 21, 2022, and titled "Glass Substrate Device with Embedded Components", the entire content of which is incorporated herein by reference. Technical Field

[0002] Embodiments relate to the packaging of electronic systems. Some embodiments relate to techniques for embedding electronic devices in a glass packaging substrate. Background Art

[0003] The complexity of electronic systems continues to increase while maintaining their small size is desired. By reducing the size of electronic circuits to include more circuits in the same or smaller package, this has led to an increase in the density of electronic circuits. Thermal management in electronic systems continues to be a challenge, which is becoming increasingly exacerbated with more complex architectures and higher power components. Brief Description of the Drawings

[0004] Figure 1 is a diagrammatic illustration of a cross-sectional side view of an example of a substrate for an electronic system according to some embodiments;

[0005] Figures 2A - 2H illustrates a flowchart of an example of a method of manufacturing a substrate for an electronic system according to some embodiments;

[0006] Figure 3 and Figure 4 is a diagrammatic illustration of a cross-sectional side view of an example of an electronic system according to some embodiments;

[0007] Figure 5 is a diagrammatic illustration of a cross-sectional side view of an example of an electronic system according to some embodiments;

[0008] Figures 6 - 9 is according to some embodiments Figure 5 a diagrammatic illustration of a top view of a glass core layer, component die, and multi-die interconnect bridge;

[0009] Figures 10A - 10H illustrates a flowchart of another example of a method of manufacturing a substrate for an electronic system according to some embodiments;

[0010] Figure 11 is a diagrammatic illustration of a cross-sectional side view of another example of an electronic system according to some embodiments;

[0011] Figures 12 - 15 is according to some embodiments Figure 11 a diagrammatic illustration of a top view of a glass core layer, component die, discrete passive components, and multi-die interconnect bridge;

[0012] Figures 16A - 16H A flowchart illustrating another example of a method for manufacturing a substrate for an electronic system in accordance with some embodiments;

[0013] Figure 17 A system-level diagram in accordance with some embodiments is illustrated. DETAILED DESCRIPTION

[0014] The following description and drawings sufficiently disclose specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments recited in the claims cover all available equivalents of those claims.

[0015] To meet the demand for increased functional complexity in smaller devices, manufacturers integrate multiple integrated circuit (IC) dies in a single electronic package to create an efficient electronic system within the package. The electronic package may include a substrate core, on which an interconnect build-up layer having interconnects for the ICs of the packaged electronic system is formed. As manufacturers continue to increase circuit density, thermal management and power management in the electronic package become challenging.

[0016] Typically, all dies included in an electronic package are placed on the top surface of the substrate of the electronic package, and interconnect bridges or a base interposer are used to connect the dies. Due to thermal crosstalk, this two-dimensional electronic packaging method may negatively impact the potential performance of the components. In thermal crosstalk, higher-power and hotter dies heat lower-power dies, resulting in thermal throttling. Additionally, the two-dimensional method typically has all inputs and power from the top surface of the substrate.

[0017] Figure 1 An illustration of a cross-sectional side view of an example of a substrate 102 for an electronic system is shown. The substrate 102 includes a glass core layer 104. The glass core layer 104 may include a silicate-based glass (e.g., lithium silicate, borosilicate, aluminosilicate, etc.). In a variant, the glass of the glass core layer is a lower-quality glass (e.g., glass made of soda-lime glass) or a higher-quality glass (e.g., fused silica glass made of fused quartz).

[0018] One or more cavities 106 are formed in the glass core layer 104, and at least one active component die 108 is disposed in each of the cavities 106. The active component die 108 includes a plurality of active circuit components, such as a plurality of transistors. The active component die 108 may also include passive circuit components (e.g., capacitors, inductors, and resistors). As a non-limiting example by way of intention, the active component die 108 may be a memory die, such as a high bandwidth memory (HBM) component die. In some examples, a plurality of memory dies may be disposed in the cavities as a stack of memory dies.

[0019] The substrate 102 includes a top build-up 110 on the top surface of the glass core layer 104 and a bottom build-up 112 on the bottom surface of the glass core layer 104. The top build-up 110 includes conductive interconnects. The conductive interconnects may include metal vias 114 and metal traces. The conductive interconnects contact the active component dies disposed in the cavities 106 and extend to the top surface of the substrate 102, where the interconnects may contact another component to provide electrical continuity between the components. In Figure 1 an example, the active component die 108 extends beyond the cavity 106 within the glass core layer 104 and into the top build-up 110 and the bottom build-up 112. In a variant, the active component die 108 does not extend beyond the surface of the glass core layer 104.

[0020] In some examples, the conductive interconnects may include multi-die interconnect bridges (MIBs) 122 embedded in the build-up. The MIB 122 is a small component having features created using a lithography process. The MIB 122 may include silicon material or organic material. The MIB 122 includes conductive interconnects having features with finer pitch and higher density compared to the build-up. The MIB 122 provides a very high density die-to-die connection where needed in the substrate 102.

[0021] The MIB 122 may provide electrical continuity between at least one input / output (I / O) pad of the active component die 108 disposed in the cavity 106 and at least one I / O pad of another component mounted on the top surface of the substrate 102. In Figure 1 an example, the bottom side of the MIB 122 is electrically connected to the top side of the active component die 108, and the top side of the MIB 122 will be electrically connected to another component on top of the substrate.

[0022] The bottom surface of the bottom build-up 112 is the bottom surface of the substrate 102. The substrate 102 includes solder bumps 116 on the bottom surface. Some of these solder bumps may contact the bottom of the active component die 108. Figure 1An example shows a solder bump formation 118 that is larger in size than other solder bumps 116. The smaller solder bumps 116 can be ball grid array (BGA) solder pumps for carrying electrical signals. The larger solder bump formation 118 can carry heat away from the substrate 102 and can be attached to a cooling structure, such as one or more heat-conducting metal slugs included in a motherboard. The bottom side of the active component die 108 can include a weldable metallization layer 120 to bond to the larger solder bump formation 118. The weldable metallization layer 120 can include one or both of titanium and nickel. The weldable metallization layer 120 can include a gold surface.

[0023] In some examples, all of the solder bumps 116 on the bottom surface of the substrate 102 are smaller-sized solder bumps 116. Some of the solder bumps 116 on the bottom surface can be electrically connected to the active review chip 108. The solder bumps 116 can be used to route one or more power inputs to the active component die 108, and the power routing can be removed from the top surface of the substrate 102.

[0024] Figures 2A - 2H Illustrated is a flowchart of an example of a method of manufacturing a substrate (such as Figure 1 the substrate 102) for an electronic system. Figure 2A is a side view of the glass core layer 104. In Figure 2B , a cavity 106 is formed in the glass core layer 104. The cavity 106 can extend all the way through the glass core layer 104, as shown in Figure 2B (through the glass core), or the cavity 106 can only partially extend through the glass core layer 104 (embedded glass core). The cavity 106 can be formed by drilling (e.g., laser drilling), and in some examples, the cavity 106 is formed by a drilling and wet etching process.

[0025] In Figure 2C , a stack-up is formed on the glass core layer 104, which includes one or more top stack-ups 110 on the top surface of the glass core layer 104 and one or more bottom stack-ups 112 on the bottom surface of the glass core layer 104. In Figure 2C 's example, the cavity 106 extends all the way through the top stack-up 110 and only extends through a portion of the bottom stack-up 112. In a variant, the cavity 106 can extend all the way through the bottom stack-up 112, or the cavity 106 can stop only within the glass core layer 104 and at the top surface of the bottom stack-up 112.

[0026] In Figure 2D , the active component die 108 is disposed in the cavity 106. In Figure 2DIn an example, a stack of memory dies is disposed in a cavity, and the stack of memory dies extends through the glass core layer 104 and reaches the top surface of the top laminate 110. An adhesive 224 can be used to attach the active component die 108 to the bottom laminate 112. A solderable metallization layer 120 can be added to the cavity before one or more active component dies 108 are placed in the cavity, or the solderable metallization layer 120 can be added to the bottom surface of one or more active component dies 108.

[0027] Figure 2E Additional laminate patterning added to the top laminate 110 is shown, which includes conductive interconnects such as vias 114 and conductive traces. The conductive interconnects contact the top surface of one or more active component dies 108 and extend to the top surface of the top laminate 110 and the substrate. Figure 2E An example shows that the conductive interconnect can include a MIB 122 disposed in the top laminate 110. The bottom side of the MIB 122 (e.g., via via 226) is connected to the I / O pads on the top surface of one or more active component dies 108. The top side of the MIB 122 can be connected to a via 228 that extends to the top surface of the substrate. In Figure 2E it can be seen that the MIB 122 and vias 226, 228 can have a finer pitch than other conductive interconnects (e.g., via 114). The vias 226, 228 can be connected to another active component that can match the pitch of via 228.

[0028] In Figure 2F an opening is formed in the bottom laminate 112, and solder is to be added to the opening. A smaller opening 230 extends to the conductive interconnect and is for a solder bump that carries a signal. A larger opening 232 extends to the solderable metallization layer 120 or the bottom surface of the active component die 108. The larger opening 232 is for a larger solder bump formation that is used to carry away heat from the active component die 108. In Figure 2G a solder bump 116 that carries a signal is formed in the smaller opening 230, and a larger heat-conductive solder bump 118 is formed in the larger opening 232.

[0029] Figure 2H An alternative is shown where a smaller opening 230 is formed under the active component die 108. The opening can be used for a power connection to the active component die 108.

[0030] Figure 3 is a side view of an electronic system 300 that includes a substrate 102, such as Figure 1The substrate. Another active component 334 is attached to the top surface of the substrate 102. In a non-limiting example, the active component 334 on the top surface of the substrate 102 is a computing component die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or other processing unit (XPU)). One active component die 108 or multiple active component dies disposed in the cavity of the substrate include multiple memory dies arranged in a stacked manner as memory dies in the cavity of the substrate 102. The bottom side of the active component 334 is electrically connected to the top side of the MIB 122. The bottom side of the MIB 122 is connected to the top side of one active component die 108 or multiple active component dies in the cavity of the substrate 102.

[0031] The substrate 102 is attached to the motherboard 336 using BGA solder bumps 116 for a BGA socket. The substrate 102 includes thermal conduction solder bumps 118 that contact a metal cooling structure (e.g., a copper bar 338) of the motherboard under the socket to assist in cooling the electronic system 300.

[0032] Figure 4 is a side view of the electronic system 400, and the electronic system 400 includes a substrate 102, such as Figure 1 the substrate. The substrate 102 includes land grid array (LGA) pins for connecting to one active component die 108 or multiple active component dies in an LGA socket to cool through one active component die 108 or multiple active component die systems.

[0033] Placing the active component die in the cavity of the glass core layer 104 also provides the advantage of solving the height mismatch between the active dies of the electronic system. For example, if the computing component die has a different height from the memory component die, placing both dies on the top surface of the substrate results in a system with different die heights. This mismatch in die height can make thermal management in the system challenging because it complicates the design of the thermal management structure (e.g., a heat sink) that contacts the top of the die.

[0034] Figure 5 is an illustration of a cross-sectional side view of another example of an electronic system 500 including a substrate 502 and an active component die 534 on the top surface of the substrate 502. The top surface active component die 534 can be a computing component die. The substrate 502 includes a glass core layer 504. The glass core layer 504 includes multiple cavities, and an active component die 508 is disposed in the cavity of the glass core layer 504. The glass core layer active component die 508 can be an HBM component. In Figure 5 the example, the HBM component includes multiple memory dies (e.g., eight memory dies) arranged in a memory die stack.

[0035] Figure 6 is a top view of a glass core layer 504 and a plurality of glass core layer active component dies 508. The example shown includes four cavities in the glass core layer 504 and glass core layer active component dies 508 in each of the cavities. For simplicity of the drawings, four cavities are shown. An actual implementation may include many cavities (e.g., dozens of cavities).

[0036] Returning to Figure 5 , the substrate 502 includes a top build-up layer 510 that contacts the top surface of the glass core layer 504. The top build-up layer 510 may be a redistribution layer (RDL) of conductive interconnects included in a dielectric material. The substrate 502 also includes a bottom build-up layer 512. In Figure 5 's example, the cavities in the glass core layer 504 extend into the bottom build-up layer 512. The stack of memory dies extends out of the glass core layer 504 into the bottom build-up layer 512 and the top build-up layer 510. An adhesive 524 may be included at the bottom of the cavities. In some examples, the glass core layer active component dies 508 are within the glass core layer 504, and the adhesive 524 may be placed on the surface of the bottom build-up layer 512.

[0037] The substrate 502 includes a molding layer 542 that contacts the top surface of the top build-up layer 510. The molding layer 542 includes at least one molding layer active component die 544 disposed in the molding layer 542. In Figure 5 's example, the molding layer active component die 544 is an I / O component die encapsulated in the molding layer 542. The I / O component die may provide I / O for the system 500. In some examples, the I / O component die may include a memory controller for managing I / O between the compute component die and the memory die.

[0038] The substrate 502 includes a MIB 522 that may electrically connect the glass core layer active component dies 508 together, electrically connect the molding layer active component dies 544 together, and electrically connect the glass core layer active component dies 508 and the molding layer active component dies 544 together.

[0039] Figure 7 is a top view of the glass core layer 504, a plurality of glass core layer active component dies 508, and the MIB 522 above the glass core layer 504. The glass core layer 504 includes four cavities and glass core layer active component dies 508 in each of these cavities. The MIB 522 may provide interconnects for the four glass core layer active component dies 508.

[0040] Figure 8It is a top view of the glass core layer 504, four glass core layer active component dies 508, the MIB 522, and two molded layer active component dies 544 above the MIB 522. The MIB 522 can provide interconnects for the glass core layer active component dies 508 and the molded layer active component dies 544.

[0041] Return Figure 5 , the substrate 502 can include a third build-up 546 that contacts the top surface of the molded layer 542. The third build-up 546 can be a second RDL and can include conductive interconnects that include vias 548. The top surface of the third build-up 546 can be the top surface of the substrate 502 and includes pads 550. The top surface active component die 534 can be attached to the pads 550. The substrate 502 can include one or more copper pillars 552 that extend from the first build-up 510 through the molded layer 542 and the third build-up 546 to the top surface of the substrate 502. The top surface active component die 534 can be electrically connected to the one or more copper pillars 552, and the first build-up 510 can electrically connect the copper pillars 552 to the glass core layer active component dies 508.

[0042] Figure 9 It is a top view of the glass core layer 504, the MIB 522, two molded layer active component dies 544 above the MIB 522, and six top surface active component dies 534 on the top surface of the substrate. The glass core layer active component dies 508 can be HBM dies, the six top surface active component dies 534 can be computing component dies, and the molded layer dies can be I / O component dies for supporting the I / O of one or both of the computing component dies and the HBM dies.

[0043] In traditional methods, all dies are attached to the top surface of the substrate. This can pose challenges for thermal management when different types of dies have different heights. The three-dimensional arrangement of the dies and interconnects eliminates height mismatches. The molded layer 542 has a consistent height. This eliminates any height mismatches in the higher layers above the molded layer 542. Additionally, since both top and bottom connections to the MIB 522 can be provided, the three-dimensional arrangement can result in a need for fewer MIBs. As Figure 7 and Figure 8 shown in the example, four HBM components and two I / O component dies can be attached in a three-dimensional arrangement using one MIB.

[0044] Figures 10A - 10H Illustrates a flowchart of an example of a method of manufacturing a substrate (such as Figure 5 the substrate 502) for an electronic system. Figure 10Ais a side view of a glass core layer 504 of a substrate 502 of an electronic system. One or more cavities 506 are formed in the glass core layer 504, such as by laser drilling and wet etching processes.

[0045] In Figure 10B , a laminated pattern of dielectric material and conductive interconnects is formed on the top and bottom surfaces of the glass core layer 504 of the top laminate 510 and the bottom laminate 512. The height of the laminated pattern depends on the size of the components to be placed in the cavities. In Figure 10B 's example, the cavity 506 extends into the bottom laminate 512 and extends to the top of the top laminate 510. In some examples, the cavity 506 is only within the glass core layer.

[0046] In Figure 10C , an adhesive 524 is added to the bottom of the cavity 506, and a glass core layer active component die 508 is disposed in each of the cavities 506 of the glass core layer 504. In Figure 10D , the laminated pattern of dielectric material and conductive interconnects 554 continues on the top laminate 510.

[0047] In Figure 10E , an MIB 522 is disposed in the first laminate 510. The MIB 522 is electrically connected to the glass core layer active component die 508. In Figure 10F , vias 548 are formed in the top laminate 510, and copper pillars 552 are formed on the top laminate 510. A molded layer active component die 544 is disposed on the top laminate 510. The glass core layer active component die 508 is connected to the molded layer active component die 544 using the MIB 522.

[0048] In Figure 10G , a molded layer 542 is formed by setting a molding material on the top laminate 510 to encapsulate the molded layer active component die 544 and the copper pillars 552. In Figure 10H , a third laminate 546 is formed on the top surface of the molded layer 542. The third laminate 546 includes conductive interconnects that include die pads 550 on the top surface. A top surface active component die 534 is attached to the pads 550 on the top surface of the third laminate 546.

[0049] Figure 11Another illustration is a cross-sectional side view of an example of an electronic system 1100 that includes a substrate 1102 and an active component die 534 (e.g., a computing component die) on the top surface of the substrate 1102. The substrate 1102 includes a glass core layer 1104. The glass core layer 1104 includes a plurality of cavities. The cavities can be two different sizes. The active component die 508 can be disposed in the larger cavities of the glass core layer 1104, and the discrete passive components 1160 can be disposed in the smaller cavities of the glass core layer 1104. The glass core layer active component die 508 can be an HBM component, which can be composed of a plurality of individual memory dies. The discrete passive components 1160 include only passive electronic components, such as discrete inductors, discrete capacitors, discrete resistors, or combinations thereof, and do not include active components.

[0050] Figure 12 is a top view of the glass core layer 104, a plurality of glass core layer active component dies 508, and a plurality of discrete passive components 1160. The example shown includes four glass core layer active component dies 508 disposed in four larger cavities of the glass core layer 1104 and four discrete passive components 1160 disposed in four smaller cavities. An actual implementation can include many cavities in larger and smaller cavities.

[0051] Return Figure 11 , the substrate 1102 includes a molding layer 542 and a top build-up layer 1110 between the top surface of the glass core layer 1104 and the bottom surface of the molding layer 542. The top build-up layer 1110 can be a redistribution layer (RDL) including conductive interconnects in a dielectric material. The conductive interconnects of the top build-up layer connect the glass core layer active component die 508, the discrete passive components 1160, and the molding layer active component die 544.

[0052] The substrate 1102 also includes a bottom build-up layer 1112 that contacts the bottom surface of the glass core layer 1104. In Figure 11 example, the larger cavities in the glass core layer 1104 extend into the bottom build-up layer 1112. The stack of memory dies extends higher and lower than the glass core layer 1104, into the bottom build-up layer 1112 and the top build-up layer 1110. An adhesive 1124 can be included in the bottom of the cavities in the bottom build-up layer 1112. The smaller cavities in the glass core layer 1104 stop at the top surface of the bottom build-up layer 1112. The adhesive 1124 can be placed on the top surface of the bottom build-up layer 1112 to hold the discrete passive components 1160. The tops of the discrete passive components 1160 can extend into the top build-up layer 1110. The bottom build-up layer 1112 can include vias 1162 from the discrete passive components 1160 to the back side of the substrate 1102. The vias 1162 allow power connections to the back side of the substrate 1102.

[0053] The molding layer 542 includes molding layer active component dies 544 (e.g., I / O component dies) disposed within the molding layer 542. The substrate 1102 includes a MIB 1122 embedded in the top stack 510. The MIB 1122 can electrically connect the discrete passive components 1160 together, electrically connect the molding layer active component dies 544 together, and electrically connect the discrete passive components 1160 and the molding layer active component dies 544 together.

[0054] Figure 13 is a top view of the glass core layer 1104, four glass core layer active component dies 508 in the cavities of the glass core layer 1104, and four discrete passive components 1160. Figure 13 Also shown is the MIB 1122 above the glass core layer 1104. The MIB 522 can be electrically connected to the four discrete passive components 1160. Figure 14 is a top view of the glass core layer 1104, four glass core layer active component dies 508, the MIB 522, and two molding layer active component dies 544 above the MIB 122. The MIB 522 can provide interconnects for the four discrete passive components 1160 and the molding layer active component dies 544.

[0055] Return Figure 11 , the substrate 1102 can include a third stack 546 that contacts the top surface of the molding layer 542. The third stack 546 can be a second RDL and can include conductive interconnects that include vias 548. The top surface active component die 534 can be attached to a pad 550 of the third stack 546. The substrate 502 can include one or more copper pillars 552 that extend from the top stack 510 through the molding layer 542 and the third stack 546 to the top surface of the substrate 502. The top surface active component die 534 can be electrically connected to the one or more copper pillars 552, and the first stack 510 can electrically connect the copper pillars 552 to the glass core layer active component dies 508.

[0056] Figure 15is a top view of a glass core layer 1104, MIB 122, four glass core layer active component dies 508, two molded layer active component dies 544 above the MIB 1122, and six top surface active component dies 534 on the top surface of the substrate 1102. The glass core layer active component dies 508 may be HBM dies, the discrete passive components may be discrete inductors, and the six top surface active component dies 534 may be computing component dies, and the molded layer dies may be I / O component dies for supporting the I / O of one or both of the computing component die and the HBM die. In a conventional method, all memory dies, computing dies, I / O dies, and discrete inductors are mounted on the top surface of the substrate. Since different types of components may have different heights, so Figures 11 - 15 the three-dimensional arrangement of components and interconnects in the example of

[0057] Figures 16A - 16H eliminates height mismatches. Additionally, the MIB 1122 may provide both top and bottom connections for components for three-dimensional connections. Figure 11 illustrates a flowchart of an example of a method of manufacturing a substrate (such as Figure 16A the substrate 1102) for an electronic system. Figure 16A is a side view of the glass core layer 1104 of the substrate 502 of the electronic system. A plurality of cavities 1106, 1107 are formed in the glass core layer 1104. The cavities can be formed in the glass core layer 1104 using laser and wet etching processes. To simplify the drawings, Figure 16A the example of

[0058] shows four cavities. The diameter of the two outer cavities 1106 is greater than the diameter of the two inner cavities 1107.

[0058] In Figure 16B , a stacked patterned dielectric material and conductive interconnects are formed on the top surface and the bottom surface of the glass core layer 1104 of the top stack 1110 and the bottom stack 1112. The height of the stacked patterning depends on the size of the components to be placed in the cavities. In Figure 11 the example of

[0059] B, the large cavities 1106 extend into the bottom stack 512 and to the top of the top stack 1110. In some examples, the larger cavities 1106 are only within the glass core layer 1104. The smaller cavities 1107 extend from the top surface of the bottom stack 1112 to the top surface of the top stack 1110. In some examples, the smaller cavities 1107 are only within the glass core layer 1104.

[0059] In Figure 16C , an adhesive 1124 is added to the bottom of the cavities. The glass core layer active component dies 508 are disposed in each of the larger cavities, and the discrete passive components 1160 are disposed in each of the smaller cavities in the glass core layer 1104. In Figure 16D, build-up patterning of dielectric material and conductive interconnect 1154 continues on top build-up layer 1110 and bottom build-up layer 1112. The conductive interconnect of bottom build-up layer 1112 includes via 1162.

[0060] exist Figure 16E , the patterning of the conductive interconnect 1154 continues. The MIB 1122 is disposed in the first build-up layer 1110. The MIB 1122 is electrically connected to the discrete passive components 1160. Figure 16F , a via 548 is formed in the top build-up layer 510, and a copper pillar 552 is formed on the top build-up layer 510. A molded layer active component die 544 is disposed on the top build-up layer 510. Discrete passive components 1160 are connected to the molded layer active component die 544 using MIB 1122.

[0061] exist Figure 16G In the embodiment, the molding layer 542 is formed by providing a molding material on the top build-up layer 510 to encapsulate the molding layer active component die 544 and the copper pillars 552. Figure 16H 11. In the embodiment of the present invention, the third build-up layer 546 is formed on the top surface of the molding layer 542. The top surface active component die 534 is attached to the die pad 550 on the top surface of the substrate 1102.

[0062] Figure 11 and Figures 16A - 16H An example device of provides a central I / O architecture with embedded discrete components in a glass core. The embedded discrete inductors provide a high permeability inductor for the circuits that provide power to the electronic system. Capacitors can also be embedded in the glass core layer of the power circuit. This technology can provide double-sided embedded connections for discrete inductors and / or capacitors.

[0063] Figure 17 A system level diagram according to an embodiment of the present disclosure is illustrated. For example, Figure 17 An example of a system that may include electronic devices packaged with a substrate having a glass core layer is depicted. The glass core layer may include active components embedded in the glass core layer and discrete passive components embedded in the glass core layer. In one embodiment, system 1700 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet computer, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smart phone, an Internet appliance, or any other type of computing device. In some embodiments, system 1700 is a system on a chip (SOC) system. In one example, components attached to the back side of the package substrate as described in the present disclosure may be used to provide a system for a device such as a processor. Figure 17 Two or more systems shown in provide circuit power.

[0064] In one embodiment, the processor 1710 has one or more processing cores 1712 and 1712N, where N is a positive integer and 1712N represents the Nth processor core inside the processor 1710. In one embodiment, the system 1700 includes multiple processors, and the multiple processors include 1710 and 1705, where the processor 1705 has logic similar to or the same as that of the processor 1710. In some embodiments, the processing core 1712 includes, but is not limited to, prefetch logic for fetching instructions, decoding logic for decoding instructions, execution logic for executing instructions, and the like. In some embodiments, the processor 1710 has a cache memory 1716 for caching instructions and / or data for the system 1700. The cache memory 1716 can be organized into a hierarchical structure including one or more levels of cache memory.

[0065] In some embodiments, the processor 1710 includes a memory controller 1714, and the memory controller 1714 is operable to perform functions that enable the processor 1710 to access and communicate with a memory 1730 including a volatile memory 1732 and / or a non-volatile memory 1734. In some embodiments, the processor 1710 is coupled to the memory 1730 and the chipset 1720. The processor 1710 can also be coupled to a wireless antenna 1778 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, the wireless antenna interface 1778 operates according to, but is not limited to, the IEEE 802.11 standard and its related series, HomePlug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0066] In some embodiments, the volatile memory 1732 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 1734 includes, but is not limited to, flash memory, phase change memory (PCM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), or any other type of non-volatile memory device.

[0067] Memory 1730 stores information and instructions to be executed by processor 1710. In one embodiment, when processor 1710 is executing instructions, memory 1730 may also store temporary variables or other intermediate information. In the illustrated embodiment, chipset 1720 is connected to processor 1710 via point-to-point (PtP or P-P) interfaces 1717 and 1722. Chipset 1720 enables processor 1710 to connect to other components in system 1700. In some embodiments, interfaces 1717 and 1722 operate according to PtP communication protocols such as Quick Path Interconnect (QPI). In other embodiments, different interconnections may be used.

[0068] In some embodiments, chipset 1720 is operable to communicate with processor 1710, 1705N, display device 1740, and other devices 1772, 1776, 1774, 1760, 1762, 1764, 1766, 1777, etc. Buses 1750 and 1755 may be interconnected together via bus bridge 1772. Chipset 1720 is connected to one or more buses 1750 and 1755 that interconnect various components 1774, 1760, 1762, 1764, and 1766. Chipset 1720 may also be coupled to wireless antenna 1778 to communicate with any device configured to transmit and / or receive wireless signals. Chipset 1720 is connected to display device 1740 via interface (I / F) 1726. Display 1740 may be, for example, a touch screen, liquid crystal display (LCD), plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In some embodiments, processor 1710 and chipset 1720 are integrated into a single SOC. In one embodiment, chipset 1720 is coupled (e.g., via interface 1724) to non-volatile memory 1760, mass storage medium 1762, keyboard / mouse 1764, and network interface 1766 via I / F 1724 and / or I / F 1726, I / O device 1774, smart TV 1776, consumer electronics 1777 (e.g., PDA, smart phone, tablet computer, etc.).

[0069] In one embodiment, the mass storage medium 1762 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash drive, or any other form of computer data storage medium. In one embodiment, the network interface 1766 is implemented through any type of known network interface standard, including but not limited to an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), ultra-wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0070] Although Figure 17 the modules shown in are depicted as separate blocks within the system 1700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit, or may be implemented using two or more separate integrated circuits. For example, although the cache memory 1716 is depicted as a separate block within the processor 1710, the cache memory 1716 (or selected aspects of 1716) may be incorporated into the processor core 1712.

[0071] The described devices, systems, and methods can provide improved power routing and reduced multi-chip package size by providing high-permeability components for power-generating circuits associated with a substrate.

[0072] To better illustrate the methods and devices disclosed herein, a non-limiting list of example embodiments is provided here:

[0073] Example 1 includes a subject matter (such as an electronic system) that includes a glass core layer, the glass core layer including a plurality of cavities formed therethrough; at least one glass core layer active component die disposed within at least one of the cavities of the plurality of cavities; at least one discrete passive component disposed within other cavities of the plurality of cavities; a molding layer, the molding layer including at least one molding layer active component die disposed within the molding layer; and a first laminate that contacts a top surface of the glass core layer and a bottom surface of the molding layer. The first laminate includes conductive interconnects that connect at least one glass core layer active component die, at least one discrete passive component, and at least one molding layer active component die. The system further includes at least one top surface active component die attached to a top surface of a substrate and electrically connected to at least one molding layer active component die.

[0074] In Example 2, the subject matter of Example 1 optionally includes at least one glass core layer active component die including a high bandwidth memory (HBM) component, at least one discrete passive component including a discrete inductor, at least one molded layer active component die including an input / output (I / O) component die, and at least one top surface active component die including a computing component die.

[0075] In Example 3, the subject matter of one or both of Example 1 and 2 optionally includes a second laminate contacting the bottom surface of the glass core layer, wherein at least one glass core layer active component die extends out of the glass core layer into the second laminate, and at least one discrete passive component contacts the top surface of the second laminate.

[0076] In Example 4, the subject matter of Example 3 optionally includes a second laminate including at least one via hole connected to at least one discrete passive component and extending to the bottom surface of the substrate.

[0077] In Example 5, the subject matter of one or both of Example 1 and 2 optionally includes a second laminate contacting the bottom surface of the glass core layer; and a third laminate contacting the top surface of the molded layer, wherein the third laminate includes conductive interconnects, and at least one top surface active component die is attached to the conductive interconnects of the third laminate.

[0078] In Example 6, the subject matter of Example 5 optionally includes one or more copper pillars extending from the first laminate through the molded layer and the third laminate to the top surface of the substrate, wherein at least one top surface active component die is electrically connected to the one or more copper pillars.

[0079] In Example 7, the subject matter of one or any combination of Example 1-6 optionally includes at least one multi-die interconnect bridge disposed in the first laminate and connecting at least one discrete passive component and at least one molded layer active component die.

[0080] In Example 8, the subject matter of one or any combination of Example 1-7 optionally includes at least one discrete passive component including a discrete capacitor and at least one molded layer active component die including an input / output (I / O) component die.

[0081] In Example 9, the subject matter of one or any combination of Example 1-8 optionally includes a multi-die interconnect bridge including an electrically connected bottom surface to at least one discrete passive component and an electrically connected top surface to at least one molded layer active component die.

[0082] In Example 10, the subject matter of one or any combination of Examples 1-9 optionally includes a glass core layer that includes a plurality of glass core layer active component dies and a plurality of discrete passive components disposed in a plurality of cavities. The molding layer includes a plurality of molding layer active component dies, and the height of the molding layer is a uniform height. The subject matter optionally includes a plurality of top surface active component dies electrically connected to the glass core layer active component dies and the molding layer active component dies.

[0083] In Example 11, the subject matter of Example 10 optionally includes a plurality of top surface active component dies electrically connected to the glass core layer active component dies and the molding layer active component dies.

[0084] Example 12 includes the subject matter (a method of manufacturing a substrate for an electronic system), or can optionally be combined with one or any combination of Examples 1-11 to include such subject matter, which includes forming a plurality of cavities in a glass core layer of a substrate; forming a first stack of dielectric material on a first surface of the glass core layer; disposing at least one glass core layer active component die in at least one of the plurality of cavities and disposing at least one discrete passive component in at least one other of the cavities in the plurality of cavities; forming a layer of conductive interconnects including die pads in the first stack; disposing at least one molding layer active component die on at least a portion of the die pads of the first stack attached to the first stack; and disposing a molding material on the first stack to encapsulate at least one molding layer active component die.

[0085] In Example 13, the subject matter of Example 12 optionally includes forming a second stack of dielectric material on a second surface of the glass core layer; extending one or more of the plurality of cavities in the glass core layer into at least one cavity portion of the second stack; disposing at least one active component die in at least one cavity portion of the second stack; and disposing at least one discrete passive component on a surface of the second stack.

[0086] In Example 14, the subject matter of one or both of Examples 12 and 13 optionally includes forming a third stack on a surface of the molding layer. The third stack includes die pads on a surface of the third stack that is the top surface of the substrate.

[0087] In Example 15, the subject matter of Example 14 optionally includes forming one or more copper pillars that extend from the first stack through the molding layer to the top surface of the third stack; and forming die pads of the third stack on one or more of the copper pillars.

[0088] In Example 16, the subject matter of one or any combination of Examples 12 - 15 optionally includes setting at least one multi-die interconnect bridge in a first laminate; and using the multi-die interconnect bridge to electrically connect at least one discrete passive component to at least one molded layer active component die.

[0089] In Example 17, the subject matter of one or any combination of Examples 12 - 16 optionally includes setting a high bandwidth memory (HBM) component in at least one cavity, and setting at least one discrete inductor in at least one other cavity, and setting at least one input / output (I / O) component die on a first laminate.

[0090] Example 18 includes the subject matter (such as a substrate for an electronic system) or can optionally be combined with one or any combination of Examples 1 - 17 to include such subject matter, the subject matter including a glass core layer, the glass core layer including a plurality of cavities in the glass core layer; a plurality of high bandwidth memory (HBM) components, with a high bandwidth memory component set in each cavity of a first portion of the plurality of cavities; a plurality of discrete inductors, with a discrete inductor set in each cavity of a second portion of the plurality of cavities; a plurality of input / output (I / O) component dies, the plurality of input / output component dies being arranged in a molded layer, the molded layer having a first surface facing the surface of the glass core layer; a multi-die interconnect bridge, the multi-die interconnect bridge connecting the plurality of discrete inductors to the plurality of I / O component dies; and a first redistribution layer, the first redistribution layer being arranged on a second surface of the molded layer and including conductive interconnects, the conductive interconnects including a plurality of die pads on a top surface of the first redistribution layer.

[0091] In Example 19, the subject matter of Example 18 optionally includes a plurality of copper pillars extending through the molded layer and the first redistribution layer. At least one copper pillar contacts a die pad on the top surface of the first redistribution layer.

[0092] In Example 20, the subject matter of Example 19 optionally includes a second redistribution layer arranged between the glass core layer and the molded layer and including conductive interconnects. The conductive interconnects of the second redistribution layer provide electrical continuity between the plurality of HBM components and the copper pillars, and the copper pillars provide electrical continuity from the conductive interconnects of the second redistribution layer to one or more of the plurality of die pads on the top surface of the first redistribution layer.

[0093] These non-limiting example embodiments may be combined in any arrangement or combination. Throughout this specification, multiple instances may implement components, operations, or structures described as a single instance. Although the various operations of one or more methods are illustrated and described as separate operations, one or more of the various operations may be performed concurrently, and the operations are not required to be performed in the order illustrated. Structures and functions presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functions presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.

[0094] Although the subject matter of the present invention has been described with reference to specific example embodiments, various modifications and changes can be made to these embodiments without departing from the broader scope of the disclosed embodiments.

[0095] The embodiments illustrated herein have been described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom such that structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. Accordingly, the detailed description is not to be taken in a limiting sense, and the scope of the various embodiments is defined only by the appended claims and the full scope of equivalents such claims are entitled to.

[0096] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. Additionally, multiple instances may be provided for resources, operations, or structures described herein as a single instance. Further, the boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of a particular illustrative configuration. Other allocations of functionality are envisioned and may fall within the scope of the various embodiments of the present disclosure. In general, structures and functions presented as separate resources in example configurations may be implemented as a combined structure or resource. Similarly, structures and functions presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within the scope of the embodiments of the present disclosure as represented by the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a limiting sense.

[0097] It will also be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the scope of the example embodiments of the present invention. Both the first contact and the second contact are contacts, but they are not the same contact.

[0098] The terms used in the description of the exemplary embodiments herein are for the purpose of describing particular exemplary embodiments only and are not intended to be limiting. As used in the description of the exemplary embodiments and the appended examples, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will also be understood that the term "comprises" when used in this specification, specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

Claims

1. An electronic system, comprising: A substrate, the substrate comprising: A glass core layer, the glass core layer comprising a plurality of cavities passing through the glass core layer; At least one glass core layer active component die within a cavity of the plurality of cavities; At least one discrete passive component within other cavities of the plurality of cavities; A molding layer, the molding layer comprising at least one molding layer active component die within the molding layer; and A first build-up layer, the first build-up layer contacting a top surface of the glass core layer and a bottom surface of the molding layer and comprising conductive interconnects connecting the at least one glass core layer active component die, the at least one discrete passive component, and the at least one molding layer active component die; and At least one top surface active component die, the at least one top surface active component die attached to a top surface of the substrate and electrically connected to the at least one molding layer active component die.

2. The electronic system according to claim 1, wherein The at least one glass core layer active component die is a high bandwidth memory (HBM) component, the at least one discrete passive component is a discrete inductor, the at least one molding layer active component die is an input / output (I / O) component die, and the at least one top surface active component die is a computing component die.

3. The electronic system according to claim 1 or 2, comprising a second build-up layer contacting a bottom surface of the glass core layer, wherein the at least one glass core layer active component die extends out of the glass core layer into the second build-up layer, and the at least one discrete passive component contacts a top surface of the second build-up layer.

4. The electronic system according to claim 3, wherein, The second build-up layer comprises at least one via connected to the at least one discrete passive component and extending to a bottom surface of the substrate.

5. The electronic system according to claim 1 or 2, comprising: A second build-up layer, the second build-up layer contacting a bottom surface of the glass core layer; And A third build-up layer, the third build-up layer contacting a top surface of the molding layer, wherein the third build-up layer comprises conductive interconnects, and the at least one top surface active component die is attached to the conductive interconnects of the third build-up layer.

6. The electronic system according to claim 5, comprising one or more copper pillars extending from the first build-up layer through the molding layer and the third build-up layer to a top surface of the substrate, wherein the at least one top surface active component die is electrically connected to the one or more copper pillars.

7. The electronic system according to any one of claims 1 to 6, comprising at least one multi-die interconnect bridge within the first build-up layer and connecting the at least one discrete passive component and the at least one molding layer active component die.

8. The electronic system according to any one of claims 1 to 7, wherein The at least one discrete passive component is a discrete capacitor, and the at least one molding layer active component die is an input / output (I / O) component die.

9. The electronic system according to claim 7 or 8, wherein, The at least one multi-die interconnect bridge comprises a bottom surface electrically connected to the at least one discrete passive component and a top surface electrically connected to the at least one molding layer active component die.

10. The electronic system according to any one of claims 1 to 9, Wherein the glass core layer includes a plurality of glass core layer active component dies and a plurality of discrete passive components in the plurality of cavities; Wherein a bottom surface of the substrate includes pads electrically connected to at least one discrete passive component among the plurality of discrete active components; Wherein the molding layer includes a plurality of molding layer active component dies, and a height of the molding layer is a uniform height; and Wherein at least one top surface active component die includes a plurality of top surface active component dies electrically connected to the glass core layer active component dies and the molding layer active component dies.

11. The electronic system according to claim 10, comprising at least one multi-die interconnect bridge electrically connected to at least two discrete passive components among the plurality of discrete passive components and at least two molding layer component dies among the plurality of molding layer active component dies.

12. A method of manufacturing a substrate for an electronic system, the method comprising: Forming a plurality of cavities in a glass core layer of the substrate; Forming a first stack of dielectric material on a first surface of the glass core layer; Disposing at least one glass core layer active component die in at least one of the plurality of cavities, and disposing at least one discrete passive component in at least one other cavity among the cavities in the plurality of cavities; Forming a layer of conductive interconnects including die pads in the first stack; Disposing at least one molding layer active component die attached to at least a portion of the die pads of the first stack on the first stack; And Disposing a molding material on the first stack to encapsulate the at least one molding layer active component die.

13. The method according to claim 12, comprising: Forming a second stack of dielectric material on a second surface of the glass core layer; Extending one or more of the plurality of cavities of the glass core layer into at least one cavity portion of the second stack; And Wherein the disposing the at least one glass core layer active component die and the at least one discrete passive component comprises: Disposing the at least one active component die in the at least one cavity portion of the second stack, and Disposing the at least one discrete passive component on a surface of the second stack.

14. The method according to claim 13, comprising: Forming a third stack on a surface of the molding layer; Wherein the third stack includes die pads on a surface of the third stack that is a top surface of the substrate.

15. The method according to claim 14, comprising: Forming one or more copper pillars extending from the first stack through the molding layer to a top surface of the third stack; And Forming the die pads of the third stack on one or more of the copper pillars.

16. The method according to any one of claims 12 to 15, wherein, The forming the layer of conductive interconnects includes: Disposing at least one multi-die interconnect bridge in the first stack; and Electrically connecting the at least one discrete passive component to the at least one molding layer active component die using the multi-die interconnect bridge.

17. The method according to any one of claims 12 to 16, wherein Said arranging the at least one glass core layer active component die and at least one discrete passive component includes: arranging a high bandwidth memory (HBM) component in the at least one cavity and arranging at least one discrete inductor in the at least one other cavity; and wherein said arranging at least one molded layer active component die includes arranging at least one input / output (I / O) component die on the first laminate.

18. A substrate for an electronic system, the substrate comprising: a glass core layer including a plurality of cavities in the glass core layer; a plurality of high bandwidth memory (HBM) components, with a high bandwidth memory component in each cavity of a first portion of the plurality of cavities; a plurality of discrete inductors, with a discrete inductor in each cavity of a second portion of the plurality of cavities; a plurality of input / output (I / O) component dies arranged in a molding layer having a first surface facing the surface of the glass core layer; a multi-die interconnect bridge connecting the plurality of discrete inductors to the plurality of I / O component dies; and a first redistribution layer arranged on a second surface of the molding layer and including conductive interconnects, the conductive interconnects including a plurality of die pads on a top surface of the first redistribution layer.

19. The substrate according to claim 18, including a plurality of copper pillars extending through the molding layer and the first redistribution layer, wherein at least one of the copper pillars contacts a die pad on the top surface of the first redistribution layer.

20. The substrate according to claim 19, including: a second redistribution layer arranged between the glass core layer and the molding layer and including conductive interconnects; and wherein the conductive interconnects of the second redistribution layer provide electrical continuity between the plurality of HBM components and the copper pillars, and the copper pillars provide electrical continuity from the conductive interconnects of the second redistribution layer to one or more of the plurality of die pads on the top surface of the first redistribution layer.

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