Linearizer circuit and method for audio switch

Abstract

The wireless device may include a plug shared by high speed data, analog audio signals, and power. A switch may be included on a wire between the plug and the circuitry providing the high speed data, analog audio signal, and power to isolate these circuitry from overvoltage conditions. A linearizer circuit may be included to provide a gate drive signal to the switch, for example, during transmission of an analog audio signal. The linearizer circuit may include a digital-to-analog converter to apply a gain factor to the analog audio signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of U.S. Patent Application No. 18 / 060279, filed on November 30, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Technical field

[0003] This application relates to linearizers, and more particularly to the linearized operation of switches on audio signal lines. Background art

[0004] Wireless communication devices are typically one of the various small - form - factor devices, such as tablet devices. Due to the small configuration of such devices, it is particularly meaningful to use the device space economically. In this regard, it may be desirable to convert the audio path on a wireless communication device (e.g., to a headset or speaker) from a 3.5 - millimeter (mm) jack to a Universal Serial Bus (USB) Type - C (USB - C) port connector, as the USB - C port connector is more versatile (e.g., sending audio, exchanging USB data, exchanging battery charger data, etc.).

[0005] Due to the additional functionality of providing audio via USB - C, the differential transmit data lines DP / DN associated with the host USB - C circuit are loaded with many components, such as switching devices that couple the differential transmit lines DP / DN to the audio circuit and other circuits. Some current designs aim to protect the circuit from over - voltage conditions by implementing large transistors to isolate the circuit from the USB - C plug.

[0006] When the transistor is turned on and supports the transmission of audio signals, there is a need in the art to improve the linearization of such transistors, such as the large transistors used for isolating the circuit. Summary of the invention

[0007] In a specific implementation, a wireless communication device includes: an application processor; a first audio signal amplifier; a multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires; a data and audio plug coupled to the set of wires; a first metal-oxide-semiconductor field-effect transistor (MOSFET) switch disposed on a first wire in the set of wires between the first audio signal amplifier and the data and audio plug; and a first gate drive circuit having an output coupled to the gate of the first MOSFET switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the output of the first audio signal amplifier through a first digital-to-analog converter (DAC).

[0008] In another specific implementation, a method for operating a wireless communication device having a first metal-oxide-semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an audio load. The method includes: isolating the first audio signal amplifier from the audio load, including applying a first gate control signal to the first MOSFET switch at a first voltage level that turns off the first MOSFET switch; and linearizing the first MOSFET switch, including applying the first gate control signal to the first MOSFET switch at a second voltage level during the on state of the first MOSFET switch, wherein linearizing the first MOSFET switch includes applying the output of the first audio signal amplifier as a reference voltage to a first digital-to-analog converter (DAC), wherein the first DAC applies a first gain level to the output of the first audio signal amplifier, and wherein a first amplifier receives the output of the first audio signal amplifier at the first gain level and wherein the first amplifier outputs the first gate control signal to the first MOSFET switch.

[0009] In another specific implementation, a wireless communication device includes: components for running an operating system; components for amplifying an analog audio signal; components for coupling the components for running the operating system and the components for amplifying the analog audio signal to a set of wires; a data and audio plug coupled to the set of wires; a first transistor coupled between the data and audio plug and the components for amplifying the analog audio signal; and components for the linearized operation of the first transistor, the components for the linearized operation of the first transistor including a first digital-to-analog converter (DAC) configured to receive a first audio signal from the components for amplifying the analog audio signal and output the first audio signal having a first gain level to a first amplifier, wherein the first amplifier is coupled to the gate of the first transistor.

[0010] In yet another specific implementation, a wireless communication device includes: an application processor; a pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel; a decoder / encoder (codec) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires; a plug coupled to the set of wires; a first switch coupled between the application processor and the plug on a first wire in the set of wires; and a first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the first audio channel through a first digital-to-analog converter (DAC).

[0011] These advantages and additional advantages can be better understood through the following specific embodiments. Brief Description of the Drawings

[0012] Figure 1 A block diagram illustrating an example wireless device including a linearization circuit according to one specific implementation.

[0013] Figure 2 Illustrates an example architecture for multiplexing audio signals, high-speed data signals, and charging in a device (such as the device in Figure 1 ) according to one specific implementation.

[0014] Figure 3 Illustrates an example gate drive circuit or left audio channel and ground path, which can also be applied to the right audio channel and is associated with the specific implementation of Figure 2 .

[0015] Figure 4Illustrates an example gate drive circuit according to one specific implementation.

[0016] Figure 5 Illustrates an example drive circuit according to one specific implementation.

[0017] Figure 6 Illustrates an example gate drive circuit according to one specific implementation.

[0018] Figure 7 Illustrates an example resistor network that is used to model the gain factor in the Figures 2 to 6 gate drive circuit.

[0019] Figure 8 Illustrates an example digital-to-analog converter (DAC) that can be used with the Figures 2 to 6 example gate drive circuit.

[0020] Figure 9 Illustrates a flowchart of an example method that can be performed by the Figure 2 example architecture.

[0021] The specific implementations and advantages of the present disclosure can be best understood by reference to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Description

[0022] In one example, a wireless device includes a Universal Serial Bus (USB) Type-C (USB-C) jack for charging, for high-speed data, and for analog audio signals. For example, the device can omit the 3.5 mm audio jack and use the USB-C jack to physically attach headphones or earbuds. The advantage of such devices is that they can use a single chip for USB-C and audio, thus saving area within the device housing.

[0023] However, an external wired plug such as used in USB-C can include a risk of overvoltage. For example, a USB-C cable can accumulate static charge that can be discharged when the cable is physically mated to the plug. Various specific implementations include large transistors that isolate internal components from potential overvoltage conditions when turned off. For example, in a device that multiplexes audio, charging, and high-speed data onto a single USB-C plug, these transistors can electrically isolate the application processor, audio signal amplifier, charging circuit, etc. from the plug when such large transistors are turned off.

[0024] However, those large transistors can pose their own challenges during operation. For example, the audio signal carried on the wire coupled to the plug can have an expected amplitude range during normal operation. Assuming the transistor is disposed along the wire from the source to the drain, the gate-source voltage of the transistor can change as the amplitude of the audio signal changes. As a result, the impedance of the transistor can vary, adding non-linearity and distortion to the audio signal.

[0025] Various embodiments include a linearization circuit to maintain the gate-source voltage within an acceptable range during normal operation, thereby reducing total harmonic distortion (THD).

[0026] In one example, a wireless communication device includes an application processor, a pair of audio signal amplifiers, and a charging integrated circuit (IC) coupled to a set of wires through a multiplexing circuit. A data and audio plug is coupled to the set of wires and the multiplexing circuit.

[0027] A switch such as a metal-oxide-semiconductor field-effect transistor (MOSFET) switch can be disposed on a first wire in the set of wires between the first audio signal amplifier and the data and audio plug. When the MOSFET switch is off, this can provide protection against overvoltage conditions at the plug. When the MOSFET switch is on, this can conduct the amplified audio signal from the audio signal amplifier through the plug to an external load (such as a wired headset set).

[0028] Linearization can be achieved by using a gate drive circuit. The gate drive circuit can have an output coupled to the gate of the MOSFET switch. The gate drive circuit can also include a buffer (e.g., implemented as an operational amplifier) having a first buffer input coupled to the output of the first audio signal amplifier. A digital-to-analog converter (DAC) can be disposed between the output of the audio signal amplifier and the first buffer input to provide a gain-adjusted audio signal to the buffer input.

[0029] A direct current (DC) voltage shift circuit can also be present at the buffer input. Another buffer input can be provided with a feedback path to the other buffer input on the output of the gate drive circuit, and the other buffer input can include a DC voltage offset. The resulting output from the gate drive circuit includes a DC component and a gain-adjusted alternating current (AC) component, where the gain-adjusted AC component corresponds to the gain-adjusted audio signal. During the on-state of the transistor, the gate of the transistor is driven by the DC component and the AC component, where the AC component approximates the audio signal to keep the gate-source voltage of the transistor stable within the operating range of the audio signal.

[0030] Advantages of certain embodiments are high performance. Specifically, maintaining the gate-source voltage of a transistor more constant during normal operation can result in a more constant impedance of the transistor. A more constant impedance can result in a lower value of THD and higher user satisfaction.

[0031] Of course, the above examples are given for a single audio channel. Some embodiments may include multiple (e.g., two) audio channels, and both of the two audio channels may have a transistor and a linearization circuit for driving the transistor. Additionally, the ground path between the plug and ground may have a transistor and a linearization circuit for driving the transistor. Such embodiments are described in more detail below.

[0032] Figure 1 Example device 100 is illustrated in which aspects of the present disclosure may be implemented. Device 100 may be a battery-powered device such as a cellular phone, a handheld device, a wireless device, a laptop computer, a tablet computer, a smart phone, a wearable device, and the like.

[0033] Device 100 may include a processor 104 that controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). A memory 106 that may include both a read only memory (ROM) and a random access memory (RAM) provides instructions and data to processor 104. A portion of memory 106 may also include a non-volatile random access memory (NVRAM). Processor 104 generally performs logical and arithmetic operations based on program instructions stored within memory 106.

[0034] In some aspects, device 100 may further include a housing 108 that may include a transmitter 110 and a receiver 112 to allow for sending and receiving data between device 100 and a remote location. For some aspects, transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0035] Device 100 may further include a signal detector 118 that may be used to detect and quantify the signal level received by transceiver 114. Signal detector 118 may detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density, as well as other signal parameters. Device 100 may also include a digital signal processor (DSP) 120 for processing the signals.

[0036] Device 100 may also include a battery 122 for powering various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of device 100. The PMIC 124 may perform various functions for the device, such as direct current (DC) - to - DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In some aspects, the PMIC 124 may include a battery charging circuit (e.g., a primary - secondary battery charging circuit) or other switched - mode power supplies. The various components of device 100 may be coupled together via a bus system 126, which may include, in addition to a data bus, a power bus, a control signal bus, and / or a status signal bus.

[0037] For some aspects, device 100 may have an input / output (I / O) module 128 for receiving and / or outputting data and / or power. In some aspects, the I / O module 128 may include a connector 130, such as a Universal Serial Bus (USB) Type - A (USB - A) socket or a USB - C socket. The pins of the connector 130 may be routed via the bus system 126 and / or signal lines of the I / O module 128 to the processor 104 and / or the PMIC 124, at least some of which may include over - voltage protection circuits, as further described herein. Also, as described herein, the I / O module 128 may include a decoder - encoder (codec) chip, which includes an audio signal path and drivers and other hardware components to facilitate audio passing through the connector 130.

[0038] Figure 2 is an illustration of an example hardware architecture 200, which provides more details on how some portions of device 100 may be implemented. For example, architecture 200 includes an application processor 210, which may include some or all of the functionality of processor 104 and DSP 120. In some examples, the application processor 210 may be a system - on - chip (SOC), which includes multiple processor cores, a digital signal processor (DSP), memory, etc. For example, one or more of these processor cores may run an operating system with kernels that provide functionality for, e.g., controlling the multiplexing circuit 235 and the VGOVP circuit 236. Architecture 200 also includes a charger integrated circuit 220, which may include some or all of the functionality of the PMIC 124.

[0039] The codec chip 230 may provide some or all of the functions of the I / O module 128 and may also include a connector 130 for physical docking with the plug 250. In this example, the plug 250 is a USB-C plug, but the scope of specific implementation may include any suitable plug, whether or not it complies with the standard. The codec chip 230 interfaces with both the audio signal path and the USB data path. For example, the codec chip 230 receives high-speed data from the USB-C plug 250 on the DNL and DPR data lines. The codec chip 230 can then route the high-speed data to the application processor 210.

[0040] Additionally, the codec chip includes audio signal amplifiers 231, 232 for the left and right channels respectively. The analog audio signals can be output to the USB-C plug 250 for use with, for example, wired headphones. It is also worth noting that the USB-C plug 250 can be used for charging such that DC power can be provided from the USB-C plug 250 to the charger IC 220.

[0041] For facilitating shared connections, the codec chip 230 includes a multiplexing circuit 235, which is illustrated as a plurality of switches in Figure 2 . For example, when audio signals are being sent from the audio signal amplifiers 231, 232 to the USB-C plug 250, the switches can be turned on to create a circuit path from the audio signal amplifiers 231, 232 to the USB-C plug 250, while other switches can be turned off to isolate the application processor 210 from the audio signal path and also isolate the charger IC 220 from the audio signal path. Similarly, when the application processor 210 is sending and receiving digital data via the DP and DN pins using the USB-C plug 250, the charger IC 220 and the audio signal amplifiers 231, 232 can be isolated from the USB-C plug via the multiplexing circuit 235. Moreover, when the charger IC 220 is receiving DC power via the DN and DP pins of the USB-C plug 250, the multiplexing circuit 235 can create an electrical connection from the charger IC 220 to the USB-C plug 250 while isolating the application processor 210 and the audio signal amplifiers 231, 232 from the DC charging power. The multiplexing circuit 235 can be controlled, for example, by the application processor 210 or some other suitable hardware or software logic within the architecture 200.

[0042] The codec chip 230 also includes an external transistor linearizer, overvoltage protection, and electrostatic discharge circuitry 236 (hereinafter referred to as the VGOVP circuitry 236), which drives the gates of transistors M1, M2, M3, etc. For example, the VGOVP circuitry 236 can turn off transistors M1, M2, M3 to electrically isolate the codec chip 230, the application processor 210, and the charger IC 220 from the USB-C plug 250. The VGOVP circuitry 236 can also turn on transistors M1, M2, M3 and provide linearization to transistors M1, M2, M3 during the on state.

[0043] Figure 3 A schematic diagram illustrating an example audio switch linearization architecture 300 in accordance with another aspect of the present disclosure is shown. Architecture 300 includes a digital-to-analog converter (DAC) 311, a direct current (DC) level shift circuit 312, and a buffer (e.g., an operational amplifier) 313. The DAC reference voltage (Vref) is an audio signal (VinL) from the output of the audio signal amplifier 232. In this example, the DAC 311 applies gain factors (α and β) to the analog audio signal from the output of the audio signal amplifier 232. Specific gain factors can be set using DAC codes (d0, d1... dn) based on digital calculations. Setting the gain factors is described in more detail below with respect to Figure 7 Voltage VGOVP_L drives the gate of transistor M1.

[0044] For purposes of illustration, Figure 3 attention is focused on the left channel corresponding to the audio signal amplifier 232. It should be understood that a similar architecture is applied to the right channel corresponding to the audio signal amplifier 231 to drive the gate of transistor M2. Additionally, the gate drive circuit 350 drives the gate of transistor M3 on the ground path, and although shown simplified here, is described in more detail with respect to Figure 6 The audio signal amplifier 232 receives an analog audio signal from the DAC 330 and provides a gain level sufficient to apply the audio signal to a transducer (such as a speaker in a headset).

[0045] Continuing with this example, the gate drive circuit 310 includes a DAC 311, a DC shift circuit 312, and a buffer 313. As described above, the DAC 311 receives the analog audio signal VinL from the output of the audio signal amplifier 232. The DAC 311 is programmed to apply gain factors (α and β) to the analog audio signal. The DC shift circuit 312 applies a voltage level shift, and a combined signal having an AC component from the audio signal and a DC component from the DC shift circuit 312 is applied to the non-inverting input of the buffer 313.

[0046] The buffer 313 is implemented using the operational amplifier in Figure 3 There is a feedback path from the output of the gate drive circuit 310 to the inverting input of the buffer 313, where the feedback path includes a resistor with a value of R. There is also a DC voltage applied to the inverting input by the DC source 314 and through another resistor with a value of R.

[0047] In an example of the architecture 300, the two resistors R coupled to the inverting input of the buffer 313 have the same value, which makes the gain value of the buffer 313 equal to 2. However, the scope of the specific implementation is not limited to resistors with the same value or a specific gain of the buffer 313. Instead, the scope of the specific implementation includes any appropriate amount of gain for a given application.

[0048] When no data or audio is being transmitted or received, the transistors M1, M2, M3 can be turned off by applying a voltage sufficient to cause a negative gate-source voltage at the corresponding gates. On the other hand, when data or audio is being transmitted or received, these transistors can be turned on by applying a gate voltage with a DC component sufficient to turn on the transistors M1, M2, M3. Additionally, during the on-state of the transistors M1, M2, M3, the gate voltage can have an AC component sufficient to provide linearization.

[0049] Figure 3 Some physical arrangements of specific implementations are also illustrated. Specifically, in the example of Figure 3 , the audio signal amplifier 232, the gate drive circuit 310, the audio DAC 330, and the gate drive circuit 350 are provided on the codec chip 230. On the contrary, the transistors M1, M2, M3 are provided outside the codec chip 230. The illustrated physical arrangement can result in a situation where the codec chip 230 can only access the gates of the transistors M1, M2, M3, but not other terminals of these transistors. Even in a physical arrangement such as Figure 3 , the various specific implementations described herein can effectively reduce THD, where the gate voltage is the only variable for adjustment and linearization.

[0050] Figure 4 illustrates an example gate drive circuit 400 according to a specific implementation of the present disclosure. The gate drive circuit 400 can be implemented on the left audio channel (as shown in Figure 3 ) or on the right audio channel. A similar structure described in more detail with respect to Figure 6 can be used to drive a transistor (e.g., M3) at the ground path.

[0051] In an example of the gate drive circuit 400, the DAC is implemented as a resistor string DAC (RDAC) 411. The voltage VinL is an analog audio signal from the left audio channel, although as described above, the example gate drive circuit 400 can be implemented on the left audio channel or on the right audio channel. In an instance where the example gate drive circuit 400 is implemented on the right audio channel, the analog audio signal VinR (from the audio signal amplifier 231) will be used.

[0052] The RDAC 411 corresponds to Figure 3 the DAC 311 in. In other words, the RDAC 411 illustrates one way in which the DAC 311 can be designed. The RDAC 411 is shown as an equivalent circuit having resistors R1 and R2, where the selected tap point generates the desired gain factor for the AC component (α*VinL). The desired tap point can be selected by a DAC code, which is illustrated in Figure 3 as (d0, d1... dn). In fact, the DAC code is the digital input to the DAC 411. The scope of the specific implementation is not limited to the RDAC, as any suitable DAC architecture can be used.

[0053] The gate drive circuit 400 also includes a DC shift circuit 412, which corresponds to Figure 3 the DC shift circuit 312 in. In other words, the DC shift circuit 412 illustrates one way in which the DC shift circuit 312 can be designed. In the Figure 4 example, the DC shift circuit 412 can be implemented using a current source Idc and a resistor Rdc arranged between the non-inverting input of the DAC 411 and the buffer 313. The DC voltage offset Vdc is equal to Idc*Rdc. The scope of the specific implementation is not limited to any particular DC shift circuit, as the DC voltage can be added in any suitable manner.

[0054] Due to the gain generated by the RDAC 411 and the DC offset generated by the DC shift circuit 412, the voltage level at the non-inverting input of the buffer 313 is Idc*Rdc + α*VinL.

[0055] Figure 4Illustrates the parasitic capacitance Cp at both the inverting and non-inverting inputs of buffer 313. Due to the parasitic capacitance, a phase delay may be experienced at the output of the gate drive circuit 400 relative to the analog audio signal VinL at the output of the audio signal amplifier 233 on the left channel (or audio signal amplifier 232 on the right channel). In various embodiments, an equalization capacitor Ceq is added in parallel with a resistor at the non-inverting input (between the voltage source 314 and the non-inverting input). This equalization capacitor Ceq can equalize the phase between the output of the gate drive circuit 400 and the corresponding audio channel. The equalization capacitor Ceq can be designed in any suitable manner, although in the specific architecture shown in Figure 4 the minimum phase delay occurs when the equation (1) is satisfied:

[0056]

[0057] In some embodiments, the equalization capacitor Ceq can be variable so that it can be adjusted for a specific application.

[0058] The output of the gate drive circuit 400 has a DC component and an AC component. The DC component is Vdc, which is equal to Idc*Rdc and equal to the voltage of the voltage source 314. Note that the inverting input of the buffer 313 receives its DC voltage component from a resistive voltage divider consisting of two resistors with a value of R. The AC component of this output is equal to 2*α*VinL. When applied to the right audio channel, the AC component of this output will be 2*α*VinR. In this embodiment, the output voltage VGOVP is applied to the gate of a transistor (such as transistor M1 on the left audio channel or M2 on the right audio channel).

[0059] Figure 5 and Figure 6 Illustrates example architectures 500 and 600 for implementing a gate drive circuit on both the left audio channel, right audio channel, and the ground path according to one embodiment. The DAC 311 receives VinL as its reference voltage and outputs the gain-adjusted audio signal α*VinL. Additionally, in this example, the DAC 311 is a dual DAC with two outputs. The other output is the gain-adjusted audio signal β*VinL. Additionally, in this example, the gain factors α and β can be the same or different to suit a given application. The example DAC 311 can include two RDACs, one for outputting α*VinL and the other for outputting β*VinL. The DAC 511 can be the same as or similar to the DAC 311.

[0060] The DC shift circuit 512 can be the same as or similar to the DC shift circuit 312, the buffer 513 can be the same as or similar to the buffer 313, and the voltage source 514 can be the same as or similar to the voltage source 314. The output voltage to the gate of transistor M1 is Vdc + 2 * α * VinL, and the output to the gate of transistor M2 is Vdc + 2 * α * VinR.

[0061] The architecture 600 can be used to provide a gate voltage to the ground path transistor M3. Contrary to the architecture 500 in which the buffers 313, 513 receive the gain-adjusted audio signals according to the gain factor α, the architecture 600 causes the buffers 613, 713 to receive the gain-adjusted audio signals according to the gain factor β. The gain factors α and β can be the same or different and can be selected as appropriate to fit a particular application. Additionally, in this example, both the left and right channels use the same gain level α; however, some embodiments may use different gain levels for the left and right channels. In such examples, the DAC 311 can apply the gain level α1 to the left channel, and the DAC 511 can apply the gain level α2 to the right channel, where α1 and α2 are different. Similarly, the DAC 311 can apply the gain level β1 to the left channel, and the DAC 511 can apply the gain level β2 to the right channel, where β1 and β2 are different.

[0062] The DC shift circuits 612, 712 can be the same as or similar to the DC shift circuit 312, the buffers 613, 713 can be the same as or similar to the buffer 313, and the voltage sources 614, 714 can be the same as or similar to the voltage source 314. The output of buffer 613 is equal to Vdc + 2β * VinL, and the output of buffer 713 is equal to Vdc + 2β * VinR. The output terminals of buffer 613 and buffer 713 are coupled to the gate of transistor M3 through a resistor divider having resistors R3 and R4. The values of resistors R3 and R4 can be the same or different. The architecture 600 applies a weighted average of the gain-adjusted versions of the left and right audio channels to the gate of transistor M3. The weights of the weighted average are set by the values of resistors R3 and R4. In embodiments where the resistance values of resistors R3 and R4 are the same, the voltage applied to the gate of transistor M3 is Vdc + β(VinL + VinR). In an example where the DAC 311 applies the gain level β1 to the left channel and the DAC 511 applies the gain level β2 to the right channel, the voltage applied to the gate of transistor M3 is Vdc + β1(VinL) + β2(VinR).

[0063] Figure 7 A resistor network 700 according to one example is illustrated. Specifically, the resistor network 700 is provided to show an example of calculating the gain factors α and β.

[0064] In Figure 7 the example, R ext is the resistance value of a given audio path transistor (e.g., M1 or M2). The voltage V x2 is the voltage at the source of the audio path transistor, and the voltage V x1 is the voltage at the drain of the audio path transistor. R L is the load resistance value measured at the USB-C plug 250. V g_aud is the voltage applied to the gate of the audio path transistor, and V g_gnd is the voltage applied to the gate of the ground path transistor (e.g., transistor M3). V in is the AC component from the audio channel, such as VinL or VinR. K1 and K2 are the weighting factors applied to the drain voltage and the source voltage. R int represents the resistance attributable to one or more switches (not shown) on the corresponding path and can be ignored for the following calculations.

[0065] The weighting factors K1 and K2 can be set through experiments and / or simulations to provide a sufficient THD level for a given application. In the example where K1 = 3 and K2 = 1, Equation (2) gives the relationship between V g_aud and V in :

[0066]

[0067] (Equation 2), where R ratio is R ext / RL.

[0068] Equation (3) gives the relationship between V g_gnd and V in :

[0069]

[0070] In one example, the gain factor α can be determined by selecting appropriate values for K1 and K2 consistent with Equation (4):

[0071]

[0072] Equation 4 applies to the left audio channel, although it is also within the scope of the implementation to use VinR from the right audio channel instead of VinL in Equation (4). Similarly, β can be determined by selecting appropriate values for K1 and K2 consistent with Equation (5):

[0073]

[0074] In some specific implementations, the gain factors α and β can be set through a digital input to one of the DACs 311, 511. For example, a bit sequence (d0, d1... dn) is used to input the values of K1 and K2. Generally, it is expected that different audio switching transistors (such as the MOSFET transistors shown as M1, M2, M3) may vary depending on the application, and the appropriate gain factors may also vary depending on the application. In other words, changes in the design or process of one or more of the transistors M1, M2, M3 can benefit from determining new gain factors α and β.

[0075] Various specific implementations may include advantages over other solutions. For example, as described above regarding Figures 3 to 7 the gate drive circuit specific implementation can provide a more precise linearization level for the transistors M1, M2, M3 by using a DAC to provide gain to the audio channel signal. A specific DAC can be selected to obtain an appropriate accuracy level to meet the THD constraints for a given application. Therefore, through the digital input to the DAC, the THD level can be reduced or at least maintained within an acceptable range. The DAC can be configured to receive a digital input from a computing resource (such as an application processor), which can monitor the distortion and make adjustments as needed and / or perform calibration at startup.

[0076] Figure 8 An example resistor string 800 that can be used in a DAC (such as Figure 4 the RDAC 411) according to one specific implementation is illustrated. Again, Figure 8 it is shown how the resistor string 800 can be applied to the left audio channel to receive the input voltage VinL, and the scope of the specific implementation includes other resistor strings receiving other audio channel input voltages (such as VinR).

[0077] When RDAC devices (such as RDAC 411) are built on a semiconductor substrate, they can have a capacitance equivalent to the body. The capacitance equivalent to the body causes the resistor network of the resistor string 800 to behave like a transmission line, and this can produce a phase lag. Figure 8 An example is shown in N where multiple resistors R0... R N are arranged in series, and the capacitance equivalent to the body is illustrated by capacitors C0... C dnw_psub and C

[0078] Various specific embodiments of the present disclosure can reduce or eliminate phase lag from RDAC specific embodiments by coupling a resistor body (res_bulk) to an input VinL. Specifically, the body of resistor res_bulk can correspond to a semiconductor substrate or semiconductor well beneath resistor res_bulk, and some specific embodiments can connect an input voltage VinL to the semiconductor substrate or well, as Figure 8 illustrated. Reducing phase lag can result in lower THD.

[0079] Now, an example method for operating a wireless communication device having a first MOSFET switch implemented between a first audio signal amplifier and an audio load will be discussed with reference to the Figure 9 flowchart shown. Method 900 can be executed by a hardware architecture such as that Figure 2 illustrated in, as it receives and transmits audio signals on a transmission line. For example, the hardware architecture can include one or more high-speed data transmission lines (e.g., DPR and DNL) that are configured to transmit audio signals and are coupled to a multiplexing circuit (e.g., multiplexing circuit 235) and an audio signal amplifier (e.g., audio signal amplifiers 231, 232). The actions of method 900 can be executed under the control of logic, such as can be implemented in a core of an application processor 210 or under the control of other suitable computing circuitry.

[0080] At action 910, the method includes isolating the first audio signal amplifier from the audio load. Action 910 can include applying a first gate control signal to the first MOSFET switch at a first voltage level that turns off the first MOSFET switch. For example, a gate driver circuit 310 can output a low voltage to transistor M1, thereby turning off transistor M1 and isolating audio signal amplifier 232 from USB-C plug 250.

[0081] Similarly, action 910 can include isolating other audio signal amplifiers, such as isolating audio signal amplifier 231 from USB-C plug 250, by applying a low voltage to the gate of transistor M2 under the action of a gate driver circuit including buffer 513. Action 910 can also include turning off transistors in a ground path, such as by applying a low voltage to the gate of transistor M3 under the action of a gate driver circuit including buffers 613, 713.

[0082] At action 920, the method includes linearizing the first MOSFET switch, including applying a first gate control signal to the first MOSFET switch at a second voltage level during the on state of the first MOSFET switch. Examples of action 920 include Figure 3The gate drive circuit 310 therein applies a gate control signal to the transistor M1, where the gate control signal includes a DC voltage (Vdc) sufficient to turn on the transistor M1 and an AC component (2*α*VinL) for linearizing the operation of the transistor M1 during the on state.

[0083] Consistent with Figures 3 to 7 the example of, the AC component can be generated at least in part by a DAC that applies a first gain level to the output of the first audio signal amplifier. In Figure 4 the example of, the gain level of the left audio channel is α.

[0084] At action 930, the method further includes linearizing other MOSFET switches. For example, on the right audio channel, the gain level α can be applied by a DAC to generate an AC component applied at the gate of the transistor M2. At the ground path, the gain level β can be applied to both audio channels by using another DAC to generate an AC component applied at the gate of the transistor M3, as Figure 6 shown.

[0085] Actions 920 to 930 can be performed when those transistors M1, M2, M3 are on and when a set of wires DPR, DNL conduct an analog audio signal from the audio signal amplifier. Accordingly, the impedance of the transistors M1, M2, M3 can remain approximately constant within the range of the audio signal.

[0086] At action 940, the MOSFET switches return to the off state. For example, the corresponding gate drive circuit can apply the gate control signal to those transistors at a voltage level sufficient to cause a negative gate-source voltage in the transistors M1, M2, M3. Action 940 can be performed when the set of wires DPR, DNL is not used to conduct an analog audio signal from the audio signal amplifier or when the MOSFET switches are used to protect the internal codec circuit from damage.

[0087] The scope of the specific implementation is not limited to the series of actions described with respect to Figure 9 Instead, actions 910 to 940 can be appropriately repeated depending on whether the wired audio capability is in use or not in use.

[0088] As will be understood by those skilled in the art so far and depending on the particular application at hand, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of using the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein (as they are only some examples of the present disclosure), but should be fully equivalent to the following appended claims and their functional equivalents.

[0089] Specific embodiments are described in the following numbered clauses:

[0090] 1. A wireless communication device, the wireless communication device comprising:

[0091] An application processor;

[0092] A first audio signal amplifier;

[0093] A multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires;

[0094] A data and audio plug coupled to the set of wires;

[0095] A first metal-oxide-semiconductor field-effect transistor (MOSFET) switch disposed on a first wire of the set of wires between the first audio signal amplifier and the data and audio plug; and

[0096] A first gate drive circuit having an output coupled to the gate of the first MOSFET switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the output of the first audio signal amplifier through a first digital-to-analog converter (DAC).

[0097] 2. The wireless communication device according to clause 1, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the wireless communication device further comprises:

[0098] A second audio signal amplifier corresponding to a second audio channel;

[0099] A second MOSFET switch disposed on a second wire of the set of wires between the second audio signal amplifier and the data and audio plug; and

[0100] A second gate drive circuit having an output coupled to the gate of the second MOSFET switch, the second gate drive circuit including a second buffer having a second buffer input coupled to the output of the second audio signal amplifier through a second DAC.

[0101] 3. The wireless communication device according to clause 2, the wireless communication device further comprising:

[0102] A third MOSFET switch, the third MOSFET switch being disposed on a third wire of the set of wires between ground and the data and audio plug; and

[0103] A third gate drive circuit, the third gate drive circuit having an output coupled to the gate of the third MOSFET switch, the third gate drive circuit including a third buffer, the third buffer having a third buffer input coupled to the output of the first audio signal amplifier through the first DAC; and

[0104] A fourth gate drive circuit, the fourth gate drive circuit having an output coupled to the gate of the third MOSFET switch, the fourth gate drive circuit including a fourth buffer, the fourth buffer having a fourth buffer input coupled to the output of the second audio signal amplifier through the second DAC.

[0105] 4. The wireless communication device according to clause 3, wherein the gate of the third MOSFET switch is coupled to the output of the third gate drive circuit and the output of the fourth gate drive circuit through a resistor divider.

[0106] 5. The wireless communication device according to clause 3, wherein the first DAC is configured to apply a gain α to the output of the first audio signal amplifier, and wherein the first DAC is configured to apply a gain β to the output of the first audio signal amplifier, where α and β are different values,

[0107] Further, wherein the second DAC is configured to apply the gain α to the output of the second audio signal amplifier, and wherein the second DAC is configured to apply the gain β to the output of the second audio signal amplifier, and

[0108] Further, wherein the first buffer is configured to receive the output of the first audio signal amplifier at the gain α, the second buffer is configured to receive the output of the second audio signal amplifier at the gain α, the third buffer is configured to receive the output of the first audio signal amplifier at the gain β, and the fourth buffer is configured to receive the output of the second audio signal amplifier at the gain β.

[0109] 6. The wireless communication device according to any one of clauses 1 to 5, wherein the first buffer has a fifth buffer input coupled to a direct current (DC) voltage source, and wherein the output of the first gate drive circuit is coupled to the fifth buffer input.

[0110] 7. The wireless communication device according to clause 6, wherein the input terminal of the fifth buffer is coupled to the DC voltage source through a first resistor, wherein the first resistor is coupled in parallel with a first capacitor, and wherein the input terminal of the fifth buffer is coupled to the output terminal of the first gate drive circuit through a second resistor. Further, wherein the input terminal of the first buffer is a non-inverting input terminal, and wherein the input terminal of the fifth buffer is an inverting input terminal.

[0111] 8. The wireless communication device according to any one of clauses 1 to 7, wherein the first gate drive circuit further includes a direct current (DC) voltage shift circuit located between the first DAC and the input terminal of the first buffer.

[0112] 9. The wireless communication device according to any one of clauses 1 to 8, wherein the data and audio plug includes a universal serial bus (USB) plug.

[0113] 10. The wireless communication device according to any one of clauses 1 to 9, the wireless communication device further comprising:

[0114] A decoder / encoder (codec) chip, the decoder / encoder (codec) chip including the set of wires, the first audio signal amplifier, and the multiplexing circuit, and wherein the first MOSFET switch is disposed outside the codec chip.

[0115] 11. The wireless communication device according to any one of clauses 1 to 10, wherein the first DAC includes a resistor string DAC (RDAC) built on a semiconductor substrate, and wherein the signal input terminal of the first DAC is coupled to the resistor body of the semiconductor substrate.

[0116] 12. A method for operating a wireless communication device, the wireless communication device having a first metal oxide semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an audio load, the method comprising:

[0117] Isolating the first audio signal amplifier from the audio load, including applying a first gate control signal to the first MOSFET switch at a first voltage level, the first voltage level turning off the first MOSFET switch; and

[0118] Linearizing the first MOSFET switch includes applying the first gate control signal to the first MOSFET switch at a second voltage level during an on-state of the first MOSFET switch, where linearizing the first MOSFET switch includes applying an output of the first audio signal amplifier as a reference voltage to a first digital-to-analog converter (DAC), where the first DAC applies a first gain level to the output of the first audio signal amplifier, and where a first amplifier receives the output of the first audio signal amplifier at the first gain level, and where the first amplifier outputs the first gate control signal to the first MOSFET switch.

[0119] 13. The method according to clause 12, wherein the wireless communication device further has a second MOSFET switch implemented between a second audio signal amplifier and the audio load, and the method further includes:

[0120] Linearizing the second MOSFET switch includes applying a second gate control signal to the second MOSFET switch during an on-state of the second MOSFET switch, where linearizing the second MOSFET switch includes applying an output of the second audio signal amplifier as a reference voltage to a second DAC, where the second DAC applies the first gain level to the output of the second audio signal amplifier, and where a second amplifier receives the output of the second audio signal amplifier at the first gain level, and where the second amplifier outputs the second gate control signal to the second MOSFET switch.

[0121] 14. The method according to clause 13, wherein the wireless communication device further has a third MOSFET switch implemented between the audio load and ground and a fourth MOSFET switch implemented between the audio load and ground, and the method further includes:

[0122] Linearizing the third MOSFET switch includes:

[0123] Applying a third gate control signal to the third MOSFET switch during an on-state of the third MOSFET switch, where the first DAC applies a second gain level to the output of the first audio signal amplifier, and where a third amplifier receives the output of the first audio signal amplifier at the second gain level, and where the third amplifier outputs the third gate control signal to the third MOSFET switch through a resistor divider; and

[0124] wherein the second DAC applies the second gain level to the output of the second audio signal amplifier, and wherein a fourth amplifier receives the output of the second audio signal amplifier at the second gain level, and wherein the fourth amplifier outputs the third gate control signal to the third MOSFET switch through the resistive voltage divider.

[0125] 15. The method according to any one of clauses 12 to 14, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the second audio signal amplifier corresponds to a second audio channel.

[0126] 16. The method according to any one of clauses 12 to 15, wherein the audio load is coupled to the first MOSFET switch through a Universal Serial Bus (USB) plug, and wherein a second audio load is coupled to the second MOSFET switch through the USB plug.

[0127] 17. A wireless communication device, the wireless communication device comprising:

[0128] means for running an operating system;

[0129] means for amplifying an analog audio signal;

[0130] means for coupling the means for running the operating system and the means for amplifying the analog audio signal to a set of wires;

[0131] a data and audio plug coupled to the set of wires;

[0132] a first transistor coupled between the data and audio plug and the means for amplifying the analog audio signal; and

[0133] means for linearizing the operation of the first transistor, the means for linearizing the operation of the first transistor including a first digital-to-analog converter (DAC) configured to receive a first audio signal from the means for amplifying the analog audio signal and output the first audio signal having a first gain level to a first amplifier, wherein the first amplifier is coupled to the gate of the first transistor.

[0134] 18. The wireless communication device according to clause 17, wherein the data and audio plug includes a Universal Serial Bus (USB) plug.

[0135] 19. The wireless communication device according to any one of clauses 17 to 18, the wireless communication device further comprising:

[0136] A decoder / encoder (codec) chip, the decoder / encoder (codec) chip including the set of wires, the component for amplifying an analog audio signal, and the component for coupling, and wherein the first transistor is disposed outside the codec chip.

[0137] 20. The wireless communication device according to any one of clauses 17 to 18, wherein the first DAC includes a resistor string DAC (RDAC) built on a semiconductor substrate, and wherein a signal input terminal of the first DAC is coupled to a resistor body of the semiconductor substrate.

[0138] 21. The wireless communication device according to any one of clauses 17 to 18, the wireless communication device further comprising:

[0139] A second transistor, the second transistor being coupled between the data and audio plug and the component for amplifying an analog audio signal; and

[0140] A component for linearizing the operation of the second transistor, the component for linearizing the operation of the second transistor including a second DAC, the second DAC being configured to receive a second audio signal from the component for amplifying an analog audio signal and output the second audio signal having the first gain level to a second amplifier, wherein the second amplifier is coupled to a gate of the second transistor.

[0141] 22. The wireless communication device according to clause 21, the wireless communication device further comprising:

[0142] A third transistor, the third transistor being coupled between the data and audio plug and ground; and

[0143] A component for linearizing the operation of the third transistor, the component for linearizing the operation of the third transistor including:

[0144] A third amplifier, the third amplifier being configured to receive the first audio signal having a second gain level from the first DAC, wherein the third amplifier is coupled to a gate of the third transistor; and

[0145] A fourth amplifier, the fourth amplifier being configured to receive the second audio signal having the second gain level from the second DAC, wherein the fourth amplifier is coupled to a gate of the third transistor.

[0146] 23. The wireless communication device according to clause 22, wherein the third amplifier and the fourth amplifier are coupled to the gate of the third transistor through a resistor divider.

[0147] 24. A wireless communication device, the wireless communication device comprising:

[0148] An application processor;

[0149] A pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel;

[0150] A decoder codec (CODEC) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires;

[0151] A plug coupled to the set of wires;

[0152] A first switch coupled between the application processor and the plug on a first wire of the set of wires; and

[0153] A first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the first audio channel through a first digital-to-analog converter (DAC).

[0154] 25. The wireless communication device according to clause 24, wherein the first switch is disposed outside the codec chip.

[0155] 26. The wireless communication device according to any one of clauses 24 to 25, the wireless communication device further comprising:

[0156] A second switch disposed on a second wire of the set of wires between the application processor and the data and audio plug; and

[0157] A second gate drive circuit having an output coupled to the gate of the second switch, the second gate drive circuit including a second buffer having a second buffer input coupled to the second audio channel through a second DAC.

[0158] 27. The wireless communication device according to clause 26, the wireless communication device further comprising:

[0159] A third switch disposed on a third wire of the set of wires between ground and the data and audio plug; and

[0160] A third gate drive circuit having an output coupled to the gate of the third switch, the third gate drive circuit including a third buffer having a third buffer input coupled to the first audio channel via the first DAC;

[0161] A fourth gate drive circuit having an output coupled to the gate of the third switch, the fourth gate drive circuit including a fourth buffer having a fourth buffer input coupled to the second audio channel via the second DAC.

[0162] 28. The wireless communication device according to clause 27, wherein the third buffer and the fourth buffer are coupled to the gate of the third switch via a resistive voltage divider.

[0163] 29. The wireless communication device according to clause 27, wherein the first DAC is configured to apply a gain α to the first audio channel, and wherein the first DAC is configured to apply a gain β to the output of the first audio channel, where

[0164] α and β are different values,

[0165] Further, wherein the second DAC is configured to apply the gain α to the second audio channel, and wherein the second DAC is configured to apply the gain β to the second audio channel, and

[0166] Further, wherein the first buffer is configured to receive the first audio channel with the gain α, the second buffer is configured to receive the second audio channel with the gain α, the third buffer is configured to receive the first audio channel with the gain β, and the fourth buffer is configured to receive the second audio channel with the gain β.

[0167] 30. The wireless communication device according to clause 29, wherein the plug includes a Universal Serial Bus (USB) plug.

Claims

1. A wireless communication device, the wireless communication device comprising: An application processor; A first audio signal amplifier; A multiplexing circuit configured to couple the application processor and the first audio signal amplifier to a set of wires; A data and audio plug coupled to the set of wires; A first metal-oxide-semiconductor field-effect transistor (MOSFET) switch disposed on a first wire of the set of wires between the first audio signal amplifier and the data and audio plug; And A first gate drive circuit having an output coupled to the gate of the first MOSFET switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the output of the first audio signal amplifier through a first digital-to-analog converter (DAC).

2. The wireless communication device according to claim 1, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the wireless communication device further comprises: A second audio signal amplifier corresponding to a second audio channel; A second MOSFET switch disposed on a second wire of the set of wires between the second audio signal amplifier and the data and audio plug; And A second gate drive circuit having an output coupled to the gate of the second MOSFET switch, the second gate drive circuit including a second buffer having a second buffer input coupled to the output of the second audio signal amplifier through a second DAC.

3. The wireless communication device according to claim 2, the wireless communication device further comprising: A third MOSFET switch disposed on a third wire of the set of wires between ground and the data and audio plug; And A third gate drive circuit having an output coupled to the gate of the third MOSFET switch, the third gate drive circuit including a third buffer having a third buffer input coupled to the output of the first audio signal amplifier through the first DAC; And A fourth gate drive circuit having an output coupled to the gate of the third MOSFET switch, the fourth gate drive circuit including a fourth buffer having a fourth buffer input coupled to the output of the second audio signal amplifier through the second DAC.

4. The wireless communication device according to claim 3, wherein the gate of the third MOSFET switch is coupled to the output of the third gate drive circuit and the output of the fourth gate drive circuit through a resistor divider.

5. The wireless communication device according to claim 3, wherein the first DAC is configured to apply a gain α to the output of the first audio signal amplifier, and wherein the first DAC is configured to apply a gain β to the output of the first audio signal amplifier, where α and β are different values, Further, wherein the second DAC is configured to apply the gain α to the output of the second audio signal amplifier, and wherein the second DAC is configured to apply the gain β to the output of the second audio signal amplifier, and Further, wherein the first buffer is configured to receive the output of the first audio signal amplifier with the gain α, the second buffer is configured to receive the output of the second audio signal amplifier with the gain α, the third buffer is configured to receive the output of the first audio signal amplifier with the gain β, and the fourth buffer is configured to receive the output of the second audio signal amplifier with the gain β.

6. The wireless communication device according to claim 1, wherein the first buffer has a fifth buffer input terminal coupled to a direct current (DC) voltage source, and wherein the output terminal of the first gate drive circuit is coupled to the fifth buffer input terminal.

7. The wireless communication device according to claim 6, wherein the fifth buffer input terminal is coupled to the DC voltage source through a first resistor, wherein the first resistor is coupled in parallel with a first capacitor, and wherein the fifth buffer input terminal is coupled to the output terminal of the first gate drive circuit through a second resistor. Further, wherein the first buffer input terminal is a non-inverting input terminal, and wherein the fifth buffer input terminal is an inverting input terminal.

8. The wireless communication device according to claim 1, wherein the first gate drive circuit further includes a direct current (DC) voltage shift circuit located between the first DAC and the first buffer input terminal.

9. The wireless communication device according to claim 1, wherein the data and audio plug includes a universal serial bus (USB) plug.

10. The wireless communication device according to claim 1, the wireless communication device further includes: A decoder / encoder (codec) chip, the decoder / encoder (codec) chip includes the set of wires, the first audio signal amplifier and the multiplexing circuit, and wherein the first MOSFET switch is disposed outside the codec chip.

11. The wireless communication device according to claim 1, wherein the first DAC includes a resistor string DAC (RDAC) built on a semiconductor substrate, and wherein the signal input terminal of the first DAC is coupled to the resistor body of the semiconductor substrate.

12. A method for operating a wireless communication device, the wireless communication device having a first metal oxide semiconductor (MOSFET) switch implemented between a first audio signal amplifier and an audio load, the method comprising: Isolate the first audio signal amplifier from the audio load, including applying a first gate control signal to the first MOSFET switch at a first voltage level that turns off the first MOSFET switch; And Linearize the first MOSFET switch, including applying the first gate control signal to the first MOSFET switch at a second voltage level during the on state of the first MOSFET switch, wherein linearizing the first MOSFET switch includes applying the output of the first audio signal amplifier as a reference voltage to a first digital-to-analog converter (DAC), wherein the first DAC applies a first gain level to the output of the first audio signal amplifier, and wherein a first amplifier receives the output of the first audio signal amplifier at the first gain level, and wherein the first amplifier outputs the first gate control signal to the first MOSFET switch.

13. The method according to claim 12, wherein the wireless communication device further has a second MOSFET switch implemented between a second audio signal amplifier and the audio load, and the method further includes: Linearize the second MOSFET switch, including applying a second gate control signal to the second MOSFET switch during the on state of the second MOSFET switch, wherein linearizing the second MOSFET switch includes applying the output of the second audio signal amplifier as a reference voltage to a second DAC, wherein the second DAC applies the first gain level to the output of the second audio signal amplifier, and wherein a second amplifier receives the output of the second audio signal amplifier at the first gain level, and wherein the second amplifier outputs the second gate control signal to the second MOSFET switch.

14. The method according to claim 13, wherein the wireless communication device further has a third MOSFET switch implemented between the audio load and ground, and a fourth MOSFET switch implemented between the audio load and ground, and the method further includes: Linearize the third MOSFET switch, including: Applying a third gate control signal to the third MOSFET switch during the on state of the third MOSFET switch, wherein the first DAC applies a second gain level to the output of the first audio signal amplifier, and wherein a third amplifier receives the output of the first audio signal amplifier at the second gain level, and wherein the third amplifier outputs the third gate control signal to the third MOSFET switch through a resistor divider; and wherein the second DAC applies the second gain level to the output of the second audio signal amplifier, and wherein a fourth amplifier receives the output of the second audio signal amplifier at the second gain level, and wherein the fourth amplifier outputs the third gate control signal to the third MOSFET switch through the resistive voltage divider.

15. The method according to claim 13, wherein the first audio signal amplifier corresponds to a first audio channel, and wherein the second audio signal amplifier corresponds to a second audio channel.

16. The method according to claim 13, wherein the audio load is coupled to the first MOSFET switch through a Universal Serial Bus (USB) plug, and wherein a second audio load is coupled to the second MOSFET switch through the USB plug.

17. A wireless communication device, the wireless communication device comprising: means for running an operating system; means for amplifying an analog audio signal; means for coupling the means for running the operating system and the means for amplifying the analog audio signal to a set of wires; a data and audio plug coupled to the set of wires; a first transistor coupled between the data and audio plug and the means for amplifying the analog audio signal; and means for linearizing the operation of the first transistor, the means for linearizing the operation of the first transistor comprising a first digital-to-analog converter (DAC) configured to receive a first audio signal from the means for amplifying the analog audio signal and output the first audio signal having a first gain level to a first amplifier, wherein the first amplifier is coupled to the gate of the first transistor.

18. The wireless communication device according to claim 17, wherein the data and audio plug comprises a Universal Serial Bus (USB) plug.

19. The wireless communication device according to claim 17, the wireless communication device further comprising: a decoder / encoder (codec) chip including the set of wires, the means for amplifying the analog audio signal, and the means for coupling, and wherein the first transistor is disposed outside the codec chip.

20. The wireless communication device according to claim 17, wherein the first DAC comprises a resistor string DAC (RDAC) built on a semiconductor substrate, and wherein the signal input terminal of the first DAC is coupled to the resistor body of the semiconductor substrate.

21. The wireless communication device according to claim 17, the wireless communication device further comprising: a second transistor coupled between the data and audio plug and the means for amplifying the analog audio signal; and Components for the linearization operation of the second transistor, the components for the linearization operation of the second transistor include a second DAC, the second DAC is configured to receive a second audio signal from the components for amplifying an analog audio signal and output the second audio signal having the first gain level to a second amplifier, wherein the second amplifier is coupled to the gate of the second transistor.

22. The wireless communication device according to claim 21, the wireless communication device further comprising: A third transistor, the third transistor being coupled between the data and audio plug and ground; And Components for the linearization operation of the third transistor, the components for the linearization operation of the third transistor include: A third amplifier, the third amplifier being configured to receive the first audio signal having a second gain level from the first DAC, wherein the third amplifier is coupled to the gate of the third transistor; And A fourth amplifier, the fourth amplifier being configured to receive the second audio signal having the second gain level from the second DAC, wherein the fourth amplifier is coupled to the gate of the third transistor.

23. The wireless communication device according to claim 22, wherein the third amplifier and the fourth amplifier are coupled to the gate of the third transistor through a resistor divider.

24. A wireless communication device, the wireless communication device comprising: An application processor; A pair of audio signal amplifiers corresponding to a first audio channel and a second audio channel; A decoder codec (CODEC) chip having a multiplexing circuit configured to couple the application processor and the pair of audio signal amplifiers to a set of wires; A plug coupled to the set of wires; A first switch coupled between the application processor and the plug on a first wire in the set of wires; And A first gate drive circuit having an output coupled to the gate of the first switch, the first gate drive circuit including a first buffer having a first buffer input coupled to the first audio channel through a first digital-to-analog converter (DAC).

25. The wireless communication device according to claim 24, wherein the first switch is disposed outside the codec chip.

26. The wireless communication device according to claim 24, the wireless communication device further comprising: A second switch disposed on a second wire in the set of wires between the application processor and the plug; And A second gate drive circuit having an output coupled to the gate of the second switch, the second gate drive circuit including a second buffer having a second buffer input coupled to the second audio channel through a second DAC.

27. The wireless communication device according to claim 26, the wireless communication device further comprising: A third switch, the third switch being disposed on a third wire of the set of wires between ground and the plug; A third gate drive circuit, the third gate drive circuit having an output coupled to the gate of the third switch, the third gate drive circuit including a third buffer, the third buffer having a third buffer input coupled to the first audio channel through the first DAC; and A fourth gate drive circuit, the fourth gate drive circuit having an output coupled to the gate of the third switch, the fourth gate drive circuit including a fourth buffer, the fourth buffer having a fourth buffer input coupled to the second audio channel through the second DAC.

28. The wireless communication device according to claim 27, wherein the third buffer and the fourth buffer are coupled to the gate of the third switch through a resistive voltage divider.

29. The wireless communication device according to claim 27, wherein the first DAC is configured to apply a gain α to the first audio channel, and wherein the first DAC is configured to apply a gain β to the output of the first audio channel, where α and β are different values, furthermore, wherein the second DAC is configured to apply the gain α to the second audio channel, and wherein the second DAC is configured to apply the gain β to the second audio channel, and furthermore, wherein the first buffer is configured to receive the first audio channel with the gain α, the second buffer is configured to receive the second audio channel with the gain α, the third buffer is configured to receive the first audio channel with the gain β, and the fourth buffer is configured to receive the second audio channel with the gain β.

30. The wireless communication device according to claim 29, wherein the plug includes a Universal Serial Bus (USB) plug.

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