Charging and discharging detection device, driving system of VCSEL and laser radar equipment

Abstract

The invention relates to the technical field of electronics, and provides a charging and discharging detection device, a VCSEL driving system and laser radar equipment. The charging and discharging detection device is applied to the driving system of the VCSEL, the driving system further comprises a GaN tube and at least two VCSEL branches, each VCSEL branch comprises a driving module, a capacitor and a VCSEL, and each VCSEL branch is connected with a corresponding charging and discharging detection device; the charging and discharging detection device comprises a charging detection circuit and a discharging detection circuit; the charging detection circuit and the discharging detection circuit are electrically connected with a connection node of the driving module and the capacitor in the corresponding VCSEL branch; the charging detection circuit is used for detecting the charging state of a capacitor according to the voltage of the capacitor and outputting a first signal when the capacitor in the corresponding VCSEL branch is charged; and the discharge detection circuit is used for detecting the discharge state of the capacitor according to the voltage of the capacitor and outputting a second signal when the capacitor in the corresponding VCSEL branch discharges. Therefore, whether driving of the VCSEL is abnormal or not is detected, and the working stability of the VCSEL is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and in particular, to a charge and discharge detection device, a driving system for a VCSEL, and a lidar device. Background Art

[0002] With the continuous development of automotive electronics, artificial intelligence has been increasingly applied, such as in the field of autonomous driving. Due to the complex and variable nature of various scenarios in modern society, autonomous driving is required to detect the surrounding environment of the vehicle extremely quickly and accurately in order to make correct decisions. In this context, VCSEL (Vertical-Cavity Surface-Emitting Laser) has been widely used due to its advantages in performance and cost, so there has been a lot of research on related technologies of VCSEL. By controlling whether the VCSEL is turned on or off to emit light, the distance to an obstacle can be measured.

[0003] The existing solution is that each VCSEL is connected to a GaN transistor, and these VCSELs cannot share a common cathode. In order to reduce costs, a solution has also been proposed to implement a common cathode for VCSELs. This architecture is controlled by a single GaN transistor for multiple VCSELs, and each VCSEL branch is driven and controlled separately. However, this architecture may cause abnormal operation of the VCSEL when the VCSEL branch is not fully charged or discharged, so it is very necessary to detect its charge and discharge. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a charge and discharge detection device, a driving system for a VCSEL, and a lidar device.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, the present invention provides a charge and discharge detection device, which is applied to a driving system for a VCSEL. The driving system further includes a GaN transistor and at least two VCSEL branches. Each VCSEL branch includes a driving module, a capacitor, and a VCSEL. One end of the capacitor is electrically connected to the driving module and the anode of the VCSEL, and the other end is grounded. The driving module is used to control the charge and discharge of the capacitor according to a driving signal. The cathode of the VCSEL in each VCSEL branch is electrically connected to the GaN transistor; each VCSEL branch is connected to a corresponding charge and discharge detection device, and the charge and discharge detection device includes a charge detection circuit and a discharge detection circuit. The charge detection circuit and the discharge detection circuit are electrically connected to the connection node between the driving module and the capacitor in the corresponding VCSEL branch;

[0007] The charging detection circuit is used to detect the charging state of the capacitor according to the voltage of the capacitor and output a first signal when the capacitor in the corresponding VCSEL branch is charging, and the first signal is used to indicate whether the capacitor is fully charged;

[0008] The discharging detection circuit is used to detect the discharging state of the capacitor according to the voltage of the capacitor and output a second signal when the capacitor in the corresponding VCSEL branch is discharging, and the second signal is used to indicate whether the capacitor is fully discharged;

[0009] Among them, when the capacitor in the VCSEL branch is fully charged, the VCSEL is in the working state; when the capacitor in the VCSEL branch is fully discharged, the VCSEL is in the non-working state.

[0010] In an optional implementation manner, the charging detection circuit includes a first sampling module, a charging state detection module, and a reset module that are electrically connected in sequence; the first sampling module is electrically connected to the capacitor in the corresponding VCSEL branch;

[0011] The first sampling module is used to sample the voltage of the capacitor to obtain a first sampling voltage when the capacitor in the corresponding VCSEL branch is charging, and transmit it to the charging state detection module;

[0012] The charging state detection module is used to detect the charging state of the capacitor according to the first sampling voltage and a preset first voltage threshold and output a first signal;

[0013] The reset module is used to generate a reset signal and transmit it to the charging state detection module when the driving signal flips, so as to reset the charging state detection module.

[0014] In an optional implementation manner, the charging state detection module includes a voltage detection unit, a signal generation unit, and a D flip-flop. The voltage detection unit is electrically connected to the data input terminal of the D flip-flop, and the signal generation unit is electrically connected to the clock input terminal of the D flip-flop;

[0015] The voltage detection unit is used to detect the charging state of the capacitor according to the first sampling voltage and the first voltage threshold, and generate a detection signal and transmit it to the D flip-flop;

[0016] The signal generation unit is used to generate a clock signal and transmit it to the D flip-flop when the driving signal flips, so that the D flip-flop outputs a first signal.

[0017] In an optional implementation manner, the voltage detection unit includes a first comparator, an RS latch, an OR gate, a first inverter, a second inverter, and a first AND gate;

[0018] The non-inverting input terminal of the first comparator is electrically connected to a first power supply for providing a first voltage threshold. The inverting input terminal of the first comparator is electrically connected to the first sampling module. The output terminal of the first comparator is electrically connected to the first input terminal of an OR gate. The enable terminal of the first comparator is used to receive a second enable signal;

[0019] The second input terminal of the OR gate is used to receive a first enable signal. The output terminal of the OR gate is electrically connected to the S terminal of the RS latch. The R terminal of the RS latch is used to receive a second enable signal. The output terminal of the RS latch is electrically connected to the input terminal of a first inverter. The output terminal of the first inverter is electrically connected to the first input terminal of the first AND gate;

[0020] The input terminal of the second inverter is used to receive the first enable signal. The output terminal of the second inverter is electrically connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is electrically connected to the data input terminal of the D flip-flop.

[0021] In an alternative embodiment, the signal generation unit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, and a second AND gate;

[0022] The input terminal of the third inverter is used to receive a trigger signal. The output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter and the first input terminal of the second AND gate. The output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter. The output terminal of the fifth inverter is electrically connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter is electrically connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is electrically connected to the clock input terminal of the D flip-flop.

[0023] In an alternative embodiment, the reset module includes a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a first delay unit, and a second delay unit;

[0024] The input terminal of the seventh inverter is used to receive the drive signal. The output terminal of the seventh inverter is electrically connected to the input terminal of the eighth inverter. The output terminal of the eighth inverter is electrically connected to the input terminal of the first delay unit. The output terminal of the first delay unit is electrically connected to the input terminal of the ninth inverter and the input terminal of the second delay module. The output terminal of the second delay unit is electrically connected to the input terminal of the tenth inverter. The output terminal of the tenth inverter is electrically connected to the reset terminal of the D flip-flop.

[0025] In an alternative embodiment, the discharge detection circuit includes a second sampling module and a discharge state detection module connected electrically. The second sampling module is electrically connected to a capacitor in a corresponding VCSEL branch;

[0026] The second sampling module is configured to sample the voltage of the capacitor to obtain a second sampling voltage when the capacitor in the corresponding VCSEL branch discharges, and transmit it to the discharge state detection module;

[0027] The discharge state detection module is configured to detect the charging state of the capacitor according to the second sampling voltage and a preset second voltage threshold, and output a second signal.

[0028] In an alternative embodiment, the discharge state detection module includes a second comparator, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a third AND gate, and a third delay unit;

[0029] The non-inverting input terminal of the second comparator is electrically connected to the second sampling module, the inverting input terminal of the second comparator is electrically connected to a second power supply, the second power supply is used to provide the second voltage threshold, the output terminal of the second comparator is electrically connected to the input terminal of the eleventh inverter, the output terminal of the eleventh inverter is electrically connected to the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is electrically connected to the first input terminal of the third AND gate;

[0030] The input terminal of the third delay unit is configured to receive a driving signal, the output terminal of the third delay unit is electrically connected to the second input terminal of the third AND gate, the output terminal of the third AND gate is electrically connected to the input terminal of the thirteenth inverter, the output terminal of the thirteenth inverter is electrically connected to the input terminal of the fourteenth inverter, and the output terminal of the fourteenth inverter is configured to output the second signal.

[0031] In a second aspect, the present invention provides a driving system for a VCSEL, including the charge and discharge detection device according to any one of the foregoing embodiments.

[0032] In a third aspect, the present invention provides a lidar device, including the driving system for a VCSEL according to the foregoing embodiment.

[0033] The charge and discharge detection device, driving system of VCSEL, and lidar device provided by the embodiments of the present invention relate to the field of electronic technology, and provide a charge and discharge detection device, a driving system of VCSEL, and a lidar device. The charge and discharge detection device is applied to the driving system of VCSEL. The driving system further includes a GaN transistor and at least two VCSEL branches. Each VCSEL branch includes a driving module, a capacitor, and a VCSEL. Each VCSEL branch is connected to a corresponding charge and discharge detection device. The charge and discharge detection device includes a charge detection circuit and a discharge detection circuit. The charge detection circuit and the discharge detection circuit are electrically connected to the connection node of the driving module and the capacitor in the corresponding VCSEL branch. The charge detection circuit is used to detect the charge state of the capacitor according to the voltage of the capacitor and output a first signal when the capacitor in the corresponding VCSEL branch is charging. The discharge detection circuit is used to detect the discharge state of the capacitor according to the voltage of the capacitor and output a second signal when the capacitor in the corresponding VCSEL branch is discharging. Thus, it is realized to detect whether the driving of VCSEL is abnormal, so as to improve the working stability of VCSEL.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 Shows a schematic structural diagram of the driving system of VCSEL provided by the embodiments of the present invention;

[0037] Figure 2 Shows a schematic structural diagram of the charge detection circuit provided by the embodiments of the present invention;

[0038] Figure 3 Shows a schematic structural diagram of the charge detection circuit provided by the embodiments of the present invention;

[0039] Figure 4 Shows a schematic structural diagram of the discharge detection circuit provided by the embodiments of the present invention;

[0040] Figure 5 Shows a schematic structural diagram of the discharge detection circuit provided by the embodiments of the present invention;

[0041] Figure 6Shows the third schematic diagram of the discharge detection circuit provided by the embodiment of the present invention;

[0042] Figure 7 Shows the schematic diagram of the working waveform of the VCSEL branch provided by the embodiment of the present invention;

[0043] Figure 8 Shows the schematic diagram of the working waveform of the charging detection circuit provided by the embodiment of the present invention.

[0044] Icons: MH - high - side switch transistor; ML - low - side switch transistor; M1 - first switch transistor; M2 - second switch transistor; M3 - third switch transistor; C - capacitor; R1 - first resistor; R2 - second resistor; R3 - third resistor; R4 - fourth resistor; R5 - fifth resistor; OR - OR gate; AND1 - first AND gate; AND2 - second AND gate; AND3 - third AND gate; INV1 - first inverter; INV2 - second inverter; INV3 - third inverter; INV4 - fourth inverter; INV5 - fifth inverter; INV6 - sixth inverter; INV7 - seventh inverter; INV8 - eighth inverter; INV9 - ninth inverter; INV10 - tenth inverter; INV11 - eleventh inverter; INV12 - twelfth inverter; INV13 - thirteenth inverter; INV14 - fourteenth inverter; First delay unit - Delay1; Second delay unit - Delay2; Third delay unit - Delay3; Fourth delay unit - Delay4. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0047] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0048] With the continuous development of automotive electronics, the application of artificial intelligence is increasing, such as in the field of autonomous driving. Due to the complex and changeable nature of various scenarios in modern society, autonomous driving is required to detect the surrounding environment of the vehicle extremely quickly and accurately in order to make correct decisions. In this context, VCSEL (Vertical-Cavity Surface-Emitting Laser) has been widely used due to its advantages in performance and cost, so there is also a lot of research on related VCSEL technologies. By controlling whether the VCSEL is turned on or off to emit light, the distance to an obstacle can be measured.

[0049] The existing solution is that each VCSEL is connected to a GaN transistor, and these VCSELs cannot share a common cathode. In order to reduce costs, a solution has also been proposed to implement a common cathode for VCSELs. This architecture is controlled by a single GaN transistor for multiple VCSELs, and each VCSEL branch is driven and controlled independently. However, this architecture will cause abnormal operation of the VCSEL when the VCSEL branch is not fully charged or discharged. For example, if a certain VCSEL branch is not fully discharged, there will be a voltage across the VCSELs in that VCSEL branch. When the GaN transistor is turned on to conduct another VCSEL branch, it will cause the VCSELs in that VCSEL branch to be mis-triggered. Moreover, if the VCSEL is not fully charged, it will cause the VCSEL to fail to conduct and emit light. Therefore, an embodiment of the present invention provides a charge and discharge detection device to detect the discharge of the VCSEL branch.

[0050] Please refer to Figure 1 , which is a schematic structural diagram of the driving system of the VCSEL provided by the embodiment of the present invention. The driving system includes a GaN transistor, at least two VCSEL branches, and a charge and discharge detection device connected to each VCSEL branch.

[0051] Among them, each VCSEL branch includes a driving module, a capacitor, and a VCSEL. One end of the capacitor is electrically connected to the anodes of the driving module and the VCSEL and the other end is grounded. The driving module is used to control the charging and discharging of the capacitor according to a driving signal. The cathode of the VCSEL in each VCSEL branch is electrically connected to a GaN transistor. The charge and discharge detection device includes a charge detection circuit and a discharge detection circuit, and the charge detection circuit and the discharge detection circuit are electrically connected to the connection node between the driving module and the capacitor in the corresponding VCSEL branch.

[0052] The charge detection circuit is used to detect the charging state of the capacitor according to the voltage of the capacitor and output a first signal when the capacitor in the corresponding VCSEL branch is charging. The first signal is used to indicate whether the capacitor is fully charged. Among them, when the capacitor in the VCSEL branch is fully charged, the VCSEL is in a working state.

[0053] The discharge detection circuit is used to detect the discharging state of the capacitor according to the voltage of the capacitor and output a second signal when the capacitor in the corresponding VCSEL branch is discharging. The second signal is used to indicate whether the capacitor is fully discharged. Among them, when the capacitor in the VCSEL branch is fully discharged, the VCSEL is in a non-working state.

[0054] It can be understood that by using the charge detection circuit and the discharge detection circuit to respectively detect the charging state and the discharging state of the capacitor in the VCSEL branch, it is possible to determine whether the VCSEL is operating abnormally, thereby facilitating the improvement of the stability of the VCSEL operation.

[0055] It can be understood that the structures of the charge and discharge detection devices connected to each VCSEL branch are the same. For the sake of brief description, the charge and discharge detection device connected to one VCSEL branch is taken as an example in the embodiments of the present invention for introduction.

[0056] Please refer to Figure 2 , which is a schematic structural diagram of a charge detection circuit provided by an embodiment of the present invention. The charge detection circuit is electrically connected to the corresponding VCSEL branch, and the VCSEL branch includes a driving module, a capacitor C, and a VCSEL.

[0057] Among them, the driving module in the VCSEL branch includes a high-side switching transistor MH and a low-side switching transistor ML. The control end of the high-side switching transistor MH is used to receive a driving signal HS_ctrl, the first end is electrically connected to a high-voltage power supply VM, the second end is electrically connected to the second end of the low-side switching transistor ML, and the first end of the low-side switching transistor ML is grounded. One end of the capacitor C is electrically connected to the connection node between the high-side switching transistor MH and the low-side switching transistor ML and the anode of the VCSEL, the other end of the capacitor C is grounded, the cathode of the VCSEL is electrically connected to the second end of the GaN transistor, and the first end of the GaN transistor is grounded.

[0058] The high-side switch transistor MH is turned on or off according to the driving signal HS_ctrl. Moreover, when the high-side switch transistor MH is turned on, it charges the capacitor C. When the capacitor C is fully charged, the VCSEL is in the working state. At this time, the GaN transistor is turned on, and a current is generated on the VCSEL, so that the VCSEL is turned on and emits light. When the high-side switch transistor MH is turned off, it discharges the capacitor C. When the capacitor C is fully discharged, the VCSEL is in the non-working state. If the GaN transistor is turned on at this time, no current will be generated on the VCSEL because there is no voltage difference across it, and it will not be turned on and emit light.

[0059] Based on the above circuit structure and working principle of the VCSEL branch, the charging detection circuit provided by the embodiment of the present invention includes a first sampling module, a charging state detection module, and a reset module that are electrically connected in sequence; the first sampling module is electrically connected to the capacitor C in the corresponding VCSEL branch.

[0060] The first sampling module is used to sample the voltage of the capacitor C to obtain a first sampling voltage when the capacitor C in the corresponding VCSEL branch is charging, and transmit it to the charging state detection module. The charging state detection module is used to detect the charging state of the capacitor C according to the first sampling voltage and a preset first voltage threshold, and output a first signal. The reset module is used to generate a reset signal and transmit it to the charging state detection module when the driving signal HS_ctrl flips, so as to reset the charging state detection module.

[0061] Please refer to Figure 3 , which is another schematic structural diagram of the charging detection circuit provided by the embodiment of the present invention. The charging state detection module includes a voltage detection unit, a signal generation unit, and a D flip-flop. The voltage detection unit is electrically connected to the data input terminal of the D flip-flop, and the signal generation unit is electrically connected to the clock input terminal of the D flip-flop.

[0062] The voltage detection unit is used to detect the charging state of the capacitor according to the first sampling voltage and the first voltage threshold, and generate a detection signal and transmit it to the D flip-flop. The signal generation unit is used to generate a clock signal Clk and transmit it to the D flip-flop when the driving signal HS_ctrl flips, so that the D flip-flop outputs a first signal CV_Fail_H.

[0063] Please continue to refer to Figure 3 . Among them, the first sampling module includes a first resistor R1, a second resistor R2, a first switch transistor M1, and a second switch transistor M2. The voltage detection unit includes a first comparator, an RS latch, an OR gate OR, a first inverter INV1, a second inverter INV2, and a first AND gate AND1.

[0064] In the first sampling module, one end of the first resistor R1 is electrically connected to the high-voltage power supply VM, the other end of the first resistor R1 is electrically connected to the first end of the first switching transistor M1, the second end of the first switching transistor M1 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is used to receive the voltage V of the capacitor C. out The control end of the first switching transistor M1 is used to receive the driving signal HS_ctrl.

[0065] The control end of the second switching transistor M2 is used to receive the driving signal HS_ctrl. The second end of the second switching transistor M2 is electrically connected to the second end of the first switching transistor M1 and the inverting input terminal of the first comparator in the voltage detection unit. The first end of the second switching transistor M2 is electrically connected to the floating ground voltage FGND. The floating ground voltage FGND is the reference potential of the high-voltage floating voltage domain, and the voltage difference between VM and FGND is about 5V.

[0066] In the voltage detection unit, the non-inverting input terminal of the first comparator is electrically connected to the first power supply. The first power supply is used to provide the first voltage threshold V thcv The inverting input terminal of the first comparator is electrically connected to the second end of the second switching transistor M2 in the first sampling module. The output terminal of the first comparator is electrically connected to the first input terminal of the OR gate OR. The enable terminal of the first comparator is used to receive the second enable signal EN2.

[0067] The second input terminal of the OR gate OR is used to receive the first enable signal EN1. The output terminal of the OR gate OR is electrically connected to the S terminal of the RS latch. The R terminal of the RS latch is used to receive the second enable signal EN2. The output terminal of the RS latch is electrically connected to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 is electrically connected to the first input terminal of the first AND gate AND1.

[0068] The input terminal of the second inverter INV2 is used to receive the first enable signal EN1. The output terminal of the second inverter INV2 is electrically connected to the second input terminal of the first AND gate AND1. The output terminal of the first AND gate AND1 is electrically connected to the data input terminal of the D flip-flop.

[0069] Please continue to refer to Figure 3 . Among them, the signal generation unit includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a second AND gate AND2.

[0070] The input terminal of the third inverter INV3 is used to receive the trigger signal HS_ctrl_H, which is the inverted signal of the drive signal HS_ctrl. The output terminal of the third inverter INV3 is electrically connected to the input terminal of the fourth inverter INV4 and the first input terminal of the second AND gate AND2. The output terminal of the fourth inverter INV4 is electrically connected to the input terminal of the fifth inverter INV5. The output terminal of the fifth inverter INV5 is electrically connected to the input terminal of the sixth inverter INV6. The output terminal of the sixth inverter INV6 is electrically connected to the second input terminal of the second AND gate AND2. The output terminal of the second AND gate AND2 is electrically connected to the clock input terminal of the D flip-flop.

[0071] Please continue to refer to Figure 3 . Among them, the reset module includes a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, a first delay unit Delay1, and a second delay unit Delay2.

[0072] The input terminal of the seventh inverter INV7 is used to receive the drive signal HS_ctrl. The output terminal of the seventh inverter INV7 is electrically connected to the input terminal of the eighth inverter INV8. The output terminal of the eighth inverter INV8 is electrically connected to the input terminal of the first delay unit Delay1. The output terminal of the first delay unit Delay1 is electrically connected to the input terminal of the ninth inverter INV9 and the input terminal of the second delay module. The output terminal of the second delay unit Delay2 is electrically connected to the input terminal of the tenth inverter INV10. The output terminal of the tenth inverter INV10 is electrically connected to the reset terminal of the D flip-flop.

[0073] Please refer to Figure 4 , which is a schematic structural diagram of a discharge detection circuit provided by an embodiment of the present invention. The discharge detection circuit is electrically connected to the corresponding VCSEL branch, and the circuit structure and working principle of the VCSEL branch have been described in the above embodiments. For the sake of brief description, the circuit structure and working principle of the VCSEL branch can refer to the corresponding content in the above embodiments.

[0074] The discharge detection circuit provided by the embodiment of the present invention includes a second sampling module and a discharge state detection module that are electrically connected. The second sampling module is electrically connected to the capacitor C in the corresponding VCSEL branch.

[0075] The second sampling module is used to sample the voltage of the capacitor C to obtain a second sampling voltage when the capacitor C in the corresponding VCSEL branch discharges, and transmit it to the discharge state detection module. The discharge state detection module is used to detect the charging state of the capacitor C according to the second sampling voltage and a preset second voltage threshold V thrv , and output a second signal.

[0076] Please refer toFigure 5 , which is another structural schematic diagram of the discharge detection circuit provided by the embodiment of the present invention. Among them, the second sampling module includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a third switching transistor M3. The discharge state detection module includes a second comparator, an eleventh inverter, a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a third AND gate AND3, and a third delay unit Delay3.

[0077] In the second sampling module, one end of the third resistor R3 is used to receive the voltage V of the capacitor C out , the other end of the third resistor R3 is electrically connected to the second end of the third switching transistor M3, the control end of the third switching transistor M3 is used to receive the driving signal HS_ctrl, the first end of the third switching transistor M3 is electrically connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is electrically connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded. The connection node of the fourth resistor R4 and the fifth resistor R5 is electrically connected to the non-inverting input terminal of the second comparator in the discharge state detection module.

[0078] In the discharge state detection module, the non-inverting input terminal of the second comparator is electrically connected to the connection node of the fourth resistor R4 and the fifth resistor R5 in the second sampling module, the inverting input terminal of the second comparator is electrically connected to the second power supply, and the second power supply is used to provide a second voltage threshold V thrv , the output terminal of the second comparator is electrically connected to the input terminal of the eleventh inverter, the output terminal of the eleventh inverter is electrically connected to the input terminal of the twelfth inverter INV12, and the output terminal of the twelfth inverter INV12 is electrically connected to the first input terminal of the third AND gate AND3.

[0079] The input terminal of the third delay unit Delay3 is used to receive the driving signal HS_ctrl, the output terminal of the third delay unit Delay3 is electrically connected to the second input terminal of the third AND gate AND3, the output terminal of the third AND gate AND3 is electrically connected to the input terminal of the thirteenth inverter INV13, the output terminal of the thirteenth inverter INV13 is electrically connected to the input terminal of the fourteenth inverter INV14, and the output terminal of the fourteenth inverter INV14 is used to output a second signal RV_Fail_H.

[0080] Please refer to Figure 6 , which is another structural schematic diagram of the discharge detection circuit provided by the embodiment of the present invention. Among them, the discharge state detection module in the discharge detection circuit further includes a fourth delay unit Delay4, the input terminal of the fourth delay unit Delay4 is electrically connected to the output terminal of the third AND gate AND3, and the output terminal of the fourth delay unit Delay4 is electrically connected to the input terminal of the thirteenth inverter INV13.

[0081] Next, it will be combined withFigure 3 The charging detection circuit shown, introduce the working principle of the charging detection circuit.

[0082] For any VCSEL branch in the driving system, when the driving signal HS_ctrl is at a low level, the high-side switch transistor MH conducts to charge the capacitor; when the driving signal HS_ctrl is at a high level, the high-side switch transistor MH turns off to discharge the capacitor. Since one GaN transistor in the driving system is connected to multiple VCSEL branches, and the GaN transistor may detect an object at any time and generate narrow pulses at any time, two situations will occur during the charging process of the VCSEL branch.

[0083] The first situation is that after the capacitor in the VCSEL branch is fully charged, the driving signal HS_ctrl is at a high level, and the GaN transistor outputs a narrow pulse, causing the capacitor to start discharging, as Figure 7 shown. The second situation is that when the driving signal HS_ctrl is at a low level, the capacitor in the VCSEL branch is charging, and the GaN transistor outputs a narrow pulse signal, causing the capacitor to charge and discharge at the same time, as Figure 7 shown. However, due to the maximum frequency limit of discharging, even if the capacitor charges and discharges at the same time, its voltage will continue to rise. Then the voltage of the capacitor may reach above the charging threshold once or multiple times and then discharge. Therefore, in the embodiment of the present invention, it is considered that the driving module can normally charge the capacitor as long as the voltage of the capacitor reaches above the charging threshold once, that is, the capacitor can normally drive the VCSEL to work.

[0084] Please refer to Figure 3 , when the driving signal HS_ctrl is at a low level, the high-side switch transistor MH conducts to charge the capacitor. The first sampling module samples the voltage V out of the capacitor to obtain the first sampling voltage V out_sns1 . When the driving signal HS_ctrl flips to a low level, the first enable signal EN1 is at a low level to reset the data input terminal of the D flip-flop, and the second enable signal EN2 is at a high level to drive the first comparator to be in a working state.

[0085] During the charging process of the capacitor, when the first sampling voltage V out_sns1 reaches the first voltage threshold V thcvWhen this happens, the output signal Comp_out of the first comparator flips to a low level. The output signal Comp_out is transmitted to the S terminal of the RS latch via the OR gate OR. The output signal RS_out of the RS latch is at a high level. The output signal RS_out passes through the first inverter INV1 and transmits a low level to the first input terminal of the first AND gate AND1. The first enable signal EN1 passes through the second inverter INV2 and transmits a low level to the second input terminal of the first AND gate AND1. The first AND gate AND1 transmits a low level to the data input terminal D of the D flip-flop, and the data input terminal D remains at a low level until the second enable signal EN2 flips to a low level. It can be seen that during the process of capacitor charging, the first sampling voltage V out_sns1 As long as it reaches the first voltage threshold V thcv once, the data input terminal D of the D flip-flop will always be at a low level.

[0086] When the drive signal HS_ctrl flips to a high level, the high-side switch transistor MH turns off, the capacitor ends charging, and the third inverter INV3 outputs a rising-edge signal. This rising-edge signal passes through the rising-edge detection unit composed of the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, and the second AND gate AND2, and outputs a high-level narrow pulse signal as the clock signal Clk to detect the signal state of the data input terminal D of the D flip-flop to output the first signal CV_Fail_H.

[0087] When the clock signal Clk arrives and the data input terminal D is at a low level, the first signal CV_Fail_H is at a low level, which indicates that the first sampling voltage V out_sns1 has reached the first voltage threshold V thcv . Then it is considered that the capacitor charging is normal. When the clock signal Clk arrives and the data input terminal D is at a high level, the first signal CV_Fail_H is at a high level, which indicates that the first sampling voltage V out_sns1 has not reached the first voltage threshold V thcv . Then it is considered that the capacitor charging is abnormal.

[0088] When the driving signal HS_ctrl flips to a high level, after the driving signal HS_ctrl passes through the seventh inverter INV7, the eighth inverter INV8, and the first delay unit Delay1 and is delayed for a time t1, such as 100 ns, the output signal of the first delay unit Delay1 is used as the first enable signal EN1, and the output signal of the ninth inverter INV9 is used as the second enable signal EN2, so as to drive the first comparator into a non-operating state and make the RS flip-flop return to its initial state, that is, to make the output signal RS_out of the RS flip-flop be at a low level. Moreover, after the output signal of the first delay unit Delay1 passes through the second delay unit Delay2 and is delayed for a time t2, such as 100 ns, that is, after the driving signal HS_ctrl is delayed for a time t1 + t2, such as 100 ns, the reset signal Reset output by the tenth inverter INV10 flips to a low level to reset the D flip-flop.

[0089] It can be understood that when the driving signal HS_ctrl flips to a high level, by using the first delay unit Delay1 and the second delay unit Delay2 to delay the driving signal HS_ctrl, the states of the first comparator, the RS flip-flop, and the D flip-flop can be reset to facilitate the next detection, and it can also ensure that the first signal CV_Fail_H has a sufficient width for subsequent circuit processing.

[0090] It should be understood that the above first delay parameter t1 and second delay parameter t2 can also be set according to the actual situation, and the embodiments of the present invention are not limited thereto.

[0091] Please refer to Figure 8 (a), which is a schematic diagram of the working waveform of a charging detection circuit provided by an embodiment of the present invention. Under normal capacitor charging conditions, when the driving signal HS_ctrl flips to a low level, the second enable signal EN2 immediately becomes high, the first comparator starts to work to detect the charging state of the capacitor, and the R terminal of the RS flip-flop and the data input terminal D of the D flip-flop are both set to high. During the process of capacitor charging, the first sampling voltage V out_sns1 reaches the first voltage threshold V thcv more than once, and the output signal Comp_out of the first comparator appears at a low level multiple times. When the output signal Comp_out is at a low level for the first time, the output signal RS_out of the RS flip-flop flips to a high level, and the data input terminal D of the D flip-flop also immediately flips from high to low and remains low.

[0092] When the drive signal HS_ctrl flips to a high level, the capacitor finishes charging, and the signal generation unit outputs a high-level narrow pulse clock signal Clk to sample the signal state at the detection data input terminal D. The first signal CV_Fail_H remains at a low level all the time. After the drive signal HS_ctrl flips to a high level and after a delay of t1, when the Clk clock ends, the second enable signal EN2 flips to a low level. After a further delay of t2, the reset signal Reset flips to a low level to reset the D flip-flop.

[0093] Please refer to Figure 8 (b), which is a schematic diagram of the working waveforms of another charge detection circuit provided by an embodiment of the present invention. In the case of abnormal capacitor charging, when the drive signal HS_ctrl flips to a low level, the second enable signal EN2 immediately becomes high, the first comparator starts to work to detect the charging state of the capacitor, and both the R terminal of the RS flip-flop and the data input terminal D of the D flip-flop are set to high level.

[0094] During the process of capacitor charging, the first sampled voltage V out_sns1 never reaches the first voltage threshold V thcv above. The output signal Comp_out of the first comparator remains at a high level, and the data input terminal D of the D flip-flop also remains at a high level. When the drive signal HS_ctrl flips to a high level, the capacitor finishes charging, and the signal generation unit outputs a high-level narrow pulse clock signal Clk to sample the signal state at the detection data input terminal D. The first signal CV_Fail_H flips from a low level to a high level. After the drive signal HS_ctrl flips to a high level and after a delay of t1, when the Clk clock ends, the second enable signal EN2 flips to a low level. After a further delay of t2, the reset signal Reset flips to a low level, and the first signal CV_Fail_H also flips from a high level to a low level to reset the D flip-flop. It can be understood that the width of the first signal CV_Fail_H is determined by the time between the rising edge of the clock Clk and the falling edge of the reset signal Reset.

[0095] Next, the working principle of the discharge detection circuit will be introduced in combination with Figure 6 the described discharge detection circuit. In this embodiment of the present invention, after the capacitor finishes charging and after a certain delay, the voltage of the capacitor is detected to determine whether the capacitor is fully discharged.

[0096] When the drive signal HS_ctrl is at a high level, the high-side switch transistor MH is turned off to discharge the capacitor. The second sampling module samples the voltage V out of the capacitor to obtain the second sampled voltage V out_sns2 .

[0097] During the process of capacitor discharging, when the second sampled voltage Vout_sns2 below the second voltage threshold V thrv When it is, the output signal of the second comparator flips to a low level and is transmitted to the first input terminal of the third AND gate AND3 after passing through the eleventh inverter INV11 and the twelfth inverter INV12. And, after the driving signal HS_ctrl is delayed by a time t3 such as 15 us by the third delay unit Delay3, it is transmitted to the second input terminal of the third AND gate AND3. The output signal of the third AND gate AND3 is delayed by a time t4 such as 1 us by the fourth delay unit Delay4 and then transmitted to the thirteenth inverter INV13 and the fourteenth inverter INV14 to output the second signal RV_Fail_H. Among them, the fourth delay unit Delay4 is a protection mechanism set to prevent false triggering caused by signal switching, which can improve the accuracy of detection.

[0098] If after the driving signal HS_ctrl flips to a high level and passes through a time t3 such as 15 us, the second sampled voltage V out_sns2 drops below the second voltage threshold V thrv then the output signal of the second comparator is at a low level, so the second signal RV_Fail_H is at a low level, and it is considered that the capacitor discharges normally. If after the driving signal HS_ctrl flips to a high level and passes through a time t3 such as 15 us, the second sampled voltage V out_sns2 has not dropped below the second voltage threshold V thrv then the output signal of the second comparator is at a high level, so the second signal RV_Fail_H is at a high level, and it is considered that the capacitor discharge is abnormal.

[0099] It should be understood that the above-mentioned third delay parameter t3 and fourth delay parameter t4 can also be set according to the actual situation, and the implementation of the present invention is not limited.

[0100] The embodiment of the present invention also provides a driving system for a VCSEL, which includes the charge and discharge detection device provided by the embodiment of the present invention.

[0101] The embodiment of the present invention also provides a lidar device, which includes the driving system for a VCSEL provided by the embodiment of the present invention.

[0102] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0103] It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A charge and discharge detection device, characterized in that: A driving system applied to VCSEL, the driving system also includes a GaN tube and at least two VCSEL branches, each VCSEL branch includes a driving module, a capacitor and a VCSEL, one end of the capacitor is electrically connected to the driving module and the anode of the VCSEL and the other end is grounded, the driving module is used to control the charging and discharging of the capacitor according to a driving signal, and the cathode of the VCSEL in each VCSEL branch is electrically connected to the GaN tube; each VCSEL branch is connected to a corresponding charging and discharging detection device, the charging and discharging detection device includes a charging detection circuit and a discharging detection circuit, and the charging detection circuit and the discharging detection circuit are electrically connected to the connection node between the driving module and the capacitor in the corresponding VCSEL branch; The charging detection circuit is used to detect the charging state of the capacitor according to the voltage of the capacitor and output a first signal when the capacitor in the corresponding VCSEL branch is charged, and the first signal is used to indicate whether the capacitor is fully charged; The discharge detection circuit is used to detect the discharge state of the capacitor according to the voltage of the capacitor and output a second signal when the capacitor in the corresponding VCSEL branch is discharged, and the second signal is used to indicate whether the capacitor is completely discharged; When the capacitor in the VCSEL branch is fully charged, the VCSEL is in a working state; when the capacitor in the VCSEL branch is completely discharged, the VCSEL is in a non-working state.

2. The charge and discharge detection device according to claim 1, characterized in that: The charging detection circuit comprises a first sampling module, a charging state detection module and a reset module which are electrically connected in sequence; the first sampling module is electrically connected to the capacitor in the corresponding VCSEL branch; The first sampling module is used to sample the voltage of the capacitor to obtain a first sampling voltage when the capacitor in the corresponding VCSEL branch is charged, and transmit the first sampling voltage to the charging state detection module; The charging state detection module is used to detect the charging state of the capacitor and output a first signal according to the first sampling voltage and a preset first voltage threshold; The reset module is used to generate a reset signal and transmit it to the charging state detection module when the driving signal is reversed, so as to reset the charging state detection module.

3. The charge and discharge detection device according to claim 2, characterized in that: The charging state detection module includes a voltage detection unit, a signal generation unit and a D flip-flop, wherein the voltage detection unit is electrically connected to a data input terminal of the D flip-flop, and the signal generation unit is electrically connected to a clock input terminal of the D flip-flop; The voltage detection unit is used to detect the charging state of the capacitor according to the first sampling voltage and the first voltage threshold, and generate a detection signal to be transmitted to the D trigger; The signal generating unit is used for generating a clock signal and transmitting the clock signal to the D flip-flop when the driving signal is flipped, so that the D flip-flop outputs a first signal.

4. The charge and discharge detection device according to claim 3, characterized in that: The voltage detection unit includes a first comparator, an RS latch, an OR gate, a first inverter, a second inverter and a first AND gate; The non-inverting input terminal of the first comparator is electrically connected to a first power supply, the first power supply is used to provide a first voltage threshold, the inverting input terminal of the first comparator is electrically connected to the first sampling module, the output terminal of the first comparator is electrically connected to the first input terminal of the OR gate, and the enable terminal of the first comparator is used to receive a second enable signal; The second input end of the OR gate is used to receive a first enable signal, the output end of the OR gate is electrically connected to the S end of the RS latch, the R end of the RS latch is used to receive a second enable signal, the output end of the RS latch is electrically connected to the input end of the first inverter, and the output end of the first inverter is electrically connected to the first input end of the first AND gate; The input end of the second inverter is used to receive the first enable signal, the output end of the second inverter is electrically connected to the second input end of the first AND gate, and the output end of the first AND gate is electrically connected to the data input end of the D flip-flop.

5. The charge and discharge detection device according to claim 3, characterized in that: The signal generating unit includes a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a second AND gate; The input end of the third inverter is used to receive a trigger signal, the output end of the third inverter is electrically connected to the input end of the fourth inverter and the first input end of the second AND gate, the output end of the fourth inverter is electrically connected to the input end of the fifth inverter, the output end of the fifth inverter is electrically connected to the input end of the sixth inverter, the output end of the sixth inverter is electrically connected to the second input end of the second AND gate, and the output end of the second AND gate is electrically connected to the clock input end of the D flip-flop.

6. The charge and discharge detection device according to claim 4, characterized in that: The reset module includes a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a first delay unit and a second delay unit; The input end of the seventh inverter is used to receive the driving signal, the output end of the seventh inverter is electrically connected to the input end of the eighth inverter, the output end of the eighth inverter is electrically connected to the input end of the first delay unit, the output end of the first delay unit is electrically connected to the input end of the ninth inverter and the input end of the second delay module, the output end of the second delay unit is electrically connected to the input end of the tenth inverter, and the output end of the tenth inverter is electrically connected to the reset end of the D flip-flop.

7. The charge and discharge detection device according to claim 1, characterized in that: The discharge detection circuit includes a second sampling module and a discharge state detection module that are electrically connected, and the second sampling module is electrically connected to the capacitor in the corresponding VCSEL branch; The second sampling module is used for sampling the voltage of the capacitor to obtain a second sampling voltage when the capacitor in the corresponding VCSEL branch is discharged, and transmitting the second sampling voltage to the discharge state detection module; The discharge state detection module is used to detect the charging state of the capacitor and output a second signal according to the second sampling voltage and a preset second voltage threshold.

8. The charge and discharge detection device according to claim 7, characterized in that: The discharge state detection module includes a second comparator, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a third AND gate and a third delay unit; The non-inverting input terminal of the second comparator is electrically connected to the second sampling module, the inverting input terminal of the second comparator is electrically connected to a second power supply, the second power supply is used to provide a second voltage threshold, the output terminal of the second comparator is electrically connected to the input terminal of the eleventh inverter, the output terminal of the eleventh inverter is electrically connected to the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is electrically connected to the first input terminal of the third AND gate; The input end of the third delay unit is used to receive a driving signal, the output end of the third delay unit is electrically connected to the second input end of the third AND gate, the output end of the third AND gate is electrically connected to the input end of the thirteenth inverter, the output end of the thirteenth inverter is electrically connected to the input end of the fourteenth inverter, and the output end of the fourteenth inverter is used to output the second signal.

9. A VCSEL driving system, characterized in that: It comprises the charge and discharge detection device as described in any one of claims 1 to 8.

10. A laser radar device, characterized in that: A driving system comprising the VCSEL according to claim 9.

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