Pixel circuit substrate, spatial light modulator and display system

Abstract

The invention relates to a pixel circuit substrate, a spatial light modulator and a display system. A pixel circuit substrate includes: a plurality of pixel electrodes; a plurality of active layer regions extending through adjacent pixel electrodes and arranged in a direction crossing an arrangement direction of the plurality of pixel electrodes; a plurality of driving switches formed at the plurality of active layer regions, respectively; a plurality of control lines, each of the plurality of control lines being connected between each control terminal and a corresponding pixel electrode of the plurality of pixel electrodes; a scan line disposed between the plurality of driving switches and the plurality of pixel electrodes and connected to the scan terminal; and a data line disposed between the plurality of driving switches and the plurality of pixel electrodes and connected to the data terminal, in which the scan line bypasses the plurality of control lines and extends between the plurality of driving switches and the plurality of pixel electrodes.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit substrate for a spatial light modulator, a spatial light modulator including the pixel circuit substrate, and a display system including the spatial light modulator. Background Art

[0002] In recent years, in order to achieve high-precision display, a pixel electrode having a fine pixel surface is required. As is well known, as the pixel surface of the pixel electrode is made fine, the channel length of the driving switch of the pixel circuit is shortened, resulting in a decrease in breakdown voltage capability. Patent Document 1 discloses a circuit configuration in which two pixel circuits each having an aspect ratio of 4:1 are respectively distributed on two pixel electrodes.

[0003] [Prior Art Documents]

[0004] Patent Document 1: US Patent Application Publication No. 2007 / 0247695.

[0005] The description provided in this background art section should not be assumed to be prior art merely because it is mentioned in or related to the background art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0006] In the circuit configuration of Patent Document 1, even if the pixel surface of the pixel electrode is made fine, the breakdown voltage capability of the driving switch can be ensured. However, since the width of the pixel circuit in the short-axis direction is shorter than the width of the pixel electrode in the short-axis direction, there is a problem that it is difficult to route the scan line or data line connected to the driving switch.

[0007] One aspect of the present disclosure is to provide a pixel circuit substrate, a spatial light modulator, and a display system that can ensure the breakdown voltage capability of a driving switch while being able to arrange a scan line or a data line connected to the driving switch.

[0008] Other features and aspects of the present disclosure will be set forth in the following description, and will be partly apparent from the description, or may be learned by practice of the present disclosure. These and other aspects of the present disclosure will be realized and attained by the structures specifically pointed out in the written description and its claims, as well as the drawings.

[0009] To achieve these and other aspects and in accordance with the objectives of the present disclosure, as implemented and broadly described herein, a pixel circuit substrate for a spatial light modulator includes: a plurality of pixel electrodes arranged spaced apart from each other and each including a pixel surface defining a pixel of the spatial light modulator; a plurality of active layer regions each extending through adjacent pixel electrodes at a position overlapping the pixel surface and arranged spaced apart from each other in a direction crossing the arrangement direction of the plurality of pixel electrodes; a plurality of driving switches respectively formed at the plurality of active layer regions and each including a scan terminal, a data terminal, and a control terminal; a plurality of control lines each connecting between each control terminal and a corresponding pixel electrode among the plurality of pixel electrodes; and a scan line arranged between the plurality of driving switches and the plurality of pixel electrodes and connected to the scan terminals, wherein the scan line bypasses the plurality of control lines and extends between the plurality of driving switches and the plurality of pixel electrodes.

[0010] In another aspect, a spatial light modulator includes: a pixel circuit substrate; a transparent electrode forming a driving circuit together with the pixel circuit of the pixel circuit substrate; and a light modulation layer provided between the plurality of pixel electrodes and the transparent electrode, and a voltage is applied from the driving circuit to the light modulation layer.

[0011] In another aspect, a display system includes a spatial light modulator.

[0012] It is to be understood that both the above general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is a block diagram exemplifying an example of the configuration of a display system according to an embodiment;

[0015] Figure 2A is an illustration of Figure 1 an example of the arrangement of the spatial light modulator in the configuration of the display system;

[0016] Figure 2B is an illustration of Figure 1 another example of the arrangement of the spatial light modulator in the configuration of the display system;

[0017] Figure 3 is a diagram schematically illustrating an example of the structure of a spatial light modulator according to an embodiment;

[0018] Figure 4Ais a perspective view schematically illustrating an example of a partial structure of a pixel circuit substrate according to an embodiment;

[0019] Figure 4B is schematically illustrated as added to Figure 4A a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0020] Figure 4C is schematically illustrated as added to Figure 4B a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0021] Figure 4D is schematically illustrated as added to Figure 4C a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0022] Figure 4E is schematically illustrated as added to Figure 4D a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0023] Figure 4F is schematically illustrated as added to Figure 4E a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0024] Figure 4G is schematically illustrated as added to Figure 4F a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0025] Figure 4H is schematically illustrated as added to Figure 4G a perspective view of an example of an additional partial structure of a pixel circuit substrate according to an embodiment;

[0026] Figure 4I is a perspective view schematically illustrating an example of the overall structure of a pixel circuit substrate according to an embodiment and an example of an additional partial structure of a pixel circuit substrate according to an embodiment added to Figure 4H ;

[0027] Figure 5 is a schematic plan view of a pixel surface of a pixel electrode in a pixel circuit substrate of Figure 4I viewed along the negative direction of the Z-axis;

[0028] Figure 6A is a perspective view schematically illustrating an example of overall wiring in a pixel circuit substrate of Figure 4I ;

[0029] Figure 6Bis a schematic illustration of Figure 4I a three-dimensional view of an example of the wiring of the n-th driving switch in a pixel circuit substrate;

[0030] Figure 6C is a schematic illustration of Figure 4I a three-dimensional view of an example of the wiring of the (n + 1)-th driving switch in a pixel circuit substrate;

[0031] Figure 6D is a schematic illustration of Figure 4I a three-dimensional view of an example of the wiring of the (n + 2)-th driving switch in a pixel circuit substrate;

[0032] Figure 6E is a schematic illustration of Figure 4I a three-dimensional view of an example of the wiring of the (n + 3)-th driving switch in a pixel circuit substrate;

[0033] Figure 7A is a cross-sectional view example corresponding to Figure 6E along line A-A of Figure 5 ;

[0034] Figure 7B is a modified example of a cross-sectional view along Figure 5 line A-A of

[0035] Figure 8A is a schematic diagram illustrating an example of data lines and scan lines in a part of a pixel circuit of a spatial light modulator according to an embodiment;

[0036] Figure 8B is a schematic diagram illustrating an example of overall wiring in a part of a pixel circuit of a spatial light modulator according to an embodiment;

[0037] Figure 8C is a circuit diagram illustrating an example of a part of a driving circuit of a spatial light modulator according to an embodiment;

[0038] Figure 9A is a schematic diagram illustrating Figure 8A a modified example of

[0039] Figure 9B is a schematic diagram illustrating Figure 8B a modified example of

[0040] Figure 9C is a schematic diagram illustrating Figure 8C a modified example of a circuit diagram of

[0041] Figure 10 is a schematic diagram illustrating Figure 8C another modified example of a circuit diagram of

[0042] Figure 11 is a schematic diagram illustratingFigure 8C Circuit diagram of a modified example of the circuit configuration in the dashed-line region B.

[0043] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their illustrations, may be exaggerated. Detailed Description

[0044] Now, refer in detail to the embodiments of the present disclosure, examples of which may be shown in the drawings. In the following description, when a detailed description of a well-known function or configuration related to this document is determined to unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order described herein and may be changed as known in the art, except for steps and / or operations that need to occur in a specific order. Similar reference numerals refer to similar elements throughout. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0045] The advantages and features of the present disclosure and their implementation methods will be clarified by the example embodiments described below with reference to the drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the example embodiments described herein. On the contrary, these example embodiments are provided so that the present disclosure may be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. Furthermore, the present disclosure is defined only by the scope of the claims.

[0046] The shapes, dimensions, ratios, angles, quantities, etc. shown in the drawings for describing various example embodiments of the present disclosure are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. Unless otherwise specified, throughout the specification, similar reference numerals refer to similar elements.

[0047] In the following description, when a detailed description of a relevant well-known function or configuration may unnecessarily obscure the features or aspects of the present disclosure, such a detailed description of the well-known function or configuration may be omitted or a brief description may be provided.

[0048] When using terms such as "comprising," "having," "including," "formed of," etc., one or more other elements may be added, unless a term such as "only" is used. An element described in the singular is intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise. Any implementation described herein as an "example" need not be construed as being preferred or advantageous compared to other implementations.

[0049] When interpreting an element, even if no explicit description of an error or tolerance range is provided, the element is interpreted as including that error or tolerance range.

[0050] When describing a temporal relationship, when the temporal order is described as, for example, "after", "following", "next", and "before", discontinuous cases may be included unless more restrictive terms such as "only", "immediately", or "directly" are used.

[0051] When describing a positional relationship, for example, when using terms such as "on", "above", "under", "over", "below", "beneath", "near", "adjacent to", or "next to", "beside", "alongside" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately", "directly", or "closely" are used. For example, when a structure is described as being "on", "above", "under", "over", "below", "beneath", "near", "adjacent to", or "next to", "beside", "alongside" another structure, this description should be interpreted as including cases where the structures are in contact with each other and cases where a third structure is disposed or interposed therebetween. In addition, terms such as "left", "right", "top", "bottom", "down", "up", "upper", "lower", etc. refer to an arbitrary reference system.

[0052] Although terms such as "first", "second", "A", "B", "(a)", "(b)", etc. may be used herein to refer to various elements, these elements should not be interpreted as being limited by these terms, as they are not used to define a specific order or precedence. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure.

[0053] The term "at least one" should be understood to include all combinations of one or more of the related elements. For example, "at least one of the first element, the second element, and the third element" may include all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0054] The transistor of the present disclosure may include one of an oxide thin film transistor, an amorphous silicon thin film transistor, and a low-temperature polycrystalline silicon thin film transistor, and the present disclosure is not limited thereto.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and not as having an overly idealized or overly formal meaning, unless expressly so defined herein. For example, the term "component" or "unit" can be applied, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as would be understood by one of ordinary skill in the art.

[0056] The features of the various embodiments of the present disclosure can be partially or fully interconnected or combined. They can be linked and operated in various ways that can be fully understood by those skilled in the art. These embodiments can be executed independently or executed in association with each other in various combinations.

[0057] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are examples and should not be construed as being limited by this specification.

[0058] Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. In the drawings, the same elements or components, and elements or components having the same function are given the same reference numerals or their reference numerals are omitted. In addition, the following embodiments are exemplary, and the content of the present disclosure should not be limited by the description of the embodiments.

[0059] First, with reference to Figure 1 、 Figure 2A and Figure 2B , the display system 1 according to an embodiment is described. In Figure 1 、 Figure 2A and Figure 2B , the flow of the optical signal is drawn by a solid arrow, the flow of the data is drawn by a dashed line, and the flow of the electrical signal is drawn by a double arrow.

[0060] The display system 1 is configured as a high-precision display. In Figure 1 , a configuration example of a holographic display for hologram reproduction, which is an example of a high-precision display, is illustrated, but the present disclosure is not limited thereto.

[0061] The display system 1 is equipped with a computing system 2. The computing system 2 acquires an image or the like to be reproduced as a hologram of a three-dimensional (3D) model and calculates the hologram through a hologram generation algorithm. The computing system 2 is configured as a computer device or a microcomputer.

[0062] The method for the computing system 2 to acquire the image to be reproduced as a hologram is not particularly limited. For example, the image to be reproduced as a hologram by the computing system 2 can be acquired by being connected to an external device capable of reproducing the image (such as an imaging device like a camera or an image device like a television receiver) either wiredly or wirelessly. Additionally, the image to be reproduced as a hologram by the computing system 2 can be acquired by reading a removable medium storing the image (such as a USB memory).

[0063] Furthermore, the hologram generation algorithm can be selected from any algorithm according to the purpose or use of hologram reproduction and is not restricted. However, for example, it can be a wavefront recording method or a random phase-free method.

[0064] The display system 1 is equipped with a control system 3. The control system 3 receives the hologram calculated in the computing system 2 as an image signal and outputs a control signal based on the image signal.

[0065] The control system 3 is configured as a computer device or a microcomputer, dedicated hardware, or a combination thereof. When the control system 3 is configured as a computer device or a microcomputer, the control system 3 can be configured in the same computer device or microcomputer as the computing system 2, or can be configured in a computer device or microcomputer separate from the computing system 2.

[0066] When the control system 3 is a computer device or a microcomputer, the control system 3 includes a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the control system 3 includes a CPU or an MPU, each function executed by the control system 3 is implemented by software, firmware, or a combination of both software and firmware. The software or firmware is described as a program in a programming language. The program is stored in the internal memory of the control system 3, and the program stored in the internal memory is read and executed by the CPU or MPU. Each function in the control system 3 is implemented by the CPU or MPU reading and executing the program stored in the internal memory. The internal memory is, for example, a non-volatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM.

[0067] If the control system 3 is dedicated hardware, the control processing in the control system 3 is implemented by, for example, a single circuit, a composite circuit, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a circuit combining these. Each function to be implemented by the control system 3 can be implemented by separate hardware, or all functions can be implemented by a single hardware.

[0068] In addition, when the computing system 2 or the control system 3 is a computer device, the type of the computer device is not particularly limited. The computer device may be, for example, a virtual server providing cloud services, or a physical server providing various services to a group within a local network. In addition, the computer device may be a quantum computer, a general-purpose desktop computer or a laptop computer, or a portable terminal such as a tablet terminal or a smart phone. In addition, the computing system 2 or the control system 3 may be designed to perform distributed processing using multiple computer devices.

[0069] The display system 1 includes a light source 5, a beam expander 7, a projection optical system 9, and a spatial light modulator 10. The operations of the light source 5 and the spatial light modulator 10 are controlled by control signals received from the control system 3.

[0070] The light source 5 irradiates a light beam toward the spatial light modulator 10 based on the control signal received from the control system 3. As the light source 5, a coherent light source having a coherent length according to the purpose or use of hologram reproduction is used. Although not limited to a coherent light source, a solid-state light source including a light-emitting diode is used, and for example, a laser light source including a laser diode or an SLD (superluminescent diode) light source including a superluminescent diode can be used.

[0071] The beam expander 7 expands the light beam irradiated from the light source 5 and guides it to the entire light modulation region of the spatial light modulator 10. The beam expander 7 is disposed on the light propagation path between the light source 5 and the spatial light modulator 10. The beam expander 7 is selected from any optical element according to the purpose or use of hologram reproduction. For example, the beam expander 7 may be, but is not limited to, a Galilean transmission type beam expander including a concave lens and a convex lens, a Kepler transmission type beam expander including two convex lenses, or a reflective expander including a curved mirror. In addition, the concave lens and the convex lens in the transmission type beam expander may be diffractive optical elements having the same refractive characteristics. In addition, the curved mirror in the reflective expander may be a diffractive optical element having the same reflection characteristics.

[0072] The spatial light modulator 10 is an optical device that modulates the spatial distribution (such as amplitude, phase, or propagation direction) of the light from the light source 5. The spatial light modulator 10 has a light modulation region formed therein. The optical characteristics such as reflection or refraction in the light modulation region of the spatial light modulator 10 are electrically controlled by a control signal from the control system 3. By the control signal from the control system 3, parameters such as amplitude, phase, or propagation direction of the light beam irradiated from the light source 5 and expanded in the beam expander 7 are modulated in the light modulation region of the spatial light modulator 10. The detailed structure of the spatial light modulator 10 will be described later.

[0073] The projection optical system 9 processes the light beam modulated in the spatial light modulator 10 at the position where the user wants to view, and reproduces a stereoscopic image such as a three-dimensional hologram. The projection optical system 9 can be formed by, but not limited to, combining lenses, mirrors, and diffractive optical elements having optical characteristics equivalent to those of the lenses and mirrors.

[0074] Although not shown, when the spatial light modulator 10 modulates the amplitude of the incident light, the display system 1 is provided with a polarization separation element that separates the light beam into two light beams in the light propagation path between the spatial light modulator 10 and a viewer such as a stereoscopic image viewer. The polarization separation element is an optical element that adjusts the ratio of vertical polarization and horizontal polarization by separating the polarization planes. Here, it has a function of controlling the intensity of light according to the polarization state of the input light. The polarization separation element can be, for example but not limited to, a polarizing plate or a polarization beam splitter (PBS). Depending on the polarization characteristics of the light source 5, the polarization separation element can be further arranged in the light propagation path between the light source 5 and the spatial light modulator 10. In addition, when the spatial light modulator 10 does not modulate the amplitude of the incident light, the polarization separation element can be omitted.

[0075] In addition, when the light source 5 is a coherent light source, the display system 1 can be equipped with a speckle noise suppression module 5a. Speckle noise may appear in light with high coherence such as a light beam irradiated from a coherent light source, and is noise that appears when multiple waves overlap and interfere with each other in a complex manner.

[0076] The speckle noise suppression module 5a can be formed as, but not limited to, a high-frequency superposition circuit that performs frequency modulation on the power (e.g., drive current) of the light source 5. The speckle noise suppression module 5a is electrically controlled by a control signal from the control system 3. The speckle noise suppression module 5a can desirably reduce the coherence of the light beam irradiated from the light source 5 by performing frequency modulation on the power of the light source 5, thereby reducing speckle noise.

[0077] In addition, the speckle noise suppression module 5a can be formed separately from the light source 5, or can be built into the light source 5.

[0078] In addition, when the light source 5 is a coherent light source, the display system 1 can be equipped with a speckle noise suppression mechanism 5b on the light output side of the light source 5. The speckle noise suppression mechanism 5b is formed by (e.g., but not limited to) a rotatable diffuser plate, such that the rotation of the diffuser plate is electrically controlled by a control signal from the control system 3. The speckle noise suppression mechanism 5b can desirably reduce the coherence of the light beam irradiated from the light source 5 by the rotation of the diffuser plate, thereby reducing speckle noise.

[0079] In addition, the speckle noise suppression mechanism 5b can be formed separately from the light source 5, or can be built into the light source 5.

[0080] In addition, when a coherent light source is not used or speckle noise does not need to be considered, the speckle noise suppression module 5a and the speckle noise suppression mechanism 5b can be omitted, but not limited thereto.

[0081] In addition, the display system 1 can have an optical isolator 5c on the output side of the light source 5. The optical isolator 5c suppresses the light beam irradiated from the light source 5 from returning to the light source 5 by reflection. By forming the optical isolator 5c on the output side of the light source 5, fluctuations in the output of the light source 5 can be suppressed, so that the stability of the light source 5 or the entire display system 1 can be improved. In addition, by forming the optical isolator 5c on the output side of the light source 5, optical damage to the light source 5 can be prevented or reduced.

[0082] In addition, the optical isolator 5c can be formed separately from the light source 5 or can be built into the light source 5. In addition, when the optical isolator 5c is formed on the output side of the light source 5, no optical components may be placed between the light source 5 and the optical isolator 5c in order to prevent or reduce reflection between the light source 5 and the optical isolator 5c. In addition, when the beam reflection of the light irradiated from the light source 5 does not need to be considered, the optical isolator 5c can be omitted, but not limited thereto.

[0083] In addition, according to the quality of the light beam irradiated from the light source 5, for example, the in-plane uniformity or parallelism of the intensity, the display system 1 is preferably equipped with a beam shaping element 5d on the output side of the light source 5. The beam shaping element 5d can be, for example but not limited to, a spatial filter including a lens and a ball. By forming the beam shaping element 5d on the output side of the light source 5, a light beam with reduced parallelism due to interference with optical components can be shaped, so that a light beam with high parallelism can be incident on the spatial light modulator 10.

[0084] Therefore, the beam shaping element 5d is preferably arranged on the upstream side of the beam expander 7 in the light propagation path between the light source 5 and the spatial light modulator 10. In addition, no optical components may be arranged between the beam expander 7 and the beam shaping element 5d. Through the above arrangement, the light beam with high parallelism formed by the beam shaping element 5d can be expanded by the beam expander 7, and the expanded light beam with high parallelism can be incident on the light modulation region of the spatial light modulator 10.

[0085] In addition, an optical device having the same function as the spatial light modulator 10 can be used to replace the beam shaping element 5d. In this case, the optical device having the same function as the spatial light modulator 10 can electrically control the quality of the light beam through a control signal from the control system 3.

[0086] In addition, although not limited thereto, when the quality of the light beam irradiated from the light source 5 is not deteriorated, for example, the parallelism is not deteriorated, the beam shaping element 5d can be omitted.

[0087] In Figure 2A and Figure 2B examples of the arrangement of the spatial light modulator 10 for realizing full-color hologram reproduction in the display system 1 are illustrated. Further, Figure 2A and Figure 2B the examples of the arrangement are merely examples, and the arrangement of the spatial light modulator 10 is not limited to any one of Figure 2A and Figure 2B The arrangement of the spatial light modulator 10 for realizing full-color hologram reproduction can be arbitrarily selected according to the purpose or use of the hologram reproduction.

[0088] Figure 2A and Figure 2B Each of the display systems 1 in

[0089] Figure 2A is equipped with an optical multiplexing system 8. The optical multiplexing system 8 combines a plurality of light beams having different wavelengths into a single light beam. The optical multiplexing system 8 is formed as, for example but not limited to, a filter type, a prism type, a grating type, or a waveguide type optical multiplexer. The optical multiplexing system 8 can be formed as a waveguide type optical multiplexer.

[0089] Figure 2A is an example in which the spatial light modulator 10 is arranged for each of the red light source 5-1, the green light source 5-2, and the blue light source 5-3 arranged as the light source 5 of the display system 1. In the structural example of Figure 2A the red light beam, the green light beam, and the blue light beam modulated by the respective spatial light modulators 10 are combined by the optical multiplexing system 8 and then transmitted as a single light beam to the projection optical system 9.

[0090] Further, Figure 2B is an example in which a single spatial light modulator 10 is arranged for the red light source 5-1, the green light source 5-2, and the blue light source 5-3. In the structural example of Figure 2B the red light beam, the green light beam, and the blue light beam irradiated from the red light source 5-1, the green light source 5-2, and the blue light source 5-3, respectively, are combined by the optical multiplexing system 8, and the combined single light beam is incident on the spatial light modulator 10. Thereafter, the single light beam modulated by the spatial light modulator 10 is transmitted to the projection optical system 9.

[0091] In the arrangement example of Figure 2A since the red light beam, the green light beam, and the blue light beam can be simultaneously modulated by the separate spatial light modulators 10, the image can be updated at a high frequency. Therefore, in the structural example of Figure 2A the video characteristics in hologram reproduction can be improved.

[0092] In addition, in Figure 2A the arrangement example of Figure 2B , since a spatial light modulator 10 is arranged for each of the red light source 5-1, the green light source 5-2, and the blue light source 5-3, the number of optical components of the display system 1 increases compared to the arrangement example of Figure 2A . In addition, since the modulated light beams are transmitted from the respective spatial light modulators 10 to the optical multiplexing system 8, there is a case where it becomes difficult to adjust the positions of the spatial light modulators 10. Therefore, in the configuration example of

[0093] In Figure 2B the arrangement example of

[0094] In addition, in Figure 2B the arrangement example of Figure 2A , since the combined single light beam is modulated by a single spatial light modulator 10, the configuration of the display system 1 can be simplified.

[0095] In addition, in the arrangement example of

[0096] , since the turning on and off of each of the red light source 5-1, the green light source 5-2, and the blue light source 5-3 are sequentially performed, full-color hologram reproduction is achieved. Therefore, in order to improve the video characteristics in hologram reproduction, it is necessary to drive each color light source 5 at a high frequency. Therefore, compared to the arrangement example of

[0097] In addition, when full-color hologram reproduction is realized in the display system 1, the light source 5 and the spatial light modulator 10 need to be synchronized with each other because the hologram varies according to the wavelength of light. The synchronization of the light source 5 and the spatial light modulator 10 can be performed by the control system 3, or can be performed by a control mechanism such as a separate electronic circuit for synchronization purposes.

[0098] The display system 1 for realizing hologram reproduction has been described above, but the display system 1 can be used for purposes other than hologram reproduction. For example, by reducing the coherence of the light beam in the entire display system 1 as compared with the display system 1 for hologram reproduction, the display system 1 can be a high-precision display system that projects the display content of the spatial light modulator 10 onto the projection optical system 9.

[0099] Hereinafter, reference will be made to Figure 3 describe the spatial light modulator 10 according to an embodiment.

[0100] The spatial light modulator 10 includes a cover glass 20. The cover glass 20 forms the appearance surface (or outer surface) of the spatial light modulator 10 and defines the light input surface of the light modulation region of the spatial light modulator 10. The material of the cover glass 20 is preferably used in a display. For example, the material of the cover glass 20 can be, but is not limited to, sapphire glass, quartz glass, or alkali-free glass.

[0101] In addition, depending on the purpose or use of the spatial light modulator 10, an antireflection film can be formed on the appearance surface (or outer surface) of the cover glass 20. By forming an antireflection film on the cover glass 20, the reflection of light incident on the surface of the cover glass 20 is suppressed, so that the modulation efficiency in the spatial light modulator 10 can be improved.

[0102] In addition, materials for the antireflection film can be used, for example, SiO2, MgF2, TiO2, Ta2O5, ZrO2, or Nb2O5, but are not limited thereto. In addition, a multilayer antireflection film can be formed on the appearance surface of the cover glass 20 by coating an organic resist such as an alkylsulfonic acid on the appearance surface of the cover glass 20 and then depositing magnesium fluoride or the like.

[0103] The spatial light modulator 10 includes a light modulation layer 30. The light modulation layer 30 is formed of, for example, liquid crystal, which is a conductive material having both the fluidity of a liquid and the anisotropy of a liquid crystal. By forming the light modulation layer 30 of liquid crystal, the anisotropy of the liquid crystal molecules 30a can be changed according to the magnitude of the applied voltage, so that optical characteristics such as reflection or refraction in the light modulation layer 30 can be modulated.

[0104] The light modulation layer 30 can use any liquid crystal material depending on the purpose or use of the spatial light modulator 10. The light modulation layer 30 uses, for example but not limited to, ferroelectric liquid crystal or nematic liquid crystal. Ferroelectric liquid crystal can be used as the light modulation layer 30. Ferroelectric liquid crystal has liquid crystal molecules 30a that can spontaneously polarize, and can prevent or reduce interference between adjacent pixels of the spatial light modulator 10 due to an electric field as compared with nematic liquid crystal.

[0105] The spatial light modulator 10 includes an alignment layer 40. The alignment layer 40 is arranged to be in contact with two side surfaces of the light modulation layer 30 (for example, the surface of the light modulation layer 30 on the cover glass 20 side and the opposite surface). The alignment layer 40 is formed of an insulator. The alignment layer 40 is formed of an organic material such as (but not limited to) polyimide or an inorganic material such as SiO2 (silicon dioxide).

[0106] The surface of the alignment layer 40 can be adjusted by a manipulation such as rubbing to adjust the alignment state of the liquid crystal molecules 30a in the light modulation layer 30. Additionally, the alignment direction of the liquid crystal molecules 30a provided by the alignment layer 40 arranged on one side of the light modulation layer 30 can be parallel to the alignment direction of the liquid crystal molecules 30a provided by the alignment layer 40 arranged on the opposite side, or can be in a twisted position with respect to the alignment direction of the liquid crystal molecules 30a provided by the alignment layer 40 arranged on the opposite side.

[0107] The spatial light modulator 10 includes a transparent electrode 50 and a pixel circuit substrate 100.

[0108] The transparent electrode 50 is arranged between the cover glass 20 and the alignment layer 40 on the cover glass side of the light modulation layer 30. The transparent electrode 50 and the pixel circuit 150 of the pixel circuit substrate 100 together form a driving circuit 200 in the spatial light modulator 10.

[0109] The transparent electrode 50 is formed as a conductive film capable of transmitting light. The transparent electrode 50 is formed of (but not limited to) ITO such as indium tin oxide (ITO) with refractive index matching (IMITO), tin oxide, a magnesium - silver alloy, or a polythiophene - based conductive polymer using PEDOT (poly(3,4 - ethylenedioxythiophene)).

[0110] The pixel circuit substrate 100 includes a substrate 60 and a pixel circuit 150 formed on the substrate 60. The pixel circuit 150 includes a driving switch circuit 70, a plurality of pixel electrodes 90, and a plurality of control lines 80 respectively connecting the plurality of driving switch circuits 70 and the plurality of pixel electrodes 90.

[0111] The pixel circuit substrate 100 is arranged such that the plurality of pixel electrodes 90 face the transparent electrode 50, and the light modulation layer 30 and the alignment layer 40 are provided on both sides of the light modulation layer 30 interposed between the plurality of pixel electrodes 90 and the transparent electrode 50. For example, in the spatial light modulator 10, the light modulation layer 30 is provided between the plurality of pixel electrodes 90 and the transparent electrode 50.

[0112] In the spatial light modulator 10, since the light modulation layer 30 is provided between the plurality of pixel electrodes 90 and the transparent electrode 50, a voltage is applied to the light modulation layer 30 from the driving circuit 200, and the optical characteristics of the light modulation layer 30 can be modulated by electrical control of the voltage. For example, but not limited to, in the case where the light modulation layer 30 is formed of ferroelectric liquid crystal, when the spatial light modulator 10 operates, half (VDD / 2) of the operating voltage (VDD) applied to the driving switch circuit 70 is constantly applied to the transparent electrode 50. In addition, by switching the driving switch circuit 70, a voltage the same as the operating voltage (VDD) or a reference voltage (GND) is applied to the pixel electrode 90, thereby modulating the optical characteristics of the light modulation layer 30.

[0113] Furthermore, the spatial light modulator 10 may modulate only a portion of the spatial distribution of light, such as amplitude, phase, propagation direction, intensity, and polarization plane. For example, the spatial light modulator 10 may be a spatial light phase modulator that modulates only the phase of light.

[0114] Furthermore, the light output type of the spatial light modulator 10 may be arbitrarily selected according to the purpose or use of the spatial light modulator 10, and may be a transmission type or a reflection type.

[0115] In addition, in the case where the light output type of the spatial light modulator 10 is a reflective type, a reflection enhancement layer formed of aluminum or the like may be placed between the alignment layer 40 disposed on the side opposite to the cover glass side of the light modulation layer 30 and the pixel electrode 90. By forming the reflection enhancement layer, the modulation efficiency of the spatial light modulator 10 can be improved. In addition, the reflection enhancement layer may be a reflection enhancement layer that has been subjected to a passivation treatment (such as oxide film formation). By performing a passivation treatment on the reflection enhancement layer, corrosion of the reflection enhancement layer can be prevented or reduced.

[0116] In addition, the spatial light modulator 10 of the present disclosure may be used for purposes other than hologram reconstruction. For example, the spatial light modulator 10 may be used for a 3D printer or a laser processing beam, but is not limited thereto.

[0117] In the following, reference is made to Figures 4A to 4I The pixel circuit substrate 100 according to the embodiment is described. For example, the pixel circuit substrate 100 may be manufactured by using a 3D printer or the like in at least some processes.

[0118] also, Figures 4A to 4I In order to facilitate the understanding of the structure of the pixel circuit substrate 100, Figures 4A to 4I Add and explain each component in the appropriate order, but Figures 4A to 4I The manufacturing sequence of the pixel circuit substrate 100 is not disclosed. In addition, although the gaps between the components of the pixel circuit substrate 100 are filled with insulating materials (79, seeFigures 6A to 6E ), but for the purpose of clarifying the internal structure, the insulating material 79 is not shown. Additionally, in the drawings illustrating the pixel circuit substrate 100 including Figures 4A to 4I , there are portions where boundary lines are illustrated even within the same component, but this does not necessarily mean the existence of boundaries. Furthermore, in the following drawings, for ease of explanation, the X, Y, and Z axes are described, and the pixel circuit substrate 100 is located at a position where all of X, Y, and Z are positive (e.g., the first quadrant with respect to the XY plane), but this does not limit the actual arrangement of the pixel circuit substrate 100 in the spatial light modulator 10. Figures 4A to 4I As

[0119] shown, the substrate 60 includes a plurality of active layer regions 65 extending in one direction. The plurality of active layer regions 65 are arranged with gaps between each other in a direction crossing the extending direction of the active layer regions 65. At the ends of the active layer regions 65 in the extending direction of the active layer regions 65, doping regions 65-1 doped with impurities such as boron or phosphorus are formed according to the purpose or use of the pixel circuit substrate 100. Figure 4A The active layer regions 65 can be formed of single crystal materials. By forming the active layer regions 65 of single crystal materials, active layer regions 65 with higher purity and regular atomic arrangements compared to polycrystalline materials can be formed, thereby reducing the resistance value and reducing the error of electrical characteristics including the resistance value of the active layer regions 65. Additionally, by forming the active layer regions 65 of single crystal materials, active layer regions 65 with regular atomic arrangements compared to polycrystalline materials can be formed, thereby improving the mobility of electrons or holes in the active layer regions 65.

[0120] Furthermore, the active layer regions 65 can also be formed of single crystal materials selected from the group including Si, SiC, GaN, and Ga2O3. By forming the active layer regions 65 of the above single crystal materials, the power conversion efficiency in the pixel circuit 150 can be improved while the breakdown voltage capability is increased.

[0121] On the outer periphery of each active layer region 65, a trench insulating portion 65a is formed. The material of the trench insulating portion 65a can be selected from any material according to the purpose or use of the pixel circuit substrate 100 and used, for example but not limited to, insulators such as SiO2. For example, the trench insulating portion 65a is formed by a shallow trench isolation (STI) method. Additionally, the trench insulating portion 65a can be formed by other methods according to the purpose or use of the pixel circuit substrate 100, but a method that can achieve making the active layer regions 65 fine can be adopted. Furthermore, the trench insulating portion 65a can adopt an insulating structure other than the trench type as long as adjacent active layer regions 65 can be electrically insulated.

[0122]

[0123] ​In addition, in Figure 4A , a plurality of active layer regions 65 are aligned at intervals in a direction (e.g., the positive direction of the Y-axis) orthogonal to the extending direction of the active layer regions 65 (e.g., the positive direction of the X-axis), but are not limited thereto. For example, the plurality of active layer regions 65 may be arranged diagonally such that a line connecting the centers of each active layer region 65 forms an angle with the positive direction of the Y-axis.

[0124] In addition, in Figure 4A , the shape of the active layer region 65 is a rectangular shape with a large aspect ratio, but any shape can be selected according to the purpose or use of the pixel circuit substrate 100. For example, the shape of the active layer region 65 may be oval.

[0125] As Figures 4B to 4D shown, the pixel circuit substrate 100 includes an insulating layer 71. The insulating layer 71 is disposed in the central portion of each active layer region 65 and extends along the extending direction of the active layer region 65 (e.g., the positive direction of the X-axis). As the material of the insulating layer 71, any material can be selected according to the purpose or use of the pixel circuit substrate 100. The insulating layer 71 uses, for example but not limited to, an insulator such as SiO2 or SiOxNy (silicon oxynitride).

[0126] In addition, as Figure 4D shown, the pixel circuit substrate 100 includes a scan terminal 72. The scan terminal 72 is disposed such that the insulating layer 71 is between each active layer region 65 and the scan terminal 72. The scan terminal 72 extends in the same direction as the insulating layer 71 and covers the insulating layer 71. The scan terminal 72 forms one of the two input terminals of the driving switch circuit 70.

[0127] In addition, as Figure 4B shown, the pixel circuit substrate 100 includes a data terminal 73 and a control terminal 81. The data terminal 73 and the control terminal 81 are disposed at the corresponding doped regions 65-1 of each active layer region 65. The data terminal 73 forms the other of the two input terminals of the driving switch circuit 70. The control terminal 81 forms the output terminal of the driving switch circuit 70.

[0128] The materials of the scan terminal 72, the data terminal 73, and the control terminal 81 can be selected from any materials according to the purpose or use of the pixel circuit substrate 100, and use, for example but not limited to, a conductor such as aluminum or copper. In addition, in the following description, if the components of the pixel circuit substrate 100 are formed of a conductor, the same material is selected unless otherwise specified.

[0129] Each active layer region 65 and the insulating layer 71, the scan terminal 72, the data terminal 73, and the control terminal 81 provided on each active layer region 65 form each of a plurality of driving switch Trs.

[0130] In addition, in the following description, as Figure 4B shown, the n-th driving switch Trn is referred to as the driving switch Tr closest to the X-axis in the first quadrant of the XYZ plane. In addition, the (n + 1)-th driving switch Trn+1 is referred to as the driving switch Tr closest to the n-th driving switch Trn. In addition, the (n + 2)-th driving switch Trn+2 is referred to as the driving switch Tr closest to the (n + 1)-th driving switch Trn+1. In addition, the (n + 3)-th driving switch Trn+3 is referred to as the driving switch Tr closest to the (n + 2)-th driving switch Trn+2. In addition, when it is not necessary to particularly distinguish the n-th driving switch Trn, the (n + 1)-th driving switch Trn+1, the (n + 2)-th driving switch Trn+2, and the (n + 3)-th driving switch Trn+3, they are collectively referred to as the driving switch Tr.

[0131] The driving switch Tr can be formed as any electronic component according to the purpose or use of the pixel circuit substrate 100, for example, formed as a transistor. For example, the driving switch Tr is preferably formed as a field effect transistor (FET) such as a MOSFET. By forming the driving switch Tr as a MOSFET, the driving switch circuit 70 can be formed by a CMOS circuit capable of performing high-speed switching operations.

[0132] In addition, in the case where the driving switch Tr is formed as a MOSFET, the MOSFET can be an n-type MOSFET or a p-type MOSFET. In addition, the MOSFET can be enhancement type or depletion type. In addition, in Figures 4B to 4D it, an insulating layer 71 is disposed on the upper surface of the active layer region 65, and the driving switch Tr is formed to be similar to a planar MOSFET, but is not limited thereto, and a trench MOSFET in which the insulating layer 71 is buried in the active layer region 65 can be formed.

[0133] In addition, in the case where the driving switch Tr is formed as a transistor, the scanning terminal 72 is sometimes referred to as a gate terminal or a base terminal. In addition, the data terminal 73 and the control terminal 81 are sometimes referred to as a source terminal and a drain terminal, or a collector terminal and an emitter terminal.

[0134] As Figure 4BAs shown, the data terminals 73 of the n-th driving switch Trn and the (n + 1)-th driving switch Trn+1 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65 (e.g., the positive direction of the Y-axis). In addition, the data terminals 73 of the (n + 2)-th driving switch Trn+2 and the (n + 3)-th driving switch Trn+3 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65, and this column is different from the column of the data terminal 73 of the n-th driving switch Trn. Further, the control terminals 81 of the n-th driving switch Trn and the (n + 1)-th driving switch Trn+1 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65, and this column is different from the two columns of the above data terminals 73. In addition, the control terminals 81 of the (n + 2)-th driving switch Trn+2 and the (n + 3)-th driving switch Trn+3 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65, and this column is different from the two columns of the above data terminals 73 and the column of the control terminal 81 of the above n-th driving switch Trn.

[0135] As will be described later with reference to Figure 8A the accompanying drawings, Figure 4B the arrangement examples of the data terminal 73 and the control terminal 81 described in

[0136] are only preferred examples, but are not limited thereto. The data terminal 73 and the control terminal 81 can be placed in any doping region 65-1 on each active layer region 65 according to the purpose or use of the pixel circuit substrate 100. Figure 4C

[0137] As shown, the pixel circuit substrate 100 includes an n-th data line DLn and an (n + 1)-th data line DLn+1. The n-th data line DLn is connected to the data terminals 73 of the n-th driving switch Trn and the (n + 1)-th driving switch Trn+1. The (n + 1)-th data line DLn+1 is connected to the data terminals 73 of the (n + 2)-th driving switch Trn+2 and the (n + 3)-th driving switch Trn+3. The n-th data line DLn and the (n + 1)-th data line DLn+1 extend through the corresponding active layer region 65 along the arrangement direction of the corresponding active layer region 65 (e.g., the positive direction of the Y-axis). In the following description, when it is not necessary to particularly distinguish them, the n-th data line DLn and the (n + 1)-th data line DLn+1 are collectively referred to as the data line 74. The n-th data line DLn and the (n + 1)-th data line DLn+1 are formed of a conductor. In addition, in Figure 4CIn this case, the data line 74 is formed separately from the data terminal 73, but they may be integrally formed. The cross-section of the data line 74 may be selected to have any shape according to the purpose or use of the pixel circuit substrate 100. For example, it may be rectangular or circular, but is not limited thereto. In addition, for the purpose of reducing the resistance and capacitance of the data line 74, a dummy line may be formed in a layer different from the data line 74 in parallel with the data line 74, and a part of the dummy line is in contact with the data line 74.

[0138] In addition, the term "line" in the data line (74) does not limit the thickness or diameter of the data line 74. The thickness or diameter of the data line 74 may be any value according to the purpose or use of the pixel circuit substrate 100.

[0139] As Figure 4D shown, the pixel circuit substrate 100 includes scan terminal lines 75. Each scan terminal line 75 is connected to each scan terminal 72. Each scan terminal line 75 extends from the scan terminal 72 in a direction away from the active layer region 65 (e.g., in the positive direction of the Z axis). The scan terminal line 75 is formed of a conductor.

[0140] The scan terminal lines 75 of the nth driving switch Trn and the (n + 2)th driving switch Trn+2 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65 (e.g., the positive direction of the Y axis). The scan terminal lines 75 of the (n + 1)th driving switch Trn+1 and the (n + 3)th driving switch Trn+3 are arranged in substantially the same column along the arrangement direction of the corresponding active layer region 65 (e.g., the positive direction of the Y axis), and this column is different from the column of the data terminal 73 of the nth driving switch Trn.

[0141] Figure 4D The arrangement example of the scan terminal line 75 described in this case is only a preferred example, but is not limited thereto. The scan terminal line 75 may be arranged at any position according to the purpose or use of the pixel circuit substrate 100. For example, by extending the scan terminal 72, the scan terminal line 75 may be formed outside the active layer region 65.

[0142] In addition, in Figure 4D this case, the scan terminal line 75 is formed separately from the scan terminal 72, but they may be integrally formed. The cross-section of the scan terminal line 75 may have any shape according to the purpose or use of the pixel circuit substrate 100, and may have, for example but not limited to, a rectangular shape or a circular shape.

[0143] In addition, the term "line" in the scan terminal line 75 does not limit the thickness or diameter of the scan terminal line 75. The thickness or diameter of the scan terminal line 75 may be any value according to the purpose or use of the pixel circuit substrate 100. As Figure 4EAs shown, the pixel circuit substrate 100 includes the n-th scan line GLn and the (n + 1)-th scan line GLn+1. The n-th scan line GLn is connected to the scan terminal lines 75 of the n-th driving switch Trn and the (n + 2)-th driving switch Trn+2. The (n + 1)-th scan line GLn+1 is connected to the scan terminal lines 75 of the (n + 1)-th driving switch Trn+1 and the (n + 3)-th driving switch Trn+3. In the following description, if there is no need to specifically distinguish between them, the n-th scan line GLn and the (n + 1)-th scan line GLn+1 are collectively referred to as the scan line 76. The scan line 76 is formed of a conductor.

[0144] The scan line 76 includes a wiring segment 76a that extends along the arrangement direction of the active layer regions 65 (e.g., the positive direction of the Y-axis), passing through adjacent active layer regions 65. The wiring segment 76a of the n-th scan line GLn is connected to the scan terminal lines 75 of the n-th driving switch Trn and the (n + 2)-th driving switch Trn+2. The wiring segment 76a of the (n + 1)-th scan line GLn+1 is connected to the scan terminal lines 75 of the (n + 1)-th driving switch Trn+1 and the (n + 3)-th driving switch Trn+3.

[0145] One side portion of the remaining wiring of the n-th scan line GLn starts from the point where the wiring segment 76a is connected to the scan terminal line 75 of the n-th driving switch Trn and extends along the active layer region 65 of the n-th driving switch Trn. Additionally, one side portion of the remaining wiring of the n-th scan line GLn extends toward the n-th data line DLn so as to cross the n-th data line DLn in a direction away from the active layer region 65 of the n-th driving switch Trn (e.g., the positive direction of the Z-axis), and there is a gap between it and the n-th data line DLn.

[0146] The other side portion of the remaining wiring of the n-th scan line GLn starts from the point where the wiring segment 76a is connected to the scan terminal line 75 of the (n + 2)-th driving switch Trn+2 and extends along the active layer region 65 of the (n + 2)-th driving switch Trn+2. Additionally, the other side portion of the remaining wiring of the n-th scan line GLn extends toward the (n + 1)-th data line DLn+1 to cross the (n + 1)-th data line DLn+1 in a direction away from the active layer region 65 of the (n + 2)-th driving switch Trn+2 (e.g., the positive direction of the Z-axis), and there is a gap between it and the (n + 1)-th data line DLn+1.

[0147] One side portion of the remaining wiring of the (n + 1)-th scan line GLn+1 starts from the point where the wiring segment 76a is connected to the scan terminal line 75 of the (n + 1)-th driving switch Trn+1, and extends along the active layer region 65 of the (n + 1)-th driving switch Trn+1. In addition, one side portion of the remaining wiring of the (n + 1)-th scan line GLn+1 extends toward the n-th data line DLn, so as to cross the n-th data line DLn in a direction away from the active layer region 65 of the (n + 1)-th driving switch Trn+1 (e.g., the positive direction of the Z axis), with a gap between it and the n-th data line DLn.

[0148] The other side portion of the remaining wiring of the (n + 1)-th scan line GLn+1 starts from the point where the wiring segment 76a is connected to the scan terminal line 75 of the (n + 3)-th driving switch Trn+3, and extends along the active layer region 65 of the (n + 3)-th driving switch Trn+3. In addition, the other side portion of the remaining wiring of the (n + 1)-th scan line GLn+1 extends toward the (n + 1)-th data line DLn+1, so as to cross the (n + 1)-th data line DLn+1 in a direction away from the active layer region 65 of the (n + 3)-th driving switch Trn+3.

[0149] In addition, in Figure 4E the wiring segment 76a is formed separately from the scan terminal line 75, but they may be integrally formed. In addition, the cross-sections of the scan line 76 and the wiring segment 76a may be selected to be any shape according to the purpose or use of the pixel circuit substrate 100, and may have, for example but not limited to, a rectangular shape or a circular shape.

[0150] Furthermore, the term "line" of the scan line 76 and its wiring segment 76a does not limit the thickness or diameter of the scan line 76 and its wiring segment 76a. The thickness or diameter of the scan line 76 and its wiring segment 76a may be any value according to the purpose or use of the pixel circuit substrate 100.

[0151] As Figure 4F shown, the pixel circuit substrate 100 includes the n-th common potential line CLn. The n-th common potential line CLn is arranged separately from the scan line (76) in a direction away from the active layer region 65 (e.g., the positive direction of the Z axis). The n-th common potential line CLn has a central position with respect to the extending direction of the active layer region 65 (e.g., the positive direction of the X axis), and the n-th common potential line CLn at the central position extends along the arrangement direction of the corresponding active layer region 65 (e.g., the positive direction of the Y axis). The n-th common potential line CLn is collectively referred to as the common potential line 77. The common potential line 77 is formed of a conductor.

[0152] In addition, the pixel circuit substrate 100 includes a plurality of branch lines 77a connected to the common potential line 77. The plurality of branch lines 77a are separately arranged from the scanning line 76 in a direction away from the active layer region 65 (e.g., the positive direction of the Z axis). Two of the plurality of branch lines 77a extend along both sides of the active layer region 65 of the n-th driving switch Trn toward the common potential line 77 with the common potential line 77 as a baseline. Another two of the plurality of branch lines 77a extend along both sides of the active layer region 65 of the (n + 1)-th driving switch Trn+1 toward the common potential line 77 with the common potential line 77 as a baseline. Another two of the plurality of branch lines 77a extend along both sides of the active layer region 65 of the (n + 2)-th driving switch Trn+2 toward the common potential line 77 with the common potential line 77 as a baseline. Another two of the plurality of branch lines 77a extend along both sides of the active layer region 65 of the (n + 3)-th driving switch Trn+3 toward the common potential line 77 with the common potential line 77 as a baseline. The plurality of branch lines 77a are formed of a conductor.

[0153] In addition, in Figure 4F , the common potential line 77 and the plurality of branch lines 77a are separately formed, but they may be integrally formed. In addition, the cross-sections of the common potential line 77 and the plurality of branch lines 77a may be selected to be any shape according to the purpose or use of the pixel circuit substrate 100, and may have, for example but not limited to, a rectangular shape or a circular shape.

[0154] In addition, the term "line" in the common potential line 77 and the plurality of branch lines 77a does not limit the thickness or diameter of the common potential line 77 and the plurality of branch lines 77a. The thickness or diameter of the common potential line 77 and the plurality of branch lines 77a may be any value according to the purpose or use of the pixel circuit substrate 100.

[0155] As Figure 4G shown, the pixel circuit substrate 100 includes control terminal lines 80a. Each control terminal line 80a is connected to each control terminal 81 and extends from each control terminal 81 in a direction away from the respective active layer regions 65 (e.g., the positive direction of the Z axis).

[0156] In addition, the control terminal line 80a may be formed separately from the control terminal 81, or may be formed integrally with the control terminal 81. Additionally, when the control terminal line 80a is formed integrally with the control terminal 81, they may be combined and referred to as the control terminal line 80a. Conversely, they may be referred to as the control terminal 81. The cross-section of the control terminal line 80a may be selected to be any shape according to the purpose or use of the pixel circuit substrate 100, and may have, for example but not limited to, a rectangular shape or a circular shape. Additionally, the term "line" in the control terminal line 80a does not limit the thickness or diameter of the control terminal line 80a. The thickness or diameter of the control terminal line 80a may be any value according to the purpose or use of the pixel circuit substrate 100.

[0157] As Figure 4G and Figure 4H shown, the pixel circuit substrate 100 includes an auxiliary capacitor dielectric 78, a relay line 80b, and an electrode line 80c.

[0158] The auxiliary capacitor dielectric 78 is disposed in a layer to cover a branch line 77a extending in the same direction as the extension direction of each active layer region 65 (e.g., the positive direction of the X-axis), and a portion of the common potential line 77 in the extension direction of the branch line 77a. The auxiliary capacitor dielectric 78 functions as a buffer that enables the control output information of the pixel circuit substrate 100 to be held for a certain period of time. As the material of the auxiliary capacitor dielectric 78, any material may be selected according to the purpose or use of the pixel circuit substrate 100. For example, dielectrics such as SiO2, tantalum oxide, or alumina may be used, but are not limited thereto.

[0159] As Figure 4H shown, the relay line 80b and the electrode line 80c together with the control terminal line 80a form a control line 80. The relay line 80b and the electrode line 80c are formed of a conductor.

[0160] Each relay line 80b is connected to the top end of each control terminal line 80a in the extension direction of the control terminal line 80a. The relay line 80b extends from the top end of the control terminal line 80a in the extension direction of the branch line 77a. The relay line 80b is arranged such that the auxiliary capacitor dielectric 78 is interposed between the relay line 80b and the common potential line 77 and the branch line 77a in the extension direction of the branch line 77a. By interposing the auxiliary capacitor dielectric 78 between the relay line 80b and the common potential line 77 and the branch line 77a, the auxiliary capacitor dielectric 78 functions as a capacitor, and the control output information of the pixel circuit substrate 100 can be held for a certain period of time. Additionally, in Figure 4H a single-layer capacitor is constructed by interposing a capacitor dielectric between two conductors, but a laminated capacitor in which more capacitor dielectrics and conductors are laminated can be constructed, as described later.

[0161] Each electrode line 80c is connected to each relay line 80b and extends in a direction away from the relay line 80b in a direction away from the active layer region 65 (e.g., the positive direction of the Z-axis). The electrode line 80c can be arranged at any position of the relay line 80b according to the arrangement position of the pixel electrode 90. In Figure 4H it, the electrode line 80c is arranged diagonally with respect to the extending direction of the active layer region 65 such that the line connecting the centers of the electrode lines 80c is away from the extending direction of the active layer region 65 (e.g., the positive direction of the X-axis).

[0162] In addition, in Figure 4H it, the control terminal line 80a, the relay line 80b, and the electrode line 80c are formed separately from each other, but some or all of them can be integrally formed. In addition, the cross-sections of the control terminal line 80a, the relay line 80b, and the electrode line 80c can be selected to be any shape according to the purpose or use of the pixel circuit substrate 100, and can have, for example but not limited to, a rectangular shape or a circular shape.

[0163] In addition, the term "line" in the control terminal line 80a, the relay line 80b, and the electrode line 80c does not limit the thickness or diameter of the control terminal line 80a, the relay line 80b, and the electrode line 80c. The thickness or diameter of the control terminal line 80a, the relay line 80b, and the electrode line 80c can be any value according to the purpose or use of the pixel circuit substrate 100.

[0164] As Figure 4I shown, the pixel circuit substrate 100 includes a plurality of pixel electrodes 90. Each pixel electrode 90 includes a pixel surface 90a that defines a pixel of the spatial light modulator 10. Each pixel electrode 90 is connected to each electrode line 80c at a surface opposite to the pixel surface 90a.

[0165] The material of the pixel electrode 90 can be any conductive material selected according to the purpose or use of the pixel circuit substrate 100. There is no limitation on the material of the pixel electrode 90, but conductors such as aluminum, copper, indium tin oxide (ITO) (e.g., refractive index-matched ITO (IMITO)), tin oxide, magnesium-silver alloy, or polythiophene-based conductive polymers using PEDOT (poly(3,4-ethylenedioxythiophene)) are used.

[0166] In the pixel circuit substrate 100, a plurality of pixel electrodes 90 are arranged along the extending direction of the active layer region 65 (e.g., the X-axis direction), and there are gaps between them. In addition, in Figure 4IAmong them, a plurality of pixel electrodes 90 are arranged with gaps in a direction (e.g., the positive direction of the X-axis) that is the same as the extending direction of the active layer region 65, but it is not limited thereto. For example, the plurality of pixel electrodes 90 may be arranged diagonally such that the line connecting the centers of the corresponding pixel electrodes 90 forms an angle with the positive direction of the X-axis. Additionally, the gaps between the pixel electrodes 90 are preferably constant because it can reduce the load of hologram operation, but the gaps can be random. For example, when the gaps between the pixel electrodes 90 are random, the hologram can be operated by machine learning the correlation between the input data of the spatial light modulator 10 and the comparison of the reproduced three-dimensional images.

[0167] In addition, in Figure 4I Among them, the shape of the pixel electrode 90 is rectangular, but any shape can be selected according to the purpose or use of the pixel circuit substrate 100. For example, the shape of the pixel electrode 90 can be a circular shape, an oval shape, or a polygonal shape other than a rectangle. Furthermore, the shapes of all the pixel electrodes 90 do not have to be the same shape, but they can be the same shape when considering the ease of arrangement.

[0168] In addition, the shape of the pixel electrode 90 is preferably rectangular. By making the shape of the pixel electrode 90 rectangular, the gap between adjacent pixel electrodes 90 can be reduced, so that the aspect ratio in the light modulation region of the spatial light modulator 10 can be increased.

[0169] In addition, the shape of the pixel electrode 90 is more preferably a square shape. Additionally, by making the shape of the pixel electrode 90 a square shape, the gap between adjacent pixel electrodes 90 can be reduced while increasing the number of pixels in the light modulation region of the spatial light modulator 10. Therefore, by making the shape of the pixel electrode 90 square, the aperture ratio in the light modulation region of the spatial light modulator 10 can be increased, and at the same time, the fineness of the pixels in the light modulation region of the spatial light modulator 10 can be ensured.

[0170] In addition, as described later Figure 4I and Figure 6B shown, the nth pixel electrode Pixn is connected to the nth driving switch Trn through the control line 80. In addition, as described later Figure 4I and Figure 6C shown, the (n + 1)th pixel electrode Pixn+1 is connected to the (n + 1)th driving switch Trn+1 through the control line 80. In addition, as described later Figure 4I and Figure 6D shown, the (n + 2)th pixel electrode Pixn+2 is connected to the (n + 2)th driving switch Trn+2 through the control line 80. In addition, as described later Figure 4I and Figure 6EAs shown, the (n + 3)-th pixel electrode Pixn+3 is connected to the (n + 3)-th driving switch Trn+3 through the control line 80. The n-th pixel electrode Pixn, the (n + 1)-th pixel electrode Pixn+1, the (n + 2)-th pixel electrode Pixn+2, and the (n + 3)-th pixel electrode Pixn+3 are collectively referred to as pixel electrodes 90 when there is no need to particularly distinguish them.

[0171] As Figure 4I and Figure 5 shown, each active layer region 65 is at a certain distance from each pixel electrode 90 at the position overlapping with the pixel plane 90a.

[0172] In addition, the plurality of active layer regions 65 extend through adjacent pixel electrodes 90 at the positions overlapping with the pixel plane 90a of the plurality of pixel electrodes 90. In other words, as Figure 4I and Figure 5 shown, in the extending direction of the active layer region 65 (for example, the X-axis direction), the length L of the active layer region 65 is longer than the width P1 of the pixel plane 90a.

[0173] For example, when the wavelength is a variable λ and the pixel pitch is a variable p, the viewing angle (2θmax) at which hologram reproduction can be performed is represented by the following formula.

[0174] 2θmax = 2sin -1 [λ / 2p].

[0175] According to this formula, in order to ensure the viewing angle (2θmax) required for hologram reproduction, both the width P1 and the width P2 of the pixel plane 90a need to be as fine as the wavelength of light (for example, less than 1 μm).

[0176] In addition, in order for the spatial light modulator 10 to respond at high speed, a high voltage (for example, 5V or higher) is required. Therefore, if the length L of the active layer region 65 (for example, the channel length) is shortened and combined with making the pixel plane 90a fine, the withstand voltage capacity of the active layer region 65 may be reduced, resulting in a failure or malfunction of the driving switch Tr.

[0177] However, in the pixel circuit substrate 100 of the present disclosure, the length L of the active layer region 65 can be made longer than the width P1 of the pixel plane 90a, so that the withstand voltage capacity of the active layer region 65 can be ensured while promoting the fineness of the pixel plane 90a.

[0178] In addition, at the positions where the plurality of active layer regions 65 overlap with the pixel plane 90a, the plurality of active layer regions 65 are arranged to be spaced apart from each other in a direction (for example, the Y-axis direction) intersecting with the arrangement direction (for example, the X-axis direction) of the plurality of pixel electrodes 90. Specifically, in the arrangement direction of the plurality of active layer regions 65 (for example, the Y-axis direction), the width W of the active layer region 65 is smaller than the width P2 of the pixel plane 90a.

[0179] If the width W of the active layer region 65 is made shorter than the width P2 of the pixel plane 90a, one pixel plane 90a can overlap with a plurality of active layer regions 65, thereby increasing the density of the pixel electrodes 90 connected to the plurality of active layer regions 65. Therefore, by making the width W of the active layer region 65 shorter than the width P2 of the pixel plane 90a, the aspect ratio in the light modulation region of the spatial light modulator 10 can be increased.

[0180] In addition, the respective active layer regions 65 have the same length L and the same width W, so that the electrical characteristics (such as the resistance value) of the active layer regions 65 can be almost the same, which is desirable, but they can have different widths.

[0181] In addition, when the number of active layer regions 65 and the number of pixel electrodes 90 arranged in the pixel circuit substrate 100 are plural, any number can be selected according to the purpose or use of the pixel circuit substrate 100.

[0182] In addition, by making the distance L1 between the scan terminal 72 and the control terminal 81 the same as Figure 6A the distance L2 between the scan terminal 72 and the data terminal 73 shown, stable operation can be achieved regardless of the current direction of the drive switch Tr.

[0183] In Figures 6A to 6E the wiring etc. in the pixel circuit substrate 100 are described. In Figures 6A to 6E an example of the same structure as Figures 4A to 4I is shown, except that the insulating material 79 is shown in the gap between the components. The insulating material 79 uses, for example but not limited to, SiO2.

[0184] As Figure 6A the perspective view shows, the scan line 76 extends between the drive switch Tr and the pixel electrode 90 without intersecting the control line 80. In addition, as Figures 6B to 6E shown, the scan line 76 bypasses all the control lines 80 and extends between the drive switch Tr and the pixel electrode 90. More specifically, the scan line 76 extends between the drive switch Tr and the relay line 80b by bypassing the control terminal line 80a of the control line 80 without crossing it.

[0185] According to the above structure, while ensuring the withstand voltage capacity of the drive switch Tr, a pixel circuit substrate 100 capable of wiring and connecting to the scan line 76 of the drive switch Tr can be provided, so that a spatial light modulator 10 with fine pixels can be realized, and ideal hologram reproduction etc. can be achieved.

[0186] In addition, the scan line 76 includes a wiring segment 76a that extends through adjacent active layer regions 65, enabling effective bypass of the scan line 76.

[0187] In addition, the pixel circuit substrate 100 of the present disclosure can be implemented by bypassing the data line 74 instead of the scan line 76.

[0188] In Figure 7A a cross-section of the (n + 3)th driving switch Trn+3 is illustrated. As described above, a voltage equal to half of the operating voltage (VDD) of the driving switch Tr, i.e., (VDD / 2), is constantly applied to the transparent electrode 50, and a voltage equal to the operating voltage (VDD) or the reference voltage (GND) is applied to the data terminal 73.

[0189] In addition, the active layer region 65 is constantly maintained at the reference voltage (GND). Additionally, a voltage equal to half of the operating voltage (VDD) of the driving switch Tr, i.e., (VDD / 2), is constantly applied to the common potential line 77 or the branch line 77a.

[0190] When driving the (n + 3)th driving switch Trn+3, a scan voltage (VG) is applied to the scan terminal 72. Therefore, when an operating voltage (VDD) is applied to the data terminal 73 and a scan voltage (VG) is applied to the scan terminal 72, an operating voltage (VDD) is applied to the pixel electrode 90, and in other cases, the reference voltage (GND) is applied.

[0191] When an operating voltage (VDD) is applied to the data terminal 73 and a scan voltage (VG) is applied to the scan terminal 72, the control output information of the pixel circuit substrate 100 is held in the auxiliary capacitance dielectric 78 for a certain period of time.

[0192] Figure 7B A modification example of Figure 7A is illustrated. In Figure 7B , a first relay line 80b1 and a second relay line 80b2 are formed. A first auxiliary capacitance dielectric 78-1 is formed between the first relay line 80b1 and the common potential line 77 or the branch line 77a, and a second auxiliary capacitance dielectric 78-2 is formed between the second relay line 80b2 and the common potential line 77 or the branch line 77a. Other structures are the same as those in Figure 7A .

[0193] According to the above configuration, the holding capacity of the control output information of the pixel circuit substrate 100 can be increased.

[0194] In Figures 8A to 8C , a circuit is illustrated in the case where the pixel circuit substrate 100 is applied to the light modulation region of the spatial light modulator 10. As in Figure 8A and Figure 8BAs shown, the circuit region having the (n-1)th to (n-4)th driving switches Trn-1 to Trn-4 is configured as a mirror image of the circuit region having the nth to (n+3)th driving switches Trn to Trn+3 (e.g., the circuit region of the pixel circuit substrate 100). Therefore, in the circuit region having the (n-1)th to (n-4)th driving switches Trn-1 to Trn-4, Figure 4I a mirror image of the YZ plane of the pixel circuit substrate 100 of Figure 4I is arranged in parallel to the scanning line 76. The pixel circuit substrate 100 and its mirror image form a unit circuit of the light modulation region of the spatial light modulator 10. In the light modulation region of the spatial light modulator 10, the unit circuits are repeatedly arranged in the extending direction of the scanning line 76 (e.g., the X-axis direction) and in the extending directions of the data line 74 and the common potential line 77 (e.g., the Y-axis direction).

[0195] In the circuit region of the pixel circuit substrate 100, two data lines and two scanning lines are wired. By independently applying voltages to the two data lines and the two scanning lines, the nth to (n+3)th driving switches Trn to Trn+3 can independently perform driving and stopping.

[0196] In Figures 8A to 8C , the data terminals 73 of the nth driving switch Trn and the (n+1)th driving switch Trn+1 are connected to the nth data line DLn. In addition, the data terminals 73 of the (n+2)th driving switch Trn+2 and the (n+3)th driving switch Trn+3 are connected to the (n+1)th data line DLn+1. In addition, the control terminals 81 of the nth driving switch Trn and the (n+1)th driving switch Trn+1 are arranged close to the (n+1)th data line DLn+1. In addition, the control terminals 81 of the (n+2)th driving switch Trn+2 and the (n+3)th driving switch Trn+3 are arranged close to the nth data line DLn.

[0197] When the control terminals 81 of the nth to (n+3)th driving switches Trn to Trn+3 are arranged almost in a column, since the control terminal line 80a extends in the Z-axis direction, there is a possibility that the wiring space for the scanning line 76 cannot be ensured. On the contrary, in Figures 8A to 8C , the control terminals 81 of the nth to (n+3)th driving switches Trn to Trn+3 are not arranged in a column, so that the wiring space for the scanning line 76 can be ensured. In addition, as shown in Figure 8B , since the scanning line 76 has a wiring segment 76a, it is possible to easily bypass the control terminal line 80a.

[0198] In Figures 9A to 9CAmong them, the data terminals 73 of the n-th driving switch Trn and the (n + 2)-th driving switch Trn+2 are connected to the n-th data line DLn. In addition, the data terminals 73 of the (n + 1)-th driving switch Trn+1 and the (n + 3)-th driving switch Trn+3 are connected to the (n + 1)-th data line DLn+1. Further, the control terminals 81 of the n-th driving switch Trn and the (n + 2)-th driving switch Trn+2 are arranged close to the (n + 1)-th data line DLn+1. Further, the control terminals 81 of the (n + 1)-th driving switch Trn+1 and the (n + 3)-th driving switch Trn+3 are arranged close to the n-th data line DLn. Other configurations are the same as Figures 8A to 8C the configuration of.

[0199] In Figures 9A to 9C among them, since the control terminals 81 of the n-th driving switch Trn to the (n + 3)-th driving switch Trn+3 are not arranged in a column, the wiring space of the scanning line 76 can be ensured. In addition, since the scanning line 76 has a wiring segment 76a, it is possible to easily achieve bypassing the control terminal line 80a. Therefore, the same effect as Figures 8A to 8C is obtained.

[0200] Further, as Figure 10 shown, the unit circuit formed by the part including the (n - 2)-th driving switch Trn-2 to the (n + 1)-th driving switch Trn+1 among the unit circuits of Figures 9A to 9C also obtains the same effect as described above.

[0201] Further, in the light modulation region of the spatial light modulator 10, it is possible to combine and use Figures 8A to 8C , Figures 9A to 9C and Figure 10 the unit circuits of.

[0202] Further, as Figure 11 shown, the driving switch Tr may include a memory element 75a. The memory element 75a is connected to the data line 74 and the scanning line 76, and can drive the driving switch Tr by sending an electrical signal to the scanning terminal line 75 based on signals from the data line 74 and the scanning line 76. In Figure 11 the case of the configuration of, the operating voltage (VDD) of the driving switch Tr is constantly applied to the terminal 73a of the data terminal 73. In addition, when storing data in the memory element 75a, the positive power supply (e.g., VDD) of the driving switch Tr is applied to the first terminal 75a1 of the memory element 75a, and the negative power supply (e.g., VSS) of the driving switch Tr is applied to the second terminal 75a2 of the memory element 75a.

[0203] In addition, the memory element 75a can be any one according to the purpose or use of the pixel circuit substrate 100. The memory element 75a is selected from, for example, DRAM, SRAM, FeRAM, or ReRAM.

[0204] According to the present disclosure, it is possible to provide a pixel circuit substrate, a spatial light modulator, and a display system that can achieve the arrangement of scan lines or data lines connected to a driving switch while ensuring the withstand voltage ability of the driving switch.

[0205] Those skilled in the art will appreciate that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

[0206] Cross-reference to related applications

[0207] This application claims the priority and benefit of Japanese Patent Application No. 2023-222518, filed in Japan on December 28, 2023, the entire content of which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A pixel circuit substrate for a spatial light modulator, the pixel circuit substrate comprising: a plurality of pixel electrodes, the plurality of pixel electrodes being arranged spaced apart from each other, and each pixel electrode comprising a pixel face defining a pixel of the spatial light modulator; a plurality of active layer regions, each of the plurality of active layer regions extending through adjacent pixel electrodes at a position overlapping the pixel surface and arranged spaced apart from each other in a direction intersecting an arrangement direction of the plurality of pixel electrodes; a plurality of driving switches, the plurality of driving switches being respectively formed at the plurality of active layer regions and each comprising a scan terminal, a data terminal and a control terminal; a plurality of control lines, each of the plurality of control lines being connected between each control terminal and a corresponding pixel electrode of the plurality of pixel electrodes; as well as a scan line disposed between the plurality of drive switches and the plurality of pixel electrodes and connected to the scan terminal, The scan lines bypass the plurality of control lines and extend between the plurality of driving switches and the plurality of pixel electrodes. 2 . The pixel circuit substrate according to claim 1 , further comprising a data line disposed between the plurality of driving switches and the plurality of pixel electrodes and connected to the data terminal.

3. The pixel circuit substrate according to claim 1, wherein: The scan line includes a wiring segment extending through adjacent active layer regions.

4. The pixel circuit substrate according to claim 1, wherein: Each of the plurality of control lines comprises: a control terminal line extending in a direction away from each control terminal; an electrode line extending in a direction away from a corresponding active layer region among the plurality of active layer regions; and a relay line connecting the control terminal line and the electrode line and extending in the arrangement direction of the plurality of pixel electrodes, The scan line bypasses the control terminal line and extends between the plurality of drive switches and the relay line.

5. The pixel circuit substrate according to claim 4, further comprising: a common potential line disposed below the plurality of control lines and extending along a direction in which the plurality of active layer regions are arranged; a plurality of branch lines, the plurality of branch lines being connected to the common potential line and extending to both sides of the common potential line along corresponding active layer regions; as well as An auxiliary capacitor dielectric is provided between the plurality of control lines and the common potential line or the plurality of branch lines.

6. The pixel circuit substrate according to claim 1, wherein: The pixel plane has a rectangular shape.

7. The pixel circuit substrate according to claim 1, wherein: In an extension direction of the active layer region, a width of the active layer region is longer than a width of the pixel surface.

8. The pixel circuit substrate according to claim 1, wherein: In an arrangement direction of the plurality of active layer regions, a width of the active layer region is shorter than a width of the pixel surface.

9. The pixel circuit substrate according to claim 1, wherein: The pixel plane has a square shape.

10. The pixel circuit substrate according to claim 1, wherein: The plurality of active layer regions are formed of a single crystal material selected from the group consisting of Si, SiC, GaN, and Ga2O3.

11. A pixel circuit substrate for a spatial light modulator, the pixel circuit substrate comprising: a plurality of pixel electrodes, the plurality of pixel electrodes being arranged spaced apart from each other, and each pixel electrode comprising a pixel face defining a pixel of the spatial light modulator; as well as a plurality of drive switches, the plurality of drive switches comprising a plurality of active layer regions, each of the active layer regions extending through adjacent pixel electrodes at a position overlapping the pixel plane and arranged spaced apart from each other in a direction intersecting an arrangement direction of the plurality of pixel electrodes, Wherein, in the extension direction of the active layer region, the width of the active layer region is longer than the width of the pixel surface, and Wherein, in the arrangement direction of the plurality of active layer regions, the width of the active layer region is shorter than the width of the pixel surface.

12. A spatial light modulator, comprising: The pixel circuit substrate according to any one of claims 1 to 11; A transparent electrode, wherein the transparent electrode and the pixel circuit of the pixel circuit substrate together form a driving circuit; as well as A light modulation layer is provided between the plurality of pixel electrodes and the transparent electrode, and a voltage is applied to the light modulation layer from the driving circuit.

13. The spatial light modulator according to claim 12, wherein: The light modulation layer is formed of ferroelectric liquid crystal.

14. A display system comprising the spatial light modulator according to any one of claims 12 to 13.

15. The display system according to claim 14, wherein: The display system is a holographic display for hologram reconstruction.

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