Method for accessing NVM (Non-Volatile Memory) chip by shielding difference of NVM chip and control component

Abstract

The invention provides a method for shielding NVM chip differences to access NVM chips and a control component, and the method comprises the steps: responding to a received storage command, processing the storage command to generate a medium interface command carrying logic PPA, and enabling the logic PPA to have a uniform format for different NVM chips; processing the medium interface command, and determining a real PPA corresponding to the logic PPA based on a first mapping relationship between the logic PPA and the real PPA; wherein the real PPA is the physical address of the NVM chip; and generating a storage medium access command according to the real PPA, and accessing the NVM chip based on the storage medium access command. The storage resources provided by the NVM chip are managed and used in a unified mode, and when the NVM chip is replaced, most components of the control component do not need to be adjusted, so that the development cost and the delivery time introduced by adapting to a new NVM chip are reduced.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a method for accessing NVM chips by shielding NVM chip differences and a control component. Background Art

[0002] Figure 1A A block diagram of a storage device is shown. The storage device 102 is coupled to a host and is used to provide storage capabilities for the host. The host and the storage device 102 can be coupled in various ways. The coupling methods include but are not limited to connecting the host and the storage device 102 through various storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication networks, etc. The host can be an information processing device capable of communicating with the storage device in the above ways. For example, a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, wear leveling, bad block management, etc. The control component 104 can be implemented in multiple ways such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field - programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, and software is executed in the processor or controller to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. The FTL table and / or the data of the cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash interface controller (or also referred to as a media interface controller, flash channel controller). The flash interface controller is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that conforms to the interface protocol of the NVM chip 105 to operate the NVM chip 105 and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] Figure 1B A detailed block diagram of the control component of the storage device is shown.

[0008] The host accesses the storage device with IO commands that conform to the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (such as programming commands, read commands, erase commands) that conform to the interface protocol of the NVM chip according to the media interface commands. The control component also tracks that all media interface commands generated from one IO command have been executed and indicates the processing result of the IO command to the host.

[0009] See Figure 1B , the control component includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface obtains the IO commands provided by the host and generates storage commands to provide to the storage command processing unit. The storage commands access the same - sized storage space, for example, 4KB.

[0010] The storage medium management unit maintains the translation of logical addresses to physical addresses for each storage command. For example, the storage medium management unit includes an FTL table. For read commands, the storage medium management unit outputs the physical address corresponding to the logical address accessed by the storage command. For write commands, the storage medium management unit allocates an available physical address for it and records the mapping relationship between the accessed logical address and the allocated physical address. The storage medium management unit also maintains functions required for managing NVM chips, such as garbage collection and wear leveling.

[0011] The storage command processing unit, according to the physical address provided by the storage medium management unit, operates the media interface controller to issue a storage medium access command to the NVM chip. For the sake of clarity, the command sent by the host to the storage device is called an IO command, the command sent by the host command processing unit to the storage command processing unit is called a storage command, the command sent by the storage command processing unit to the media interface controller is called a media interface command, and the command sent by the media interface controller to the NVM chip is called a storage medium access command. The storage medium access command follows the interface protocol of the NVM chip.

[0012] Each NVM chip includes one or more LUNs (Logical UNits), and each logical unit includes multiple physical blocks. A large block includes physical blocks from multiple logical units, and the multiple logical units that provide physical blocks for the large block are called a logical unit group. Each logical unit in the logical unit group can provide one physical block for the large block. For example, in Figure 2A the schematic diagram of the large block shown, a large block is constructed on 16 logical units, and each large block includes 16 physical blocks respectively from 16 logical units. Large block 0 includes physical block 0 from each of the 16 logical units, and large block 2 includes physical block 2 from each logical unit. The large block can also be constructed in many other ways. Figure 2A In, the physical block is indicated by a reference numeral in the form of Bb-a, where a indicates that the physical block is provided by the logical unit (LUN a), and b indicates that the block number of the physical block in the logical unit is b. In the Chinese patent application with the application number 201710752321.0, other construction methods of the large block are provided.

[0013] A logical unit is the smallest unit in an NVM chip that independently executes commands and reports status. A memory target is one or more logical units within an NVM chip package that share a CE (Chip Enable) signal. An NAND flash (non-volatile storage technology) package may include one or more dies. Typically, a logical unit corresponds to a single die. The meaning of "target", "logical unit", and "plane" is provided in the "OpenNAND Flash Interface Specification (Revision 5.1)" obtained from the following link: https: / / media-www.micron.com / - / media / client / onfi / specs / onfi_5_1_final_1,-d-,0.pdf?la=en&rev=27ed5d740c8543f8bba06dbbd56fe6fe, which is part of the prior art.

[0014] A logical unit may include one or more planes, as Figure 2B shown, which is an implementation for constructing large blocks in a multi-plane logical unit. Multiple planes within a logical unit can be accessed in parallel (e.g., read / write operations), and multiple logical units in an NVM chip can execute commands and report status independently of each other. The operation of performing parallel access on multiple planes simultaneously is called a Multi-Plane operation. An NVM chip can support Multi-Plane Program operations and Multi-Plane read operations; among them, the multi-plane programming operation is the multi-plane write operation; Multi-Plane Program, for example, includes 2 planes, 4 planes, 6 planes, 8 planes, which indicates programming operations on 2 planes, 4 planes, 6 planes, or 8 planes simultaneously; Multi-Plane read, for example, includes 2 planes, 4 planes, 6 planes, 8 planes, which indicates read operations on 2 planes, 4 planes, 6 planes, or 8 planes simultaneously.

[0015] There are various ways to program an NVM chip. For example, one-shot Program (full programming) or two-Pass Program (two-part programming). NVM chip types include, for example, SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Trinary-Level Cell). Each SLC cell stores one bit of information (1 bit); each MLC cell stores 2 bits (2 bits); each TLC cell stores 3 bits (3 bits).

[0016] Taking the TLC type of NVM chip as an example, the storage states of the NVM chip are respectively mapped to 3-bit binary codes, such as 111 or 110. The 3-bit binary code is named LSB (Least Significant Bit), CSB (Center Significant Bit), and MSB (Most Significant Bit) from left to right in sequence. The word line (WL) of the TLC type of NVM chip can include multiple physical pages. For example, 3 physical pages, and the 3 physical pages respectively come from the LSB, MSB, and CSB of each storage cell (Cell) on the word line. The one-shot Program method programs the 3 physical pages represented by the LSB, CSB, and MSB as a whole. The two-Pass Program first programs the physical page corresponding to the LSB, and then programs the physical pages of the CSB and MSB, or the two-Pass Program first programs the physical pages corresponding to the LSB and CSB, and then programs the physical page of the MSB. As Figure 3A shown, it is a schematic diagram of programming the physical page by the one-shot Program method, as Figure 3B shown, it is a schematic diagram of programming the physical page by the two-Pass Program method. Summary of the Invention

[0017] When constructing a storage device using a control component, the NVM chips used in conjunction with the control component on the storage device may have various specifications. For example, the NVM chips used come from different suppliers (such as Yangtze Memory Technologies, Micron, Samsung, SK Hynix, etc.), and NVM chips from different manufacturers or different models have different capacities (64 Gbit, 128 Gbit, ……) and different sizes of storage medium access command formats (ONFI, Toggle, etc.). For different NVM chips, due to the different capacities of different NVM chips, the address formats (such as the address length) of different NVM chips are also different. For example, the physical address length of the NVM chip ranges from 31 to 37 bits. Therefore, when replacing the NVM chip coupled to the control component in the storage device, the control component needs to be modified to adapt to the replaced NVM chip, which, however, will introduce additional development costs and longer delivery times.

[0018] This application hopes to minimize the modification of the control component when the control component adapts to different NVM chips. To this end, most components in the control component manage and use the storage resources provided by the NVM chip in a unified manner. When changing the NVM chip used in conjunction with the control component, most components of the control component do not need to be adjusted, and the parts that need to be modified are concentrated in a few components, thereby reducing the development costs and delivery times introduced by adapting to the new NVM chip.

[0019] In a first aspect, an embodiment of this application provides a data access method, including:

[0020] In response to a received storage command, process the storage command to generate a media interface command carrying a logical PPA, where the logical PPA has a unified format for different NVM chips;

[0021] Process the media interface command, and based on a first mapping relationship between the logical PPA and the real PPA, determine the real PPA corresponding to the logical PPA; where the real PPA is the physical address of the NVM chip;

[0022] Generate a storage medium access command according to the real PPA, and access the NVM chip based on the storage medium access command.

[0023] Optionally, the step of, in response to a received storage command, processing the storage command to generate a media interface command carrying a logical PPA includes:

[0024] In response to the received storage command, parse the storage command to obtain the logical address carried therein;

[0025] Obtain the logical PPA based on the logical address, and generate the media interface command according to the logical PPA.

[0026] Optionally, obtaining the logical PPA based on the logical address includes:

[0027] Querying the FTL table based on the logical address to determine the table PPA corresponding to the logical address; wherein, the table PPA is the physical address recorded in the FTL table entry; determining the logical PPA corresponding to the table PPA based on the second mapping relationship between the table PPA and the logical PPA; or

[0028] Allocating a corresponding logical PPA based on the logical address.

[0029] Optionally, the method further includes:

[0030] Determining the table PPA corresponding to the logical PPA based on the second mapping relationship between the table PPA and the logical PPA, and recording the table PPA in the corresponding entry of the FTL table.

[0031] Optionally, the size of the table PPA is not fixed, and its size is positively correlated with the storage capacity provided by the storage device corresponding to the control component; the logical PPA is of a fixed size, and the size of the table PPA is not greater than the size of the logical PPA.

[0032] Optionally, based on the table PPA, adding invalid data with a specified number of bits to expand it to the size of the logical PPA to obtain the logical PPA, where the specified number of bits is the difference between the size of the logical PPA and the size of the table PPA;

[0033] Extracting corresponding bits of data from the logical PPA according to the size of the table PPA to obtain the table PPA.

[0034] Optionally, the unified format of the logical PPA is <LUN, Block, TU>, where LUN represents the first logical unit number, Block represents the first physical block number, and TU represents the first transmission unit number.

[0035] Optionally, the real PPA includes LUN, Block, TU, Plane, and Page, where LUN in the real PPA represents the second logical unit number, Block represents the second physical block number, TU represents the second transmission unit number, Plane represents the plane number, and Page represents the physical page number;

[0036] Determining the real PPA corresponding to the logical PPA based on the first mapping relationship between the logical PPA and the real PPA includes:

[0037] Determine the second logical unit number of the true PPA according to the first logical unit number of the logical PPA;

[0038] Determine the second physical block number of the true PPA according to the first physical block number of the logical PPA;

[0039] Determine the plane number, physical page number, and second transmission unit number included in the true PPA according to the first transmission unit number of the logical PPA.

[0040] Optionally, the first mapping relationship includes a first sub-mapping relationship between the first logical unit number of the logical PPA and the second logical unit number of the true PPA, and a second sub-mapping relationship between the first physical block number of the logical PPA and the second physical block number of the true PPA;

[0041] The determining the second logical unit number of the true PPA according to the first logical unit number of the logical PPA includes:

[0042] Determine the second logical unit number of the true PPA according to the first sub-mapping relationship and the first logical unit number of the logical PPA;

[0043] The determining the second physical block number of the true PPA according to the first physical block number of the logical PPA includes:

[0044] Determine the second physical block number of the true PPA according to the second sub-mapping relationship and the first physical block number of the logical PPA.

[0045] Optionally, the first sub-mapping relationship includes that the first logical unit number in the logical PPA corresponds one-to-one with the second logical unit number in the true PPA, and the first logical unit number in the logical PPA is the same as the second logical unit number in the true PPA; or, the first logical unit number in the logical PPA is different from the second logical unit number in the true PPA;

[0046] The second sub-mapping relationship includes that the first physical block number in the logical PPA corresponds one-to-one with the second physical block number in the true PPA, and the first physical block number in the logical PPA is the same as the second physical block number in the true PPA; or, the first physical block number in the logical PPA is different from the second physical block number in the true PPA.

[0047] Optionally, send a media interface command indicating a write operation according to a Write Unit, where the Write Unit is a set of the minimum number of transmission units TU that a media interface command indicating a write operation can transmit.

[0048] Optionally, there is a third sub - mapping relationship between the TUs in the Write Unit and the TUs in the NVM chip, and the first mapping relationship includes the third sub - mapping relationship;

[0049] Determining the plane number, physical page number, and second transmission unit number included in the real PPA according to the first transmission unit number of the logical PPA includes:

[0050] Determining the plane number, physical page number, and second transmission unit number of the real PPA according to the third sub - mapping relationship and the first transmission unit number of the logical PPA;

[0051] Wherein, the number corresponding to the TU in the NVM chip is the second transmission unit number of the real PPA, and the number corresponding to the TU in the Write Unit is the first transmission unit number in the logical PPA.

[0052] Optionally, the third sub - mapping relationship includes a one - to - one correspondence between the first transmission unit number in the logical PPA and the plane number, physical page number, and second transmission unit number in the real PPA.

[0053] Optionally, the TUs in the Write Unit are continuously numbered according to the number of TUs included in the Write Unit, and the TUs in the NVM chip are numbered according to physical pages, and each physical page corresponds to a specified number of TUs;

[0054] Determining the second transmission unit number, plane number, and physical page number corresponding to the first transmission unit number in the logical PPA based on the mapping relationship between the TUs in the Write Unit and the TUs in the NVM chip; the plane number and physical page number determine the plane and physical page in the NVM chip; based on the second transmission unit number, determine the TUs in the NVM chip. Optionally, processing the media interface command to generate a Flash abstraction layer command carrying the logical PPA, where the format of the Flash abstraction layer command is different from that of the media interface command;

[0055] Processing the Flash abstraction layer command to convert the logical PPA into the real PPA, generating a LUN controller command carrying the real PPA; and

[0056] Generating the storage media access command according to the LUN controller command carrying the real PPA.

[0057] Optionally, processing the media interface command to generate a Flash abstraction layer command carrying the logical PPA includes:

[0058] In response to the media interface command indicating a read operation, a first Flash abstraction layer command is generated according to the media interface command, where the types of the media interface command include indicating reading 4KB of data, reading data of one physical page (Page), or reading data of a multi-plane physical page (Multiplane Page);

[0059] In response to the media interface command indicating a write operation, at least one second Flash abstraction layer command is generated according to the WriteUnit indicated by the media interface command;

[0060] In response to the media interface command indicating an erase operation, corresponding third Flash abstraction layer commands are generated according to each physical block in the large block indicated by the media interface command. The media interface command indicates a large block, and the large block includes multiple physical blocks. Each of the third Flash abstraction layer commands indicates one physical block.

[0061] Optionally, in response to the media interface command indicating a write operation, according to the configuration information of the NVM chip coupled to the control component, the number of programming commands required for programming the Write Unit indicated by the media interface command is determined, and the same number of second Flash abstraction layer commands as the number of programming commands is generated according to the Write Unit.

[0062] Optionally, if the NVM chip coupled to the control component supports the one-shot Program programming mode, 1 second Flash abstraction layer command carrying the logical PPA is generated according to the media interface command;

[0063] If the NVM chip coupled to the control component supports the two-pass Program programming mode, 2 second Flash abstraction layer commands carrying the logical PPA are generated according to the media interface command.

[0064] Optionally, the generation of the LUN controller command carrying the real PPA includes:

[0065] A first LUN controller command indicating the real PPA is generated according to the first Flash abstraction layer command; where the first LUN controller command indicates reading data;

[0066] A second LUN controller command indicating the real PPA is generated according to the second Flash abstraction layer command; where the second LUN controller command indicates writing data;

[0067] A third LUN controller command indicating the real PPA is generated according to the third Flash abstraction layer command; where the third LUN controller command indicates erasing data.

[0068] Optionally, generating the storage medium access command according to the LUN controller command carrying the true PPA includes:

[0069] Generating a storage medium access command indicating a read operation according to a first LUN controller command carrying the true PPA, and sending the storage medium access command to a corresponding LUN to read data of a physical page in the LUN;

[0070] Generating a storage medium access command indicating a programming operation according to a second LUN controller command carrying the true PPA, and sending the storage medium access command to a corresponding LUN to perform a programming operation on a physical page in the LUN and write data to the physical page;

[0071] Generating a storage medium access command indicating an erase operation according to a third LUN controller command carrying the true PPA, and sending the storage medium access command to a corresponding LUN to perform an erase operation on a physical block in the LUN based on the true PPA.

[0072] Optionally, in the case of replacing the NVM chip coupled to the control component, the format of the logical PPA indicated by the medium interface command remains unchanged, and the size of the Write Unit indicated by the medium interface command changes.

[0073] Optionally, in the case of replacing the NVM chip coupled to the control component, it further includes:

[0074] Generating a fourth Flash abstraction layer command according to the medium interface command, where the information indicated by the fourth Flash abstraction layer command matches the configuration parameters of the replaced NVM chip;

[0075] Processing the fourth Flash abstraction layer command to generate a corresponding LUN controller command, where the information indicated by the LUN controller command matches the configuration parameters of the replaced NVM chip;

[0076] Generating a storage medium access command according to the generated LUN controller command to access the replaced NVM chip.

[0077] Optionally, when the programming mode supported by the replaced NVM chip changes, generating the fourth Flash abstraction layer command according to the medium interface command includes:

[0078] Generating a fourth Flash abstraction layer command corresponding to the medium interface command according to the updated programming mode type, where the programming mode indicated by the fourth Flash abstraction layer command is the programming mode supported by the replaced NVM chip.

[0079] Optionally, when the number of planes corresponding to the LUN in the replaced NVM chip changes and / or the physical page size in the NVM chip changes, the processing of the fourth Flash abstraction layer command to generate a corresponding LUN controller command includes:

[0080] Generating a LUN controller command according to the number of planes corresponding to the LUN in the replaced NVM chip and / or the physical page size, where the LUN, plane, and physical page in the real PPA indicated by the LUN controller command match the replaced NVM chip.

[0081] Optionally, when the number of planes corresponding to the LUN in the replaced NVM chip increases, the number of planes for the operations indicated by the generated LUN controller command increases, and the number of planes for the operations indicated by each LUN controller command is the same as the number of planes corresponding to the LUN in the replaced NVM chip.

[0082] Optionally, when the physical page becomes larger in the replaced NVM chip, the number of the fourth Flash abstraction layer commands generated according to the media interface command becomes smaller.

[0083] Optionally, when the physical address format of the replaced NVM chip changes, update the first mapping relationship between the logical PPA and the real PPA;

[0084] Convert the logical PPA indicated in the Flash abstraction layer command to the real PPA corresponding to the replaced NVM chip according to the updated first mapping relationship, where the real PPA corresponding to the replaced NVM chip is different from the real PPA corresponding to the NVM chip before replacement.

[0085] Optionally, when the physical address format of the replaced NVM chip changes, generate a storage medium access command according to the real PPA corresponding to the replaced NVM chip, where the format of the storage medium access command is different from the format of the storage medium access command corresponding to the NVM chip before replacement.

[0086] In a second aspect, an embodiment of the present application provides a control component, including a storage command processing unit, a storage medium management unit, and a media interface controller;

[0087] The storage command processing unit receives a storage command and obtains the logical address carried by the storage command;

[0088] The storage medium management unit receives the logical address, determines the logical PPA based on the logical address and sends it to the storage command processing unit, where the logical PPA is the physical address of the storage space of the NVM chip managed and maintained by the storage medium management unit, and the logical PPA has a unified format for different NVM chips;

[0089] The storage command processing unit generates a media interface command carrying the logical PPA based on the logical PPA;

[0090] The media interface controller receives the media interface command. In response to the media interface command, based on the first mapping relationship between the logical PPA and the real PPA, it determines the real PPA corresponding to the logical PPA, generates a storage medium access command according to the real PPA, and accesses the NVM chip based on the storage medium access command; where the real PPA is the physical address of the NVM chip.

[0091] Optionally, in response to the received storage command, the storage command processing unit parses the storage command to obtain the logical address carried therein;

[0092] The storage medium management unit queries the FTL table based on the logical address to determine the table PPA corresponding to the logical address; where the table PPA is the physical address recorded in the FTL table entry; based on the second mapping relationship between the table PPA and the logical PPA, it determines the logical PPA corresponding to the table PPA; or, the storage medium management unit allocates a corresponding logical PPA based on the logical address, determines the table PPA corresponding to the logical PPA based on the second mapping relationship between the table PPA and the logical PPA, and records the table PPA to the corresponding entry of the FTL table.

[0093] Optionally, the size of the table PPA is not fixed, and its size is positively correlated with the storage capacity provided by the storage device corresponding to the control component; the logical PPA is of a fixed size, and the size of the table PPA is not greater than the size of the logical PPA.

[0094] Optionally, the storage medium management unit adds invalid data with a specified number of bits based on the table PPA to expand it to the size of the logical PPA to obtain the logical PPA, where the specified number of bits is the difference between the size of the logical PPA and the size of the table PPA;

[0095] The storage medium management unit extracts corresponding bits of data from the logical PPA according to the size of the table PPA to obtain the table PPA.

[0096] Optionally, the unified format of the logical PPA is <LUN, Block, TU>, where LUN represents the first logical unit number, Block represents the first physical block number, and TU represents the first transmission unit number; the actual PPA includes LUN, Block, TU, Plane, and Page, where in the actual PPA, LUN represents the second logical unit number, Block represents the second physical block number, TU represents the second transmission unit number, Plane represents the plane number, and Page represents the physical page number.

[0097] Optionally, the media interface controller determines the second logical unit number of the actual PPA according to the first logical unit number of the logical PPA, determines the second physical block number of the actual PPA according to the first physical block number of the logical PPA, and determines the plane number, physical page number, and second transmission unit number included in the actual PPA according to the first transmission unit number of the logical PPA.

[0098] Optionally, the media interface controller includes a media interface command processing unit and a LUN controller. The media interface command processing unit includes a Common layer processing unit and a Flash abstraction layer processing unit. The Common layer processing unit provides a unified interface to the storage command processing unit to receive the media interface commands sent by the storage command processing unit. The Flash abstraction layer processing unit provides interfaces for docking with the Common layer processing unit and the LUN controller respectively;

[0099] The Common layer processing unit processes the media interface commands to generate Flash abstraction layer commands carrying the logical PPA, where the formats of the Flash abstraction layer commands and the media interface commands are different;

[0100] The Flash abstraction layer processing unit receives the Flash abstraction layer commands, processes the Flash abstraction layer commands, converts the logical PPA into the actual PPA, generates LUN controller commands carrying the actual PPA, and sends the LUN controller commands to the LUN controller;

[0101] The LUN controller generates storage medium access commands according to the LUN controller commands carrying the actual PPA and accesses the NVM chip based on the storage medium access commands.

[0102] Optionally, in response to receiving a media interface command indicating a read operation, the Common layer processing unit generates a first Flash abstraction layer command according to the media interface command, where the types of the media interface commands include commands indicating reading 4KB of data, reading data of one physical page (Page), or reading data of a multi-plane physical page (Multiplane Page).

[0103] Optionally, the storage command processing unit sends a media interface command indicating a write operation according to a Write Unit;

[0104] where the Write Unit is a set of the minimum number of transmission units (TUs) that a media interface command indicating a write operation can transmit.

[0105] Optionally, in response to receiving a media interface command indicating a write operation, the Common layer processing unit generates at least one second Flash abstraction layer command according to the Write Unit indicated by the media interface command.

[0106] Optionally, the Common layer processing unit determines the number of programming commands required for programming the Write Unit indicated by the media interface command according to the configuration information of the NVM chip coupled to the control component; and generates the same number of second Flash abstraction layer commands as the number of programming commands according to the Write Unit.

[0107] Optionally, the NVM chip coupled to the control component supports the one-shot Program programming mode, and the Common layer processing unit generates 1 second Flash abstraction layer command carrying a logical PPA according to the media interface command;

[0108] The NVM chip coupled to the control component supports the two-pass Program programming mode, and the Common layer processing unit generates 2 second Flash abstraction layer commands carrying a logical PPA according to the media interface command.

[0109] Optionally, in response to receiving a media interface command indicating an erase operation, the Common layer processing unit generates corresponding third Flash abstraction layer commands according to each physical block in the large block indicated by the media interface command;

[0110] where the media interface command indicates a large block, the large block includes a plurality of physical blocks, and each of the third Flash abstraction layer commands indicates a physical block.

[0111] Optionally, the Common layer processing unit obtains the processing status of the sent Flash abstraction layer command. In response to the completion of the Flash abstraction layer command processing, the Common layer processing unit reads data from the NVM chip and stores the media interface command processing result;

[0112] In response to the completion of the media interface command processing, it returns a media interface command processing completion message to the storage command processing unit.

[0113] Optionally, in response to an error in the read data, the Common layer processing unit initiates a reread operation for rereading.

[0114] Optionally, in the case where the media interface command indicates an erase operation, the Common layer processing unit collects the physical block erase status of large blocks and returns an erase completion message after all physical blocks are erased.

[0115] Optionally, the Flash abstraction layer processing unit generates a first LUN controller command indicating the real PPA according to the first Flash abstraction layer command; wherein, the first LUN controller command indicates reading data;

[0116] The Flash abstraction layer processing unit generates a second LUN controller command indicating the real PPA according to the second Flash abstraction layer command; wherein, the second LUN controller command indicates writing data;

[0117] The Flash abstraction layer processing unit generates a third LUN controller command indicating the real PPA according to the third Flash abstraction layer command; wherein, the third LUN controller command indicates erasing data.

[0118] Optionally, the Flash abstraction layer processing unit includes a first mapping relationship between the logical PPA and the real PPA. Based on the first mapping relationship, according to the first logical PPA indicated by the first Flash abstraction layer command, the corresponding first real PPA is determined, and a first LUN controller command is generated according to the first real PPA.

[0119] Optionally, the first mapping relationship includes a first sub - mapping relationship between the first logical unit number of the logical PPA and the second logical unit number of the real PPA, and a second sub - mapping relationship between the first physical block number of the logical PPA and the second physical block number of the real PPA;

[0120] The Flash abstraction layer processing unit determines the second logical unit number of the first real PPA according to the first sub - mapping relationship and the first logical unit number of the first logical PPA;

[0121] The Flash abstraction layer processing unit determines the second physical block number of the first true PPA according to the second sub-mapping relationship and the first physical block number of the first logical PPA.

[0122] Optionally, the first sub-mapping relationship includes that the first logical unit number in the logical PPA corresponds one-to-one with the second logical unit number in the true PPA, and the first logical unit number in the logical PPA is the same as the second logical unit number in the true PPA; or, the first logical unit number in the logical PPA is different from the second logical unit number in the true PPA.

[0123] The second sub-mapping relationship includes that the first physical block number in the logical PPA corresponds one-to-one with the second physical block number in the true PPA, and the first physical block number in the logical PPA is the same as the second physical block number in the true PPA; or, the first physical block number in the logical PPA is different from the second physical block number in the true PPA.

[0124] Optionally, there is a third sub-mapping relationship between the TU in the Write Unit and the TU in the NVM chip, and the first mapping relationship includes the third sub-mapping relationship.

[0125] The Flash abstraction layer processing unit determines the plane number, physical page number, and second transfer unit number of the first true PPA according to the third sub-mapping relationship and the first transfer unit number of the first logical PPA.

[0126] Wherein, the number corresponding to the TU in the NVM chip is the second transfer unit number of the true PPA, and the number corresponding to the TU in the Write Unit is the first transfer unit number in the logical PPA.

[0127] Optionally, the third sub-mapping relationship includes that the first transfer unit number in the logical PPA corresponds one-to-one with the plane number, physical page number, and second transfer unit number in the true PPA.

[0128] Optionally, the TUs in the Write Unit are numbered continuously according to the number of TUs included in the Write Unit, and the TUs in the NVM chip are numbered according to physical pages, and each physical page corresponds to a specified number of TUs.

[0129] Among them, the Flash abstraction layer processing unit determines the second transfer unit number, plane number, and physical page number corresponding to the first transfer unit number in the first logical PPA based on the mapping relationship between the TUs in the Write Unit and the TUs in the NVM chip; the plane number and physical page number determine the plane and physical page in the NVM chip; based on the second transfer unit number, the TU in the NVM chip is determined.

[0130] Optionally, the LUN controller generates a storage medium access command according to the first LUN controller command carrying the real PPA, and the storage medium access command is a read operation and carries the real PPA;

[0131] In response to the storage medium access command, the LUN controller sends the storage medium access command to the corresponding LUN to read the data of the physical page in the LUN.

[0132] Optionally, the LUN controller generates a storage medium access command according to the second LUN controller command carrying the real PPA, and the storage medium access command indicates a programming operation and carries the real PPA;

[0133] In response to the storage medium access command, the LUN controller sends the storage medium access command to the corresponding LUN to perform a programming operation on the physical page in the LUN and write data to the physical page.

[0134] Optionally, the LUN controller generates a storage medium access command according to the third LUN controller command carrying the real PPA, and the storage medium access command indicates an erase operation and carries the real PPA;

[0135] In response to the storage medium access command, the LUN controller sends the storage medium access command to the corresponding LUN to perform an erase operation on the physical block in the LUN based on the real PPA.

[0136] Optionally, in the case of replacing the NVM chip coupled to the control component, the format of the logical PPA indicated by the media interface command sent by the storage command processing unit to the media interface controller remains unchanged, and the size of the Write Unit indicated by the media interface command sent by the storage command processing unit to the media interface controller changes.

[0137] Optionally, in the case of replacing the NVM chip coupled to the control component, the Common layer processing unit generates a fourth Flash abstraction layer command according to the media interface command, where the information indicated by the fourth Flash abstraction layer command matches the configuration parameters of the replaced NVM chip;

[0138] The Flash abstraction layer processing unit processes the fourth Flash abstraction layer command according to the replaced NVM chip to generate a corresponding LUN controller command, wherein the information indicated by the LUN controller command matches the configuration parameters of the replaced NVM chip.

[0139] Optionally, in response to a change in the programming mode supported by the replaced NVM chip, the Common layer processing unit updates the programming mode type encapsulated in the Flash abstraction layer command;

[0140] The Common layer processing unit generates a fourth Flash abstraction layer command corresponding to the media interface command according to the updated programming mode type, wherein the programming mode indicated by the fourth Flash abstraction layer command is the programming mode supported by the replaced NVM chip.

[0141] Optionally, in response to a change in the number of planes corresponding to the LUN in the replaced NVM chip and / or a change in the physical page size in the NVM chip, the Flash abstraction layer processing unit generates a LUN controller command according to the number of planes corresponding to the LUN in the replaced NVM chip and / or the physical page size, wherein the LUN, plane, and physical page in the real PPA indicated by the LUN controller command match the replaced NVM chip.

[0142] Optionally, in response to an increase in the number of planes corresponding to the LUN in the replaced NVM chip, the number of planes indicated by the LUN controller command generated by the Flash abstraction layer processing unit increases, and the number of planes indicated by each LUN controller command is the same as the number of planes corresponding to the LUN in the replaced NVM chip.

[0143] Optionally, in response to an increase in the physical page size in the replaced NVM chip, the number of the fourth Flash abstraction layer commands generated by the Common layer processing unit according to the media interface command decreases.

[0144] Optionally, in response to a change in the physical address format of the replaced NVM chip, the Flash abstraction layer processing unit updates the first mapping relationship between the logical PPA and the real PPA;

[0145] The Flash abstraction layer processing unit converts the logical PPA indicated in the Flash abstraction layer command into the real PPA corresponding to the replaced NVM chip according to the updated first mapping relationship, wherein the real PPA corresponding to the replaced NVM chip is different from the real PPA corresponding to the NVM chip before replacement.

[0146] Optionally, in response to a transformation of the physical address format of the replaced NVM chip, the Flash abstraction layer processing unit generates a storage medium access command according to the true PPA corresponding to the replaced NVM chip, where the format of the storage medium access command is different from the format of the storage medium access command corresponding to the NVM chip before replacement.

[0147] According to an embodiment of the present application, for different NVM chips, the logical PPA is described in a unified format, enabling most components in the control unit to manage the storage space and use the storage resources provided by the NVM chip in a unified manner, rather than managing them separately according to the address format of each NVM chip, thereby avoiding the complexity brought by the differences between different NVM chips. When the NVM chip is replaced, most components in the control unit do not need to be adjusted, thus reducing the development cost and delivery time introduced by adapting to the new NVM chip. Brief Description of the Drawings

[0148] Figure 1A Block diagram showing a storage device;

[0149] Figure 1B Detailed block diagram showing the control unit of the storage device;

[0150] Figure 2A Schematic diagram showing a large block - Diagram 1;

[0151] Figure 2B Schematic diagram showing a large block - Diagram 2;

[0152] Figure 3A Schematic diagram showing the programming of a physical page using the one - shot Program method,

[0153] Figure 3B Schematic diagram showing the programming of a physical page using the two - Pass Program method;

[0154] Figure 4 Structural schematic diagram of the storage device provided by an embodiment of the present application;

[0155] Figure 5 Schematic diagram of the mapping between the table PPA and the logical PPA provided by an embodiment of the present application;

[0156] Figure 6A Schematic diagram of the mapping relationship between the logical PPA and the LUN indicated by the true PPA provided by an embodiment of the present application;

[0157] Figure 6B Schematic diagram of the mapping relationship between the logical PPA and the LUN indicated by the true PPA provided by another embodiment of the present application;

[0158] Figure 7 Shows a schematic diagram of the Write Unit provided by this application;

[0159] Figure 8A Shows a mapping schematic diagram between the TU of the logical PPA and the TU of the real PPA provided by an embodiment of this application;

[0160] Figure 8B Shows a mapping schematic diagram between the TU of the logical PPA and the TU of the real PPA provided by another embodiment of this application;

[0161] Figure 9 Is a schematic diagram showing the mapping relationship among the table PPA, the logical PPA, and the real PPA;

[0162] Figure 10 Shows a structural schematic diagram of a control component provided by an embodiment of this application;

[0163] Figure 11 Is a flowchart for accessing an NVM chip based on a read operation provided by an embodiment of this application;

[0164] Figure 12 Is a flowchart for accessing an NVM chip based on a write operation provided by an embodiment of this application;

[0165] Figure 13 Is a flowchart for accessing an NVM chip based on an erase operation provided by an embodiment of this application;

[0166] Figure 14 Shows a structural schematic diagram of the control component provided by another embodiment of this application.

[0167] Related technical terms

[0168] Table PPA: The physical address recorded in the FTL table of the DRAM, accommodated by an entry in the FTL table, and its size depends on the physical address space size of the NVM chip managed by the FTL table;

[0169] Logical PPA: The physical address used by the storage medium management unit to manage the physical address space of the NVM chip, which has a fixed size and a specified format.

[0170] Real PPA: The physical address carried by the storage medium access command sent by the media interface controller to the NVM chip;

[0171] TU: The transmission unit in the control component, which is the smallest unit for reading and has a size of 4KB;

[0172] Write Unit: A set indicating the minimum number of TUs that can be transmitted by a media interface command for a write operation. Detailed implementation manners

[0173] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0174] Figure 4 The structural schematic diagram of the storage device provided by the embodiment of the present application is shown.

[0175] As an example, refer to Figure 4 , the storage device includes a control component, a memory, and an NVM chip; wherein, the control component is coupled to the memory and the NVM chip; the control component includes a host interface, a host command processing unit, a storage command processing unit, a storage medium management unit, and a media interface controller. The memory is, for example, DRAM, and an FTL table for recording the mapping relationship between logical addresses and physical addresses is stored in the DRAM.

[0176] For example, when the storage device receives a read command sent by the host, the host command processing unit processes the read command to generate a storage command and sends the storage command to the storage command processing unit; the storage command processing unit, in response to receiving the storage command, parses the storage command to obtain the logical address indicated by the storage command and sends the logical address to the storage medium management unit. The storage medium management unit queries the FTL table based on the logical address to determine the physical address corresponding to the logical address, and calls the physical address the table PPA. The storage medium management unit determines the physical address managed and maintained by the storage medium management unit based on the table PPA, calls the physical address managed and maintained by the storage medium management unit the logical PPA, and provides the logical PPA to the storage command processing unit. The storage command processing unit generates a media interface command based on the logical PPA and sends it to the media interface controller; the media interface controller receives and processes the media interface command, determines the physical address corresponding to the NVM chip based on the logical PPA, calls it the real PPA, and generates a storage medium access command based on the real PPA to access the NVM chip based on the storage medium access command.

[0177] Three physical addresses are involved in the process of the control component processing an IO command such as sent by the host, namely the table PPA, the logical PPA, and the real PPA; continue to combine below Figure 4Introduce these three physical addresses. Table PPA is the physical address recorded by each entry in the FTL table in the memory. The effective lengths corresponding to table PPA of different NVM chips are different. For example, the number of bits of the effective length corresponding to table PPA is any value in the range of 31 to 37 bits. The size of table PPA is not fixed and is related to the storage capacity provided by the storage device. For example, if the storage device provides 16TB of physical storage space, the length of table PPA is at least 32 bits. In the memory, a 64-bit storage unit can be allocated for each entry in the FTL table, and a table PPA is recorded through the 64-bit storage unit. Since the length of table PPA is generally less than 64 bits, some storage resources will be wasted. To reduce the waste of storage resources, table PPA will be stored in a compressed form in the FTL table. For example, storage units are allocated based on the actual effective bit length of table PPA. If the effective length of table PPA is 31 bits, the size of each storage unit recording table PPA in the memory is also 31 bits instead of 64 bits. For the scheme and process of compressed storage of table PPA, refer to the Chinese patent application with the application number CN202011622162.0, which will not be elaborated here. The following mainly focuses on the case where table PPA is stored in a compressed form in the FTL table.

[0178] The logical PPA is the physical address managed and maintained by the storage medium management unit, which has a fixed size length (e.g., 64 bits). Due to differences in the number of logical units (LUNs) contained in different NVM chips, the number of planes in each LUN, the number of physical blocks, the physical page size, and the supported modes (such as the multi-plane mode), the logical PPA formats corresponding to different NVM chips are also different. As an example, to shield the complexity brought by the different logical PPA formats corresponding to different NVM chips, for different NVM chips, the logical PPA is described in the unified format of <LUN, Block, TU>. LUN represents the LUN number of the logical unit, Block represents the block number of the physical block, and TU represents the transfer unit number; among them, the transfer unit (TU) is the smallest unit for reading, and its size is, for example, 4 kB. The storage medium management unit manages the NVM chips according to the number of LUNs in the storage device, the number of Blocks corresponding to each LUN, and the number of TUs corresponding to the transferred data, without having to handle the differences in physical address formats caused by differences in the number of NVM chips, physical block sizes, programming methods, etc. Thus, based on the logical PPA with the specific format <LUN, Block, TU>, the storage medium management unit abstracts the logical PPAs corresponding to different NVM chips into a physical address space represented by the LUN number, Block number, and TU number, realizing the management of the storage space in the unified storage space organization method of <LUN, Block, TU>, rather than managing it separately according to the address format of each NVM chip, thereby avoiding the complexity brought by the differences of different NVM chips.

[0179] The real PPA is the physical address of the NVM chip. The size and format of the real PPA are determined by the specification parameters of the NVM chip. The real PPA may carry information such as plane, multi-plane, Page (physical page), chip type (such as TLC type), etc.

[0180] For another example, during the process of the storage device processing a write command sent by the host, the storage command processing unit in the control component receives the storage command, parses the storage command to obtain the logical address indicated by the storage command, and sends the logical address to the storage medium management unit. The storage medium management unit allocates a corresponding logical PPA for it based on the logical address, determines the corresponding table PPA based on the logical PPA, and records the table PPA in the corresponding entry of the FTL table stored in the memory. And the logical PPA is provided to the storage command processing unit, and the storage command processing unit generates a media interface command according to the logical PPA and sends it to the media interface controller; the media interface controller receives and processes the media interface command, determines the corresponding real PPA based on the logical PPA, generates a storage medium access command based on the real PPA, and accesses the NVM chip based on the storage medium access command.

[0181] During the process of the control component processing the IO command sent by the host, the conversion between three physical addresses is involved, such as the conversion between the table PPA and the logical PPA, and the conversion between the logical PPA and the real PPA. Figure 5 It is a schematic diagram of the mapping between the table PPA and the logical PPA. As an example, the table PPA recorded in each entry of the FTL table in DRAM is 36 bits. After the storage medium management unit obtains the table PPA, it expands it into a 64-bit logical PPA in a unified format. For example, the 0-27 bits in the logical PPA are filled with invalid data, and the 28-63 bits are filled with the information of the table PPA, thus realizing the conversion from the table PPA to the logical PPA.

[0182] Continue to refer to Figure 5 , during the process of the storage device processing the write command sent by the host, the storage medium management unit allocates a 64-bit logical PPA for the logical address indicated by the write command, extracts the data of the 28-63 bits from the logical PPA as its corresponding table PPA, and stores it in the corresponding entry in the FTL table, thus realizing the conversion from the logical PPA to the table PPA.

[0183] As an example, the real PPA format in the NVM chip is <LUN, Block, TU, Plane, Page>, where LUN represents the LUN number of the logical unit in the NVM chip; Block represents the physical block number in the NVM chip; TU represents the TU number in the NVM chip; Plane represents the plane number in the NVM chip; Page represents the physical page number in the NVM chip. When mapping the logical PPA <LUN, Block, TU> in a unified format to the real PPA required by the NVM chip, it is based on the mapping rule between the logical PPA and the real PPA.

[0184] For example, during the process of converting a logical PPA to a physical PPA, the block number corresponding to the physical PPA can be determined according to the block number corresponding to the logical PPA. For example, the block number corresponding to the logical PPA may be the same as the block number corresponding to the physical PPA. For example, each plane of an NVM chip includes 16 blocks, and the block numbers range from 0 to 15. In the logical PPA, 4 bits are used to represent a block, and the value range of the 4 bits is from 0 to 15. Then, the block numbers in the logical PPA range from 0 to 15. In this case, the block number corresponding to the physical PPA is the same as the block number corresponding to the logical PPA. Another example is that the block number corresponding to the logical PPA may not be the same as the block number corresponding to the physical PPA. For example, each plane of an NVM chip includes 500 blocks, and the block numbers range from 0 to 499. To represent 500 blocks, 9 bits are used to represent a block in the logical PPA, and the value range of the 9 bits is from 0 to 511. Since the block numbers in each plane range from 0 to 499, the blocks numbered 500 to 511 do not exist in the logical PPA.

[0185] For example, during the process of converting a logical PPA to a physical PPA, the LUN number corresponding to the physical PPA can be determined according to the LUN number corresponding to the logical PPA. For example, the LUN number corresponding to the logical PPA may be the same as the LUN number corresponding to the physical PPA. For example, a control component is connected to an NVM chip, and the NVM chip includes 2 LUNs. The LUN numbers corresponding to the NVM chip range from 0 to 1. The LUN numbers in the logical PPA also range from 0 to 1. In this case, the LUN number corresponding to the physical PPA is the same as the LUN number corresponding to the logical PPA. Another example is that the LUN number corresponding to the logical PPA may not be the same as the LUN number corresponding to the physical PPA. In this case, there is a specified mapping relationship between the LUN number corresponding to the physical PPA and the LUN number corresponding to the logical PPA, and the LUN number corresponding to the physical PPA is determined according to the specified mapping relationship.

[0186] Figure 6A Schematic diagram of the mapping relationship between the LUNs indicated by the logical PPA and the physical PPA provided in an embodiment of the present application.

[0187] For example, such as Figure 6AAs shown, the control component is connected to two NVM chips, namely NVM chip 0 and NVM chip 1. NVM chip 0 includes 4 LUNs, namely LUN0, LUN1, LUN2, and LUN3. NVM chip 1 also includes 4 LUNs, namely LUN0, LUN1, LUN2, and LUN3. These 8 LUNs are uniformly numbered as LUN 0 to LUN7 in the logical PPA. For example, LUN 1, LUN 3, LUN 5, and LUN 7 in the logical PPA correspond to the 4 LUNs in NVM chip 1, and LUN 0, LUN 2, LUN 4, and LUN 6 in the logical PPA correspond to the 4 LUNs in NVM chip 0. For instance, LUN 1 in the logical PPA corresponds to LUN0 in NVM chip 1, LUN 3 in the logical PPA corresponds to LUN1 in NVM chip 1, LUN 5 in the logical PPA corresponds to LUN2 in NVM chip 1, LUN 7 in the logical PPA corresponds to LUN3 in NVM chip 1, LUN 0 in the logical PPA corresponds to LUN0 in NVM chip 0, LUN 2 in the logical PPA corresponds to LUN1 in NVM chip 0, LUN 4 in the logical PPA corresponds to LUN2 in NVM chip 0, and LUN 6 in the logical PPA corresponds to LUN3 in NVM chip 0.

[0188] Figure 6B Schematic diagram of the mapping relationship between the LUNs indicated by the logical PPA and the real PPA provided by another embodiment of this application.

[0189] By way of example, such as Figure 6BAs shown in the figure, the control component is connected to 4 NVM chips. Each NVM chip includes 2 LUNs, namely LUN0 and LUN1. In the logical PPA, these 8 LUNs are uniformly numbered as LUN 0 to LUN7. LUN 0 and LUN4 in the logical PPA correspond to the two LUNs in NVM chip 0. For example, LUN 0 in the logical PPA corresponds to LUN0 in NVM chip 0, and LUN 4 in the logical PPA corresponds to LUN1 in NVM chip 0; LUN 1 and LUN 5 in the logical PPA correspond to the two LUNs in NVM chip 1. For example, LUN 1 in the logical PPA corresponds to LUN0 in NVM chip 1, and LUN 5 in the logical PPA corresponds to LUN1 in NVM chip 1; LUN 2 and LUN 6 in the logical PPA correspond to the two LUNs in NVM chip 2. For example, LUN 2 in the logical PPA corresponds to LUN0 in NVM chip 2, and LUN 6 in the logical PPA corresponds to LUN1 in NVM chip 2; LUN 3 and LUN 7 in the logical PPA correspond to the two LUNs in NVM chip 3. For example, LUN 3 in the logical PPA corresponds to LUN0 in NVM chip 3, and LUN 7 in the logical PPA corresponds to LUN1 in NVM chip 3.

[0190] In order to shield the complexity brought by the different logical PPA formats corresponding to different NVM chips, the logical PPA is unified into the <LUN, Block, TU> format. Based on this format, for example, information such as Plane, Page, and TU in the NVM chip is unified into the TU information in the logical PPA. Therefore, when converting the logical PPA into the real PPA, it is necessary to determine information such as Plane, Page, and TU in the real PPA according to the TU information in the logical PPA. For different NVM chips, the address formats used for the media interface commands corresponding to the programming operations are different, and the data volumes transmitted are different. The different data volumes transmitted by the media interface controller will cause the lengths occupied by information such as TU in the logical PPA corresponding to different NVM chips to be different, which will still bring differences in the logical PPA format. In order to avoid the differences brought by the different data volumes transmitted by the media interface commands, the embodiment of the present application introduces Write Unit to represent the data volume transmitted by the media interface commands. Write Unit is a set of the minimum number of transfer units (Transfer Unit, TU) that a media interface command indicating a write operation can transmit. For example, WriteUnit includes 24 consecutive TUs or 48 TUs, etc. The TU numbers in the logical PPA are uniformly represented by the TU numbers within the Write Unit.

[0191] For example, taking an NVM chip of TLC type as an example, a single programming command depends on different programming modes (one-shot Program / two-Pass Program), and 3 pages / 2 pages of data will be written in a single programming. In an NVM chip that supports MultiPlane operation, the number of physical pages carried by a single programming command is a multiple of 3 pages / 2 pages (determined by the number of planes in the LUN). Therefore, due to differences in programming modes and NVM chip specifications (such as physical page size, the number of planes corresponding to the logical unit, and NVM chip type), the amount of data required for a single programming command corresponding to different NVM chips is different. And the amount of data required for a single programming command depends on the amount of data transmitted by the media interface command. Therefore, for different NVM chips, the amount of data transmitted by the media interface command corresponding to the execution of the programming operation is different.

[0192] The control component uses Write Unit to uniformly manage the amount of data to be transmitted by the media interface command. Regardless of the differences in the amount of data to be transmitted by the programming commands received by the NVM chip, in the control component (such as the storage command processing unit or the media interface controller), the amount of data to be transmitted by the media interface command is regarded as Write Unit, and it manages and operates according to WriteUnit, thereby avoiding the differences in the amount of data transmitted by the media interface command brought about by different NVM chips.

[0193] To adapt to NVM chips of different specifications, the size of the Write Unit needs to consider the data transfer volume of a single programming command corresponding to NVM chips of different specifications. As an example, obtain the data transfer volumes of single programming commands corresponding to multiple NVM chips of different specifications, and determine the data transfer volume corresponding to the Write Unit according to the least common multiple of the data transfer volumes of multiple single programming commands. For example, the data transfer volumes of single programming commands corresponding to 3 NVM chips of different specifications (such as NVM Chip 1, NVM Chip 2, and NVM Chip 3) are 64K, 128K, and 192K respectively. Calculate the least common multiple 384 based on the three data transfer volumes, then the data transfer volume corresponding to the Write Unit is 384K. When operating NVM Chip 1, one WriteUnit generates 6 programming commands; when operating NVM Chip 2, one Write Unit generates 3 programming commands; when operating NVM Chip 3, one Write Unit generates 2 programming commands. In this way, when changing the NVM chip, the control component does not need to redefine the size of the Write Unit, shielding the differences brought by different NVM chips. Of course, other methods can also be used to determine the size of the Write Unit, not limited to the method of finding the least common multiple listed above. Among them, after determining the data transfer volume corresponding to the Write Unit, determine the number of TUs corresponding to the Write Unit based on the ratio of the data transfer volume corresponding to the Write Unit to the data transfer volume corresponding to a single TU (such as 4K).

[0194] Figure 7 Shows a schematic diagram of the Write Unit provided by this application.

[0195] As an example, such as Figure 7 As shown, a LUN includes 2 Planes (such as Plane0 and Plane1), the NVM chip is of TLC type. Write data to WL a (including physical page 0 corresponding to MSB, physical page 1 corresponding to CSB, and physical page 2 corresponding to LSB) of physical block 0-0 of Plane0 of a certain LUN and write data to WL a of physical block 1-0 of Plane1 of the same LUN based on the media interface command indicating the write operation. The data transfer volume corresponding to the Write Unit is the sum of the data amounts corresponding to WL a of physical block 0-0 and physical block 1-0.

[0196] As another example, the Write Unit may include multiple TUs, and the TU numbers in the Write Unit are not necessarily the same as the TU numbers in the NVM chip, so that the TU numbers in the logical PPA are different from the TU numbers in the NVM chip. For example, the TU numbers in the Write Unit are continuously numbered according to the number of TUs included in the Write Unit, and the TU numbers in the NVM chip can be numbered according to physical pages. For example, if the Write Unit includes 24 TUs, the TU numbers included in the Write Unit are TU0 to TU23; each physical page in the NVM chip includes 4 TUs, and the TU numbers corresponding to the NVM chip are, for example, physical block 0, physical page 0, TU0; physical block 0, physical page 0, TU1; physical block 0, physical page 0, TU2; physical block 0, physical page 0, TU3. In order to map the TUs in the Write Unit to the TUs in the NVM chip. The embodiment of the present application also provides a mapping relationship between the TUs in the Write Unit and the TUs in the NVM chip. Figure 8A Shows a mapping schematic diagram between the TUs of the logical PPA provided by an embodiment of the present application and the TUs of the real PPA.

[0197] As an example, such as Figure 8AAs shown, the Write Unit includes 24 TUs with consecutive numbers, numbered TU0 to TU23. The Write Unit corresponds to physical pages 0, 1, and 2 in physical block 0-0 of LUN0, Plane0 of the NVM chip, and also corresponds to physical pages 0, 1, and 2 in physical block 1-0 of LUN0, Plane1 of the NVM chip. Each physical page in the NVM chip includes 4 TUs, numbered TU0' to TU3'. For example, the mapping relationship between the 24 TUs in the Write Unit and the TUs in the NVM chip corresponding to the Write Unit is as follows: TU0 corresponds to TU0' in physical page 0 of Plane0, TU2 corresponds to TU1' in physical page 0 of Plane0, TU4 corresponds to TU2' in physical page 0 of Plane0, TU6 corresponds to TU3' in physical page 0 of Plane0; TU1 corresponds to TU0' in physical page 0 of Plane1, TU3 corresponds to TU1' in physical page 0 of Plane1, TU5 corresponds to TU2' in physical page 0 of Plane1, TU7 corresponds to TU3' in physical page 0 of Plane1; TU8 corresponds to TU0' in physical page 1 of Plane0, TU10 corresponds to TU1' in physical page 1 of Plane0, TU12 corresponds to TU2' in physical page 1 of Plane0, and TU14 corresponds to TU3' in physical page 1 of Plane0; TU16 corresponds to TU0' in physical page 2 of Plane0, TU18 corresponds to TU1' in physical page 2 of Plane0, TU20 corresponds to TU2' in physical page 2 of Plane0, and TU22 corresponds to TU3' in physical page 2 of Plane0; TU9 corresponds to TU0' in physical page 1 of Plane1, TU11 corresponds to TU1' in physical page 1 of Plane1, TU13 corresponds to TU2' in physical page 1 of Plane1, and TU15 corresponds to TU3' in physical page 1 of Plane1; TU17 corresponds to TU0' in physical page 2 of Plane1, TU19 corresponds to TU1' in physical page 2 of Plane1, TU21 corresponds to TU2' in physical page 2 of Plane1, and TU23 corresponds to TU3' in physical page 2 of Plane1. Among them, the mapping relationship between TU8 to TU23 and the TUs in the NVM chip is not marked in Figure 8A is not marked.

[0198] As another example, if the logical PPA is <LUN0, Block1-0, TU15>, when converting the logical PPA to the real PPA, if the LUN number in the logical PPA is the same as the LUN number in the real PPA, and the Block numbers are also the same, then the LUN number of the real PPA is determined to be LUN0 and the Block number is Block1-0 based on LUN0 and Block1-0 in the logical PPA. Since the TU of the logical PPA is 15, based on Figure 8A the mapping relationship in it, it can be seen that TU15 is mapped to TU3' in physical page 1 of Plane1. Then the Plane number of the real PPA is Plane1, the Page number is physical page 1, and the TU number is TU3'. At this point, the real PPA can be determined to be <LUN0, Block1-0, TU3', Plane1, Page1>.

[0199] As another example, Figure 8B shows a mapping schematic diagram between the TU of the logical PPA provided by another embodiment of the present application and the TU of the real PPA. As Figure 8BAs shown, the Write Unit includes 48 TUs with consecutive numbers, numbered TU0 to TU47. The Write Unit corresponds to physical pages 0, 1, and 2 in physical block 0-0 of LUN0, Plane0 of the NVM chip, to physical pages 0, 1, and 2 in physical block 1-0 of LUN0, Plane1 of the NVM chip, to physical pages 0, 1, and 2 in physical block 2-0 of LUN0, Plane2 of the NVM chip, and to physical pages 0, 1, and 2 in physical block 3-0 of LUN0, Plane3 of the NVM chip. Each physical page in the NVM chip includes 4 TUs, numbered TU0' to TU3'. For example, the mapping relationship between the 48 TUs in the Write Unit and the TUs in the NVM chip corresponding to the Write Unit is as follows: TU0 corresponds to TU0' in physical page 0 of Plane0, TU4 corresponds to TU1' in physical page 0 of Plane0, TU8 corresponds to TU2' in physical page 0 of Plane0, TU12 corresponds to TU3' in physical page 0 of Plane0; TU1 corresponds to TU0' in physical page 0 of Plane1, TU5 corresponds to TU1' in physical page 0 of Plane1, TU9 corresponds to TU2' in physical page 0 of Plane1, TU13 corresponds to TU3' in physical page 0 of Plane1; TU2 corresponds to TU0' in physical page 0 of Plane2, TU6 corresponds to TU1' in physical page 0 of Plane2, TU10 corresponds to TU2' in physical page 0 of Plane2, TU14 corresponds to TU3' in physical page 0 of Plane2; TU3 corresponds to TU0' in physical page 0 of Plane3, TU7 corresponds to TU1' in physical page 0 of Plane3, TU11 corresponds to TU2' in physical page 0 of Plane3, TU15 corresponds to TU3' in physical page 0 of Plane3.

[0200] TU16 corresponds to TU0' in physical page 1 of Plane0, TU20 corresponds to TU1' in physical page 1 of Plane0, TU24 corresponds to TU2' in physical page 1 of Plane0, TU28 corresponds to TU3' in physical page 1 of Plane0; TU17 corresponds to TU0' in physical page 1 of Plane1, TU21 corresponds to TU1' in physical page 1 of Plane1, TU25 corresponds to TU2' in physical page 1 of Plane1, TU29 corresponds to TU3' in physical page 1 of Plane1; TU18 corresponds to TU0' in physical page 1 of Plane2, TU22 corresponds to TU1' in physical page 1 of Plane2, TU26 corresponds to TU2' in physical page 1 of Plane2, TU30 corresponds to TU3' in physical page 1 of Plane2; TU19 corresponds to TU0' in physical page 1 of Plane3, TU23 corresponds to TU1' in physical page 1 of Plane3, TU27 corresponds to TU2' in physical page 1 of Plane3, TU31 corresponds to TU3' in physical page 1 of Plane3. TU32 corresponds to TU0' in physical page 2 of Plane0, TU36 corresponds to TU1' in physical page 2 of Plane0, TU40 corresponds to TU2' in physical page 2 of Plane0, TU44 corresponds to TU3' in physical page 2 of Plane0; TU33 corresponds to TU0' in physical page 2 of Plane1, TU37 corresponds to TU1' in physical page 2 of Plane1, TU41 corresponds to TU2' in physical page 2 of Plane1, TU45 corresponds to TU3' in physical page 2 of Plane1; TU34 corresponds to TU0' in physical page 2 of Plane2, TU38 corresponds to TU1' in physical page 2 of Plane2, TU42 corresponds to TU2' in physical page 2 of Plane2, TU46 corresponds to TU3' in physical page 2 of Plane2; TU35 corresponds to TU0' in physical page 2 of Plane3, TU39 corresponds to TU1' in physical page 2 of Plane3, TU43 corresponds to TU2' in physical page 2 of Plane3, TU47 corresponds to TU3' in physical page 2 of Plane3. Among them, the mapping relationship between TU16~TU47 and TU in the NVM chip is not marked in Figure 8B is not marked.

[0201] As another example, if the logical PPA is <LUN0, Block2-0, TU10>, when converting the logical PPA to the real PPA, if the LUN number in the logical PPA is the same as the LUN number in the real PPA and the Block numbers are also the same, then the LUN number of the real PPA is determined to be LUN0 and the Block number is Block2-0 based on LUN0 and Block2-0 in the logical PPA. Since the TU of the logical PPA is 10, based on Figure 8B the mapping relationship in it, it can be known that TU10 is mapped to TU2' in physical page 0 of Plane2. Then the Plane number of the real PPA is Plane2, the Page number is physical page 0, and the TU number is TU2'. At this point, the real PPA can be determined to be <LUN0, Block2-0, TU2', Plane2, Page0>.

[0202] For table PPA, logical PPA, and real PPA, there is a mapping relationship among these three physical addresses. As Figure 9 shown, the table PPA is mapped and transformed into the logical PPA, and the logical PPA is mapped and transformed into the real PPA. Through two PPA mappings, regardless of the specifications of the NVM chips (the size of the table PPA corresponds to the storage space provided by all NVM chips on the storage device), the table PPA with variable size (different formats) can be mapped into the logical PPA with a unified format, and then the logical PPA with a unified format can be mapped into the real PPA required by the NVM chips, which can achieve compatibility with more NVM chips.

[0203] Since the logical PPA describes the physical address in the form of <LUN, Block, TU>, the storage medium management unit manages the storage space in this unified storage space organization mode of <LUN, Block, TU>, rather than managing it separately according to the address format of each NVM chip. The real PPA is used to access the NVM chip. When the NVM chip is switched, it is directly associated with the real PPA, and the real PPA is generated in the media interface controller. Therefore, it is necessary to modify the media interface controller based on the change of the NVM chip. Most components in the control unit manage and use the storage resources provided by the NVM chip in a unified manner (that is, manage the storage space based on the unified storage space organization mode of <LUN, Block, TU>) without adjustment, thereby reducing the development cost and delivery time introduced by adapting to new NVM chips.

[0204] Figure 10 Fig. shows a schematic structural diagram of a control unit provided by an embodiment of the present application.

[0205] As an example, such as Figure 10As shown, the control component is coupled to a memory (such as DRAM) and at least one NVM chip, where the memory is used to store the FTL table. The control component includes a storage command processing unit, a storage medium management unit, and a media interface controller. The media interface controller includes a media interface command processing unit and a LUN controller. The media interface command processing unit includes a Common layer processing unit (referred to as the Common layer for short) and a Flash abstraction layer processing unit (referred to as the Flash abstraction layer for short). The Common layer provides an interface for docking with the storage command processing unit, and through this interface, receives a media interface command carrying a logical PPA sent by the storage command processing unit. The media interface command is a media interface command indicating, for example, a read operation, a write operation, or an Erase operation, and the media interface command carries a logical PPA.

[0206] The Common layer processes the media interface command to generate a Flash abstraction layer command. The Flash abstraction layer command carries a logical PPA and can indicate, for example, a read operation, a write operation, or an erase operation. The Common layer provides the Flash abstraction layer command to the Flash abstraction layer. The Flash abstraction layer converts the Flash abstraction layer command into a LUN controller command (such as indicating a read operation, a write operation, or an erase operation), converts the logical PPA into a real PPA, and sends the LUN controller command carrying the real PPA to the LUN controller. In the media interface controller, the conversion of the logical PPA to the real PPA is performed by the Flash abstraction layer. The Flash abstraction layer docks with the LUN controller and sends the LUN controller command to the LUN controller. The LUN controller generates a storage medium access command (indicating a read operation, a programming operation, or an erase operation) based on the LUN controller command, and accesses the NVM chip based on the storage medium access command to implement reading data from the storage space of the NVM chip, writing data to the storage space, or erasing data in the storage space.

[0207] As an example, for the media interface command indicating a read operation received by the Commom layer, there are various command types. For example, the command types include reading 4K, reading a physical page Page, or reading a multi-plane physical page MultiPlane Page. For different command types, the number of TUs to be read indicated by them is different. For example, reading 4K corresponds to one TU, reading Page corresponds to 4 TUs belonging to the same physical page, and reading MultiPlane Page corresponds to multiple TUs from multiple physical pages in different Planes, such as 16 TUs for 4 physical pages.

[0208] As another example, for the media interface command indicating a write operation received by the Commom layer, since the embodiments of the present application use Write Unit to represent the data volume transmitted by the media interface command indicating a write operation, the operation object of the media interface command indicating a write operation is Write Unit. Another example is that the erasure operation of the NVM chip is performed in units of large blocks. Therefore, when the Commom layer receives a media interface command indicating an erasure operation, its operation object is a large block.

[0209] When the Commom layer converts the media interface command into a Flash abstraction layer command, it corresponds to the following three cases:

[0210] For the media interface command indicating a read operation, when the Common layer converts it into a Flash abstraction layer command, it parses the media interface command and repackages it into a command format recognizable by the Flash abstraction layer to obtain the Flash abstraction layer command A, and sends it to the Flash abstraction layer.

[0211] For the media interface command indicating a write operation, the Common layer determines how many programming commands are actually required to complete the programming operation of the Write Unit according to the current configuration of the NVM chip (such as the type of NVM chip, supported programming mode, physical page size, and the number of planes corresponding to the LUN), and generates the corresponding number of commands recognizable by the Flash abstraction layer according to the required programming commands, such as the Flash abstraction layer command B. For example, if 1 programming command is required, the Common layer will generate a Flash abstraction layer command B and send it to the Flash abstraction layer. The Flash abstraction layer generates a LUN controller command according to the Flash abstraction layer command B and sends it to the LUN controller. The LUN controller generates a programming command according to the LUN controller command and sends it to the NVM chip, and completes the programming operation of the Write Unit according to the programming command. Another example is that if 2 programming commands are required, the Common layer will generate two Flash abstraction layer commands B and send them to the Flash abstraction layer. The Flash abstraction layer generates the corresponding LUN controller commands according to each Flash abstraction layer command B and sends them to the LUN controller. The LUN controller generates the corresponding programming commands according to each LUN controller command and sends them to the NVM chip; the NVM chip completes the programming operation of the Write Unit according to each programming command.

[0212] For the media interface command indicating an erase operation, the operation object corresponding to the media interface command received by the Common layer is a large block, and the large block includes multiple physical blocks. Therefore, the Common layer needs to generate corresponding Flash abstraction layer commands C (each Flash abstraction layer command C indicates a physical block) based on each physical block included in the large block and send them to the Flash abstraction layer.

[0213] As another example, in addition to converting the media interface command into a Flash abstraction layer command, the Commom layer also has an error handling function. For example, when a read operation reads data incorrectly, the Common layer initiates a reread operation. For example, the Common layer will initiate a reread operation, and the reread methods include read retry or soft read, etc., to achieve rereading. Another example is that after the Flash abstraction layer sends the LUN controller command to the LUN controller, the Common layer also obtains the processing status of the Flash abstraction layer command sent by the Flash abstraction layer. After the Flash abstraction layer command is processed, it reads data from the NVM chip and stores the processing result. When the data reading from the NVM chip is completed (the command is processed), the Common layer generates and returns a command processing completion message to the storage command processing unit.

[0214] As another example, for the erase operation, the Common layer can also return the execution status of the erase operation. For example, the Common layer collects the physical block erase status of the large block and returns an erase completion message after all physical blocks of the large block are erased.

[0215] The Flash abstraction layer in the media interface command processing unit of the media interface controller is used to receive Flash abstraction layer commands indicating read operations, write operations, or erase operations, and convert the Flash abstraction layer commands into LUN controller commands. Among them, the LUN controller command indicates the real PPA, and the conversion of the logical PPA to the real PPA is achieved by the Flash abstraction layer.

[0216] As an example, the Flash abstraction layer provides an interface to the Common layer. Through this interface, the Flash abstraction layer can receive, for example, Flash abstraction layer command A sent by the Common layer, which indicates a read operation. The command type can be read 4K, read Page, or read MultiPlane Page. The Flash abstraction layer can also receive Flash abstraction layer command B sent by the Common layer, which indicates a write operation. The types of programming operations indicated by Flash abstraction layer command B include, for example, MultiPlane Program, one-shot Program, and Two-Pass Program. If the NVM chip supports one shot program, the corresponding Flash abstraction layer command B of the Flash abstraction layer corresponds to a Write Unit. If the NVM chip supports two-pass program, for one write Unit, 2 Flash abstraction layer commands B are generated and sent to the Flash abstraction layer. The two Flash abstraction layer commands B correspond to one Write Unit.

[0217] When converting the Flash abstraction layer command into a LUN controller command, for a read operation, the corresponding Flash abstraction layer command A is converted into LUN controller command M1 and sent to the LUN controller. The LUN controller processes LUN controller command M1 to generate a storage medium access command 1 (read command), and sends the storage medium access command 1 to the corresponding logical unit through the LUN controller to perform a read operation. For a write operation, the corresponding Flash abstraction layer command B is converted into LUN controller command M2 and sent to the LUN controller. The LUN controller processes LUN controller command M2 to generate a storage medium access command 2 (programming command), and sends the storage medium access command 2 to the corresponding logical unit through the LUN controller, and performs a programming operation on the physical page in the logical unit according to the storage medium access command 2. For an erase operation, the corresponding Flash abstraction layer command C is converted into LUN controller command M3 and sent to the LUN controller. The LUN controller processes LUN controller command M3 to generate a storage medium access command 3 (erase command), and sends the storage medium access command 3 to the corresponding logical unit through the LUN controller to perform a large block erase operation.

[0218] The following introduces the specific implementation processes of the read operation, write operation, and erase operation through specific examples.

[0219] Figure 11 It is a flowchart for accessing the NVM chip based on a read operation.

[0220] As Figure 11As shown, the storage command processing unit receives a storage command indicating a read operation. In response to the storage command, it parses the storage command to obtain the LBA indicated by the storage command. The storage medium management unit calculates the address of the DRAM based on the LBA, indexes to the corresponding entry in the FTL table according to the address of the DRAM, and obtains the table PPA corresponding to the LBA from the corresponding entry. The storage medium management unit adds an invalid bit to the table PPA to obtain a logical PPA corresponding to a 64-bit, unified format. The storage command processing unit receives the logical PPA, generates a media interface command indicating a read operation based on the logical PPA, and sends the media interface command carrying the logical PPA to the media interface controller. The Common layer in the media interface controller receives the media interface command based on the unified interface to the storage command processing unit. The media interface command, for example, indicates a read of 4K, a read of a Page, or a read of a MultiPlane Page. The Common layer converts the received media interface command into a Flash abstraction layer command recognizable by the Flash abstraction layer and carrying the logical PPA, and sends it to the Flash abstraction layer. The Flash abstraction layer parses the received Flash abstraction layer command to obtain the logical PPA, converts the logical PPA into a real PPA, generates a LUN controller command based on the real PPA, and sends the LUN controller command to the LUN controller. The LUN controller generates a storage medium access command carrying the real PPA based on the received LUN controller command, and sends the storage medium access command to the corresponding LUN to read the data within the corresponding physical page based on the real PPA.

[0221] During the above read operation process, the Common layer can also obtain the processing status of the Flash abstraction layer command. After the Flash abstraction layer command is processed, it receives the read data from the NVM chip and stores the processing result as the response to the storage command. The Common layer can also identify whether there are uncorrectable errors in the read data and, if necessary, initiate a reread operation. The reread methods include read retry or soft read, etc., to achieve rereading. In the reread process, the Common layer generates one or more Flash abstraction layer commands to provide to the Flash abstraction layer and obtains the data output by the NVM chip.

[0222] Figure 12 It is a flowchart for accessing the NVM chip based on a write operation.

[0223] As Figure 12As shown, the storage command processing unit receives a storage command indicating a write operation. In response to this storage command, it parses the storage command to obtain the LBA indicated by the storage command. The storage medium management unit assigns a logical PPA to the LBA, calculates the address of the DRAM based on the LBA, indexes to the corresponding entry in the FTL table according to the address of the DRAM, and processes the logical PPA to obtain a table PPA, and stores the table PPA in the corresponding entry. After the storage command processing unit waits for all TUs of the Write Unit to be allocated, it generates a media interface command indicating a write operation and sends this media interface command to the Common layer in the media interface controller, and this command indicates the Write Unit for example. If the NVM chip coupled to the current control component accepts one-shot Program, it generates 1 Flash abstraction layer command (carrying the logical PPA) according to the media interface command and sends it to the Flash abstraction layer; if the NVM chip coupled to the current control component accepts two-pass Program, it generates 2 Flash abstraction layer commands according to the media interface command and sends them to the Flash abstraction layer. The Flash abstraction layer parses the received Flash abstraction layer command to obtain the logical PPA, converts the logical PPA into a real PPA, generates a LUN controller command according to the real PPA, and sends the LUN controller command to the corresponding LUN controller. The LUN controller generates a storage medium access command (programming command) carrying the real PPA according to the received LUN controller command, and sends the storage medium access command to the corresponding LUN to perform a programming operation on the physical page in the logical unit and write data to the physical page based on the real PPA.

[0224] Figure 13 It is a flowchart for accessing the NVM chip based on an erase operation.

[0225] As Figure 13As shown, the storage command processing unit provides a media interface command indicating an erase operation to the Common layer in the media interface controller. This command, for example, indicates erasing a large block. The Common layer parses the media interface command to determine the multiple physical blocks included in the large block, generates corresponding Flash abstraction layer commands (carrying logical PPA) for each physical block, and sends them to the Flash abstraction layer. The Flash abstraction layer parses the received Flash abstraction layer command to obtain the logical PPA, converts the logical PPA to a real PPA, generates a LUN controller command based on the real PPA, and sends the LUN controller command to the LUN controller. The LUN controller generates a storage media access command (erase command) carrying the real PPA based on the received LUN controller command, and sends the storage media access command to the corresponding LUN to perform an erase operation on the physical blocks in the logical unit based on the real PPA.

[0226] Among them, the Common layer can also obtain the erase status of the physical blocks corresponding to the issued Flash abstraction layer commands. After all the physical blocks corresponding to the large block are erased, it returns an erase completion message.

[0227] The Commom layer is connected to the storage command processing unit. It provides a unified interface to the storage command processing unit through the Common layer. And for the logical PPA carried in the media interface commands sent to the Commom layer in different NVM chip control components, they are organized in a unified format <LUN, Block, TU>. Therefore, other units outside the media interface controller in the control component cannot perceive the differences brought by different NVM chips, and for the logical PPA formats carried in the media interface commands received by the Commom layer for different NVM chips are unified, so it also cannot perceive the differences brought by different NVM chips. Furthermore, it can shield the differences brought by coupling different NVM chips. The processing of the media interface command and the conversion of the logical PPA to the real PPA are done in the Commom layer and the Flash abstraction layer in the media interface controller. Therefore, when replacing the NVM chip, only the Commom layer or the Flash abstraction layer needs to be modified, realizing the modification of a small part of the components in the control component. Most components in the control component manage and use the storage resources provided by the NVM chip in a unified manner (based on the unified storage space organization method of <LUN, Block, TU>) without modification, achieving a reduction in the development cost and delivery time introduced by adapting to the new NVM chip.

[0228] The following introduces the process of making relevant modifications when the NVM chip coupled to the control component is switched.

[0229] For example, when replacing the NVM chip, if the type of programming operation changes, the type of programming operation indicated by the Flash abstraction layer command generated by the Common layer and sent to the Flash abstraction layer will change. For example, if the previous NVM chip supported one-shot Program and the current NVM chip supports two-pass Program, when the Common layer generates the Flash abstraction layer command, the type of programming operation encapsulated in the command will change from one-shot Program to two-pass Program. In this case, the modification is made in the Common layer.

[0230] Again, for example, when replacing the NVM chip, if the number of planes corresponding to the LUN changes, the number of programming commands generated by the Flash abstraction layer will change. As an example, for the previous NVM chip 1, each LUN included 2 planes, and for each write command, 6 pages (sized, for example, 96KB) needed to be operated on. For the replaced NVM chip 2, each LUN includes 4 planes, and for each write command, 12 pages (sized, for example, 192KB) need to be operated on. If the size of the Write Unit is 384KB, then for NVM chip 1, 4 programming commands are needed to write 96 * 4KB of data, and for NVM chip 2, 2 programming commands are needed to write 192 * 2KB of data. Among them, the number of physical pages to be operated on by each write command is determined by the characteristics of the NVM chip itself. In this case, the modification is made in the Flash abstraction layer.

[0231] For example, if the actual PPA formats supported by different NVM chips are different, when the NVM chip is replaced, the actual PPA format generated by the Flash abstraction layer will change. Specifically, for a certain NVM chip corresponding to a definite actual PPA format, the actual PPA format supported by the NVM chip can be obtained by querying the relevant manual. Based on this format, the Flash abstraction layer can convert the logical PPA to the actual PPA. In this case, the modification is made in the Flash abstraction layer.

[0232] Again, for example, if the command formats supported by different NVM chips are different, when the NVM chip is replaced, the format of the storage medium access command generated by the Flash abstraction layer will change to access the NVM chip with a storage medium access command with a compatible format. In this case, the modification is made in the Flash abstraction layer.

[0233] When replacing the NVM chip, if the physical page size changes, the number of programming commands generated by the Flash abstraction layer changes. For example, before replacing the NVM chip 1, each LUN includes 2 planes, and for each write command, 6 pages need to be operated (the size is, for example, 96KB, and the physical page size is 16KB). After replacing with the NVM chip 2, each LUN includes 2 planes, and for each write command, 6 pages need to be operated (the size is, for example, 192KB, and the physical page size is 32KB). If the size of the WriteUnit is 384KB, then for the NVM chip 1, 4 programming commands are required to write 96 * 4KB of data, and for the NVM chip 2, 2 programming commands are required to write 192 * 2KB of data. In this case, the modification is made in the Flash abstraction layer.

[0234] When replacing the NVM chip, if the type of the NVM chip changes, it may cause changes in the physical page size and the number of planes. In this case, the modification is made in the Flash abstraction layer. If only the type of the programming operation changes, the modification is made in the Common layer.

[0235] From the above content, it can be seen that for two NVM chips before and after, if only the geometric features change (such as the physical page size and the number of planes change), but the programming mode remains unchanged, then the Common layer does not need to be modified, and only the Flash abstraction layer needs to be modified; for two NVM chips before and after, if only the programming mode changes and the geometric features remain unchanged, then only the Common layer is modified, and the Flash abstraction layer does not need to be modified.

[0236] For the adaptation when the NVM chip changes, for example, as Figure 14 shown, the Flash abstraction layer includes a Flash instance module and a PPA conversion module; the PPA conversion module is an algorithm module for generating the real PPA adapted to the current NVM chip, and the Flash instance module is used to provide the configuration information for generating the currently used NVM chip. For example, the real PPA format accepted by the NVM chip, the geometric features of the NVM chip (the number of LUNs included in the NVM chip, the number of planes / blocks in the LUN, the number of WL / pages in the block, the page size, etc.). The PPA conversion module uses this information to perform the conversion from the logical PPA to the real PPA. The Flash instance module also provides such as the timing parameters and initialization sequence supported by the current NVM chip. When the NVM chip changes, for the modification of the Flash abstraction layer, only the Flash instance module and the PPA conversion module need to be modified, and other parts do not need to be modified.

[0237] Since the storage medium management unit manages the storage space according to <LUN, Block, TU>, when the NVM chip is switched, the value ranges of LUN / Block / TU can be modified. The change in the value ranges of LUN / Block / TU represents the change in the physical storage space size, without the need to perceive the change in the geometric features of the NVM chip. Moreover, since the interface provided by the Common layer for the storage command processing unit remains unchanged, the storage command processing unit does not need to perceive the change in the NVM chip.

[0238] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments as well as all changes and modifications falling within the scope of the present application. Obviously, those skilled in the art can make various changes and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A data access method, characterized in that, Including: In response to the received storage command, processing the storage command to generate a media interface command carrying a logical PPA, wherein the logical PPA has a unified format for different NVM chips; Processing the media interface command, and determining the real PPA corresponding to the logical PPA based on the first mapping relationship between the logical PPA and the real PPA; wherein, the real PPA is the physical address of the NVM chip; Generating a storage medium access command according to the real PPA, and accessing the NVM chip based on the storage medium access command.

2. The method according to claim 1, wherein The unified format of the logical PPA is <LUN, Block, TU>, where LUN represents the first logical unit number, Block represents the first physical block number, and TU represents the first transmission unit number.

3. A control component, characterized in that, Including a storage command processing unit, a storage medium management unit, and a media interface controller; The storage command processing unit receives a storage command and obtains the logical address carried by the storage command; The storage medium management unit receives the logical address, determines the logical PPA based on the logical address, and sends it to the storage command processing unit, wherein the logical PPA is the physical address of the storage space of the NVM chip managed and maintained by the storage medium management unit, and the logical PPA has a unified format for different NVM chips; The storage command processing unit generates a media interface command carrying the logical PPA based on the logical PPA; The media interface controller receives the media interface command, in response to the media interface command, determines the real PPA corresponding to the logical PPA based on the first mapping relationship between the logical PPA and the real PPA, generates a storage medium access command according to the real PPA, and accesses the NVM chip based on the storage medium access command; wherein, the real PPA is the physical address of the NVM chip.

4. The control component according to claim 3, characterized in that, The media interface controller includes a media interface command processing unit and a LUN controller. The media interface command processing unit includes a Common layer processing unit and a Flash abstraction layer processing unit. The Common layer processing unit provides a unified interface to the storage command processing unit to receive the media interface command sent by the storage command processing unit. The Flash abstraction layer processing unit provides interfaces for docking with the Common layer processing unit and the LUN controller respectively; The Common layer processing unit processes the media interface command to generate a Flash abstraction layer command carrying the logical PPA, wherein the format of the Flash abstraction layer command is different from that of the media interface command; The Flash abstraction layer processing unit receives the Flash abstraction layer command, processes the Flash abstraction layer command, converts the logical PPA into the real PPA, generates a LUN controller command carrying the real PPA, and sends the LUN controller command to the LUN controller; The LUN controller generates a storage medium access command according to the LUN controller command carrying the true PPA, and accesses the NVM chip based on the storage medium access command.

5. The control component according to claim 4, wherein The Common layer processing unit generates a first Flash abstraction layer command according to the media interface command in response to receiving a media interface command indicating a read operation, where the type of the media interface command includes indicating reading 4KB of data, reading data of one physical page (Page), or reading data of a multi-plane physical page (Multiplane Page).

6. The control component according to claim 4 or 5, characterized in that, The storage command processing unit sends a media interface command indicating a write operation in accordance with the WriteUnit; wherein the Write Unit is a set of the minimum number of transmission units (TUs) that a media interface command indicating a write operation can transmit.

7. The control component according to claim 6, wherein The Common layer processing unit generates at least one second Flash abstraction layer command according to the Write Unit indicated by the media interface command in response to receiving a media interface command indicating a write operation.

8. The control component according to claim 4, wherein The Common layer processing unit generates corresponding third Flash abstraction layer commands for each physical block in the large block indicated by the media interface command in response to receiving a media interface command indicating an erase operation; wherein the media interface command indicates a large block, the large block includes a plurality of physical blocks, and each of the third Flash abstraction layer commands indicates a physical block.

9. The control component according to claim 6 or 7, characterized in that, In the case where the NVM chip coupled to the control component is replaced, the format of the logical PPA indicated by the media interface command sent by the storage command processing unit to the media interface controller remains unchanged, and the size of the Write Unit indicated by the media interface command sent by the storage command processing unit to the media interface controller changes.

10. The control component according to claim 9, wherein, In response to a change in the programming mode supported by the replaced NVM chip, the Common layer processing unit updates the programming mode type encapsulated in the Flash abstraction layer command; The Common layer processing unit generates a fourth Flash abstraction layer command corresponding to the media interface command according to the updated programming mode type, where the programming mode indicated by the fourth Flash abstraction layer command is the programming mode supported by the replaced NVM chip.

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