Data processing method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a data processing method and device, a storage medium and electronic equipment, and relates to the technical field of computers, the method is applied to a solid state disk, the method comprises the steps that in response to a write-in request, first information of the solid state disk is obtained, and the first information represents a working mode of the solid state disk; according to the working mode and the write-in request, executing a write-in operation; wherein the processing priorities of garbage collection and the write-in request are different in different working modes; the triggering conditions of different working modes are different. Therefore, garbage collection and write-in request processing are performed through different working modes, so that the garbage collection processing mechanism is improved, and the average delay of IO operation is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, apparatus, storage medium, and electronic device. Background Art

[0002] In a mechanical hard disk, the process of writing a file is relatively simple and flexible. Since a mechanical hard disk adopts magnetic storage technology, the read / write head magnetizes the magnetic substances on the disk platter, making them present a magnetization pattern corresponding to the data. Due to this characteristic of the mechanical hard disk, when a user needs to write new data, if the storage location of the new data is the same as or overlaps with the old data, the new data will directly overwrite the old data.

[0003] However, in a solid state drive (SSD), since NAND (a non-volatile flash memory technology) flash memory adopts non-volatile storage technology and cannot directly overwrite written data, each storage unit must be erased first before writing data, and the erasure unit is a flash memory block. This means that on a flash memory block that has already been written with data, if new data needs to be written, the valid data on the flash memory block must be moved to another flash memory block first. After the entire flash memory block is full of invalid data, the entire flash memory block is erased. Garbage collection is exactly based on this NAND mechanism to be responsible for sorting out the valid data on the data block and cleaning up the flash memory blocks that are no longer in use, so as to make room for new data. The currently widely used garbage collection technology generally adopts a preset fixed threshold mechanism, which is based on a key condition: when the number of flash memory blocks available for allocation in the system drops below a preset critical value, the garbage collection process will be triggered. The main purpose of this design is to ensure that the storage system can effectively manage its limited space resources and avoid the situation where users cannot write data due to insufficient space. Specifically, when the system monitors that the number of remaining available flash memory blocks is lower than the fixed threshold, the garbage collection starts to operate, by identifying and cleaning up the data blocks that are no longer required by the system or users (i.e., "garbage" data), so as to release the occupied space and make it available again for subsequent data writing requirements.

[0004] However, in the prior art, due to the adoption of a fixed threshold strategy for triggering garbage collection, once the threshold is reached and the garbage collection process is started, in the context of input / output (IO) load, the garbage collection process will inevitably increase the workload of migrating valid data and the operation of cleaning up discarded flash blocks. This additional burden may cause delays in the IO read and write operations issued by the host side, thereby temporarily weakening the overall performance of the SSD. More seriously, this process may also trigger unstable fluctuations in the overall performance, that is, performance jitter, posing a challenge to the smooth operation of the system. Summary of the Invention

[0005] The present disclosure provides a data processing method, apparatus, storage medium, and electronic device to at least solve the above technical problems existing in the prior art.

[0006] The technical solution of the embodiment of the present disclosure is implemented as follows: In a first aspect, an embodiment of the present disclosure provides a data processing method, which is applied to a solid-state drive, and the method includes: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive; Execute a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different in different working modes; the triggering conditions of different working modes are different.

[0007] In a second aspect, an embodiment of the present disclosure provides a data processing apparatus, which is applied to an electronic device, and the apparatus includes: A first processing module, configured to obtain first information of the solid-state drive in response to a write request, where the first information characterizes the working mode of the solid-state drive; A second processing module, configured to execute a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different in different working modes; the triggering conditions of different working modes are different.

[0008] In the above solution, the obtaining of the first information of the solid-state drive includes: Determine the number of available flash blocks of the solid-state drive; If the number is less than a first threshold and greater than a second threshold, determine that the working mode is a first mode; If the number is less than the second threshold, determine that the working mode is a second mode; If the number is greater than the first threshold, determine that the working mode is a third mode.

[0009] In the above solution, if the working mode is the first mode, according to the working mode and the write request, perform a write operation, including: Obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel; Determine the erase decision probability and write decision probability of each flash chip corresponding to each channel according to the first statistical data; Determine a first target operation to be executed according to the erase decision probability and the write decision probability, where the first target operation is an erase operation or a write operation corresponding to the write request.

[0010] In the above solution, determining the erase decision probability and write decision probability of each flash chip corresponding to each channel according to the first statistical data includes: Determine an erase decision coefficient according to the average idle duration per unit block and the average erase duration per unit block of each flash chip; determine the erase decision probability according to the erase decision coefficient; Determine a write decision coefficient according to the average idle duration per unit block and the average read / write duration per unit block of each flash chip; determine the write decision probability according to the write decision coefficient.

[0011] In the above solution, the determining the first target operation to be executed according to the erase decision probability and the write decision probability includes: If the erase decision probability is greater than a third threshold, generate a first pseudo-random number. If the first pseudo-random number meets the random number condition, determine that the first target operation is an erase operation; If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number. If the second pseudo-random number meets the random number condition, determine that the first target operation is a write operation corresponding to the write request.

[0012] In the above solution, the first pseudo-random number meets the random number condition, including: a first evaluation value obtained by performing a modulo operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold; The second pseudo-random number meets the random number condition, including: a second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

[0013] In the above solution, if the first target operation is an erase operation, the method further includes: Obtain second statistical data; the second statistical data includes historical information related to erase and write operations; Determine the erase gain of at least one flash block according to the second statistical data; Determine a target flash block whose erase gain meets the erase condition as the flash block to be subjected to the erase operation.

[0014] In the above solution, the second statistical data includes at least one of the following information for each flash memory block: Erase duration; Coefficient of relationship between the number of erase / write cycles and time; Total data space and damaged data space; Maximum number of erase / write cycles and number of executed erase / write cycles; Determining the erase gain of at least one flash memory block according to the second statistical data includes: Determining the remaining data space according to the total data space and the damaged data space; Determining the remaining number of erase / write cycles according to the maximum number of erase / write cycles and the number of executed erase / write cycles; Determining the erase gain according to the erase duration, the coefficient of relationship between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles.

[0015] In the above solution, the target flash memory blocks whose determined erase gain meets the erase condition include: Determining the flash memory block with the maximum erase gain from at least one flash memory block to be erased; If the erase gain of the flash memory block with the maximum erase gain is positive, determining the flash memory block with the maximum erase gain as the target flash memory block.

[0016] In the above solution, if the working mode is the second mode, performing a write operation according to the working mode and the write request includes: Determining the amount of recycled data corresponding to garbage collection and the amount of write data corresponding to the write request; If the amount of recycled data is greater than the amount of write data, adding the write request to the execution command queue; If the amount of recycled data is less than or equal to the amount of write data, adding the write request to the waiting command queue.

[0017] In the above solution, if the working mode is the third mode, performing a write operation according to the working mode and the write request includes: Performing a write operation according to the write request.

[0018] In the above solution, the solid-state drive includes: a controller, flash memory chips, and channels, and the channels are used to connect the flash memory chips and the controller; Each of the channels is connected to one or more flash memory chips; Each of the flash memory chips includes: one or more flash memory blocks.

[0019] In a third aspect, embodiments of the present disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute any one of the data processing methods.

[0020] In a fourth aspect, embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute a data processing method according to any one of the above.

[0021] Embodiments of the present disclosure have the following beneficial effects: By applying the data processing method, device, storage medium, and electronic device provided by embodiments of the present disclosure, in response to a write request, first information of a solid-state drive is obtained, and the first information characterizes a working mode of the solid-state drive; a write operation is performed according to the working mode and the write request; wherein the processing priorities of garbage collection and the write request are different under different working modes; and the triggering conditions of different working modes are different. In this way, garbage collection and IO requests (such as write requests) are processed through different working modes to improve the processing mechanism of garbage collection and reduce the average latency of IO operations.

[0022] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic flowchart of a data processing method provided by an embodiment of the present disclosure; Figure 2 is a schematic structural diagram of a solid-state drive provided by an embodiment of the present disclosure; Figure 3 is a flowchart of a processing method in an IGC mode provided by an embodiment of the present disclosure; Figure 4 is a schematic flowchart of an erasure processing method provided by an embodiment of the present disclosure; Figure 5 is a schematic flowchart of a method for optimizing the IO load performance of a solid-state drive provided by an embodiment of the present disclosure; Figure 6 is a schematic structural diagram of an electronic device for optimizing the IO load performance of a solid-state drive provided by an embodiment of the present disclosure; Figure 7 is a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure; Figure 8 Schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0024] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present disclosure.

[0025] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0026] If similar descriptions such as "first / second" appear in the application documents, the following explanation will be added. In the following description, the terms "first\second\third" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] Figure 1 Flowchart of a data processing method provided by an embodiment of the present disclosure, as Figure 1 shown, the method is applied to a solid-state drive, and the data processing method includes: Step 101: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive; Step 102: Perform a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different in different working modes; the triggering conditions of different working modes are different.

[0029] Here, the working mode characterizes how to handle write requests and garbage collection (GC); that is, based on the working mode, the priorities of garbage collection and write requests are determined, as well as whether garbage collection can be interrupted, etc.

[0030] Among them, the working mode includes at least one of the following: the first mode, the second mode, and the third mode; The first mode characterizes the interruptible garbage collection (IGC) mode; in this mode, the garbage collection process can be interrupted by other operations (such as write requests), that is, when there is a write request, the garbage collection will pause and the write request will be processed first.

[0031] The second mode is the uninterruptible garbage collection (UGC) mode; in this mode, the garbage collection will continue and cannot be interrupted by write requests, and the write requests must wait until the garbage collection operation is completed before being executed.

[0032] The third mode characterizes a mode that is neither the IGC mode nor the UGC mode; in this mode, no garbage collection processing is enabled, and the write requests are directly executed.

[0033] Here, in different working modes, the priorities of garbage collection and write operations are different. For example, in the first mode (IGC mode), the priority of write requests is higher than that of garbage collection, while in the second mode (UGC mode), the priority of garbage collection is higher and the write requests will be delayed. In the third mode, there is no garbage collection operation, only write requests.

[0034] In the embodiments of the present disclosure, by setting two thresholds, multiple working modes are triggered. In different working modes, the solid-state drive processes write requests and garbage collection operations according to the priorities, ensuring that the system can minimize the waste of storage space without affecting performance. In the IGC mode, write requests can be processed first to ensure efficient read and write operations. In the UGC mode, garbage collection is executed first, avoiding repeated writing of storage units, thereby extending the service life of the hard disk. Through these flexible working modes, the solid-state drive can adjust its working mode according to different load requirements, reduce latency, improve the system response speed, optimize storage performance, and enhance the user experience.

[0035] In some embodiments, the obtaining of the first information of the solid-state drive includes: Determining the number of available flash blocks of the solid-state drive; If the number is less than the first threshold and greater than the second threshold, determining the working mode to be the first mode; If the quantity is less than the second threshold, determine that the operating mode is the second mode; If the quantity is greater than the first threshold, determine that the operating mode is the third mode.

[0036] Here, a solid state drive (SSD) is used as a storage device, and it stores data through flash memory chips.

[0037] Flash memory chips (NAND Flash Chip) are the storage units inside the solid state drive and are responsible for storing all data. The solid state drive includes multiple flash memory chips, and each flash memory chip can contain multiple flash blocks. These flash memory chips use NAND flash technology to store binary data.

[0038] Flash blocks are an important part of flash memory chips. Each flash block can contain multiple pages. Flash blocks can also be referred to as blocks or data blocks, and it can be understood that flash blocks are the underlying storage units.

[0039] Available flash blocks represent the flash blocks that can be used to store new data. In the management of the solid state drive, the controller of the solid state drive can monitor which blocks are idle and unused, that is, determine the available data blocks. The number of available flash blocks is denoted as , the first threshold is greater than the second threshold, that is, the first threshold is a high threshold, denoted as , the second threshold is a low threshold, denoted as .

[0040] When , do not start any processing, determine that the operating mode is the third mode, and the write operation can be directly executed; When , determine that the operating mode is the first mode, that is, enter the processing flow of the IGC mode; When , determine that the operating mode is the second mode, that is, enter the processing flow of the UGC mode.

[0041] The first threshold and the second threshold are set based on experience, experiments, etc., and no specific values are limited.

[0042] In some embodiments, the method further includes: Receiving a read request; In response to the read request, performing a read operation corresponding to the read request.

[0043] Here, considering the unique nature of the flash memory in the solid-state drive, its read speed is often significantly faster than the write speed. Therefore, when the IO request is a read request, the read operation can be directly executed; if the IO request is a write request, the data processing operation is performed according to step 101 and step 102 to implement the operation corresponding to the write request.

[0044] In some embodiments, if the working mode is the first mode, according to the working mode and the write request, the write operation is performed, including: Obtain the first statistical data; Determine the erase decision probability and write decision probability of each flash memory chip corresponding to each channel according to the first statistical data; Determine the first target operation to be executed according to the erase decision probability and the write decision probability, where the first target operation is an erase operation or the write operation corresponding to the write request.

[0045] Here, the first statistical data includes the historical input / output (IO) load conditions of each channel. For example, it may include at least one of the following: The number of write operations, duration, and data volume of each flash memory chip through each channel in the past period of time; The number of erase operations, duration, and data volume of each flash memory chip through each channel in the past period of time; The usage condition of the free space of each flash memory chip.

[0046] It should be noted that the above information for each memory chip includes the information of each flash memory block in each memory chip, such as the free space of the flash memory block, the number of write operations, etc.

[0047] In some embodiments, determining the erase decision probability and write decision probability of each flash memory chip corresponding to each channel according to the first statistical data includes: Determine the erase decision coefficient according to the average free duration per unit block and the average erase duration per unit block of each flash memory chip; determine the erase decision probability according to the erase decision coefficient; Determine the write decision coefficient according to the average free duration per unit block and the average read / write duration per unit block of each flash memory chip; determine the write decision probability according to the write decision coefficient.

[0048] Here, the erase decision coefficient is calculated according to the average free duration per unit block and the average erase duration per unit block, and is used to evaluate whether the flash memory chip is suitable for being erased. This coefficient can reflect the efficiency of the erase operation; The erase decision probability is used to indicate the demand and priority for erasing the flash memory chip by the current solid-state drive.

[0049] Among them, the average idle duration of a unit block refers to the average duration for which a flash block in a flash memory chip is in an idle state.

[0050] The average erase duration of a unit block refers to the average duration of the erase operation for a flash block in a flash memory chip. The erase speeds of different solid-state drives can be different, resulting in different erase durations.

[0051] Here, the write decision coefficient is calculated based on the average read / write duration of a unit block and is used to evaluate whether a flash memory chip is suitable for a write operation. The lower the write decision coefficient, the higher the efficiency of the write operation, and the more inclined to select the flash memory chip for writing.

[0052] The write decision probability is determined based on the write decision coefficient and reflects whether to select the current channel to perform a write operation on the corresponding flash memory chip.

[0053] The average read / write duration of a unit block refers to the average duration of the read / write operation for a flash block in a flash memory chip.

[0054] Specifically, according to the first statistical data, the erase decision probability and the write decision probability of each flash memory chip corresponding to each channel are determined (denoted as ), and the calculation process is as follows: Step 001: Determine the erase decision coefficient (denoted as ) according to the average idle duration of a unit block and the average erase duration of a unit block of each flash memory chip, as shown in the following formula: (1) Among them, is the average idle duration of a unit block. Here, the idle durations within each statistical period can be statistically counted according to the statistical period, and the average value of the idle durations of each statistical period is calculated to obtain the average idle duration of the unit block; is the average erase duration of a unit block; As shown in formula 1, when , is 1; otherwise is 0.

[0055] Step 002: Determine the erase decision probability according to the erase decision coefficient; as shown in the following formula: (2) Among them, is the erase decision probability, is the i-th time point; m is less than n. For example, m is 5 and n is a value greater than 5; is the proportion of the processing mechanism judgment for the current time (i.e., from the 1st time point to the m-th time point as described above), is the proportion of the processing mechanism judgment for the overall time (i.e., from the 1st time point to the n-th time point); The processing mechanism determination here refers to: determining whether to perform an erase operation on the flash memory chip; It can be adjusted according to the operation conditions in a specific period. For example, if the memory chip frequently performs erase operations within a certain period, then the value will be relatively high, indicating that the operations in the current period have a greater impact on the decision-making.

[0056] If there have been only write operations for a long time, then the value will gradually decrease. Adjusting according to this change makes the decision-making mechanism more stable. That is, gradually reducing the weight of the operations in the current period, and thus relying more on the overall operation trend over a longer period.

[0057] Considering that in the garbage collection process, since the valid data needs to be read out first and then subsequent write operations are performed, therefore, in the embodiments of the present disclosure, the read and write operations are regarded as an overall write operation for processing.

[0058] Specifically, calculate the write decision probability for each channel according to the first statistical data ( ), including: Step 011: Determine the write decision coefficient according to the average free duration of the unit block and the average read and write duration of the unit block, as shown in the following formula: (3) Wherein, is the write decision coefficient, is the average free duration of the unit block, is the average read and write duration of the unit block, is the average read duration of the unit block, is the evaluated write duration of the unit block. When , is 1; otherwise is 0.

[0059] Step 012: Determine the write decision probability according to the write decision coefficient, as shown in the following formula: (4) Wherein, is the write decision probability, is the i-th time point; m is less than n. For example, m is 5 and n is a value greater than 5; is the proportion of the processing mechanism determination for the current time (i.e., from the 1st time point to the m-th time point as described above), represents the proportion of the processing mechanism determination for the overall time (i.e., from the 1st time point to the n-th time point); The processing mechanism determination here refers to: determining whether to perform a write operation on the flash memory chip; It can be adjusted according to the operation conditions during a specific period. For example, if the memory chip performs frequent write operations within a certain period, then the value will be higher, indicating that the operations in the current period have a greater impact on the decision-making.

[0060] If there are always write operations for a long time, then the value will gradually decrease. Adjusting according to this change makes the decision-making mechanism more stable. That is, gradually reducing the weight of the operations in the current period, and thus relying more on the overall operation trend in the longer term.

[0061] In some embodiments, determining the first target operation to be executed according to the erase decision probability and the write decision probability includes: If the erase decision probability is greater than a third threshold, generate a first pseudo-random number. If the first pseudo-random number meets the random number condition, determine that the first target operation is an erase operation; If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number. If the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

[0062] Here, the third threshold and the fourth threshold are preset thresholds for determining whether to generate a random number; they can be the same or different.

[0063] There can be a hardware module (referred to as a pseudo-random number generation module) in the solid-state drive. If the write decision probability or the erase decision probability is greater than the corresponding threshold, call the pseudo-random number generation module to generate the corresponding first pseudo-random number or second pseudo-random number.

[0064] Here, the first pseudo-random number meets the random number condition, including: the first evaluation value obtained by performing a modulo operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold; The second pseudo-random number meets the random number condition, including: the second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

[0065] For example, the third threshold and the fourth threshold can be the same or different. Taking the same as an example, they are both 70%; the fifth threshold and the sixth threshold can be the same or different. Taking the same as an example, they are both 70. Specifically, if the erase decision probability is greater than 70%, call the pseudo-random number generation module to generate a first pseudo-random number. When the number obtained by taking the remainder of the first pseudo-random number by 100 is greater than 70, an erase operation will be performed on the flash block in the flash chip on the corresponding channel. If the write decision probability When it is greater than 70%, the pseudo-random number generation module is called to generate a second pseudo-random number. When the number obtained by taking the remainder of the second pseudo-random number by 100 is greater than 70, a write operation will be performed on the flash memory block in the flash memory chip on the corresponding channel.

[0066] In some embodiments, if the first target operation is an erase operation, the method further includes: Obtaining second statistical data; Determining the erase gain of at least one flash memory block according to the second statistical data; Determining a target flash memory block whose erase gain meets the erase condition as the flash memory block to be subjected to the erase operation.

[0067] Here, the second statistical data includes the historical input / output load conditions of each channel, specifically referring to additional statistical information related to the erase and write operations, which may include: the historical erase times of the flash memory block, the utilization of the free space of the flash memory block, the write times, and the health status of the flash memory block, etc.

[0068] The erase gain refers to the benefits that can be brought after performing the erase operation. For example, erasing a certain flash memory block will release a large amount of storage space, reduce the latency of subsequent writes, or help improve the overall performance of the system.

[0069] The erase condition refers to the requirements or criteria for performing the erase operation. By defining the erase condition, only when the erase gain of the flash memory block is high enough and meets the erase condition, will it be selected as the object to perform the erase operation.

[0070] In this way, unnecessary erase operations can be avoided, thereby improving the efficiency of the storage device and extending its service life.

[0071] In some embodiments, the second statistical data includes at least one of the following information for each flash memory block: Erase duration; The relationship coefficient between the number of erase and write times and time; Total data space and damaged data space; Maximum number of erase and write times and the number of erase and write times that have been executed; Determining the erase gain of at least one flash memory block according to the second statistical data includes: Determining the remaining data space according to the total data space and the damaged data space; Determining the remaining number of erase and write times according to the maximum number of erase and write times and the number of erase and write times that have been executed; Determining the erase gain according to the erase duration, the relationship coefficient between the number of erase and write times and time, the remaining data space, and the remaining number of erase and write times.

[0072] Specifically, determining the erasure benefit according to the erasure time, the relationship coefficient between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles includes: Step 021: Determine the relationship coefficient between the number of erase / write cycles and time according to the number of erase / write cycles and the erasure time, as shown in the following formula: (5) where k represents the relationship coefficient between the number of erase / write cycles and time within a certain time period; is the i-th time point (i.e., the erase / write time); is the number of erase / write cycles at the i-th time point, represents the number of erase / write cycles at the (i + 100)-th time point, ( ) represents the change in the number of erase / write cycles from the i-th time point to the (i + 100)-th time point.

[0073] Step 022: Determine the erasure benefit according to the relationship coefficient between the number of erase / write cycles and time, the erasure duration, the remaining data space, and the remaining number of erase / write cycles, as shown in the following formula: (6) where, is the total data space on the flash block (this value is obtained based on the attributes of each flash block of the solid-state drive), is the damaged data space on the flash block (i.e., the data space that is broken and unavailable), which can be obtained by detecting the flash block; is the remaining data space; is the maximum number of erase / write cycles of the flash block (this value is obtained based on the attributes of each flash block of the solid-state drive), is the number of erase / write cycles that have been executed on the flash block (i.e., the current number of erase / write cycles), which is obtained by detecting the flash block; is the remaining number of erase / write cycles; is the executed erasure duration.

[0074] In the embodiments of the present disclosure, considering that after the execution of the erasure duration , a data space of available size is obtained. If the number of erase / write cycles of the flash block exceeds , it may cause problems with the entire flash block, and the data space on the entire flash block will be cleared. If erasing is performed according to the current relationship coefficient between the number of erase / write cycles and time, data loss will occur. Therefore, the sum of the two is used as the erasure benefit M, representing the actual benefit of erasing a certain flash block.

[0075] Thus, by calculating the erasure benefit, the utilization efficiency of flash memory blocks can be maximized during the erase-write operation, while minimizing data loss and extending the service life of flash memory blocks. Reasonably arranging the erase-write operation can reduce unnecessary data loss, ensure that the erase-write is performed only at the appropriate time, and avoid damage to flash memory blocks caused by over-erasure. This method improves the utilization rate of flash memory by balancing the acquisition of data space and the risks brought by the erase-write operation, reduces the risk of premature damage to flash memory, and enhances the stability and reliability of the system. In addition, the erasure benefit model helps optimize the erase-write decision, ensuring that the remaining available space is maximally utilized without exceeding the maximum number of erasures, thereby improving the long-term operational stability of the entire system.

[0076] In some embodiments, determining the target flash memory block whose erasure benefit meets the erasure condition includes: Determining the flash memory block with the largest erasure benefit from at least one flash memory block to be erased; If the erasure benefit of the flash memory block with the largest erasure benefit is positive, determining the flash memory block with the largest erasure benefit as the target flash memory block.

[0077] Here, among all the flash memory blocks to be erased, a hardware module (referred to as the search module) is used to search for the flash memory block with the largest benefit M. Moreover, only when the erasure benefit M of this flash memory block is positive will the erasure operation of this flash memory block be considered for execution.

[0078] Among them, a positive erasure benefit indicates that the benefit brought by erasing this flash memory block is positive (such as releasing available space and extending the service life of the flash memory block), and then this flash memory block is selected as the target for erasure.

[0079] Thus, by selecting the flash memory block with the largest erasure benefit, it can be ensured that the erase-write operation brings the greatest benefit, avoiding meaningless erasure of flash memory blocks. By reasonably selecting the erasure object, the overall service life of the flash memory device can be extended, unnecessary losses can be reduced, and the efficient utilization of storage space can be ensured, thereby improving the operating efficiency of the entire system.

[0080] In some embodiments, if the working mode is the second mode, according to the working mode and the write request, performing the write operation includes: Determining the amount of recycled data corresponding to garbage collection and the amount of write data corresponding to the write request; If the amount of recycled data is greater than the amount of write data, adding the write request to the execution command queue; If the amount of recycled data is less than or equal to the amount of write data, adding the write request to the waiting command queue. Here, the execution command queue is used to store the queue of commands to be executed immediately.

[0081] The waiting command queue is a queue used to store commands that cannot be executed temporarily.

[0082] It can be understood that the commands in the execution command queue can be directly executed, the commands in the waiting command queue are in a state to be processed, and the execution time of the commands in the execution command queue is earlier than that of the commands in the waiting command queue.

[0083] The second mode is the UGC mode. Considering that both garbage collection and IO operations consume system resources, if the consumption of both is not controlled, it may lead to waste or bottleneck of system resources. By ensuring that the amount of data recycled by garbage collection is slightly larger than the amount of data written, serious imbalance between garbage collection and IO operations can be avoided, and the situation where one operation occupies too many resources and causes delay of the other operation can be avoided. Therefore, in this mode, it is necessary to ensure that the amount of data recycled by garbage collection is slightly larger than (i.e., does not need to be larger than a certain amount, just being larger is enough) the amount of data that IO is going to write. When the amount of data recycled by garbage collection is larger than the amount of data that IO is going to write, the IO write request is stuffed into the execution command queue to reduce memory pressure, and at the same time, it will not cause too much backlog of IO writes in the waiting queue, which helps the system maintain a high response speed and throughput; when the amount of data recycled by garbage collection is smaller than the amount of data that IO is going to write, the IO write request is stuffed into the waiting command queue, that is, the execution is postponed. In this way, the system can have more time to process other tasks during the waiting process, thereby improving the concurrent processing ability.

[0084] In some embodiments, if the working mode is the third mode, according to the working mode and the write request, perform a write operation, including: Perform a write operation according to the write request.

[0085] Here, the third mode represents a mode that is neither the IGC mode nor the UGC mode; in this mode, no garbage collection processing is enabled, and the write request is directly executed.

[0086] In some embodiments, the method is applied to a solid-state drive, and the solid-state drive includes: a controller, flash memory chips, and channels, and the channels are used to connect the flash memory chips and the controller; Each of the channels can be connected to one or more flash memory chips; Each flash memory chip can include: one or more flash memory blocks.

[0087] As Figure 2 shown, Figure 2 is a structural schematic diagram of a solid-state drive provided by an embodiment of the present disclosure. The solid-state drive includes: an SSD main controller (i.e., a controller), NAND flash memory, and channels.

[0088] The NAND flash memory includes: a plurality of flash memory chips, Figure 1"CHIP0-n" in it represents multiple flash memory chips connected to the channel. Each flash memory chip is a unit of data storage, storing actual files or information. Each flash memory chip may include: one or more flash memory blocks.

[0089] Flash memory chips on the same channel share the channel bus, that is, multiple flash memory chips on the same channel share the same channel bus, which means sharing the data transmission path. Multiple flash memory chips can execute operation commands simultaneously, that is, within one channel, multiple flash memory chips can execute the commands issued by the SSD controller in parallel to improve the data read and write efficiency.

[0090] The method provided by the embodiments of the present disclosure takes into account that during the garbage collection process triggered by the reduction of available flash memory blocks in a solid-state drive, the system simultaneously bears the IO load, resulting in a significant increase in the average latency of IO operations for the additional operations of garbage collection. The reason is that the data migration and block erasure operations take a long time, which in turn causes delays in additional write operations during this period. Through the provided data processing method, the processing mechanism of garbage collection is optimized, significantly reducing the average latency of IO operations. At the same time, during the erasure processing, the wear leveling processing effect is further optimized by quantifying future benefits. It shows significant advantages in controlling the average latency of IO operations and improving the overall service life of the SSD.

[0091] Figure 3 It is a flowchart of a processing method in the IGC mode provided by the embodiments of the present disclosure; as Figure 3 shown, in this IGC mode, a statistical module and a pseudo-random number generation module need to be called; among them, the statistical module is used to count the historical IO load situation on each channel (channel), and the pseudo-random number generation module is used to generate pseudo-random numbers (such as the above-mentioned first pseudo-random number and second pseudo-random number). By judging whether there are flash memory chips on the channel that meet the conditions (such as Figure 1 judging the first pseudo-random number and the second pseudo-random number in the method shown), if so, execute the corresponding erasure operation or write operation, if not, do not execute the operation.

[0092] Figure 4 It is a schematic flowchart of an erasure processing method provided by the embodiments of the present disclosure; as Figure 4 shown, in the erasure processing method, a statistical module and a search module need to be called. The statistical module is used to count the historical IO load situation on each channel, and the search module is used to search and sort to the corresponding extreme value result according to a certain value (that is, the flash memory block with the largest erasure gain), and is responsible for quickly locating and accessing specific storage units inside the SSD according to a specific order.

[0093] Figure 5Schematic flowchart of a method for optimizing the performance of solid - state drive (SSD) I / O load provided by an embodiment of the present disclosure; as Figure 5 shown, the statistical module respectively counts the I / O load conditions under different channels. Due to the characteristics of flash memory, the speed of reading data is much slower than that of writing data. Therefore, if the I / O request sent from the host is a read request, the corresponding read operation is directly executed according to the read request; otherwise, if the I / O request is a write request, judge the number of available flash blocks at this time , and compare it with the high threshold and the low threshold to determine the operation to be executed based on the comparison result; including: If , no processing is enabled and the I / O write is directly executed; If the IGC threshold is reached, that is , enter the processing in the IGC mode according to Figure 3 ; If the UGC threshold is reached, that is , enable the processing mechanism in the UGC mode. In the UGC mode, it is necessary to ensure that the amount of data reclaimed by garbage collection is slightly greater than the amount of data to be written by the I / O. When the amount of data reclaimed by garbage collection is greater than the amount of data to be written by the I / O, the I / O write request is stuffed into the execution command queue. When the amount of data reclaimed by garbage collection is less than the amount of data to be written by the I / O, the I / O write request is stuffed into the waiting command queue. In the UGC mode, it is necessary to ensure that the amount of data released by garbage collection is slightly greater than the amount of data required to be written by the I / O operation. Specifically, if the amount of data released by garbage collection exceeds the amount of data required for I / O writing, the I / O write request is added to the execution command queue; conversely, if the amount of data released by garbage collection is not enough to meet the I / O writing requirement, the I / O write request is placed in the waiting command queue. Due to the reasonable setting of the high threshold and the IGC processing mechanism, the UGC mode generally hardly enters.

[0094] Figure 6 Schematic structural diagram of an electronic device for optimizing the performance of solid - state drive (SSD) I / O load provided by an embodiment of the present disclosure; as Figure 6 shown, the electronic device includes: a host and a solid - state drive (SSD); the solid - state drive includes: The NAND Flash Memory is a memory, that is, NAND flash memory; The SSD interface unit is responsible for communicating with the host, receiving and parsing the data packets and I / O requests from the host.

[0095] The garbage collection processing module is used to organize the content of flash memory blocks, clear useless data (i.e., "garbage"), and migrate valid data to new flash memory blocks, so as to ensure that as many free flash memory blocks as possible are retained. This module integrates two advanced processing mechanisms, IGC and UGC.

[0096] The erasure module is used to clean the flash memory blocks completely occupied by invalid data, ensuring further purification and effective utilization of storage resources.

[0097] The statistics module acts as a data traffic monitor, statistically analyzing the IO load conditions under different channels in detail, providing detailed data support for system optimization.

[0098] The pseudo-random number generation module is used to generate pseudo-random numbers (such as the first pseudo-random number and the second pseudo-random number mentioned above).

[0099] The search module is used to quickly lock and access specific storage units inside the SSD according to established rules. Based on the erasure processing mechanism, the search module can properly save the address value of the flash memory block with the maximum sorting value in the register according to the calculated erasure benefit M value.

[0100] In the embodiments of the present disclosure, by introducing the hardware acceleration module, that is, the search module, the block search process is accelerated. When performing an erasure operation, according to the evaluation of future benefits, search and preferentially perform erasure on the flash memory block with the greatest future benefit (i.e., the above-mentioned target flash memory block). The search module finds the block with the largest benefit M and only considers performing erasure when the benefit M of this block is positive. By optimizing the erasure order of flash memory blocks, while ensuring efficient erasure, wear leveling is also taken into account, thus providing a strong guarantee for extending the overall service life of the SSD.

[0101] Figure 7 It is a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure; as Figure 7 shown, the device is applied to a solid-state drive, and the device includes: The first processing module is used to obtain the first information of the solid-state drive in response to a write request, and the first information characterizes the working mode of the solid-state drive; The second processing module is used to perform a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

[0102] In some embodiments, the first processing module is used to determine the number of available flash memory blocks of the solid-state drive; If the number is less than the first threshold and greater than the second threshold, it is determined that the working mode is the first mode; If the quantity is less than a second threshold, determine that the operating mode is a second mode; If the quantity is greater than a first threshold, determine that the operating mode is a third mode.

[0103] In some embodiments, the second processing module is configured to, if the operating mode is a first mode, obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel; Determine the erasure decision probability and the write decision probability of each flash chip corresponding to each channel according to the first statistical data; Determine a first target operation to be executed according to the erasure decision probability and the write decision probability, where the first target operation is an erasure operation or a write operation corresponding to the write request.

[0104] In some embodiments, the second processing module is configured to determine an erasure decision coefficient according to the average idle duration per unit block and the average erasure duration per unit block of each flash chip; determine the erasure decision probability according to the erasure decision coefficient; Determine a write decision coefficient according to the average idle duration per unit block and the average read / write duration per unit block of each flash chip; determine the write decision probability according to the write decision coefficient.

[0105] In some embodiments, the second processing module is configured to, if the erasure decision probability is greater than a third threshold, generate a first pseudo-random number, and if the first pseudo-random number meets the random number condition, determine that the first target operation is an erasure operation; If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number, and if the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

[0106] In some embodiments, the first pseudo-random number meeting the random number condition includes: a first evaluation value obtained by performing a modulo operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold; The second pseudo-random number meeting the random number condition includes: a second evaluation value obtained by performing a modulo operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

[0107] In some embodiments, if the first target operation is an erasure operation, the second processing module is further configured to obtain second statistical data; the second statistical data includes historical information related to erase-write operations; Determine the erasure gain of at least one flash block according to the second statistical data; Determine a target flash block whose erasure gain meets the erasure condition as the flash block to be subjected to the erasure operation.

[0108] In some embodiments, the second statistical data includes at least one of the following information for each flash memory block: Erasure duration; Coefficient of relationship between the number of erase / write cycles and time; Total data space and damaged data space; Maximum number of erase / write cycles and number of executed erase / write cycles; The second processing module is configured to determine the remaining data space according to the total data space and the damaged data space; Determine the remaining number of erase / write cycles according to the maximum number of erase / write cycles and the number of executed erase / write cycles; Determine the erasure gain according to the erasure duration, the coefficient of relationship between the number of erase / write cycles and time, the remaining data space, and the remaining number of erase / write cycles.

[0109] In some embodiments, the second processing module is configured to determine the flash memory block with the maximum erasure gain from at least one flash memory block to be erased; If the erasure gain of the flash memory block with the maximum erasure gain is positive, determine the flash memory block with the maximum erasure gain as the target flash memory block.

[0110] In some embodiments, the second processing module is configured to, if the working mode is the second mode, determine the amount of recycled data corresponding to garbage collection and the amount of written data corresponding to the write request; If the amount of recycled data is greater than the amount of written data, add the write request to the execution command queue; If the amount of recycled data is less than or equal to the amount of written data, add the write request to the waiting command queue.

[0111] In some embodiments, the second processing module is configured to, if the working mode is the third mode, perform a write operation according to the write request.

[0112] In some embodiments, the solid-state drive includes: a controller, a flash memory chip, and a channel, and the channel is used to connect the flash memory chip and the controller; Each of the channels is connected to one or more flash memory chips; Each of the flash memory chips includes: one or more flash memory blocks.

[0113] It can be understood that when implementing the corresponding data processing method, the data processing device provided in the above embodiments can, as needed, allocate the above processing to different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the embodiments of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiments and will not be repeated here.

[0114] An embodiment of the present application provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes a data processing method.

[0115] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, where the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be caused to execute the data processing method provided by the embodiment of the present application.

[0116] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or may be various devices including one or any combination of the above memories.

[0117] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, and may be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0118] As an example, the executable instructions may or may not correspond to a file in a file system, and may be stored as part of a file that stores other programs or data. For example, they may be stored in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or stored in multiple cooperating files (for example, files that store one or more modules, subroutines, or code portions).

[0119] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed at multiple locations and interconnected by a communication network.

[0120] Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present disclosure; as Figure 8 shown, the electronic device 80 includes: a processor 801 and a memory 802 communicatively connected to the processor 801; the memory 802 stores instructions executable by the processor 801. The instructions are executed by the processor 801 so that the processor 801 can execute: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive; Execute a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

[0121] The electronic device provided in the above embodiment and the embodiment of the corresponding data processing method belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be elaborated here.

[0122] In practical applications, the electronic device 80 may further include: at least one network interface 803. Each component in the electronic device 80 is coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear description, in Figure 8 all kinds of buses are labeled as the bus system 804. Among them, the number of the processors 801 can be at least one, and the number of the memories 802 can be at least one. The network interface 803 is used for wired or wireless communication between the electronic device 80 and other devices.

[0123] The memory 802 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 80.

[0124] The method disclosed in the above embodiments of the present disclosure can be applied to the processor 801 or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 801 or the instructions in the form of software. The above-mentioned processor 801 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by the hardware decoding processor, or by a combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 802. The processor 801 reads the information in the memory 802 and combines its hardware to complete the steps of the foregoing data processing method.

[0125] In some embodiments, the electronic device 80 may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components for performing the foregoing methods.

[0126] It should be understood that the various forms of the processes shown above may be used, steps may be reordered, added, or deleted. For example, the steps described in this disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. No limitation is imposed herein.

[0127] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0128] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0129] It should be understood that in the various embodiments of this disclosure, the magnitude of the sequence number of each implementation process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this disclosure.

[0130] In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0131] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A data processing method, characterized in that, The method is applied to a solid-state drive, and the method includes: In response to a write request, obtain first information of the solid-state drive, where the first information characterizes the working mode of the solid-state drive; Perform a write operation according to the working mode and the write request; Among them, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

2. The method according to claim 1, characterized in that, The obtaining of the first information of the solid-state drive includes: Determine the number of available flash blocks of the solid-state drive; If the number is less than a first threshold and greater than a second threshold, determine that the working mode is the first mode; If the number is less than the second threshold, determine that the working mode is the second mode; If the number is greater than the first threshold, determine that the working mode is the third mode.

3. The method according to claim 1, characterized in that, If the working mode is the first mode, performing a write operation according to the working mode and the write request includes: Obtain first statistical data; the first statistical data includes the historical input / output load conditions of each channel; Determine the erasure decision probability and write decision probability of each flash chip corresponding to each channel according to the first statistical data; Determine a first target operation to be executed according to the erasure decision probability and the write decision probability, where the first target operation is an erasure operation or a write operation corresponding to the write request.

4. The method according to claim 3, wherein Determining the erasure decision probability and write decision probability of each flash chip corresponding to each channel according to the first statistical data includes: Determine an erasure decision coefficient according to the average idle duration per unit block and the average erasure duration per unit block of each flash chip; determine the erasure decision probability according to the erasure decision coefficient; Determine a write decision coefficient according to the average idle duration per unit block and the average read / write duration per unit block of each flash chip; determine the write decision probability according to the write decision coefficient.

5. The method according to claim 3, characterized in that, The determining of the first target operation to be executed according to the erasure decision probability and the write decision probability includes: If the erasure decision probability is greater than a third threshold, generate a first pseudo-random number. If the first pseudo-random number meets the random number condition, determine that the first target operation is an erasure operation; If the write decision probability is greater than a fourth threshold, generate a second pseudo-random number. If the second pseudo-random number meets the random number condition, determine that the first target operation is the write operation corresponding to the write request.

6. The method according to claim 5, wherein The first pseudo-random number meets the random number condition, including: a first evaluation value obtained by performing a remainder operation on the first pseudo-random number based on a preset rule is greater than a fifth threshold; The second pseudo-random number meets the random number condition, including: a second evaluation value obtained by performing a remainder operation on the second pseudo-random number based on a preset rule is greater than a sixth threshold.

7. The method according to claim 3, wherein If the first target operation is an erasure operation, the method further includes: Obtain second statistical data; the second statistical data includes historical information related to erase / write operations; Determine the erasure gain of at least one flash block according to the second statistical data; Determine a target flash block whose erasure gain meets the erasure condition as the flash block to be subjected to the erasure operation.

8. The method according to claim 7, characterized in that The second statistical data includes at least one of the following information of each flash block: Erasure duration; The relationship coefficient between the number of erase / write cycles and time; All data space and damaged data space; Maximum number of erase cycles and number of executed erase cycles; Determining the erase gain of at least one flash memory block according to the second statistical data, including: Determining the remaining data space according to the all data space and the damaged data space; Determining the remaining number of erase cycles according to the maximum number of erase cycles and the number of executed erase cycles; Determining the erase gain according to the erase duration, the relationship coefficient between the number of erase cycles and time, the remaining data space, and the remaining number of erase cycles.

9. The method according to claim 8, wherein The target flash memory block whose determined erase gain meets the erase condition includes: Determining the flash memory block with the largest erase gain from at least one flash memory block to be erased; If the erase gain of the flash memory block with the largest erase gain is positive, determining the flash memory block with the largest erase gain as the target flash memory block.

10. The method according to claim 1, characterized in that, If the working mode is the second mode, performing a write operation according to the working mode and the write request, including: Determining the amount of recycled data corresponding to garbage collection and the amount of write data corresponding to the write request; If the amount of recycled data is greater than the amount of write data, adding the write request to the execution command queue; If the amount of recycled data is less than or equal to the amount of write data, adding the write request to the waiting command queue.

11. The method according to claim 1, wherein If the working mode is the third mode, performing a write operation according to the working mode and the write request, including: Performing a write operation according to the write request.

12. The method according to claim 1, wherein The solid state drive includes: a controller, a flash memory chip, and a channel for connecting the flash memory chip and the controller; Each of the channels is connected to one or more flash memory chips; Each of the flash memory chips includes: one or more flash memory blocks.

13. A data processing device, characterized in that, The device is applied to a solid state drive, and the device includes: A first processing module, configured to obtain first information of the solid state drive in response to a write request, where the first information characterizes the working mode of the solid state drive; A second processing module, configured to perform a write operation according to the working mode and the write request; Wherein, the processing priorities of garbage collection and the write request are different under different working modes; the triggering conditions of different working modes are different.

14. An electronic device, characterized in that, Including: At least one processor; And a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 12.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 12.

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