Controller simulation system construction method and device, equipment and medium

Abstract

The invention discloses a controller simulation system construction method and device, equipment and a medium, relates to the technical field of simulation, is applied to a preset transaction-level component, and comprises the following steps: connecting a simulation model of a controller and equipment based on a nonvolatile memory host controller interface specification, and connecting a preset virtual operating system simulator through an inter-process communication component; converting a first transaction level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message; and converting a second transaction layer data packet message sent by the simulation model into a second transaction level modeling message, and sending the second transaction level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction level modeling message, and realizing connection communication between the preset virtual operating system simulator and the simulation model so as to construct the simulation system. And the construction of the controller simulation model is realized.

Description

Technical Field

[0001] The present invention relates to the field of simulation technology, and in particular to a method, device, equipment and medium for constructing a controller simulation system. Background Art

[0002] In the storage field, NVMe (Non-Volatile Memory Express) technology has become the mainstream storage technology. With the continuous expansion of the market scale of NVMe, the design and manufacturing of NVMe controller chips have become increasingly mature, and the simulation technology of NVMe controllers has gradually become popular. For existing simulation software for NVMe controllers and devices, the relatively popular NVMe simulation system framework is SimpleSSD (a high-fidelity simulator for simulating the detailed characteristics of the internal software and hardware of solid-state drives). There is a software simulation system for NVMe controllers designed based on the SimpleSSD and gem5 (an open-source framework for processor architecture simulation) simulation models. SimpleSSD and gem5 together form a complete simulation system, where SimpleSSD NVMe provides the simulation implementation of the NVMe controller and device functions, the gem5 software provides the simulation implementation of the CPU (Central Processing Unit) and related peripheral functions, and the SimpleSSD software provides seamless docking with the gem5 software. The Linux operating system runs in the simulated CPU environment provided by gem5, and the NVMe test software runs in the Linux operating system. In the direction of simulation technology, since gem5 is more inclined to the simulation research of CPU architecture and has higher simulation accuracy and details, but when executing instructions, its execution speed is slower compared with QEMU (Quick EMUlator, a virtual operating system simulator). Especially when the CPU model runs the Linux operating system and software, the running speed on gem5 is also unacceptable. At this time, when not pursuing the simulation accuracy and details of the CPU architecture, using this simulation system to research and test verify SimpleSSD is very inefficient. At this time, QEMU can be used to replace gem5 for CPU simulation processing, but the SimpleSSD simulation model does not support direct docking with the QEMU emulator. It can be seen that how to construct an NVMe controller simulation model through the SimpleSSD simulation model and the QEMU emulator is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0003] The purpose of the embodiments of the present invention is to provide a method, device, equipment and medium for constructing a controller simulation system. An NVMe controller simulation model can be constructed through the SimpleSSD simulation model and the QEMU emulator, so as to support software programs to more quickly develop and debug the NVMe controller and device simulation models constructed by SimpleSSD. The specific solution is as follows:

[0004] In a first aspect, the present invention provides a method for constructing a controller simulation system, which is applied to a preset transaction-level component and includes:

[0005] Connect the simulation models of the controller and device based on the Non-Volatile Memory Host Controller Interface Specification, and connect to a preset virtual operating system simulator through an inter-process communication component;

[0006] Convert the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and call the simulation model to process the first transaction layer data packet message;

[0007] Convert the second transaction layer data packet message sent by the simulation model into a second transaction-level modeling message, and send the second transaction-level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction-level modeling message, realizes the connection and communication between the preset virtual operating system simulator and the simulation model, and constructs a controller simulation system based on the preset virtual operating system simulator and the simulation model.

[0008] Optionally, the preset transaction-level component includes a root port, an endpoint, and an endpoint device interface based on the Peripheral Component Interconnect Express standard;

[0009] Correspondingly, converting the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message includes:

[0010] Receive the first transaction-level modeling message corresponding to the target request sent by the preset virtual operating system simulator through the root port based on the Peripheral Component Interconnect Express standard;

[0011] Convert the first transaction-level modeling message into a first transaction layer data packet message through the root port, and forward the first transaction layer data packet message to the endpoint, so that the endpoint parses the first transaction layer data packet message to determine the type of the target request;

[0012] If the target request is a memory request, identify the register access content in the target request, and send the register access content to the endpoint device interface;

[0013] Perform corresponding read and write operations on the register - to - register access content of the simulation model through the endpoint device interface.

[0014] Optionally, after invoking the simulation model to process the first transaction layer packet message, it further includes:

[0015] Obtain the register read - write data through the endpoint device interface; the register read - write data is the data generated by the corresponding read and write operations of the registers of the simulation model on the register - to - register access content.

[0016] Return the register read - write data to the endpoint through the endpoint device interface so that the endpoint can generate a corresponding first completion message based on the register read - write data, send the first completion message to the root port, so that the root port can convert the first completion message into a first transaction - level modeling response message, and send the first transaction - level modeling response message to the preset virtual operating system simulator; the first completion message is a message in the format of a transaction layer packet.

[0017] Optionally, after determining the type of the target request, it further includes:

[0018] If the target request is a configuration request, directly process the target request through the endpoint to obtain the corresponding configuration content information, and send the configuration content information and the second completion message to the root port; the second completion message is a message in the format of a transaction layer packet.

[0019] Convert the second completion message into a second transaction - level modeling response message through the root port and send the second transaction - level modeling response message to the preset virtual operating system simulator.

[0020] Optionally, converting the second transaction layer packet message sent by the simulation model into a second transaction - level modeling message includes:

[0021] Receive the second transaction layer packet message corresponding to the direct memory access data read - write request sent by the simulation model through the endpoint device interface, and send the second transaction layer packet message to the endpoint.

[0022] Send the second transaction layer packet message to the root port through the endpoint so that the root port can convert the second transaction layer packet message into a second transaction - level modeling message.

[0023] Optionally, sending the second transaction - level modeling message to the preset virtual operating system simulator so that after the preset virtual operating system simulator processes the second transaction - level modeling message, it further includes:

[0024] After the preset virtual operating system simulator processes the second transaction - level modeling message, generate a corresponding second transaction - level modeling response message and send the second transaction - level modeling response message to the root port.

[0025] Convert the second transaction-level modeling response message into a third completion message in the transaction layer packet format through the root port, and send the third completion message to the endpoint;

[0026] Parse the third completion message through the endpoint to obtain the corresponding direct memory access data result, and send the direct memory access data result to the endpoint device interface;

[0027] Forward the direct memory access data result to the simulation model through the endpoint device interface for corresponding processing.

[0028] Optionally, before converting the first transaction-level modeling message sent by the preset virtual operating system simulator into the first transaction layer packet message, it further includes:

[0029] Initialize the simulation model, the root port of the preset transaction-level component based on the Peripheral Component Interconnect Express (PCIe) standard, the endpoint, and the endpoint device interface;

[0030] Communicatively connect the transaction layer packet communication interfaces between the root port and the endpoint, and communicatively connect the transaction layer packet communication interfaces between the endpoint and the endpoint device interface.

[0031] In a second aspect, the present invention provides a controller simulation system construction device, which is applied to a preset transaction-level component and includes:

[0032] A connection module, configured to connect the simulation models of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification (NVMe), and connect the preset virtual operating system simulator through an inter-process communication component;

[0033] A message processing module, configured to convert the first transaction-level modeling message sent by the preset virtual operating system simulator into the first transaction layer packet message, and call the simulation model to process the first transaction layer packet message;

[0034] A simulation system construction module, configured to convert the second transaction layer packet message sent by the simulation model into the second transaction-level modeling message, and send the second transaction-level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction-level modeling message, realizes the connection and communication between the preset virtual operating system simulator and the simulation model, and constructs a controller simulation system based on the preset virtual operating system simulator and the simulation model.

[0035] In a third aspect, the present invention provides an electronic device, including:

[0036] A memory, configured to store a computer program;

[0037] A processor, configured to execute the computer program to implement the foregoing controller simulation system construction method.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the foregoing method for constructing a controller simulation system is implemented.

[0039] The present invention presets a transaction-level component to connect a simulation model of a controller and a device based on the Non-Volatile Memory Host Controller Interface Specification (NVMe), and connects a preset virtual operating system simulator through an inter-process communication component; converts a first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and invokes the simulation model to process the first transaction layer data packet message; converts a second transaction layer data packet message sent by the simulation model into a second transaction-level modeling message, and sends the second transaction-level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction-level modeling message, realizes the connection and communication between the preset virtual operating system simulator and the simulation model, and constructs a controller simulation system based on the preset virtual operating system simulator and the simulation model.

[0040] Beneficial effects: The present invention connects a simulation model of a controller and a device based on the Non-Volatile Memory Host Controller Interface Specification (NVMe) and a preset virtual operating system simulator through a preset transaction-level component, mutually converts the transaction-level modeling requests and responses of the bus and the transaction layer data packet requests and responses, processes the transaction layer data packet requests and responses, and forwards them to the simulation model of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification (NVMe) and the preset virtual operating system simulator, thereby realizing the communication from the simulation model of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification (NVMe) to the preset virtual operating system simulator, constructing a controller simulation system based on the preset virtual operating system simulator and the simulation model, and further realizing the more rapid development and debugging of the simulation model. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a flowchart of a method for constructing a controller simulation system provided by an embodiment of the present invention;

[0043] Figure 2 It is a schematic diagram of an NVMe controller chip simulation system provided by an embodiment of the present invention;

[0044] Figure 3Schematic diagram of the function of a transaction-level conversion module provided by an embodiment of the present invention;

[0045] Figure 4 Schematic diagram of the processing flow of a configuration request initiated by the host side provided by an embodiment of the present invention;

[0046] Figure 5 Schematic diagram of the processing flow of a Memory request initiated by the host side provided by an embodiment of the present invention;

[0047] Figure 6 Schematic diagram of the processing flow of a DMA Memory request initiated by the controller device side provided by an embodiment of the present invention;

[0048] Figure 7 Schematic diagram of the top-level initialization process of a chip simulation system model provided by an embodiment of the present invention;

[0049] Figure 8 Schematic diagram of the processing flow of a simulation sub-module provided by an embodiment of the present invention;

[0050] Figure 9 Schematic diagram of the processing flow of receiving a TLP packet provided by an embodiment of the present invention;

[0051] Figure 10 Schematic diagram of the processing flow of receiving a DMA request packet provided by an embodiment of the present invention;

[0052] Figure 11 Schematic diagram of the processing flow of a register provided by an embodiment of the present invention;

[0053] Figure 12 Schematic diagram of the processing flow of a DMA request provided by an embodiment of the present invention;

[0054] Figure 13 Schematic diagram of the structure of a controller simulation system construction device provided by an embodiment of the present invention;

[0055] Figure 14 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0056] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0057] As used in the specification of the present invention and the above-mentioned drawings, the terms "comprising" and "having", and any variations related to "comprising" and "having", are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0058] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0059] There is a software simulation system for an NVMe controller, which is a simulation system designed based on the SimpleSSD and gem5 (an open-source framework for processor architecture simulation) simulation models. The SimpleSSD and gem5 together constitute a complete simulation system. Among them, SimpleSSD NVMe provides the simulation implementation of the NVMe controller and device functions, the gem5 software provides the simulation implementation of the CPU (Central Processing Unit) and related peripheral functions, and the SimpleSSD software provides seamless docking with the gem5 software. The Linux operating system runs in the simulated CPU environment provided by gem5, and the NVMe test software runs in the Linux operating system. In the direction of simulation technology, since gem5 is more inclined to the simulation research of the CPU architecture, the simulation accuracy and details are higher, but when executing instructions, the execution speed is slower compared with QEMU. Especially when the CPU model runs the Linux operating system and software, the speed when running on gem5 is also unacceptable. At this time, when not pursuing the simulation accuracy and details of the CPU architecture, the efficiency of using this simulation system to research and test verify SimpleSSD is very low. To solve the above technical problems, the present invention discloses a method, device, equipment, and medium for constructing a controller simulation system, which can construct an NVMe controller simulation model through the SimpleSSD simulation model and the QEMU emulator, so as to support the software program to more quickly develop and debug the NVMe controller and device simulation models constructed by SimpleSSD.

[0060] See Figure 1 As shown, an embodiment of the present invention provides a method for constructing a controller simulation system, which is applied to a preset transaction-level component and includes:

[0061] Step S11: Connect the simulation models of the controller and device based on the Non-Volatile Memory Host Controller Interface Specification, and connect the preset virtual operating system simulator through the inter-process communication component.

[0062] In an embodiment of the present invention, the NVMe controller chip simulation system is as Figure 2As shown in the figure, the present invention constructs a transaction-level component, which provides an interface to the device side to dock with the functional interface of SimpleSSD. At the same time, the transaction-level conversion module provides an interface to the host side to complete the PCIe-RC docking with the QEMU simulation system through the inter-process communication component (QEMU side - device side). Thus, the NVMe controller and device of SimpleSSD are connected to the QEMU simulation system in the form of a PCIe-EP (Peripheral Component Interconnect Express Endpoint, an endpoint device based on the high-speed serial computer expansion bus standard) device. Among them, the preset transaction-level component includes a root port, an endpoint, and an endpoint device interface based on the high-speed serial computer expansion bus standard. It should be noted that the preset transaction-level component here can also be called a transaction-level conversion module constructed based on the SystemC (a library written in C++ language, often used for simulation modeling) framework, such as Figure 3 As shown in the figure, the transaction-level conversion module includes a simulation PCIe-RC-Port (PCIe Root Complex Port, a root port based on the high-speed serial computer expansion bus standard) sub-module, a simulation PCIe-EP (PCIe EndPoint, an endpoint based on the high-speed serial computer expansion bus standard) sub-module, and a simulation PCIe-EP device interface sub-module.

[0063] Among them, the simulation PCIe-RC-Port sub-module is responsible for receiving the TLM (Transaction-Level Modeling) packets of the configuration requests and Memory requests from the host side (QEMU side), encapsulating the TLM requests into TLP (Transaction Layer Package) packets, and forwarding them to the simulation PCIe-EP sub-module; and waiting to receive the completed TLP packets. After receiving the completed TLP packets, it replies with a TLM response packet to the host. The simulation PCIe-RC-Port sub-module is also responsible for receiving the TLP packets of the DMA data requests from the simulation PCIe-EP sub-module on the device side, converting the TLP packets into TLM packets, and sending them to the host; and waiting to receive the TLM response from the host. After receiving the response, it converts the TLM response into a TLP completion packet and sends it to the simulation PCIe-EP sub-module.

[0064] The simulation PCIe-EP sub-module is responsible for receiving and parsing the TLP packets from the simulation PCIe-RC-Port sub-module; meanwhile, it processes them according to the packet types respectively. If it is a configuration request, it is processed by the simulation PCIe-EP sub-module, and the content of the configuration request is returned to generate a Complete packet, which is sent to the simulation PCIe-RC-Port sub-module. If it is a Memory request, the request is parsed into register read / write processing and passed to the simulation PCIe-EP device interface sub-module, and then waits for the return result. After receiving the return result, a Complete packet is generated and sent to the simulation PCIe-RC-Port sub-module. The simulation PCIe-EP sub-module is also responsible for receiving the DMA data requests from the simulation PCIe-EP device interface sub-module, organizing the Memory read / write TLP packets, and sending them to the simulation PCIe-RC-Port sub-module; and waits to receive the complete packets from the simulation PCIe-RC-Port sub-module. After receiving the complete packets, it parses the DMA data results and forwards the data results to the simulation PCIe-EP device interface sub-module. The simulation PCIe-EP device interface sub-module is responsible for receiving the register read / write processing requests from the simulation PCIe-EP sub-module, then calling the register read / write processing of the attached SimpleSSD NVMe controller and device module, and returning the register read / write data to the simulation PCIe-EP sub-module. The simulation PCIe-EP device interface sub-module is also responsible for receiving the DMA data read / write requests from the SimpleSSD NVMe controller. After parsing the information of the DMA data read / write requests, it is transferred to the simulation PCIe-EP sub-module for processing; and waits to receive the DMA data read / write results from the simulation PCIe-EP sub-module. After receiving the read / write result data, it is passed to the attached SimpleSSD NVMe controller for processing. In this way, based on the SystemC framework, through transaction-level conversion, the transaction-level TLM access is converted into TLP protocol access, isolating the bus address domain. At the same time, when the TLM requests and responses of the bus are mutually converted with the TLP requests and responses, it is to convert the local processor bus address domain into the PCIe bus address domain, which facilitates device attachment and expansion based on the PCIe bus address domain.

[0065] Step S12: Convert the first transaction-level modeling packet sent by the preset virtual operating system simulator into a first transaction layer data packet, and call the simulation model to process the first transaction layer data packet.

[0066] In the embodiments of the present invention, there are three common data flows: the configuration request packet initiated by the host side; the Memory request packet initiated by the host side; the Memory request packet initiated by the device side. Among them, the processing flow of the configuration request initiated by the host side is asFigure 4 As shown, the processing flow of the Memory request initiated by the host side is as follows Figure 5 As shown. In literal description, when converting the first transaction-level modeling message sent by the preset virtual operating system simulator into the first transaction-layer data packet message and invoking the simulation model to process the first transaction-layer data packet message, the first transaction-level modeling message corresponding to the target request sent by the preset virtual operating system simulator is received through the root port based on the Peripheral Component Interconnect Express (PCIe) standard; the first transaction-level modeling message is converted into the first transaction-layer data packet message through the root port, and the first transaction-layer data packet message is forwarded to the endpoint so that the endpoint can parse the first transaction-layer data packet message to determine the type of the target request; if the target request is a memory request, the register access content in the target request is identified and sent to the endpoint device interface; the register of the simulation model is invoked through the endpoint device interface to perform corresponding read and write processing on the register access content. After determining the type of the target request, if the target request is a configuration request, the target request is directly processed by the endpoint to obtain the corresponding configuration content information, and the configuration content information and the second completion message are sent to the root port; the second completion message is a message in the format of a transaction-layer data packet; the second completion message is converted into the second transaction-level modeling response message through the root port, and the second transaction-level modeling response message is sent to the preset virtual operating system simulator.

[0067] In the embodiment of the present invention, according to Figure 5 More specifically, after invoking the simulation model to process the first transaction-layer data packet message, the register read and write data is obtained through the endpoint device interface; the register read and write data is the data generated by the register of the simulation model performing corresponding read and write processing on the register access content; the register read and write data is returned to the endpoint through the endpoint device interface so that the endpoint can generate the corresponding first completion message according to the register read and write data and send the first completion message to the root port so that the root port can convert the first completion message into the first transaction-level modeling response message and send the first transaction-level modeling response message to the preset virtual operating system simulator; the first completion message is a message in the format of a transaction-layer data packet.

[0068] Step S13: Convert the second transaction-layer data packet message sent by the simulation model into the second transaction-level modeling message, and send the second transaction-level modeling message to the preset virtual operating system simulator so that the preset virtual operating system simulator can process the second transaction-level modeling message, realize the connection and communication between the preset virtual operating system simulator and the simulation model, and construct a controller simulation system based on the preset virtual operating system simulator and the simulation model.

[0069] In an embodiment of the present invention, the processing flow of a DMA Memory (Direct Memory Access) request initiated by the SimpleSSD NVMe controller device side is as follows Figure 6 shown. First, receive a second transaction layer packet message corresponding to a direct memory access data read / write request sent by the simulation model through the endpoint device interface, and send the second transaction layer packet message to the endpoint; send the second transaction layer packet message to the root port through the endpoint so that the root port can convert the second transaction layer packet message into a second transaction level modeling message. Send the second transaction level modeling message to a preset virtual operating system simulator so that after the preset virtual operating system simulator processes the second transaction level modeling message, after the preset virtual operating system simulator processes the second transaction level modeling message, generate a corresponding second transaction level modeling response message, and send the second transaction level modeling response message to the root port; convert the second transaction level modeling response message into a third completion message in the format of a transaction layer packet through the root port, and send the third completion message to the endpoint; parse the third completion message through the endpoint to obtain the corresponding direct memory access data result, and send the direct memory access data result to the endpoint device interface; forward the direct memory access data result to the simulation model through the endpoint device interface for corresponding processing.

[0070] In addition, before converting the first transaction level modeling message sent by the preset virtual operating system simulator into a first transaction layer packet message, the present invention initializes the simulation model, the root port, the endpoint, and the endpoint device interface of the preset transaction level component based on the Peripheral Component Interconnect Express (PCIe) standard; communicate and connect the transaction layer packet communication interfaces between the root port and the endpoint, and communicate and connect the transaction layer packet communication interfaces between the endpoint and the endpoint device interface. As Figure 7As shown, when the NVMe controller simulation model of the simulation system is initialized, the first part is the pre-initialization, including initializing the system bus in S1001. The simulation system bus is responsible for connecting each simulation unit and handling bus requests and responses. It also includes initializing the device-side part of the inter-process communication module in S1002 and initializing the TLM interface module in S1003 to prepare for building the NVMe controller and device simulation system. The second part is the initialization of the transaction-level conversion module in the top-level module, including initializing the simulation PCIe-RC-Port sub-module in S1004, initializing the simulation PCIe-EP sub-module in S1005, and initializing the simulation PCIe-EP device interface sub-module in S1006. The initialization of the PCIe-EP interface sub-module also includes the initialization of the NVMe controller and device models of SimpleSSD. The third part is the interface binding between modules, including binding the TLM communication interface of the TLM interface module and the simulation PCIe-RC-Port sub-module in S1007, binding the TLP communication interface of the simulation PCIe-RC-Port sub-module and the simulation PCIe-EP sub-module in S1008, and binding the simulation PCIe-EP sub-module and the simulation PCIe-EP device interface sub-module in S1009. Finally, the initialization of the top-level module of the simulation system is completed, and the simulation system runs. In this way, the present invention realizes hanging the NVMe controller and device simulation model based on SimpleSSD onto the QEMU simulation platform, thus realizing a system that supports the NVMe controller and device simulation model. Accessing the NVMe controller and device simulation model built based on SimpleSSD through the QEMU virtualization software is faster and more efficient than accessing the NVMe controller and device simulation model built based on SimpleSSD through the gem5 system, facilitating software to build and debug the environment of the NVMe controller and device simulation model, improving the performance of the NVMe controller and device simulation system, and shortening the debugging and testing time. It solves the problem of the slow access of the software program to the system environment of the NVMe controller and device simulation model built based on gem5 and SimpleSSD during the R & D process of the NVMe controller chip.

[0071] It should be noted that in order to implement a controller simulation system based on a preset virtual operating system simulator and a simulation model, the present invention mainly needs to solve the mutual conversion between TLP packets and TLM packets. In addition to using the transaction-level conversion model mentioned in the present invention, it can also be achieved through a protocol gateway architecture. First, the parsing layer: decode the TLP header to extract information such as the target address, operation type (read / write), data payload, etc.; parse the application layer data and transport layer port information of the TLM packet. The mapping layer: establish field mapping rules. For example, the storage read / write request of the TLP is mapped to the data acquisition instruction of the TLM, and the completion packet is mapped to the response frame. The real-time data payload of the TLM is encapsulated as the valid data segment of the TLP, and the address space alignment problem needs to be handled. The encapsulation layer: reconstruct the packet according to the target protocol. When converting TLP to TLM, a TRDP application layer header needs to be added and UDP / TCP (User Datagram Protocol / Transmission Control Protocol) is selected for transmission; for the reverse conversion, a TLP header needs to be generated and the PCIe link layer needs to be adapted. Or the TLP and TLM packets are uniformly converted into an intermediate format (such as JSON (JavaScript Object Notation) or a custom binary structure), and then serialized according to the target protocol. This method is suitable for flexible adaptation between heterogeneous systems.

[0072] Advantageous effects: The present invention connects a controller and a simulation model of a device based on the Non-Volatile Memory Host Controller Interface Specification and a preset virtual operating system simulator through a preset transaction-level component, mutually converts the transaction-level modeling requests and responses of the bus and the transaction layer data packet requests and responses, and processes the transaction layer data packet requests and responses, and transfers them to the simulation model of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification and the preset virtual operating system simulator, so as to realize the communication from the simulation model of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification to the preset virtual operating system simulator, build a controller simulation system based on the preset virtual operating system simulator and the simulation model, and further realize faster development and debugging of the simulation model.

[0073] Based on the previous embodiment, the present invention provides a transaction-level conversion module including a simulated PCIe-RC-Port sub-module, a simulated PCIe-EP sub-module, and a simulated PCIe-EP device interface sub-module. Next, a detailed description will be given of the simulated PCIe-RC-Port (root port based on the Peripheral Component Interconnect Express bus standard) sub-module.

[0074] In the embodiment of the present invention, the simulation PCIe-RC-Port sub-module provides an interface on the host side to dock with the TLM interface module, which is used to receive and send TLM messages. The simulation PCIe-RC-Port sub-module also provides an interface on the device side to dock with the simulation PCIe-EP sub-module, which is used to receive and send TLP messages. The simulation PCIe-RC-Port sub-module is responsible for receiving the TLM messages of the configuration requests and Memory requests from the host, encapsulating the TLM requests into TLP messages, and forwarding them to the simulation PCIe-EP sub-module; and waiting to receive the completed TLP messages. After receiving the completed TLP messages, it replies with TLM response messages to the host. The simulation PCIe-RC-Port sub-module is also responsible for receiving the TLP messages of the DMA data requests from the simulation PCIe-EP sub-module on the device side, converting the TLP messages into TLM messages, and sending them to the host; and waiting to receive the TLM response from the host. After receiving the response, it converts the TLM response into a TLP completion message and sends it to the simulation PCIe-EP sub-module. As Figure 8 shown, the core of the simulation PCIe-RC-Port sub-module is the TLM-to-TLP conversion bridge, which is a mature integrated module. The specific implementation process of the conversion bridge will not be introduced in detail here. The TLM sending interface here is the initiator interface of the SystemC TLM model, and the TLM receiving interface is the target interface of the SystemC TLM model. The TLP sending interface is the initiator interface of the SystemC TLM model, and the TLP receiving interface is the target interface of the SystemC TLM model. The TLP messages are transmitted in the message payload of the TLM model.

[0075] The main process of the simulation PCIe-RC-Port sub-module is to receive TLM messages from the TLM receiving interface, convert the TLM message format into the TLP message format through the TLM-to-TLP conversion bridge, and send it out from the TLP sending interface. Receive TLP messages from the TLP receiving interface, convert the TLP message format into the TLM message format through the TLP-to-TLM conversion bridge, and send it out from the TLM sending interface.

[0076] Beneficial effects: Through the conversion of the simulation PCIe-RC-Port sub-module, the TLM access and TLP access are converted, realizing the isolation between the host address domain and the PCIe address domain, which is convenient for subsequent access to other simulated PCIe devices connected in an extended manner through TLP messages.

[0077] Next, a detailed description will be given for the simulation PCIe-EP (Endpoint based on the Peripheral Component Interconnect Express bus standard) sub-module.

[0078] In the embodiment of the present invention, the simulated PCIe-EP sub-module is responsible for receiving and parsing the TLP packets from the simulated PCIe-RC-Port sub-module; meanwhile, it processes according to the packet types respectively; if it is a configuration request, it is processed by the simulated PCIe-EP sub-module, and the content of the configuration request is returned to generate a Complete packet (completion packet), which is sent to the simulated PCIe-RC-Port sub-module. If it is a Memory request, the register access part is identified; and the access is passed to the simulated PCIe-EP device interface sub-module. If it is a Memory request, the request is parsed into register read / write processing, passed to the simulated PCIe-EP device interface sub-module, and waits for the return result. After receiving the return result, a Complete packet (completion packet) is generated and sent to the simulated PCIe-RC-Port sub-module. The simulated PCIe-EP sub-module is also responsible for receiving the DMA data request from the simulated PCIe-EP device interface sub-module, organizing the Memory read / write TLP packets, and sending them to the simulated PCIe-RC-Port sub-module; and waits for the completion packet from the simulated PCIe-RC-Port sub-module. After receiving the completion packet, it parses the DMA data result and forwards the data result to the simulated PCIe-EP device interface sub-module.

[0079] See Figure 9 As shown, the main working process of the simulated PCIe-EP sub-module for processing the received TLP packets is as follows:

[0080] S2001: Read the payload of the host-side request sent from the interface of the simulated PCIe-RC-Port module. The payload is in the TLP packet format of the PCIe protocol, and extract the type field of the packet.

[0081] S2002: Compare according to the type field of the packet.

[0082] S2003: If it is a completion packet, it means it is a completion packet for the host-side response to the memory request initiated by the device-side. Parse the data in the completion packet, notify the simulated PCIe-EP interface module to process, and after the packet processing is completed, return OK. If it is not a completion packet, jump to S2004.

[0083] S2004: If it is a Memory packet, it means it is a completion packet for the host-side initiated memory request. Parse the address, length, and data information in the request packet, notify the simulated PCIe-EP interface sub-module to process, and after the packet processing is completed, fill the processed data as the result into the completed TLP packet, and go to S2007. If it is not a Memory packet, jump to S2005.

[0084] S2005: If it is a configuration message, it indicates that it is a message for a configuration request initiated by the host side. Parse the accessed register address, length, and data information in the request message, and have the emulated PCIe-EP module handle the configuration register access. After the message processing is completed, fill the processed data as the result into the completed TLP message, and go to S2007. If it is not a configuration message, jump to S2006.

[0085] S2006: This branch processes other types of messages. Fill the all-zero data as the processed result into the completed TLP message, and go to S2007.

[0086] S2007: Send the completed message to the emulated PCIe-RC-Port module. Return.

[0087] See Figure 10 As shown, the processing flow of the emulated PCIe-EP sub-module receiving the DMA request from the device side.

[0088] S3001: Read the information of the DMA request passed from the interface of the emulated PCIe-EP interface sub-module, including the address of the DMA request, the data length, and the address of the DMA data buffer.

[0089] S3002: Assemble a TLP message for the Memory request according to the DMA request information.

[0090] S3003: Send the TLP message to the emulated PCIe-RC-Port sub-module.

[0091] S3004: Wait to receive the completed message passed back from the emulated PCIe-RC-Port sub-module.

[0092] S3005: Process the data carried in the completed message and pass it to the emulated PCIe-EP device interface sub-module.

[0093] Beneficial effects: By distinguishing and processing different types of TLP messages, the present invention separates the configuration processing on the device side of the PCIe-EP device and the Memory message processing on the SimpleSSD NVMe controller side, facilitating the device interface sub-module to connect and process devices.

[0094] Next, a detailed description will be given for the emulated PCIe-EP device interface (endpoint device interface based on the Peripheral Component Interconnect Express bus standard) sub-module.

[0095] In the embodiment of the present invention, the simulation PCIe-EP device interface sub-module provides an interface for hooking up the register read / write interfaces of the SimpleSSD NVMe controller and the device module. The simulation PCIe-EP device interface sub-module also provides interfaces for hooking up the DMA request and response interfaces of the SimpleSSD NVMe controller and the device module. Refer to Figure 11 As shown, after the simulation PCIe-EP device interface sub-module is responsible for receiving the register read / write processing requests from the simulation PCIe-EP sub-module, it is responsible for calling the register read / write processing of the hooked SimpleSSD NVMe controller and the device module, and returning the register read / write data to the simulation PCIe-EP sub-module. Refer to Figure 12 As shown, the simulation PCIe-EP device interface sub-module is also responsible for receiving the DMA data read / write requests from the SimpleSSD NVMe controller. After parsing the information of the DMA data read / write requests, it forwards them to the simulation PCIe-EP sub-module for processing; and waits to receive the DMA data read / write results from the simulation PCIe-EP sub-module. After receiving the read / write result data, it passes it to the hooked SimpleSSD NVMe controller for processing.

[0096] In addition, when the simulation PCIe-EP device interface sub-module hooks up an external device, the simulation PCIe-EP device interface sub-module provides an external device binding interface. Through this interface, the external device handle pointer is saved in the simulation PCIe-EP device interface sub-module, which is convenient for accessing the external device. In the present invention, it is used to bind the object handles of the SimpleSSD NVMe controller and the device module. Binding and hooking are called during the initialization of the top-level module.

[0097] Beneficial effects: The present invention realizes device hooking through the simulation PCIe-EP device interface to complete the transfer of memory transactions and DMA requests and results, and the interfaces between modules are more flexible.

[0098] Refer to Figure 13 As shown, the embodiment of the present invention provides a controller simulation system construction device, which is applied to a preset transaction-level component, including:

[0099] A connection module 11, which is used to connect the simulation models of the controller and the device based on the Non-Volatile Memory Host Controller Interface Specification, and connect to the preset virtual operating system simulator through an inter-process communication component;

[0100] A message processing module 12, which is used to convert the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and call the simulation model to process the first transaction layer data packet message;

[0101] The simulation system construction module 13 is configured to convert the second transaction layer data packet message sent by the simulation model into a second transaction level modeling message, and send the second transaction level modeling message to a preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction level modeling message, realizes the connection and communication between the preset virtual operating system simulator and the simulation model, and constructs a controller simulation system based on the preset virtual operating system simulator and the simulation model.

[0102] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part are described with reference to the embodiments of the above method part and will not be repeated here.

[0103] Beneficial effects: The present invention connects a controller and a simulation model of a device based on the Non-Volatile Memory Host Controller Interface Specification through a preset transaction level component and a preset virtual operating system simulator, mutually converts the transaction level modeling requests and responses of the bus and the transaction layer data packet requests and responses, processes the transaction layer data packet requests and responses, and forwards them to the simulation model of the controller and device based on the Non-Volatile Memory Host Controller Interface Specification and the preset virtual operating system simulator, thereby realizing the communication from the simulation model of the controller and device based on the Non-Volatile Memory Host Controller Interface Specification to the preset virtual operating system simulator, constructing a controller simulation system based on the preset virtual operating system simulator and the simulation model, and further realizing faster development and debugging of the simulation model.

[0104] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 14 It is a structural diagram of an electronic device shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the scope of use of the present application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the controller simulation system construction method disclosed in any of the foregoing embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0105] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and specific limitations are not imposed here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and specific limitations are not imposed here.

[0106] In addition, as a carrier for storing resources, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be transient storage or permanent storage.

[0107] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the controller emulation system construction method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0108] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the controller emulation system construction method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0109] Furthermore, the present application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, the controller emulation system construction method disclosed above is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0110] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0111] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0112] The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0113] Finally, it should also be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0114] The technical solutions provided in this application have been introduced in detail above. Specific examples are used herein to illustrate the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A controller simulation system construction method, characterized in that: Applies to preset transaction-level components, including: Connecting to the simulation model of the controller and the device based on the non-volatile memory host controller interface specification, and connecting to the preset virtual operating system simulator through the inter-process communication component; Converting the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message; The second transaction layer data packet message sent by the simulation model is converted into a second transaction level modeling message, and the second transaction level modeling message is sent to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction level modeling message to achieve connection communication between the preset virtual operating system simulator and the simulation model, so as to build a controller simulation system based on the preset virtual operating system simulator and the simulation model.

2. The controller simulation model construction method according to claim 1, characterized in that: The preset transaction level components include root ports, endpoints, and endpoint device interfaces based on high-speed serial computer expansion bus standards; Correspondingly, the converting the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message includes: Receiving a first transaction-level modeling message corresponding to a target request sent by the preset virtual operating system simulator through a root port based on a high-speed serial computer expansion bus standard; Converting the first transaction-level modeling message into the first transaction-layer data packet message through the root port, and forwarding the first transaction-layer data packet message to the endpoint so that the endpoint parses the first transaction-layer data packet message to determine the type of the target request; If the target request is a memory request, identifying register access content in the target request, and sending the register access content to the endpoint device interface; The register of the simulation model is called through the endpoint device interface to perform corresponding read and write processing on the register access content.

3. The controller simulation model construction method according to claim 2, characterized in that: After calling the simulation model to process the first transaction layer data packet message, the method further includes: Acquiring register read and write data through the endpoint device interface; the register read and write data is data generated by the register of the simulation model performing corresponding read and write processing on the register access content; The register read and write data is returned to the endpoint through the endpoint device interface so that the endpoint generates a corresponding first completion message according to the register read and write data, and the first completion message is sent to the root port so that the root port converts the first completion message into a first transaction-level modeling response message, and sends the first transaction-level modeling response message to the preset virtual operating system simulator; the first completion message is a message in the transaction layer data packet format.

4. The controller simulation model construction method according to claim 2, characterized in that: After determining the type of the target request, the method further includes: If the target request is a configuration request, the target request is directly processed through the endpoint to obtain corresponding configuration content information, and the configuration content information and a second completion message are sent to the root port; the second completion message is a message in a transaction layer data packet format; The second completion message is converted into a second transaction level modeling response message through the root port, and the second transaction level modeling response message is sent to the preset virtual operating system simulator.

5. The controller simulation model construction method according to claim 2, characterized in that: The converting the second transaction layer data packet message sent by the simulation model into a second transaction level modeling message includes: Receiving, through the endpoint device interface, a second transaction layer data packet message corresponding to the direct memory access data read and write request sent by the simulation model, and sending the second transaction layer data packet message to the endpoint; The second transaction layer data packet message is sent to the root port through the endpoint so that the root port converts the second transaction layer data packet message into a second transaction level modeling message.

6. The controller simulation model construction method according to claim 2, characterized in that: After sending the second transaction-level modeling message to the preset virtual operating system simulator so that the preset virtual operating system simulator processes the second transaction-level modeling message, the method further includes: After the preset virtual operating system simulator processes the second transaction level modeling message, generating a corresponding second transaction level modeling response message, and sending the second transaction level modeling response message to the root port; Converting the second transaction-level modeling response message into a third completion message in a transaction layer data packet format through the root port, and sending the third completion message to the endpoint; Parsing the third completion message through the endpoint to obtain a corresponding direct memory access data result, and sending the direct memory access data result to the endpoint device interface; The direct memory access data result is forwarded to the simulation model through the endpoint device interface for corresponding processing.

7. The controller simulation model construction method according to any one of claims 1 to 6, characterized in that: Before converting the first transaction-level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, the method further includes: Initializing the simulation model, the root port, the endpoint and the endpoint device interface of the preset transaction level component based on the high-speed serial computer expansion bus standard; A transaction layer data packet communication interface between the root port and the endpoint is communicatively connected, and a transaction layer data packet communication interface between the endpoint and the endpoint device interface is communicatively connected.

8. A controller simulation system construction device, characterized in that: Applies to preset transaction-level components, including: A connection module, used to connect the controller and the simulation model of the device based on the non-volatile memory host controller interface specification, and connect the preset virtual operating system simulator through the inter-process communication component; A message processing module, used for converting the first transaction level modeling message sent by the preset virtual operating system simulator into a first transaction layer data packet message, and calling the simulation model to process the first transaction layer data packet message; A simulation system construction module is used to convert the second transaction layer data packet message sent by the simulation model into a second transaction level modeling message, and send the second transaction level modeling message to the preset virtual operating system simulator, so that the preset virtual operating system simulator processes the second transaction level modeling message, thereby realizing the connection and communication between the preset virtual operating system simulator and the simulation model, so as to build a controller simulation system based on the preset virtual operating system simulator and the simulation model.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program to implement the steps of the controller simulation system construction method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the controller simulation system construction method according to any one of claims 1 to 7 are implemented.

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