Standard cell library test chip and test method, and computer readable storage medium

Abstract

The invention relates to a standard cell library test chip and test method, and a computer readable storage medium, the chip comprising: a standard cell set module comprising at least one standard cell in a standard cell library, each standard cell in the standard cell set module being classified according to a preset rule; the test vector generation module is connected with the standard unit collection module and is used for generating a test vector corresponding to each type of standard units according to the preset rule; and the output module is connected with the standard unit collection module and is used for outputting results obtained by the standard units according to the corresponding test vectors input by the input ends of the standard units. According to the invention, the redundancy of the test vectors and the increase of operand caused by the input of redundant test vectors by the sequential logic standard unit can be avoided, and the data storage requirements in the standard cell library test chip are reduced.

Description

Technical Field

[0001] This application relates to semiconductor manufacturing, in particular to a standard cell library test chip, a standard cell library test method, and a computer-readable storage medium. Background Art

[0002] With the continuous progress of semiconductor technology, the design scale of digital integrated circuits has been increasing. Especially after MOS (Metal Oxide Semiconductor Field Effect Transistor) enters the ultra-deep sub-micron level of 0.18 microns and below, the design scale of tens of millions or even more transistors has been achieved on a single chip. In the process of digital circuit design, in order to simplify the design process, it is usually necessary to repeatedly call various modules that implement specific basic functions to complete the design and simplify the design process. These modules that implement specific logic functions are standard cells, and the set that encompasses all the standard cells that need to be called is the standard cell library. In summary, the standard cell library plays a crucial role in digital chip design. The correct logic function and performance of the standard cells directly affect the quality of the finally produced chip. Therefore, before a newly developed standard cell library is put into use, it is a crucial task to verify and test its functions and performance. To achieve this goal, the standard cell library test chip came into being.

[0003] An exemplary standard cell library test chip connects the inputs of all the standard cells in parallel after instantiation to a test vector generation module. The number of bits of the test vectors generated by the test vector generation module is determined according to the cell with the most inputs in the standard cell library. During the test, the test vectors change among all possible situations. Each change represents the completion of the test of a standard cell. During this process, the results of the target standard cell are selected and output through a selection signal. The above operations are repeated until all the standard cells are covered by the test. See Figure 8 . The finally obtained output is compared with the expected result to evaluate the functions and performance of the standard cell library. During the test, the test vectors generally change in the form of Gray code or incremental data.

[0004] However, the above-mentioned standard cell library test chip requires a relatively long test time. Summary of the Invention

[0005] Based on this, it is necessary to provide a standard cell library test chip, a test method, and a computer-readable storage medium with a relatively fast test speed.

[0006] A standard cell library test chip, comprising: a standard cell set module, including at least one standard cell in the standard cell library, and each standard cell in the standard cell set module has been classified according to a preset rule; a test vector generation module, connected to the standard cell set module, for generating test vectors corresponding to each type of the standard cells respectively according to the preset rule; an output module, connected to the standard cell set module, for outputting the results obtained by each standard cell according to the corresponding test vectors input to its input end.

[0007] For the above-mentioned standard cell library test chip, each standard cell is classified according to a preset rule. During testing, the test vectors corresponding to each type of standard cell are input to each standard cell, rather than inputting all the test vectors to the standard cells, which avoids the redundancy of test vectors and the increase in the amount of computation caused by the standard cells inputting redundant test vectors, and reduces the internal data storage requirements of the standard cell library test chip.

[0008] In one embodiment, the standard cell set module includes a plurality of sequential logic standard cells in the standard cell library, and those sequential logic standard cells that implement the same function are classified into the same category.

[0009] In one embodiment, among the sequential logic standard cells, those sequential logic standard cells with all input ends except the clear input end and the set input end being the same are classified into the same category.

[0010] In one embodiment, "implementing the same function" means that when the inputs of the first data input ends of the sequential logic standard cells are the same, the outputs of the sequential logic standard cells are the same.

[0011] In one embodiment, at least some of the sequential logic standard cells in the standard cell set module are target sequential logic standard cells. The target sequential logic standard cell includes a first input end and a second input end. The signal of the test vector corresponding to the target sequential logic standard cell input to the first input end changes at a first moment, and the signal input to the second input end changes at a second moment; the second moment is later than the first moment.

[0012] In one embodiment, the first input end is a set input end, the second input end is a clear input end, and the target sequential logic standard cell further includes a first data input end. The signal of the test vector corresponding to the target sequential logic standard cell input to the first data input end changes at a third moment; the third moment is later than the second moment.

[0013] In one embodiment, the second moment is when the system clock first changes after the first moment.

[0014] In one embodiment, after each type of sequential logic standard cell receives the corresponding test vector, it also receives another test vector output by the test vector output module, and then receives the corresponding test vector again; the result output module is configured to output the results obtained by the sequential logic standard cell receiving the corresponding test vector twice successively.

[0015] In one embodiment, the test vector output module is configured to output each test vector in a preset order, and the other test vector is the next test vector of the corresponding test vector.

[0016] In one embodiment, the standard cell set module includes a plurality of combinational logic standard cells in the standard cell library. Combinational logic standard cells with the same number of input terminals are classified into the same category, and the number of input terminals is the same as the number of bits of the corresponding test vector.

[0017] A method for testing a standard cell library includes: classifying each standard cell in the standard cell library according to a preset rule; inputting the test vectors corresponding to each type of standard cell into each standard cell according to the preset rule; the test vectors corresponding to the same type of standard cell are the same; outputting the results obtained by each standard cell based on the corresponding test vector.

[0018] In the above method for testing a standard cell library, each standard cell is classified according to a preset rule. During testing, the test vectors corresponding to each type of standard cell are input into each standard cell, rather than inputting all test vectors into the standard cells, thus avoiding redundancy of test vectors and increased computational complexity caused by the standard cells receiving redundant test vectors.

[0019] In one embodiment, the standard cell library includes a plurality of sequential logic standard cells. The step of classifying each standard cell in the standard cell library according to a preset rule includes: classifying sequential logic standard cells that implement the same function into the same category.

[0020] In one embodiment, among the sequential logic standard cells, sequential logic standard cells with all input terminals the same except for the clear input terminal and the set input terminal are classified into the same category.

[0021] In one embodiment, "implementing the same function" means that when the inputs of the first data input terminal of the sequential logic standard cell are the same, the outputs of the sequential logic standard cell are the same.

[0022] In one embodiment, at least part of the timing logic standard cells are target timing logic standard cells, and the target timing logic standard cells include a first input terminal and a second input terminal; the step of inputting the test vectors corresponding to each type of the standard cells into the respective standard cells according to the preset rule includes: the signal of the test vector corresponding to the target timing logic standard cell input into the first input terminal changes at a first moment; the signal of the test vector corresponding to the target timing logic standard cell input into the second input terminal changes at a second moment; the second moment is later than the first moment.

[0023] In one embodiment, the first input terminal is a set-one input terminal, the second input terminal is a set-zero input terminal, and the target timing logic standard cell further includes a first data input terminal; the step of inputting the test vectors corresponding to each type of the standard cells into the respective standard cells according to the preset rule further includes: the signal of the test vector corresponding to the target timing logic standard cell input into the first data input terminal changes at a third moment; the third moment is later than the second moment.

[0024] In one embodiment, the step of inputting the test vectors corresponding to each type of the standard cells into the respective standard cells according to the preset rule is to input different test vectors into the corresponding standard cells of each type in a preset order; the step of inputting the test vectors corresponding to each type of the standard cells into the respective standard cells according to the preset rule includes: Step 1, inputting the test vector corresponding to the currently tested timing logic standard cell into the currently tested timing logic standard cell; Step 2, after Step 1, inputting the next test vector of the corresponding test vector into the currently tested timing logic standard cell; Step 3, after Step 2, inputting the corresponding test vector into the currently tested timing logic standard cell; the step of outputting the results obtained by the respective standard cells based on the corresponding test vectors includes outputting the results obtained in Step 1 and Step 3.

[0025] In one embodiment, the standard cell library includes a plurality of combinational logic standard cells, and those combinational logic standard cells with the same number of input terminals are classified into the same type, and the number of their input terminals is the same as the number of bits of the corresponding test vector.

[0026] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the method of any of the above embodiments are implemented.

[0027] It is also necessary to provide a computer device, including a memory and a processor, where a computer program is stored in the memory, and when the processor executes the computer program, the steps in the method described in any of the foregoing embodiments are implemented.

[0028] It is also necessary to provide a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0030] Figure 1 is a schematic diagram of the structure of a standard cell library test chip in an embodiment of the present application;

[0031] Figure 2 Schematic diagram of grouping of combinational logic standard cells and sequential logic standard cells in one embodiment of the present application;

[0032] Figure 3 is a test vector assignment sorting diagram in an embodiment of the present application;

[0033] Figure 4 It is the schematic diagram of the sequential logic standard unit cycle test;

[0034] Figure 5 is a flow chart of a standard cell library testing method in one embodiment of the present application;

[0035] Figure 6 This is a flow chart of time-sharing value assignment for each bit of a test vector in one embodiment of the present application;

[0036] Figure 7 is a flow chart of a sequential logic standard unit cycle test in one embodiment of the present application;

[0037] Figure 8 It is a standard unit library test schematic diagram of related technology. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0040] The terms used herein are for the purpose of describing specific embodiments only and are not to be construed as limiting the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] Figure 1 It is a schematic structural diagram of a standard cell library test chip in an embodiment of the present application, including a test vector output module 10, a standard cell set module 20 and a result output module 30. The standard cell set module 20 includes each standard cell in the standard cell library, and each standard cell in the standard cell set module 20 has been classified according to a preset rule. The test vector output module 10 is connected to the standard cell set module 20 and is configured to output test vectors corresponding to each type of standard cell generated according to a preset rule. The result output module 30 is connected to the standard cell set module 20 and is configured to output the results obtained by each standard cell based on the corresponding test vectors input to its input terminal. In an embodiment of the present application, the test vector output module 10 generates test vectors corresponding to each type of standard cell according to a preset rule; in another embodiment of the present application, the test vector output module 10 outputs the test vectors corresponding to each type of standard cell generated according to a preset rule input from the outside of the standard cell library test chip to the corresponding standard cells. In an embodiment of the present application, the result output module 30 outputs the result obtained by selecting a target standard cell (i.e., the currently tested standard cell).

[0042] For the above-mentioned standard cell library test chip, each standard cell is classified according to a preset rule. During testing, the test vectors corresponding to each type of standard cell are input to each standard cell (i.e., test vectors of different bit widths are input to the corresponding standard cells), rather than inputting all the test vectors to the standard cells, which avoids the redundancy of test vectors and the increase in the amount of calculation caused by the standard cells receiving redundant test vectors, and reduces the internal data storage requirements of the standard cell library test chip.

[0043] In one embodiment of the present application, the test vectors output by the test vector output module 10 are generated by a state machine. To achieve the output control of different types of test vectors and test results, different modules can be triggered through logical judgment statements to generate different test vectors for the purpose of controlling the test vectors. The standard cell set module 20 can first output the test results of all standard cells in parallel, and then the result output module 30 selects the results of the currently tested standard cells according to the test item signal for output, and then compares the output with the expected results.

[0044] In one embodiment of the present application, the standard cell set module 20 includes all the sequential logic standard cells in the standard cell library, and those sequential logic standard cells that implement the same function are classified into the same category.

[0045] To simplify the number of test vectors output by the test vector output module 10, the present application groups (classifies) the sequential logic standard cells in the standard cell library during design. For the test of sequential logic standard cells, different types of sequential logic standard cells have different types of inputs, such as RN (reset input terminal), SN (set input terminal), SE (data selection terminal), SI (second data input terminal), D (first data input terminal), CLK (clock input terminal), etc. Among them, SE is used to enable the selection between SI and D. When SE is in the first state (for example, the input signal is 0), the input terminal that takes effect is D (enabling the data input by the first data input terminal); when SE is in the second state (for example, the input signal is 1), the input terminal that takes effect is SI. The registers and latches corresponding to these sequential logic standard cells that implement different functions have certain requirements for the input order and input priority. For different sequential logic standard cells with the same main function and thus the same function, their input terminals may be different. For example, for RN and SN, there may be only RN or only SN, or both. However, the functions implemented by these sequential logic standard cells are the same. Specifically, for example, when a specific value is input to the first data input terminal D, the output results Q of these sequential logic standard cells are the same. Therefore, the sequential logic standard cells that implement the same function are grouped into the same group during grouping to avoid excessive grouping. In one embodiment of the present application, implementing the same function means that when the input of the first data input terminal (D) of the sequential logic standard cell is the same, the output of the sequential logic standard cell is the same. In one embodiment of the present application, the sequential logic standard cells with all input terminals the same except for the reset input terminal and the set input terminal are classified into the same category.

[0046] In an embodiment of the present application, the standard cell set module 20 includes all combinational logic standard cells in the standard cell library. For the test of combinational logic standard cells, since combinational logic standard cells are insensitive to timing, the input order of all input terminals and the state of the previous moment of the input terminals have no influence on the output result. Therefore, it is only necessary to divide the combinational logic standard cells into several groups according to the number of input terminals, and the number of input terminals of the combinational logic standard cells in each group is the same as the number of bits of the corresponding test vector.

[0047] In an embodiment of the present application, the test vector output module 10 has multiple output terminals, and each output terminal outputs one bit of data in the test vector. The input terminals with the same attribute in each combinational logic standard cell and sequential logic standard cell are connected to the same output terminal of the test vector output module 10. Here, the same attribute means that the access signal types are the same. For example, they are all RN, or they are all SN, etc. Further, the input terminals with the same attribute of different standard cells can be connected in parallel and then connected to the same output terminal of the test vector output module 10.

[0048] Figure 2 It is a schematic diagram of the grouping of combinational logic standard cells and sequential logic standard cells in an embodiment of the present application, where COMB represents combinational logic and DFF represents sequential logic. For combinational logic, the combinational logic standard cells with two input terminals are divided into one group, the combinational logic standard cells with three input terminals are divided into one group, the combinational logic standard cells with four input terminals are divided into one group... Figure 2 The test vector corresponding to the two input terminals in it is the two-bit VECTORC0[1:0], that is, when testing, the combinational logic standard cells with two input terminals are tested through VECTORC0[1:0]. Similarly, the test vector corresponding to the three input terminals is the three-bit VECTORC1[2:0], and the test vector corresponding to the four input terminals is the four-bit VECTORC2[3:0]. For sequential logic, the sequential logic standard cells with input terminals CLK and D are divided into one group, and the corresponding test vector is the two-bit VECTORD0[1:0]. The sequential logic standard cells with input terminals including CLK and D and at least one of SN and RN are divided into one group, and the corresponding test vector is the four-bit VECTORD1[3:0]. The sequential logic standard cells with input terminals CLK, D, SI, and SE are divided into one group, and the corresponding test vector is the four-bit VECTORD2[3:0]... In addition, all the test vectors generated according to the preset rules and corresponding to each type of standard cell output by the test vector output module 10 ( Figure 2VECTORC0[1:0], VECTORC1[2:0], VECTORC0[3:0], VECTORD0[1:0], VECTORD1[3:0], VECTORD2[3:0], etc. in it), and their functions are all fixed. For example, VECTORD*[0] serves as the input of the RN (reset input terminal) of all standard cells, and VECTORD*[1] serves as the input of the SN (set input terminal) of all standard cells, etc.

[0049] After grouping the combinational logic standard cells and sequential logic standard cells, corresponding test vectors can be configured for each group. The test vectors can be generated by the test vector output module 10 according to pre-configured rules. In an embodiment of the present application, the test vector output module 10 is configured to output each test vector in a preset order.

[0050] For sequential logic standard cells, strictly speaking, there are certain input order requirements and usage rules for inputs of types such as set, reset, data, and clock. If all bits of the test vector are input simultaneously when testing sequential logic standard cells, it is likely to cause the output result of the sequential logic standard cell to be invalid or incorrect. To truly simulate the application of standard cells in practice, variables with mutually exclusive logic or race hazards should be assigned values separately. In actual applications, due to the existence of cell delay, wire delay, and other delays, there is usually no situation where two signals arrive completely simultaneously. Therefore, when assigning the test vector each time, each bit of the test vector is assigned time-divisionally in a preset order.

[0051] In an embodiment of the present application, at least some of the sequential logic standard cells in the standard cell set module 20 include a first input terminal and a second input terminal. For the corresponding test vector, the signal input to the first input terminal changes at a first moment, and the signal input to the second input terminal changes at a second moment, and the second moment is later than the first moment. In an embodiment of the present application, the second moment is the first time the system clock changes after the first moment. In an embodiment of the present application, the first input terminal is a set input terminal, the second input terminal is a reset input terminal, and the sequential logic standard cell further includes a first data input terminal. The signal input to the first data input terminal of the corresponding test vector changes at a third moment; the third moment is later than the second moment. In an embodiment of the present application, the sequential logic standard cell further includes a clock input terminal. The signal input to the clock input terminal of the corresponding test vector changes at a fourth moment; the fourth moment is later than the third moment.

[0052] In an embodiment of the present application, for the test vector output by the test vector output module 10 to test the sequential logic standard cell a with a reset input terminal (RN) or a set input terminal (SN), the valid signal of the test vector is received by the reset input terminal (RN) of the sequential logic standard cell a later than the set input terminal (SN). The data input terminal (D) of the sequential logic standard cell a receives the valid signal of the test vector later than the reset input terminal (RN). The valid signal means that, for example, if the data corresponding to the RN bit of a certain test vector is "1", then when "1" (i.e., high level) is received, it is the valid signal of the test vector, and when "0" (i.e., low level) is received, it is not the valid signal of the test vector.

[0053] Figure 3 This is a test vector assignment sorting diagram in an embodiment of the present application. Taking the inputs D, RN, SN, clk, and other data inputs (OTHER) as an example, the implementation method of time-sharing assignment is introduced. Figure 3 The signal DFF_CLK in it is the signal of the clock input terminal (CLK) of the input sequential logic standard cell, and the signal CLK is the system clock signal. First, SN is assigned at the rising edge of the first clock cycle of the system clock (CLK), then RN is assigned at the falling edge of the first clock cycle of the system clock, and then D and other inputs are assigned at the rising edge of the second clock cycle of the system clock. After all the data is stable at the input terminal of the sequential logic standard cell, the valid edge of DFF_CLK is given at the rising edge of the next system clock for testing. The clock of the input sequential logic standard cell is reset after one system clock cycle to start the test process of the next test vector. Figure 3 The shown assignment order corresponds to the grouping of sequential logic standard cells with a reset input terminal (RN) or a set input terminal (SN). The actual designed assignment order is subject to the target sequential logic standard cell. The above time-sharing assignment can be implemented by the state machine embedded in the standard cell library test chip.

[0054] In an embodiment of the present application, after each type of sequential logic standard cell receives the corresponding test vector (test vector i), it will also receive another test vector output by the test vector output module 10, and then receive the corresponding test vector (test vector i) again. The result output module 30 is used to output the results obtained by the sequential logic standard cell receiving the corresponding test vector twice, that is, whether both of these two results meet the expectations needs to be verified.

[0055] To verify whether the sequential logic standard cells can work properly during the jumping process of different test vectors (simulating whether the high-frequency use of sequential logic standard cells in different states in a real application scenario will cause functional abnormalities, etc.), a loop test process can be added. That is, during the test process of each test vector (denoted as test vector i), it will jump to the next test vector i + 1, and then return to test vector i again. Refer to Figure 4 。

[0056] In an embodiment of the present application, before this loop test, the "reset and set method" can also be used to test each test vector. Since the output result of the sequential logic standard cell is related not only to the output at the current moment but also to the state of the output terminal Q of the sequential logic standard cell at the previous moment. Therefore, to ensure the integrity and accuracy of the test, when testing the same test vector, the state of the Q terminal can be set to zero and one respectively. That is, after setting the Q terminal to zero, input the target test vector to the sequential logic standard cell; after setting the Q terminal to one, input the target test vector to the sequential logic standard cell. The test results obtained in the reset and set states need to be verified whether they meet the expectations. In an embodiment of the present application, after the reset and set test, the standard cell library test chip will automatically jump to the aforementioned loop test to save the test cost and time.

[0057] Based on all the above embodiments, the present application pre-classifies and sets the standard cells to be tested, and uses test vectors with different numbers of bits to test the standard cells with different inputs, which ensures the test coverage while effectively reducing the test vectors generated inside the standard cell library test chip, reducing redundancy, and further reducing the internal data storage requirements and chip area. During the test process of the sequential logic standard cell, the input order of the input terminal is controlled by a state machine to test the cell more in line with the actual usage situation, avoiding the generation of logical confusion and incorrect data, thereby reducing the subsequent debugging cost. And a loop test is performed on the sequential logic standard cell to improve the test coverage of the sequential logic standard cell and ensure the logical correctness of its jump in different states.

[0058] The present application correspondingly provides a method for testing a standard cell library. Figure 5 is a flowchart of the method for testing a standard cell library in an embodiment of the present application, including the following steps:

[0059] S510, classify each standard cell in the standard cell library according to a preset rule.

[0060] In an embodiment of the present application, it includes classifying each timing logic standard cell in the standard cell library, and the timing logic standard cells that implement the same function are classified into the same class (group). Implementing the same function means that when the inputs of the data input terminals (D) of the timing logic standard cells are the same, the outputs of the timing logic standard cells are the same. In an embodiment of the present application, the timing logic standard cells with all input terminals the same except for the reset input terminal (RN) and the set input terminal (SN) are classified into the same class.

[0061] In an embodiment of the present application, it further includes classifying each combinational logic standard cell in the standard cell library. The combinational logic standard cells with the same number of input terminals are classified into the same class, and the number of its input terminals is the same as the number of bits of the corresponding test vector.

[0062] S520, input the test vectors corresponding to each class of standard cells into each standard cell according to a preset rule.

[0063] The test vectors corresponding to the same class of standard cells are the same.

[0064] S530, output the results obtained by each standard cell based on the corresponding test vector.

[0065] The above-mentioned standard cell library testing method classifies each standard cell according to a preset rule. When testing, the test vectors corresponding to each class of standard cells are input into each standard cell, rather than inputting all the test vectors into the standard cell, which avoids the redundancy of test vectors and the increase in the amount of calculation caused by the standard cell inputting redundant test vectors.

[0066] In an embodiment of the present application, step S520 provides the corresponding test vectors for each class of timing logic standard cells and each class of combinational logic standard cells in a preset order.

[0067] In an embodiment of the present application, at least some of the timing logic standard cells are target timing logic standard cells, and the target timing logic standard cells include a first input terminal and a second input terminal. Step S520 includes:

[0068] The signal of the test vector corresponding to the target timing logic standard cell input to the first input terminal changes at the first moment.

[0069] The signal of the test vector corresponding to the target timing logic standard cell input to the second input terminal changes at the second moment. The second moment is later than the first moment.

[0070] In an embodiment of the present application, the first input terminal is a set-one input terminal (SN), the second input terminal is a set-zero input terminal (RN), and the target timing logic standard cell further includes a first data input terminal (D). Step S520 further includes that the signal of the test vector corresponding to the target timing logic standard cell input to the first data input terminal changes at a third moment. The third moment is later than the second moment.

[0071] In an embodiment of the present application, in order to avoid invalid or incorrect results output by the timing logic standard cell caused by inputting all signals of the test vector at the same time during the test of the timing logic standard cell, each bit of the test vector is assigned time-divisionally in a preset order. See Figure 6 , in an embodiment of the present application, step S520 includes:

[0072] S632, the valid signal of the test vector arrives at the set-one input terminal of the target timing logic standard cell.

[0073] The valid signal means that, for example, if the data of the bit corresponding to RN in a certain test vector is "1", then when receiving "1" (i.e., high level), it is receiving the valid signal of the test vector, and when receiving "0" (i.e., low level), it is not the valid signal of the test vector.

[0074] S634, the valid signal of the test vector arrives at the set-zero input terminal of the target timing logic standard cell.

[0075] The set-zero input terminal (RN) receives the valid signal of the same test vector later than the set-one input terminal (SN).

[0076] S636, the valid signal of the test vector arrives at the data input terminal of the target timing logic standard cell.

[0077] The data input terminal (D) receives the valid signal of the same test vector later than the set-zero input terminal (RN).

[0078] S638, the valid signal of the test vector arrives at the clock input terminal of the target timing logic standard cell.

[0079] After all data is stable at the input terminal of the target timing logic standard cell, the clock input terminal (CLK) receives the valid signal of the same test vector.

[0080] In order to verify whether the timing logic standard cell can work properly during the transition process of different test vectors, a cyclic test is performed on the timing logic standard cell. See Figure 7 , in an embodiment of the present application, step S520 includes:

[0081] S631, input the corresponding test vector i into the currently tested timing logic standard cell.

[0082] S633, input the next test vector i + 1 of the test vector i into the current standard cell of the timing logic under test.

[0083] S635, input the corresponding test vector i into the current standard cell of the timing logic under test again.

[0084] It is necessary to verify whether the output results of the current standard cell of the timing logic under test in steps S631 and S635 meet the expectations. In an embodiment of the present application, a set-to-zero and set-to-one test can be performed before the loop test.

[0085] It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0086] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., and are not limited thereto. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., and are not limited thereto.

[0087] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the method described in any of the above embodiments are implemented.

[0088] The present application also provides a computer device, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps in the method described in any of the foregoing embodiments are implemented.

[0089] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the method described in any of the foregoing embodiments are implemented.

[0090] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0091] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0092] The above-described embodiments only represent several implementation manners of the present invention, and the descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A standard cell library test chip, characterized in that, Comprising: A standard cell set module, including a plurality of standard cells in a standard cell library, and each standard cell in the standard cell set module has been classified according to a preset rule; A test vector output module, connected to the standard cell set module, for outputting test vectors corresponding to each type of the standard cells respectively generated according to the preset rule; A result output module, connected to the standard cell set module, for outputting the results obtained by each of the standard cells based on the corresponding test vectors input to their input terminals.

2. The standard cell library test chip according to claim 1, wherein The standard cell set module includes a plurality of sequential logic standard cells in the standard cell library, and those sequential logic standard cells that implement the same function are classified into the same category.

3. The standard cell library test chip according to claim 2, wherein At least some of the sequential logic standard cells in the standard cell set module are target sequential logic standard cells, the target sequential logic standard cells include a first input terminal and a second input terminal, the signal of the test vector corresponding to the target sequential logic standard cell input to the first input terminal changes at a first moment, and the signal of the test vector input to the second input terminal changes at a second moment; the second moment is later than the first moment.

4. The standard cell library test chip according to claim 2, wherein After each type of sequential logic standard cell receives the corresponding test vector, it will also receive another test vector output by the test vector output module, and then receive the corresponding test vector again; The result output module is used to output the results obtained by the sequential logic standard cell receiving the corresponding test vector twice successively.

5. The standard cell library test chip according to claim 4, characterized in that The test vector output module is configured to output each test vector in a preset order, and the other test vector is the next test vector of the corresponding test vector.

6. The standard cell library test chip according to claim 1, characterized in that The standard cell set module includes a plurality of combinational logic standard cells in the standard cell library, and those combinational logic standard cells with the same number of input terminals are classified into the same category, and the number of their input terminals is the same as the number of bits of the corresponding test vector.

7. A standard cell library testing method, characterized in that, Comprising: Classifying each standard cell in the standard cell library according to a preset rule; Inputting the test vectors corresponding to each type of the standard cells respectively into the respective standard cells according to the preset rule; the test vectors corresponding to the same type of standard cells are the same; Outputting the results obtained by the respective standard cells based on the corresponding test vectors.

8. The standard cell library testing method according to claim 7, characterized in that The standard cell library includes a plurality of sequential logic standard cells, and the step of classifying each standard cell in the standard cell library according to a preset rule includes: classifying the sequential logic standard cells that implement the same function into the same category.

9. The standard cell library testing method according to claim 8, characterized in that At least some of the sequential logic standard cells are target sequential logic standard cells, and the target sequential logic standard cells include a first input terminal and a second input terminal; The step of inputting the test vectors corresponding to each type of the standard cells respectively into the respective standard cells according to the preset rule includes: The signal of the test vector corresponding to the target sequential logic standard cell input to the first input terminal changes at a first moment; The signal of the test vector corresponding to the target sequential logic standard cell input to the second input terminal changes at a second moment; the second moment is later than the first moment.

10. The standard cell library testing method according to claim 8, characterized in that, The step of inputting the test vectors respectively corresponding to each type of the standard cells according to the preset rule into the respective standard cells is to input different test vectors into the corresponding types of standard cells respectively in a preset order; The step of inputting the test vectors respectively corresponding to each type of the standard cells according to the preset rule into the respective standard cells includes: Step 1, inputting the test vector corresponding to the currently tested sequential logic standard cell into the currently tested sequential logic standard cell; Step 2, after Step 1, inputting the next test vector of the corresponding test vector into the currently tested sequential logic standard cell; Step 3, after Step 2, inputting the corresponding test vector into the currently tested sequential logic standard cell; The step of outputting the results obtained by the respective standard cells based on the corresponding test vectors includes outputting the results obtained in Step 1 and Step 3.

11. The standard cell library testing method according to claim 7, wherein The standard cell library includes a plurality of combinational logic standard cells. Those combinational logic standard cells with the same number of input terminals are classified into the same type, and the number of their input terminals is the same as the number of bits of the corresponding test vector.

12. A computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps in the standard cell library testing method according to any one of claims 7-11.

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