A bit line driving circuit for a FLASH memory and computing array

Abstract

The present invention discloses a bit line driving circuit for a FLASH memory and computing array, belonging to the field of integrated circuits, which includes a switching potential transfer module, a read / write and computing switch module, and an erase / program switch module. The input end of the switching potential transfer module receives a working state control signal and a power supply signal, and the output end is connected to the source, drain, and substrate of the read / write and computing switch module and the erase / program switch module; the source, drain, and substrate of the read / write and computing switch module are connected to the output end of the switching potential transfer module, the gate is connected to a control signal, and the output end is connected to the bit line of the FLASH memory and computing array; the source, drain, and substrate of the erase / program switch module are connected to the output end of the switching potential transfer module, the gate is connected to a control signal, and the output end is connected to the bit line of the FLASH memory and computing array. The present invention can quickly and accurately provide the bit line potential of each unit in the FLASH memory and computing array according to the requirements of the control signal, while maintaining a low power consumption level of the unselected array units.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a bit-line driving circuit for a FLASH memory-computation array. Background Art

[0002] In today's mainstream memory-computation integrated arrays, the media mainly include phase change memory (PCM), resistive random access memory (RRAM), and floating gate devices (Flash). Among them, floating gate devices have the characteristics of mature technology, high storage density, low cost, large-scale production, and natural compatibility with CMOS technology, showing unique advantages in the field of in-memory computing. In addition, FLASH devices also have the characteristics of more accurate reading of multi-resistance state data, and are a common choice for constructing memory-computation arrays.

[0003] The design of traditional Flash driving circuits is mainly oriented to storage functions, and it is difficult to meet the requirements of high computing efficiency and low power consumption in the memory-computation scenario. There is an urgent need for a targeted circuit to drive the memory-computation array constructed by FLASH devices. Summary of the Invention

[0004] The purpose of the present invention is to provide a bit-line driving circuit for a FLASH memory-computation array to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a bit-line driving circuit for a FLASH memory-computation array.

[0006] The output of the bit-line driving circuit is used to provide the potentials of the bit-lines of multiple memory-computation array units in the FLASH memory-computation array.

[0007] The bit-line driving circuit includes a switching potential transfer module, a read / write-compute switch module, and an erase / program switch module.

[0008] The input end of the switching potential transfer module receives a control signal and a power supply signal, and outputs six potentials, namely the first potential to the sixth potential, which are connected to the source, drain, substrate, and deep n-well of each device in the read / write-compute switch module and the erase / program switch module.

[0009] The source, drain, substrate, and deep n-well of the read / write-compute switch module are connected to the output end of the switching potential transfer module, the gates of the internal devices are connected to the control signal and the fourth potential and the fifth potential, and the output end is connected to the bit-line of the FLASH memory-computation array.

[0010] The source, drain, and substrate of the erase / program switch module are connected to the output end of the switching potential transfer module, the gate is connected to the control signal, and the output end is connected to the bit-line of the FLASH memory-computation array.

[0011] The read / write and computing switch module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first inverter, and requires the source line potential as an input; among them,

[0012] The first NMOS transistor is fabricated in a p-well within a deep n-well. Its gate terminal is connected to the fourth potential output by the switch potential transfer module. Its source terminal is connected to the drain terminals of the second NMOS transistor and the third NMOS transistor. Its drain terminal is connected to the drain terminal of the fourth NMOS transistor and is connected to the bit line output. Its substrate is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply;

[0013] The gate terminal of the second NMOS transistor is connected to the column select signal. Its source terminal and substrate are grounded. Its drain terminal is connected to the source terminal of the first NMOS transistor and the drain terminal of the third NMOS transistor;

[0014] The gate terminal of the third NMOS transistor is connected to the output of the first inverter. Its source terminal is connected to the source line potential. Its drain terminal is connected to the source terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor. Its substrate is grounded;

[0015] The gate terminal of the fourth NMOS transistor is connected to the fifth potential. Its source terminal and substrate are grounded. Its drain terminal is connected to the drain terminal of the first NMOS transistor and is connected to the bit line output;

[0016] The input of the first inverter is connected to the column select signal, and the output is connected to the gate terminal of the third NMOS transistor.

[0017] In one embodiment, the control signals input by the switch potential transfer module include four working state signals of default, erase, program, read / write and computing, and a bit line selection control signal. The power supply signals input by the switch potential transfer module include five power supply signals and a ground signal;

[0018] The switch potential transfer module includes five potential output modules: a first potential output module, a second potential output module, a third potential output module, a fourth potential output module, and a fifth potential output module. Each potential output module consists of a level conversion module and an output transistor. Among them:

[0019] The input terminal of the level conversion module receives the control signal and the power supply signal, and the converted level output is used as the control signal received by the output transistor;

[0020] The output terminal of the output transistor determines the source, drain, substrate, and deep n-well potentials of each device in the read / write and computing switch module and the erase / program switch module.

[0021] In one embodiment, the erase / program switch module includes a fifth NMOS transistor, a first PMOS transistor, and a second inverter; among them,

[0022] The fifth NMOS transistor is fabricated in a p-well within a deep n-well. Its gate terminal is connected to the programming state control signal, its source terminal is connected to the sixth potential, its drain terminal is connected to the drain terminal of the first PMOS transistor and is connected to the bit line output, its substrate is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply;

[0023] The first PMOS transistor is fabricated in a deep n-well. Its gate terminal is connected to the output of the second inverter, its source terminal is connected to the second potential, its drain terminal is connected to the drain terminal of the fifth NMOS transistor and is connected to the bit line output, its substrate is connected to the first potential, and the deep n-well is grounded;

[0024] The input of the second inverter is connected to the programming state control signal, and the output is connected to the gate terminal of the fifth NMOS transistor.

[0025] In one embodiment, the first potential output module includes two first-level conversion modules; wherein,

[0026] The input potential of the first-level conversion module is connected to the erase working state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential and the second output potential are connected to the gate of the output transistor.

[0027] In one embodiment, the second potential output module includes one first-level conversion module and two second-level conversion modules; wherein,

[0028] The input potential of the first-level conversion module is connected to the erase working state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, the first output potential is connected to the gate of the output transistor and is left floating, and the second output potential is connected to the gate of the output transistor;

[0029] The input potential of the first second-level conversion module is connected to the programming working state signal, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential is connected to the gate of the output transistor, and the second output potential is left floating;

[0030] The input potential of the second second-level conversion module is connected to the NOR of the erase and programming working state signals, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential is connected to the gate of the output transistor, and the second output potential is left floating.

[0031] In one embodiment, the third potential output module includes one third-level conversion module; wherein,

[0032] The input potential of the third-level conversion module is connected to the programming working state signal, the VP terminal is connected to the second power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential and the second output potential are connected to the gate of the output transistor.

[0033] In one embodiment, two third-level level conversion modules are included in the fourth potential output module; among them,

[0034] The input potential of the first third-level level conversion module is connected to the read / write arithmetic operation state signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module, VDD is connected to the third power supply, VSS is grounded, the first output potential is connected to the gate terminal of the first NMOS transistor in the read / write arithmetic operation switch module, and the second output potential is left floating;

[0035] The input potential of the second third-level level conversion module is connected to the default state operation state signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module, VDD is connected to the third power supply, VSS is grounded, the first output potential is connected to the gate terminal of the fourth NMOS transistor in the read / write arithmetic operation switch module, and the second output potential is left floating.

[0036] In one embodiment, a fourth-level level conversion module is included in the fifth potential output module; among them,

[0037] The input potential of the fourth-level level conversion module is connected to the bit selection signal, the VP terminal is connected to the third power supply, the VN1 terminal is connected to the output terminal of the second potential output module, the VN2 terminal is connected to the output terminal of the third potential output module, VDD is connected to the third power supply, VSS is grounded, and the output potential is connected to the gate terminal of the first NMOS transistor in the programming / erasing switch module.

[0038] In one embodiment, the bit line driving circuit is default in the default state and needs to be briefly switched to the default state first and then to the next working state when switching between different working states.

[0039] A bit line driving circuit for a FLASH arithmetic operation array provided by the present invention can quickly and accurately provide the bit line potentials of each unit in the FLASH arithmetic operation array according to the requirements of control signals, and at the same time maintain the low power consumption level of the unselected array units. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of the structural principle of the bit line driving circuit and the FLASH arithmetic operation array.

[0041] Figure 2 It is a schematic diagram of the structure of a single FLASH arithmetic operation unit.

[0042] Figure 3 It is a schematic diagram of the structure of the bit line driving circuit in the embodiment.

[0043] Figure 4 It is a timing diagram of the input control signal in the embodiment.

[0044] Figure 5 It is a schematic diagram of the structure of the switch potential transfer module in the embodiment.

[0045] Figure 6 It is a schematic structural diagram of the first potential output module in the embodiment.

[0046] Figure 7 It is a schematic structural diagram of the second potential output module in the embodiment.

[0047] Figure 8 It is a schematic structural diagram of the third potential output module in the embodiment.

[0048] Figure 9 It is a schematic structural diagram of the fourth potential output module in the embodiment.

[0049] Figure 10 It is a schematic structural diagram of the fifth potential output module in the embodiment.

[0050] Figure 11 It is a schematic structural diagram of the read / write arithmetic switch module in the embodiment.

[0051] Figure 12 It is a schematic structural diagram of the programming / erasing switch module in the embodiment.

[0052] Figure 13 It is a schematic structural diagram of the first level conversion module used in this application.

[0053] Figure 14 It is a schematic structural diagram of the second level conversion module used in this application.

[0054] Figure 15 It is a schematic structural diagram of the third level output module used in this application.

[0055] Figure 16 It is a schematic structural diagram of the fourth level conversion circuit used in this application.

[0056] Figure 17 It is a timing diagram of the input control signal and a schematic diagram of the output signal in the embodiment.

[0057] Figure 18 It is a specific schematic diagram of a bit line driving circuit for a FLASH arithmetic array provided by the present invention. Detailed implementation manners

[0058] The following further describes in detail a bit line driving circuit for a FLASH arithmetic array proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0059] Figure 1 It is a schematic diagram of the principle of the bit line driving circuit and the FLASH memory and computing array structure, including the bit line driving circuit 100 and multiple memory and computing array units 101. The output of the bit line driving circuit 100 is used to provide the potential of the bit line BL in multiple memory and computing array units 101.

[0060] The structure of a single FLASH memory and computing unit is as Figure 2 shown, including the word line WL, the source line SL, and the bit line BL. The structure of the bit line driving circuit 100 is as Figure 3 shown, including the switch potential transfer module 102, the read / write and compute switch module 103, and the erase / program switch module 104. A specific schematic diagram of the bit line driving circuit for the FLASH memory and computing array provided by the present invention is as Figure 18 shown; among them, the structure of the switch potential transfer module 102 is as Figure 5 shown. Its input terminal receives the control signal and the power supply signal, and outputs the first potential to the sixth potential, a total of six potentials, which are connected to the source, drain, substrate, and deep n-well of each device in the read / write and compute switch module 103 and the erase / program switch module 104.

[0061] The structure of the read / write and compute switch module 103 is as Figure 11 shown. Its source, drain, substrate, and deep n-well are connected to the output terminal of the switch potential transfer module 102. The gates of the internal devices are connected to the control signal, the fourth potential, and the fifth potential, and the output terminal is connected to the bit line BL of the FLASH memory and computing array.

[0062] The structure of the erase / program switch module 104 is as Figure 12 shown. Its source, drain, and substrate are connected to the output terminal of the switch potential transfer module 102, the gate is connected to the control signal, and the output terminal is connected to the bit line BL of the FLASH memory and computing array.

[0063] In the present invention, the control signals input to the switch potential transfer module 102 include four working state signals of default, erase, program, read / write and compute, and a column selection (bit line selection) control signal. The power supply signals input to the switch potential transfer module 102 include five power supply signals and a ground signal.

[0064] In the present invention, five potential output modules are used in the switch potential transfer module 102: the first potential output module 110, the second potential output module 120, the third potential output module 130, the fourth potential output module 140, and the fifth potential output module 150, which are respectively as Figure 6 , Figure 7 , Figure 8 , Figure 9 , 10 shown. Each potential output module consists of a level conversion module and an output transistor, where:

[0065] The input end of the level conversion module receives a control signal and a power supply signal, and outputs the converted level as the control signal received by the output transistor; the output end of the output transistor determines the source, drain, substrate, and deep n-well potentials of each device in the read / store arithmetic switch module 103 and the erase / program switch module 104.

[0066] In the present invention, the read / store arithmetic switch module 103 is composed of four NMOS transistors and an inverter, and requires the source line potential as an input; the first NMOS transistor 1031 is fabricated in a p-well in a deep n-well, its gate terminal is connected to the fourth potential output by the switch potential transfer module 102, the source terminal is connected to the drain terminals of the second NMOS transistor 1032 and the third NMOS transistor 1033, the drain terminal of the first NMOS transistor 1031 is connected to the drain terminal of the fourth NMOS transistor 1034 and connected to the bit line BL output, the substrate of the first NMOS transistor 1031 is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply;

[0067] The gate terminal of the second NMOS transistor 1032 is connected to the column select signal, the source terminal and the substrate are grounded, and the drain terminal is connected to the source terminal of the first NMOS transistor 1031 and the drain terminal of the third NMOS transistor 1033;

[0068] The gate terminal of the third NMOS transistor 1033 is connected to the output of the inverter 1035, the source terminal is connected to the source line potential, the drain terminal is connected to the source terminal of the first NMOS transistor 1031 and the drain terminal of the second NMOS transistor 1032, and the substrate is grounded;

[0069] The gate terminal of the fourth NMOS transistor 1034 is connected to the fifth potential, the source terminal and the substrate are grounded, and the drain terminal is connected to the drain terminal of the first NMOS transistor 1031 and connected to the bit line BL output;

[0070] The input of the inverter 1035 is connected to the column select signal, and the output is connected to the gate terminal of the third NMOS transistor 1033.

[0071] The erase / program switch module 104 is composed of a PMOS transistor, an NMOS transistor, and an inverter, where:

[0072] The PMOS transistor 1041 is fabricated in a deep n-well, its gate terminal is connected to the output of the inverter 1043, the source terminal is connected to the second potential, the drain terminal is connected to the drain terminal of the NMOS transistor 1042 and connected to the bit line BL output, the substrate is connected to the first potential, and the deep n-well is grounded;

[0073] The NMOS transistor 1042 is fabricated in a p-well in a deep n-well, its gate terminal is connected to the programming state control signal, the source terminal is connected to the sixth potential, the drain terminal is connected to the drain terminal of the PMOS transistor 1041 and connected to the bit line BL output, the substrate is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply;

[0074] The input of the inverter 1043 is connected to the programming state control signal, and the output is connected to the gate terminal of the NMOS transistor 1042.

[0075] In some embodiments, the first potential output module 110 uses a first level conversion module 2000 and a first level conversion module 2001, as Figure 13 shown, where:

[0076] The input potential of the first level conversion module is connected to the erasing working state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential (output potential 1) and the second output potential (output potential 2) are connected to the gate of the output transistor;

[0077] In some embodiments, the second potential output module 120 uses a first level conversion unit 2100 and two second level conversion modules 2101 and 2102, as Figure 14 shown, where:

[0078] The input potential of the first level conversion module is connected to the erasing working state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, the first output potential (output potential 1) is connected to the gate of the output transistor and is floating, and the second output potential (output potential 2) is connected to the gate of the output transistor;

[0079] The input potential of the first second level conversion module is connected to the programming working state signal, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential (output potential 1) is connected to the gate of the output transistor, and the second output potential (output potential 2) is floating;

[0080] The input potential of the second second level conversion module is connected to the NOR of the erasing and programming working state signals, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential (output potential 1) is connected to the gate of the output transistor, and the second output potential (output potential 2) is floating;

[0081] In some embodiments, the third potential output module 130 uses a third level conversion module 2200, as Figure 15 shown, where:

[0082] The input potential of the third level conversion module is connected to the programming working state signal, the VP terminal is connected to the second power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential (output potential 1) and the second output potential (output potential 2) are connected to the gate of the output transistor;

[0083] In some embodiments, the fourth potential output module 140 uses two third level conversion modules 2300 and 2301, as Figure 15 shown, where:

[0084] The input potential of the first third level conversion module is connected to the read / store operation status signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module 120, the VDD terminal is connected to the third power supply, and the VSS terminal is grounded. The first output potential (output potential 1) is connected to the gate terminal of the first NMOS transistor 1031 in the read / store switch module 103, and the second output potential (output potential 2) is left floating.

[0085] The input potential of the second third level conversion module is connected to the default working state signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module 120, the VDD terminal is connected to the third power supply, and the VSS terminal is grounded. The first output potential (output potential 1) is connected to the gate terminal of the fourth NMOS transistor 1034 in the read / store switch module 103, and the second output potential (output potential 2) is left floating.

[0086] In some embodiments, the fifth potential output module 150 uses a fourth level conversion module 2400, such as Figure 16 As shown, where:

[0087] The input potential of the third level conversion module is connected to the bit selection signal, the VP terminal is connected to the third power supply, the VN1 terminal is connected to the output terminal of the second potential output module 120, the VN2 terminal is connected to the output terminal of the third potential output module 130, VDD is connected to the third power supply, VSS is grounded, and the output potential is connected to the gate terminal of the first NMOS tube 1031 in the program / erase switch module 103.

[0088] When the circuit switches between different working states, it needs to be briefly switched to the default state before switching to the next working state.

[0089] In this embodiment, the input working state control timing is as follows Figure 4 As shown, the circuit defaults to the default state. After a certain period of time, the column select signal is pulled high. After a certain period of time, it enters the erase state, then the programming state, then the read / store state, and finally returns to the default state. The circuit needs to enter the default state briefly when switching between different states.

[0090] When the circuit is in the default state, the input erase state, programming state and read / store state signals are all low level.

[0091] In the switch potential transfer module 102:

[0092] In the first potential output module 110: The potential of node a1 converted by the first type of level conversion module 2000 (i.e., the output potential 1 of the first type of level conversion module 2000) is ground, the potential of node a2 (i.e., the output potential 2 of the first level conversion module 2000) is the potential of the first power supply, and the output transistors 1101 and 1102 are turned off; the potential of node a3 converted by the first type of level conversion module 2001 (i.e., the output potential 2 of the first type of level conversion module 2001) is the ground potential, the potential of node a4 (i.e., the output potential 2 of the first type of level conversion module 2001) is the potential of the first power supply, the output transistors 1103 and 1104 are turned on, and the finally output first potential is the potential of the third power supply;

[0093] In the second potential output module 120: The potential of node b1 converted by the first type of level conversion module 2100 (i.e., the output potential 2 of the first type of level conversion module 2100) is the potential of the first power supply; the potential of node b2 converted by the second type of level conversion module 2101 (i.e., the output potential 1 of the second type of level conversion module 2101) is the ground potential; the potential of node b3 converted by the second type of level conversion module 2102 (i.e., the output potential 1 of the second type of level conversion module 2102) is the ground potential, the output transistors 1201 and 1202 are turned off, 1203 is turned on, and the finally output second potential is the ground potential;

[0094] In the third potential output module 130: The potential of node c1 converted by the third type of level conversion module 2200 (i.e., the output potential 1 of the third type of level conversion module 2200) is the potential of the fifth power supply, the potential of node c2 (i.e., the output potential 2 of the third type of level conversion module 2200) is the second power supply, the output transistors 1301 and 1302 are turned off, the output transistors 1303 and 1304 are turned on, and the finally output third potential is the ground potential;

[0095] In the fourth potential output module 140: The potential of node d1 converted by the third type of level conversion module 2300 (i.e., the output potential 1 of the third type of level conversion module 2300) is the ground potential output by the third potential output module at this time; the potential of node d2 converted by the third type of level conversion module 2301 (i.e., the output potential 2 of the third type of level conversion module 2301) is the potential of the second power supply at this time, the finally output fourth potential is the ground potential, and the fifth potential is the potential of the second power supply;

[0096] In the fifth potential output module 150: The input column select signal is low, the potential of node d1 converted by the fourth type of level conversion module 2400 is the ground potential output by the second potential output module 120 at this time, and the finally output sixth potential is the ground potential;

[0097] In the read / write arithmetic switch module 103: The first NMOS transistor 1031 and the fourth NMOS transistor 1034 are turned off, which has no effect on the bit line potential.

[0098] In the programming / erasing switch module 104: The PMOS transistor 1041 is turned on and the NMOS transistor 1042 is turned off, which has no impact on the bit line potential.

[0099] In summary, the bit line potential is at ground in the default state.

[0100] When the circuit is in the erasing state, the input erasing state is at a high level, and the programming state and read / write computing state signals are both at low levels. At this time,

[0101] In the switch potential transfer module 102:

[0102] In the first potential output module 110: The potential of the a1 node (i.e., the output potential 1 of the first level conversion module 2000) converted by the first level conversion module 2000 is the potential of the first power supply, the potential of the a2 node (i.e., the output potential 2 of the first level conversion module 2000) is the potential of ground, the output transistors 1101 and 1102 are turned on, the potential of the a3 node (i.e., the output potential 2 of the first level conversion module 2001) converted by the first level conversion module 2001 is the potential of the first power supply, the potential of the a4 node (i.e., the output potential 2 of the first level conversion module 2001) is the potential of ground, the output transistors 1103 and 1104 are turned on, and the finally output first potential is the potential of the first power supply;

[0103] In the second potential output module 120: The potential of the b1 node (i.e., the output potential 2 of the first level conversion module 2100) converted by the first level conversion module 2100 is the potential of ground, the potential of the b2 node (i.e., the output potential 1 of the second level conversion module 2101) converted by the second level conversion module 2101 is the potential of the fourth power supply, the potential of the b3 node (i.e., the output potential 1 of the second level conversion module 2102) converted by the second level conversion module 2102 is the potential of the fourth power supply, the output transistor 1201 is turned on, and 1202 and 1203 are turned off. The finally output second potential is the potential of the first power supply;

[0104] In the third potential output module 130: The potential of the c1 node (i.e., the output potential 1 of the third level conversion module 2200) converted by the third level conversion module 2200 is the potential of the fifth power supply, the potential of the c2 node (i.e., the output potential 2 of the third level conversion module 2200) is the second power supply, the output transistors 1301 and 1302 are turned off, the output transistors 1303 and 1304 are turned on, and the finally output third potential is the ground potential;

[0105] In the fourth potential output module 140: The potential of the d1 node converted by the third level conversion module 2300 (i.e., the output potential 1 of the third level conversion module 2300) is the ground potential output by the third potential output module at this time. The potential of the d1 node converted by the third level conversion module 2301 (i.e., the output potential 1 of the third level conversion module 2301) is the potential of the third power supply output by the third potential output module 130 at this time. The finally output fourth potential is the ground potential, and the fifth potential is the potential of the third power supply;

[0106] In the fifth potential output module 150: The input column select signal is high. The potential of the d1 node converted by the fourth level conversion module 2400 is the ground potential output by the third potential output module 130 at this time. The finally output sixth potential is the ground potential;

[0107] In the read / store-compute switch module 103: The first NMOS transistor 1031 and the fourth NMOS transistor 1034 are turned off, having no impact on the bit line potential.

[0108] In the programming / erasing switch module 104: The PMOS transistor 1041 is turned on, and the NMOS transistor 1042 is turned off. The bit line potential is the first power supply.

[0109] In summary, the bit line potential in the erased state is the potential of the first power supply.

[0110] When the circuit is in the programming state, the input programming state is high level, and both the erased state and the read / store-compute state signals are low level. At this time,

[0111] In the switch potential transfer module 102:

[0112] In the first potential output module 110: The potential of the a1 node converted by the first level conversion module 2000 (i.e., the output potential 1 of the first level conversion module 2000) is the ground potential. The potential of the a2 node (i.e., the output potential 2 of the first level conversion module 2000) is the potential of the first power supply. The output transistors 1101 and 1102 are turned off. The potential of the a3 node converted by the first level conversion module 2001 (i.e., the output potential 2 of the first level conversion module 2001) is the ground potential. The potential of the a4 node (i.e., the output potential 2 of the first level conversion module 2001) is the potential of the first power supply. The output transistors 1103 and 1104 are turned on. The finally output first potential is the potential of the third power supply;

[0113] In the second potential output module 120, the potential of the node b1 converted by the first level conversion module 2100 (i.e., the output potential 2 of the first level conversion module 2100) is the potential of the third power supply, the potential of the node b2 converted by the second level conversion module 2101 (i.e., the output potential 1 of the second level conversion module 2101) is the potential of the fourth power supply, and the potential of the node b3 converted by the second level conversion module 2102 (i.e., the output potential 1 of the second level conversion module 2102) is the potential of the fourth power supply. The output transistors 1201 and 1203 are turned off, and 1202 is turned on. Finally, the second potential outputted is the potential of the fourth power supply.

[0114] In the third potential output module 130, the potential of the node C1 converted by the third level conversion module 2200 (i.e., output potential 1 of the third level conversion module 2200) is the potential of the third power supply, the potential of the node C2 (i.e., output potential 2 of the third level conversion module 2200) is the fifth power supply, the output transistors 1301 and 1302 are turned on, and the output transistors 1303 and 1304 are turned off. The third potential finally outputted is the potential of the fifth power supply.

[0115] In the fourth potential output module 140, the potential of the node d1 converted by the third level conversion module 2300 (i.e., the output potential 1 of the third level conversion module 2300) is the potential of the fifth power supply output by the third potential output module 130 at this time. The potential of the node d1 converted by the third level conversion module 2301 (i.e., the output potential 1 of the third level conversion module 2301) is the potential of the fifth power supply output by the third potential output module 130 at this time. Finally, the fourth potential outputted is the potential of the fifth power supply, and the fifth potential is the potential of the fifth power supply.

[0116] In the fifth potential output module 150 , when the column selection signal is high, the potential of the node d1 converted by the fourth level conversion module 2400 is the potential of the fifth power supply output by the third potential output module 130 . The sixth potential outputted is the potential of the fifth power supply.

[0117] In the read / store / calculate switch module 103 , the first NMOS transistor 1031 and the fourth NMOS transistor 1034 are turned off, which does not affect the bit line potential.

[0118] In the program / erase switch module 104: the PMOS transistor 1041 is turned off, the NMOS transistor 1042 is turned on, and the bit line potential is the potential of the fifth power supply;

[0119] In summary, the potential of the bit line in the programming state is the potential of the fifth power supply.

[0120] When the circuit is in the read / store state, the input read / store state is high, and the erase state and programming state signals are both low.

[0121] In the switch potential transfer module 102:

[0122] In the first potential output module 110, the potential of the node a1 converted by the first level conversion module 2000 (i.e., the output potential 1 of the first level conversion module 2000) is the ground potential, the potential of the node a2 (i.e., the output potential 2 of the first level conversion module 2000) is the potential of the first power supply, the output transistors 1101 and 1102 are turned off, the potential of the node a3 converted by the first level conversion module 2001 (i.e., the output potential 2 of the first level conversion module 2001) is the ground potential, the potential of the node a4 (i.e., the output potential 2 of the first level conversion module 2001) is the potential of the first power supply, the output transistors 1103 and 1104 are turned on, and the first potential outputted is the potential of the third power supply.

[0123] In the second potential output module 120, the potential of the node b1 converted by the first level conversion module 2100 (i.e., output potential 2 of the first level conversion module 2100) is the potential of the first power supply, the potential of the node b2 converted by the second level conversion module 2101 (i.e., output potential 1 of the second level conversion module 2101) is the ground potential, and the potential of the node b3 converted by the second level conversion module 2102 (i.e., output potential 1 of the second level conversion module 2102) is the ground potential. The output transistors 1201 and 1202 are turned off, and 1203 is turned on. Finally, the second potential output is the ground potential.

[0124] In the third potential output module 130, the potential of the node C1 converted by the third level conversion module 2200 (i.e., output potential 1 of the third level conversion module 2200) is the potential of the fifth power supply, the potential of the node C2 (i.e., output potential 2 of the third level conversion module 2200) is the third power supply, the output transistors 1301 and 1302 are turned off, and the output transistors 1303 and 1304 are turned on. The final output third potential is the ground potential.

[0125] In the fourth potential output module 140, the potential of the node d1 converted by the third level conversion module 2300 (i.e., the output potential 1 of the third level conversion module 2300) is the potential of the second power supply. The potential of the node d1 converted by the third level conversion module 2301 (i.e., the output potential 1 of the third level conversion module 2301) is the potential of the fifth power supply output by the third potential output module 130. Finally, the fourth potential outputted is the potential of the second power supply, and the fifth potential is the potential of the fifth power supply.

[0126] In the fifth potential output module 150 , the input column selection signal is high, and the potential of the node d1 converted by the fourth level conversion module 2400 is the ground potential output by the third potential output module 130 at this time. The sixth potential outputted is the ground potential.

[0127] In the read / store-compute switch module 103: the first NMOS transistor 1031 and the second NMOS transistor 1032 are turned on, the third NMOS transistor 1033 and the fourth NMOS transistor 1034 are turned off, and the bit line potential is at the ground potential.

[0128] In the programming / erasing switch module 104: the PMOS transistor 1041 is turned off and the NMOS transistor 1042 is turned off, which has no effect on the bit line potential.

[0129] In summary, the bit line potential is at the ground potential when reading / storing the computing state.

[0130] The circuit output result of the entire embodiment is as Figure 17 shown.

[0131] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A bitline driving circuit for a FLASH memory and computing array, characterized in that the output of the bitline driving circuit is used to provide the potentials of the bitlines of multiple memory and computing array units in the FLASH memory and computing array; the bitline driving circuit includes a switching potential transfer module, a read / write and computing switch module, and an erase / program switch module; the input end of the switching potential transfer module receives a control signal and a power supply signal, and outputs six potentials, namely the first potential to the sixth potential, which are connected to the source, drain, substrate, and deep n-well of each device in the read / write and computing switch module and the erase / program switch module; the source, drain, substrate, and deep n-well of the read / write and computing switch module are connected to the output end of the switching potential transfer module, the gates of the internal devices are connected to the control signal, the fourth potential, and the fifth potential, and the output end is connected to the bitlines of the FLASH memory and computing array; the source, drain, and substrate of the erase / program switch module are connected to the output end of the switching potential transfer module, the gate is connected to the control signal, and the output end is connected to the bitlines of the FLASH memory and computing array; the read / write and computing switch module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a first inverter, and requires the source line potential as an input; among them, the first NMOS transistor is fabricated in a p-well in a deep n-well, its gate terminal is connected to the fourth potential output by the switching potential transfer module, the source terminal is connected to the drain terminal of the second NMOS transistor and the drain terminal of the third NMOS transistor, the drain terminal is connected to the drain terminal of the fourth NMOS transistor and is connected to the bitline output, the substrate is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply; the gate terminal of the second NMOS transistor is connected to the column selection signal, the source terminal and the substrate are grounded, and the drain terminal is connected to the source terminal of the first NMOS transistor and the drain terminal of the third NMOS transistor; the gate terminal of the third NMOS transistor is connected to the output of the first inverter, the source terminal is connected to the source line potential, the drain terminal is connected to the source terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor, and the substrate is grounded; the gate terminal of the fourth NMOS transistor is connected to the fifth potential, the source terminal and the substrate are grounded, and the drain terminal is connected to the drain terminal of the first NMOS transistor and is connected to the bitline output; the input of the first inverter is connected to the column selection signal, and the output is connected to the gate terminal of the third NMOS transistor.

2. The bit line driving circuit for a FLASH memory and computing array according to claim 1, wherein the control signals input by the switching potential transfer module include four working state signals of default, erase, program, read / write and computing, and a bitline selection control signal, and the power supply signals input by the switching potential transfer module include five power supply signals and a ground signal; the switching potential transfer module includes five potential output modules: a first potential output module, a second potential output module, a third potential output module, a fourth potential output module, and a fifth potential output module. Each potential output module consists of a level conversion module and an output transistor, where: the input end of the level conversion module receives a control signal and a power supply signal, and the converted level output is used as the control signal received by the output transistor; the output end of the output transistor determines the potentials of the source, drain, substrate, and deep n-well of each device in the read / write and computing switch module and the erase / program switch module.

3. The bit line driving circuit for a FLASH memory and computing array according to claim 1, wherein the erase / program switch module includes a fifth NMOS transistor, a first PMOS transistor, and a second inverter; among them, The fifth NMOS transistor is fabricated in a p-well within a deep n-well. Its gate terminal is connected to the programming state control signal, its source terminal is connected to the sixth potential, its drain terminal is connected to the drain terminal of the first PMOS transistor and is connected to the bit line output, its substrate is connected to the third potential, the deep n-well is grounded, and the p-well is connected to the third power supply; The first PMOS transistor is fabricated in a deep n-well. Its gate terminal is connected to the output of the second inverter, its source terminal is connected to the second potential, its drain terminal is connected to the drain terminal of the fifth NMOS transistor and is connected to the bit line output, its substrate is connected to the first potential, and the deep n-well is grounded; The input of the second inverter is connected to the programming state control signal, and the output is connected to the gate terminal of the fifth NMOS transistor.

4. The bit line driving circuit for the FLASH memory and computing array according to claim 2, wherein Two first-level level conversion modules are included in the first potential output module; among them, The input potential of the first-level level conversion module is connected to the erase operation state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential and the second output potential are connected to the gate of the output transistor.

5. The bit line driving circuit for a FLASH memory and computing array according to claim 2, wherein One first-level level conversion module and two second-level level conversion modules are included in the second potential output module; among them, The input potential of the first-level level conversion module is connected to the erase operation state signal, the VP terminal is connected to the first power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, the first output potential is left floating and connected to the gate of the output transistor, and the second output potential is connected to the gate of the output transistor; The input potential of the first second-level level conversion module is connected to the programming operation state signal, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential is connected to the gate of the output transistor, and the second output potential is left floating; The input potential of the second second-level level conversion module is connected to the NOR of the erase and programming operation state signals, the VP terminal and the VDD terminal are connected to the third power supply, the VN terminal is connected to the fourth power supply, the VSS terminal is grounded, the first output potential is connected to the gate of the output transistor, and the second output potential is left floating.

6. The bit line driving circuit for the FLASH memory and computing array according to claim 2, characterized in that, One third-level level conversion module is included in the third potential output module; among them, The input potential of the third-level level conversion module is connected to the programming operation state signal, the VP terminal is connected to the second power supply, the VDD terminal is connected to the third power supply, the VSS terminal is grounded, and the first output potential and the second output potential are connected to the gate of the output transistor.

7. The bit line driving circuit for the FLASH memory and computing array according to claim 2, characterized in that, Two third-level level conversion modules are included in the fourth potential output module; among them, The input potential of the first third-level level conversion module is connected to the read / write operation state signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module, VDD is connected to the third power supply, VSS is grounded, the first output potential is connected to the gate of the first NMOS transistor in the read / write switch module, and the second output potential is left floating; The input potential of the second third-level level conversion module is connected to the default state operation state signal, the VP terminal is connected to the second power supply, the VN terminal is connected to the output terminal of the second potential output module, VDD is connected to the third power supply, VSS is grounded, the first output potential is connected to the gate of the fourth NMOS transistor in the read / write switch module, and the second output potential is left floating.

8. The bit line driving circuit for the FLASH memory and computing array according to claim 2, wherein A fourth-level level conversion module is included in the fifth potential output module; among them, The input potential of the fourth level conversion module is connected to the bit selection signal, the VP terminal is connected to the third power supply, the VN1 terminal is connected to the output terminal of the second potential output module, the VN2 terminal is connected to the output terminal of the third potential output module, VDD is connected to the third power supply, VSS is grounded, and the output potential is connected to the gate terminal of the first NMOS transistor in the programming / erasing switch module.

9. The bit line driving circuit for a FLASH memory and computing array according to any one of claims 1-8, characterized in that, The bit line driving circuit is default in the default state. When switching between different working states, it needs to be briefly switched to the default state first and then switched to the next working state.

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