Encoding and decoding method, encoder and decoder

Abstract

The invention relates to the field of hardware simulation, and provides an encoding and decoding method, an encoder, a decoder, a programmable logic device and a hardware simulation system.The method is applied to a first PLD in the hardware simulation system, the hardware simulation system comprises a plurality of PLDs, and the method comprises the steps that an original data sequence is obtained, and the original data sequence comprises 6N pieces of original data; 6 pieces of original data in the 6N pieces of original data are coded through the coding matrix to obtain 4 pieces of coded data, the 6 pieces of original data are the 6i-5th to 6i-th pieces of original data in the original data sequence, and i is a positive integer smaller than or equal to N; a first data sequence is sent to a second PLD, the first data sequence comprises 10N pieces of first data, and the 10i-ninth to 10i pieces of first data in the first data sequence comprise 6 pieces of original data and 4 pieces of coded data. According to the method, error correction coding and decoding with low error rate and low time delay can be realized in a hardware simulation system.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of hardware emulation, and more particularly, to a coding and decoding method, an encoder, a decoder, a programmable logic device, and a hardware emulation system. Background Art

[0002] With the development of large-scale integrated circuit (IC) technology, the logic scale of chips and the complexity of circuits are getting higher and higher. To ensure the chip quality and time to market, accurate and fast hardware emulation of chips is required. The hardware emulation technology maps a design under test (DUT) onto a programmable logic device (PLD) included in a hardware emulator (EMU) to perform hardware emulation and system-level debugging on the DUT.

[0003] To meet the hardware emulation requirements of DUTs with large logic scales, an EMU may include hundreds or even thousands of PLDs, and the PLDs communicate with each other through high-speed serial links. To ensure the hardware emulation performance, the high-speed serial link of the EMU needs to ensure a low bit error rate (i.e., bit error ratio (BER)). By adding error correction coding to the transmitted data, the system can be made to have the ability to correct bit errors, thereby reducing the BER.

[0004] However, adding error correction coding will increase the communication overhead, resulting in an increase in the cross-chip delay of the high-speed serial link in the EMU, which in turn affects the hardware emulation performance. Existing error correction coding and decoding schemes all have a high error correction delay and cannot meet the hardware emulation performance requirements of current ultra-large-scale hardware emulation systems. Therefore, how to reduce the delay of error correction coding and decoding while ensuring a low bit error rate in a hardware emulation system has become a technical problem that urgently needs to be solved. Summary of the Invention

[0005] Embodiments of the present application provide a coding and decoding method, an encoder, a decoder, a programmable logic device, and a hardware emulation system, which can implement error correction coding and decoding with a low bit error rate and a low delay in a hardware emulation system.

[0006] In a first aspect, a coding method is provided. The method is applied to an encoder in a first programmable logic device (PLD) in a hardware simulation system. The hardware simulation system includes multiple PLDs. The method includes: obtaining an original data sequence, where the original data sequence includes 6N original data, and N is a positive integer; encoding 6 of the 6N original data using a coding matrix to obtain 4 coded data, where the 6 original data are the 6i - 5th to 6i - th original data in the original data sequence, and i is a positive integer less than or equal to N; sending a first data sequence to a second PLD, where the first data sequence includes 10N first data, and the 10i - 9th to 10i - th first data in the first data sequence include the 6 original data and the 4 coded data.

[0007] According to the technical solution provided by the present application, by encoding the original data in groups of 6 on the encoder side, the amount of coded data per group is reduced, so as to reduce the time delay required for the decoder side to wait for the transmission of coded data before each decoding starts, thereby reducing the cross - chip time delay of encoding and decoding in the hardware simulation system. In addition, by configuring 4 coded data for error correction for each group of 6 data, the error correction effect can be ensured without reduction, so as to ensure a low bit error rate of the serial link in the hardware simulation system while providing low time delay, and further enable the hardware simulation system to support larger - scale chip verification.

[0008] Optionally, the first PLD may include a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logical device (CPLD), a field - programmable gate array (FPGA), or any combination thereof.

[0009] It should be understood that the programmable logic units such as the above-mentioned PLA, GAL, and FPGA may only be a part of the first PLD, and the encoding and decoding methods provided in the embodiments of the present application are not limited to being executed by the programmable logic units in the PLD. As an example, the function of the encoder in the first PLD may be implemented by the above-mentioned programmable logic units; or the encoder may also include an independent processor and memory for implementing the encoding method provided in the embodiments of the present application. Among them, the above-mentioned processor may be an application-specific integrated circuit (ASIC), or any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), etc., and the present application does not make specific limitations on this.

[0010] Optionally, the length of the original data is 4 bits (bit), and the length of the encoded data is 4 bit.

[0011] Combined with the first aspect, in some implementation manners of the first aspect, 6 pieces of original data and 4 pieces of encoded data are used to be decoded by the decoding matrix in the second PLD to obtain 4 pieces of first decoded data, and the 4 pieces of first decoded data are 0.

[0012] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0013]

[0014] Among them, G is the encoding matrix, p0, p1, p2, and p3 are 4 pieces of encoded data, m0, m1, m2, m3, m4, and m5 are 6 pieces of original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), where k is the bit length of the original data and k is a positive integer.

[0015] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0016]

[0017] Among them, H is the decoding matrix, p0, p1, p2, and p3 are 4 pieces of encoded data, m0, m1, m2, m3, m4, and m5 are 6 pieces of original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k) In the algorithm rule, k is the bit length of the original data, and k is a positive integer.

[0018] Optionally, the encoding matrix and the decoding matrix satisfy:

[0019]

[0020]

[0021] Wherein, G is the encoding matrix and H is the decoding matrix.

[0022] In a second aspect, a decoding method is provided. The method is applied to a decoder in a second PLD in a hardware simulation system. The hardware simulation system includes a plurality of PLDs. The method includes: receiving a second data sequence, where the second data sequence includes 10N second data, and N is a positive integer; using the decoding matrix to decode 10 second data among the 10N second data to obtain 4 second decoded data, where the 10 second data are the 10i - 9th to 10i - th second data in the second data sequence, and i is a positive integer less than or equal to N; when the 4 second decoded data are 0, determining 6 original data and 4 encoded data included in the 10 second data, where the 6 original data are the 6i - 5th to 6i - th original data in the original data sequence, the original data sequence includes 6N original data, and the 4 encoded data are obtained by encoding the 6 original data with the encoding matrix in the first PLD.

[0023] Optionally, the second PLD may include a PLA, a PAL, a GAL, a CPLD, an FPGA, or any combination thereof.

[0024] It should be understood that the above programmable logic units such as PLA, GAL, and FPGA may only be a part of the second PLD. The encoding and decoding methods provided in the embodiments of the present application are not limited to being executed by the programmable logic units in the PLD. As an example, the function of the decoder in the second PLD may be implemented by the above programmable logic units; or the decoder may also include an independent processor and a memory for implementing the decoding method provided in the embodiments of the present application. Wherein, the above processor may be an application - specific integrated circuit (ASIC), or any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), etc. The present application does not make specific limitations in this regard.

[0025] Optionally, the length of the second data is 4 bits, and the length of the second decoded data is 4 bits.

[0026] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0027]

[0028] where H is the decoding matrix, s0, s1, s2, and s3 are 4 second decoded data, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are 10 second data, and the operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0029] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0030]

[0031] where G is the encoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0032] Optionally, the encoding matrix and the decoding matrix satisfy:

[0033]

[0034]

[0035] where G is the encoding matrix and H is the decoding matrix.

[0036] Combined with the second aspect, in some implementation manners of the second aspect, the method further includes: when the 4 second decoded data are not all 0, determining the number of error data in the decoding of the 10 second data according to the 4 second decoded data, where the error data is the second data different from the 6 original data and the 4 encoded data.

[0037] According to the above technical solution, when the decoder side determines that there is error data in the received data relative to the data sent by the encoder side through decoding, it can determine the number of error data according to the decoded data, so as to correct the error data within a certain range, thereby reducing the bit error rate of the serial link in the hardware simulation system.

[0038] In combination with the second aspect, in some implementations of the second aspect, determining the number of incorrect data among the 10 second data based on 4 second decoded data includes: when the 4 second decoded data meet the following conditions, determining that the number of incorrect data is 1:

[0039]

[0040] where s0, s1, s2, and s3 are the 4 second decoded data, and the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ); when the 4 second decoded data are not all 0 and do not meet the above conditions, determining that the number of incorrect data is a positive integer greater than or equal to 2 and less than or equal to 10.

[0041] According to the above technical solution, when there are errors in the received data relative to the transmitted data, the decoder can determine whether the incorrect data is one or more based on the decoded data, so as to select the corresponding error correction method according to the number of incorrect data and locate the incorrect data, thereby improving the error correction efficiency.

[0042] In combination with the second aspect, in some implementations of the second aspect, the method further includes: correcting the incorrect data according to the number of incorrect data and the 4 second decoded data to obtain 6 original data and 4 encoded data.

[0043] According to the above technical solution, when the incorrect data can be corrected, the decoder can restore the correct data transmitted by the encoder side based on the incorrect data and the decoded data to obtain the original data, so as to perform hardware simulation in the PLD on the encoder side.

[0044] In a third aspect, an encoder is provided. The encoder is disposed in the first PLD of a hardware simulation system. The hardware simulation system includes multiple PLDs. The encoder includes: an acquisition module for acquiring an original data sequence, where the original data sequence includes 6N original data, and N is a positive integer; an encoding module for encoding 6 original data among the 6N original data using an encoding matrix to obtain 4 encoded data, where the 6 original data are the 6i - 5th to 6i - th original data in the original data sequence, and i is a positive integer less than or equal to N; a sending module for sending a first data sequence to a second PLD, where the first data sequence includes 10N first data, and the 10i - 9th to 10i - th first data in the first data sequence include 6 original data and 4 encoded data.

[0045] In combination with the third aspect, in some implementations of the third aspect, the 6 original data and the 4 encoded data are used to be decoded by a decoding matrix in the second PLD to obtain 4 first decoded data, and the 4 first decoded data are 0.

[0046] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0047]

[0048] where G is the encoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), k is the bit length of the original data, and k is a positive integer.

[0049] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0050]

[0051] where H is the decoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), k is the bit length of the original data, and k is a positive integer.

[0052] Optionally, the encoding matrix and the decoding matrix satisfy:

[0053]

[0054]

[0055] where G is the encoding matrix and H is the decoding matrix.

[0056] In a fourth aspect, a decoder is provided. The decoder is disposed in the second PLD in the hardware simulation system. The hardware simulation system includes multiple PLDs. The decoder includes: a receiving module, configured to receive a second data sequence, where the second data sequence includes 10N second data, and N is a positive integer; a decoding module, configured to decode 10 second data among the 10N second data by using a decoding matrix to obtain 4 second decoded data, where the 10 second data are the 10i - 9th to 10ith second data in the second data sequence, and i is a positive integer less than or equal to N; an error correction module, configured to determine 6 original data and 4 encoded data included in the 10 second data when the 4 second decoded data are 0, where the 6 original data are the 6i - 5th to 6ith original data in the original data sequence, the original data sequence includes 6N original data, and the 4 encoded data are obtained by encoding the 6 original data by the encoding matrix in the first PLD.

[0057] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0058]

[0059] where H is the decoding matrix, s0, s1, s2, and s3 are 4 second decoded data, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are 10 second data, and the operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

[0060] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0061]

[0062] where G is the encoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

[0063] Optionally, the encoding matrix and the decoding matrix satisfy:

[0064]

[0065]

[0066] where G is the encoding matrix and H is the decoding matrix.

[0067] Combined with the fourth aspect, in some implementation manners of the fourth aspect, the error correction module is further configured to: when the 4 second decoded data are not all 0, determine the number of error data in the decoding of the 10 second data according to the 4 second decoded data, where the error data is the second data different from the 6 original data and the 4 encoded data.

[0068] Combined with the fourth aspect, in some implementation manners of the fourth aspect, the error correction module is configured to: when the 4 second decoded data meet the following conditions, determine that the number of error data is 1:

[0069]

[0070] Among them, s0, s1, s2, and s3 are four second decoded data, and the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ). In the case where the four second decoded data are not all 0 and do not satisfy the above conditions, it is determined that the number of error data is a positive integer greater than or equal to 2 and less than or equal to 10.

[0071] Combined with the fourth aspect, in some implementation manners of the fourth aspect, the error correction module is further configured to: correct the error data according to the number of error data and the four second decoded data to obtain six original data and four encoded data.

[0072] In a fifth aspect, a computing device is provided, including a processor and a memory. Among them, the memory is used to store instructions, and the processor is used to call and run the instructions from the memory, so that the programmable logic device executes the method in the first aspect or any possible implementation manner of the first aspect.

[0073] In a sixth aspect, a computing device is provided, including a processor and a memory. Among them, the memory is used to store instructions, and the processor is used to call and run the instructions from the memory, so that the programmable logic device executes the method in the second aspect or any possible implementation manner of the second aspect.

[0074] In a seventh aspect, a chip is provided, and the chip obtains and executes the instructions to implement the method in the first aspect or any possible implementation manner of the first aspect.

[0075] In an eighth aspect, a chip is provided, and the chip obtains and executes the instructions to implement the method in the second aspect or any possible implementation manner of the second aspect.

[0076] Optionally, as an implementation manner, the chip includes a processor and a data interface. The processor reads the instructions stored on the memory through the data interface and executes the method in the first aspect or any possible implementation manner of the first aspect and / or the method in the second aspect or any possible implementation manner of the second aspect.

[0077] Optionally, as an implementation manner, the chip may further include a memory. Instructions are stored in the memory, and the processor is used to execute the instructions stored on the memory. When the instructions are executed, the processor is used to execute the method in the first aspect or any possible implementation manner of the first aspect and / or the method in the second aspect or any possible implementation manner of the second aspect.

[0078] In a ninth aspect, there is provided a computer program product including instructions which, when run on a computing device, cause the computing device to execute the method in the above first aspect or any possible implementation of the first aspect.

[0079] In a tenth aspect, there is provided a computer program product including instructions which, when run on a computing device, cause the computing device to execute the method in the above second aspect or any possible implementation of the second aspect.

[0080] In an eleventh aspect, there is provided a computer-readable storage medium including computer program instructions which, when executed by a computing device, cause the computing device to execute the method in the above first aspect or any possible implementation of the first aspect.

[0081] In a twelfth aspect, there is provided a computer-readable storage medium including computer program instructions which, when executed by a computing device, cause the computing device to execute the method in the above second aspect or any possible implementation of the second aspect.

[0082] By way of example, these computer-readable storage media include, but are not limited to, one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), Flash memory, electrically EPROM (EEPROM), and hard drive.

[0083] Optionally, as an implementation, the above storage medium may specifically be a non-volatile storage medium.

[0084] In a thirteenth aspect, there is provided a hardware emulation system including at least one programmable logic device as in the fifth aspect and at least one programmable logic device as in the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 is a schematic diagram of a hardware emulation system.

[0086] Figure 2 is a schematic diagram of the interconnection of PLDs in a hardware emulation system.

[0087] Figure 3 is a schematic diagram of the data transfer process between PLDs in a hardware emulation system.

[0088] Figure 4 is a schematic diagram of the system architecture to which an embodiment of the present application is applied.

[0089] Figure 5 It is a schematic flowchart of an encoding method provided by an embodiment of the present application.

[0090] Figure 6 It is a schematic diagram of an encoder encoding process provided by an embodiment of the present application.

[0091] Figure 7 It is a schematic flowchart of a decoding method provided by an embodiment of the present application.

[0092] Figure 8 It is a schematic structural block diagram of an encoder provided by an embodiment of the present application.

[0093] Figure 9 It is a schematic structural block diagram of a decoder provided by an embodiment of the present application.

[0094] Figure 10 It is a schematic structural block diagram of a computing device provided by an embodiment of the present application. Detailed implementation manners

[0095] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0096] The present application will present various aspects, embodiments or features around a system including multiple devices, components, modules, etc. It should be understood and clear that each system may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. In addition, combinations of these solutions can also be used.

[0097] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0098] In the embodiments of the present application, "corresponding" and "corresponding" can sometimes be used interchangeably. It should be noted that when not emphasizing their differences, the meanings they express are the same.

[0099] The system architecture and business scenarios described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0100] As used in this specification, references to "one embodiment" or "some embodiments" etc. mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0101] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can mean: including the case where A exists alone, where A and B exist simultaneously, and where B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are an "or" relationship. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, at least one (item) of a, b, or c can mean: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0102] With the development of large-scale integrated circuit technology, the logic scale of chips and the complexity of circuits are getting higher and higher. The number of devices integrated in large-scale chips can be as high as tens of billions of gates. To ensure chip quality and time to market, accurate and rapid hardware simulation of chips is required. Hardware simulation technology maps the DUT to the PLD included in the hardware simulation system (such as EMU) to perform hardware simulation and system-level debugging on the DUT.

[0103] Figure 1 It is a schematic diagram of a hardware simulation system. As Figure 1As shown in the figure, a hardware simulation system may include a hardware simulation parallel machine 110, a host system 120, a driver board 130, and a management unit 140. The hardware simulation parallel machine 110 is used to provide resources required for hardware simulation, including but not limited to hardware resources, clock resources, interconnection resources, etc. Among them, the hardware resource is a PLD (which may also be referred to as a programmable logic chip in some solutions) that can map the DUT. The PLD may include a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or any combination thereof. Each hardware simulation parallel machine 110 may be composed of multiple interconnected cabinets, and each cabinet may include one or more PLDs, so as to provide sufficient hardware resources for the hardware simulation system. The host system 120 is used to communicate with the hardware simulation parallel machine 110, load instructions into the PLD during the hardware simulation process, and obtain simulation data. The driver board 130 may be used to enhance the driving ability of signal transmission between the hardware simulation parallel machines 110. The management unit 140 may be used to manage the hardware simulation resources provided by the hardware simulation parallel machine 110.

[0104] To meet the hardware simulation requirements of DUTs with large logic scales, the hardware simulation system may include hundreds or even thousands of PLDs. Figure 2 The figure shows a schematic diagram of the interconnection of PLDs in a hardware simulation system. As Figure 2 shown, the PLDs communicate with each other through high-speed serial links. In order to cover as many simulation scenarios as possible, there may be serial links between each PLD and other PLDs. As the chip simulation scale increases, the number of PLDs in the hardware simulation system increases, and the growth rate of the number of serial links gradually increases.

[0105] When data is transmitted between PLDs through serial links, affected by the receiving channel interference, the data received by the receiving-end PLD may not be exactly the same as the data sent by the sending-end PLD. These inconsistent error data can be called bit errors, and the bit error situation can be reflected by BER (that is, the bit error rate). BER is the proportion of error data in the data sequence. Figure 3 The figure shows a schematic diagram of the data transmission process between PLDs in a hardware simulation system. As Figure 3 shown, the data sequence sent by the sending-end PLD includes n data, which can be expressed as (m0, m1, m2,..., m n), where the positive integer n is the length of the data sequence. After the transmitted data sequence passes through the channel, the data sequence received by the receiving-end PLD may become (r0, r1, r2, ……, r n ), where the data that is not equal at the corresponding positions in the received data sequence and the transmitted data sequence can be called error codes. For example, assume that m i = r i , i is a positive integer greater than or equal to 0 and less than n, and i≠2, i≠5, that is, r2 and r5 in the received data sequence are incorrect data relative to m2 and m5 in the transmitted data sequence. In the above example, the number of error codes is 2, and the bit error rate can be calculated by the following formula: BER = 2 / n. To ensure the hardware simulation performance, the high-speed serial link of the hardware simulation system needs to ensure a low BER. For example, for a hardware simulation system with a large number of high-speed serial links, its overall BER needs to be controlled below 10 -23 .

[0106] Improving the channel quality can reduce the BER of the high-speed serial link to a certain extent. This method is mainly achieved by reducing the channel insertion loss, and the cost will increase exponentially with the improvement of the channel material. In addition, restricted by the channel material, there are also bottlenecks in the control of BER by this method. For example, it is generally difficult to reduce the BER of a channel containing an optical link below 10 -13 by reducing the channel insertion loss.

[0107] Another way to reduce the BER of the serial link is to add error correction codes to the transmitted data to enable the system to have the ability to correct error codes. However, adding error correction coding will increase the communication overhead. Since the receiving end needs to receive a complete set of original data and the corresponding error correction codes before it can perform error correction, the increase in communication overhead will lead to an increase in the cross-chip delay between the data sending end and the data receiving end in the hardware simulation system, thereby affecting the hardware simulation performance.

[0108] Existing error correction encoding and decoding schemes all have a high error correction delay and cannot meet the hardware simulation performance requirements of current ultra-large-scale hardware simulation systems. Therefore, how to reduce the delay of error correction encoding and decoding on the premise of ensuring a low bit error rate in the hardware simulation system has become an urgent technical problem to be solved.

[0109] In view of this, the embodiments of the present application provide an encoding and decoding method that can achieve error correction encoding and decoding with a low bit error rate and low delay in a hardware simulation system.

[0110] Figure 4 is a schematic diagram of the system architecture applied in the embodiments of the present application. As Figure 4As shown, the system 400 may include a first PLD 410 and a second PLD 420. The first PLD 410 may include an encoder 411, and the second PLD 420 may include a decoder 421. The encoder 411 is used to encode the data in the first PLD 410 and send it to other PLDs (such as the second PLD 420) in the system 400. The decoder 421 is used to receive the data sent by other PLDs (such as the first PLD 410) in the system 400 and provide the decoded data to the second PLD 420 for simulation.

[0111] It should be understood that the system 400 may be a hardware simulation system, such as an EMU. The system 400 may also be a part of a hardware simulation system, such as Figure 1 a part of the hardware simulation system shown. Among them, the first PLD 410 and the second PLD 420 may be PLDs in different hardware simulation parallel machines of the hardware simulation system, or may be PLDs in different cabinets of the same hardware simulation parallel machine, or may be different PLDs in the same cabinet. The present application does not make specific limitations on this.

[0112] It should be understood that the first PLD 410 and the second PLD 420 in the system 400 are only examples and do not represent all of the system 400. For example, the system 400 may also include multiple other PLDs. As an example, the system 400 may also include a third PLD. Optionally, the third PLD may also include Figure 4 the encoder 411 and / or the decoder 421 shown therein.

[0113] Optionally, the above-mentioned first PLD 410 and second PLD 420 may also include programmable logic units such as PLA, PAL, GAL, CPLD, FPGA, or any combination thereof.

[0114] Optionally, the PLD in the system 400 may execute the encoding method provided by the embodiments of the present application or may execute the decoding method provided by the embodiments of the present application. For example, in some possible implementation manners, in addition to the encoder 411, the first PLD 410 may also include a decoder, and / or, in addition to the decoder 421, the second PLD 420 may also include an encoder. Again, for example, in some other possible implementation manners, the encoder 411 in the first PLD 410 may also be used to execute the decoding method provided by the embodiments of the present application, and / or, the decoder 421 in the second PLD 420 may also be used to execute the encoding method provided by the embodiments of the present application. In the above cases, the second PLD 420 may be used to encode the data and send it to the first PLD 410, and the first PLD 410 may be used to receive and decode the data sent by the second PLD 420.

[0115] Figure 5FIG. 0 shows a schematic flowchart of an encoding method provided by an embodiment of the present application. Optionally, this method can be executed by an encoder, and can also be executed by a decoder. The present application does not make specific limitations. For the convenience of description, in the following embodiments, the encoder is used as the execution subject for description. The encoder can be set in the first PLD of the hardware simulation system, and multiple PLDs are included in the hardware simulation system. For example, the hardware simulation system can be Figure 4 the system 400 shown in Figure 4 and the encoder can be

[0116] As shown in Figure 5 FIG. 9, the method includes the following steps.

[0117] S510: Obtain the original data sequence.

[0118] For example, in step S510, the encoder can obtain the original data to be sent in the first PLD. Multiple original data to be sent can be input into the encoder in the expected sending order (or generation order). The above-mentioned multiple original data arranged in order can constitute the original data sequence. Optionally, the original data sequence can include 6N original data, where N is a positive integer. It should be understood that the number of original data in the original sequence being an integer multiple of 6 is only for encoding every 6 as a group in subsequent steps. For example, the number of original data in the original data sequence may not be a multiple of 6. In this case, when the number of remaining original data to be sent is less than 6, the encoder can wait to obtain new original data and then encode and send the remaining original data together with the new original data.

[0119] S520: Encode 6 out of 6N original data using the encoding matrix to obtain 4 encoded data.

[0120] For example, in step S520, the encoder can encode every 6 original data as a group according to the arrangement order of the original data in the original data sequence, and 4 encoded data are generated for each group of encoding. By way of example, the 6 original data can be the 6i - 5th to 6ith original data in the original data sequence, where i is a positive integer less than or equal to N.

[0121] Optionally, the size of the above-mentioned encoding matrix can be 4×6 (4 rows and 6 columns), and the encoding method can be matrix multiplication of the encoding matrix and the matrix composed of 6 original data. Specifically as follows:

[0122]

[0123] Among them, G is the encoding matrix, p0, p1, p2, and p3 are 4 encoded data, and m0, m1, m2, m3, m4, and m5 are 6 original data. It should be understood that p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 are all elements in the finite field GF(2 k ), and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

[0124] Optionally, the length of the original data can be 4 bits, and correspondingly, the length of the encoded data can also be 4 bits. For example, the original data can be represented by 4-bit binary numbers. In this case, the matrix composed of 6 original data is a 6×4 matrix, and the matrix composed of the encoded data generated by encoding is a 4×4 matrix.

[0125] In some possible implementation manners, the sequence composed of 6 original data and 4 encoded data can be decoded by the decoding matrix in the second PLD to obtain 4 first decoded data, and all 4 first decoded data are 0. In other words, when there is no error in the data received by the second PLD, the decoded data obtained by decoding by the decoder in the second PLD satisfies that all are 0.

[0126] Optionally, the size of the above decoding matrix can be 4×10, and the decoding method can be to perform matrix multiplication on the decoding matrix and the matrix composed of 6 original data and 4 encoded data. Specifically as follows:

[0127]

[0128] Among them, H is the decoding matrix, p0, p1, p2, and p3 are 4 encoded data, and m0, m1, m2, m3, m4, and m5 are 6 original data. It should be understood that the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 also conform to the operation rules in the finite field GF(2 k ), and are the same as the operation rules during encoding.

[0129] In some possible implementation manners, a set of encoding matrix and decoding matrix that conform to the above encoding and decoding rules can be:

[0130]

[0131]

[0132] In this case, the encoding process is as follows:

[0133]

[0134] The encoding result satisfies:

[0135]

[0136] S530: Send the first data sequence to the second PLD.

[0137] For example, in step S530, the encoder may jointly form the first data sequence with the original data and the encoded data obtained in step S520 and send it. Optionally, the first data in the first data may be divided into groups of every 10 data in the sending order. Each group of data includes 6 original data that are the encoding objects in step S520, and 4 encoded data obtained by encoding the 6 original data. As an example, when the number of original data in the original data sequence is 6N, the first data sequence may include 10N first data. The 10i - 9th to 10ith first data may be 6 original data and 4 encoded data. The 6 original data may be the 6i - 5th to 6ith original data in the original data sequence, and the 4 encoded data are the encoded data obtained by encoding the 6 original data through the encoding matrix.

[0138] Figure 6 shows a schematic diagram of an encoder encoding process. As Figure 6 shown, whenever the encoder receives 6 original data (m0, m1, m2, m3, m4, m5), it encodes the 6 original data to obtain 4 encoded data (p0, p1, p2, p3), and sends the 6 original data and the 4 encoded data in the sequence order of (p0, p1, p2, p3, m0, m1, m2, m3, m4, m5). Whenever the encoder obtains 6 new original data, the above process can be repeated to send 10 first data, thereby forming the first data sequence sent from the first PLD to the second PLD.

[0139] Through the above technical solution, the original data is encoded in groups of every 6 on the encoder side, reducing the amount of encoded data for each group, so as to reduce the delay required for the decoder to wait for the transmission of encoded data before each decoding starts, thereby reducing the cross - chip delay of encoding and decoding in the hardware simulation system. In addition, by configuring 4 encoded data for error correction for every 6 - data group, the error - correction effect can be ensured without reduction, so as to ensure the low bit - error rate of the serial link in the hardware simulation system while providing low delay, and further enable the hardware simulation system to support larger - scale chip verification.

[0140] Figure 7FIG. 0 shows a schematic flowchart of a decoding method provided by an embodiment of the present application. Optionally, this method may be executed by a decoder, or may be executed by an encoder, which is not specifically limited in the present application. For the convenience of description, in the following embodiments, the decoder is used as the execution subject for description. The decoder may be disposed in the second PLD of the hardware simulation system, and the hardware simulation system includes multiple PLDs. For example, the hardware simulation system may be Figure 4 the system 400 shown in Figure 4 and the encoder may be the decoder 421 shown in

[0141] As shown in Figure 7 , this method includes the following steps.

[0142] S710: Receive a second data sequence.

[0143] For example, in step S710, the decoder may receive the second data sequence through a serial link. The second data sequence may be a data sequence transformed from the first data sequence after passing through the channel in the serial link. The first data sequence may be a data sequence sent by the first PLD to the second PLD through the encoder. It should be understood that due to the interference of the channel on the transmitted data, the second data sequence may not be exactly the same as the first data sequence, that is, there may be an error code in the second data sequence relative to the first data sequence. Optionally, the second data sequence includes 10N second data, where N is a positive integer. It should be understood that the number of second data in the second data sequence being an integer multiple of 10 is only for decoding every 10 as a group in subsequent steps. For example, the number of second data in the second data sequence may also not be a multiple of 10. In this case, when the number of remaining undecoded second data is less than 10, the decoder may wait to receive new second data and then decode the remaining second data together with the new second data.

[0144] S720: Decode 10 second data out of the 10N second data using a decoding matrix to obtain 4 second decoded data.

[0145] For example, in step S720, the decoder may decode the second data every 10 as a group according to the arrangement order of the second data in the second data sequence, and each group of decoding generates 4 second decoded data. For example, the 10 second data may be the 10i - 9th to 10ith second data in the second data sequence, where i is a positive integer less than or equal to N.

[0146] Optionally, the size of the above decoding matrix may be 4×10, and the decoding method may be to perform matrix multiplication on the matrix formed by the decoding matrix and the 10 second data. Specifically as follows:

[0147]

[0148] Wherein, H is a decoding matrix, s0, s1, s2, and s3 are four second decoded data, and r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are ten second data. It should be understood that s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are all elements in the finite field GF(2 k ). The operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the second data (i.e., the bit length of the original data on the encoding side), and k is a positive integer.

[0149] Optionally, the length of the second data can be 4 bits, and correspondingly, the length of the decoded data can also be 4 bits. For example, the second data can be represented by a 4-bit binary number. In this case, the matrix composed of ten second data is a 10×4 matrix, and the matrix composed of the decoded data generated by decoding is a 4×4 matrix.

[0150] In some possible implementation manners, the 10i - 9th to 10i - th second data in the second data sequence are generated after the 10i - 9th to 10i - th first data in the first data sequence are interfered by the channel. Among them, the 10i - 9th to 10i - th first data can be composed of six original data and four encoded data. The six original data can be the 6i - 5th to 6i - th original data in the original data sequence. The original data sequence includes 6N original data. The four encoded data are obtained by encoding the six original data with the encoding matrix in the first PLD.

[0151] Optionally, the size of the above encoding matrix can be 4×6, and the encoding method can be matrix multiplication of the encoding matrix and the matrix composed of six original data. Specifically as follows:

[0152]

[0153] Wherein, G is the encoding matrix, p0, p1, p2, and p3 are four encoded data, and m0, m1, m2, m3, m4, and m5 are six original data. It should be understood that p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 are all elements in the finite field GF(2 k ). The operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), and are the same as the operation rules during the above decoding.

[0154] In some possible embodiments, a set of encoding matrices and decoding matrices that conform to the above encoding and decoding rules may be as follows:

[0155]

[0156]

[0157] S730: When the four second decoded data are 0, determine the six original data and four encoded data included in the ten second data.

[0158] For example, in step S730, when all four second decoded data obtained by decoding in step S720 are 0, the decoder may determine that the ten second data are composed of the above six original data and four encoded data. That is, there is no error in the ten second data relative to the ten first data at the corresponding positions in the first data sequence sent by the first PLD. That is, when the four second decoded data satisfy the following conditions:

[0159] s0 = 0, s1 = 0, s2 = 0, s3 = 0

[0160] The above ten second data and the six original data and four encoded data satisfy the following relationship:

[0161]

[0162] Thus, the second PLD can obtain the six original data (m0, m1, m2, m3, m4, m5) that the first PLD hopes to transmit from the ten second data (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9) received for simulation in the second PLD.

[0163] Optionally, in some possible embodiments, the above decoding method may further include step S740.

[0164] S740: When the four second decoded data are not all 0, determine the number of error data in the decoding of the ten second data according to the four second decoded data.

[0165] For example, in step S740, if the execution condition of S730 is not satisfied, the decoder may determine that there is at least one error data in the ten second data relative to the above six original data and four encoded data, and can determine the number of error data.

[0166] It should be understood that the above-mentioned error data refers to the situation where the second data in the second data sequence is different from the first data at the corresponding position in the first data sequence. For example, assuming that the second data sequence (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9) corresponds to the first data sequence (p0, p1, p2, p3, m0, m1, m2, m3, m4, m5), then when r0≠p0, r0 can be considered as an error data, or when r4≠m0, r4 can be considered as an error data.

[0167] Optionally, in some possible implementation manners, the method for determining the number of error data is to determine that the number of error data is 1 when the following conditions are satisfied for 4 second decoded data:

[0168]

[0169] When the 4 second decoded data are not all 0 and do not satisfy at least one of the above conditions, determine that the number of error data is a positive integer greater than or equal to 2 and less than or equal to 10.

[0170] It should be understood that since the 4 second decoded data s0, s1, s2, and s3 are elements in the finite field GF(2 k ), the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ).

[0171] The above method can determine whether the error data is one or more according to the decoded data, so as to select the corresponding error correction method according to the number of error data and locate the error data, thereby improving the subsequent error correction efficiency.

[0172] Through the above optional step S740, when the decoder side determines through decoding that there is error data in the received data relative to the data sent by the encoder side, it can determine the number of error data according to the decoded data, so as to correct the error data within a certain range to reduce the bit error rate of the serial link in the hardware simulation system.

[0173] Optionally, in some possible implementation manners, the above decoding method may further include step S750 in step S740.

[0174] S750: Correct the error data according to the number of error data and the 4 second decoded data.

[0175] For example, in step S750, the decoder can correct the above-mentioned 10 second data after determining the number of error data to obtain the above-mentioned 6 original data and 4 encoded data.

[0176] In some possible embodiments, the decoder may substitute the above-mentioned 10 second data (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9) into the error correction polynomial Λ(x) as variables x respectively, and count the number of second data that can make Λ(x) = 0 hold. Among them, when it is determined in step S740 that there is 1 error data, the error correction polynomial used is:

[0177] Λ(x) = s0·x + s1

[0178] When it is determined in step S740 that there are 2 or more error data, the error correction polynomial used is:

[0179]

[0180] Among them, s0, s1, s2, and s3 are 4 second decoding data, and the operations between s0, s1, s2, and s3 and x conform to the operation rules in the finite field GF(2 k )

[0181] When the number of second data that can make Λ(x) = 0 hold is equal to the highest power of x in Λ(x) = 0, it means that the error data can be corrected, and the second data that can make Λ(x) = 0 hold is the error data; otherwise, it means that the error data cannot be corrected. For example, in the case where the error can be corrected, if Λ(r5) = 0, it means that r5 is an error data.

[0182] Optionally, when it is determined that the error can be corrected and the position of the error data is determined, the decoder can obtain the correct value corresponding to the correct second data and the decoding matrix error data. For example, assume that the error data of the second data sequence (r0, r1, r2, r3, r4, r5, r6, r7, r8, r9) relative to the first data sequence (p0, p1, p2, p3, m0, m1, m2, m3, m4, m5) is r5, that is, r4≠m1, and the other 9 second data except r5 are equal to the first data at the corresponding positions in the first data sequence. Then according to the foregoing encoding and decoding rules:

[0183]

[0184] The correct second data r0, r1, r2, r3, r4, r6, r7, r8, and r9 can be substituted into the following formula to solve the correct data r5' corresponding to the error data r5:

[0185]

[0186] Through the above optional step S750, when the error data can be corrected, the decoder can restore the correct data sent by the encoder side based on the error data and the decoded data to obtain the original data, so as to perform subsequent hardware simulation steps in the PLD on the encoder side.

[0187] Through the encoding and decoding method provided in the embodiments of the present application above, error correction encoding and decoding with low bit error rate and low latency can be achieved, thereby increasing the maximum simulation capacity of the hardware simulation system. The maximum simulation capacity can be expressed as the product of the number of logic units and the simulation time, which is limited by the requirements for the total latency or total bit error rate in the hardware simulation system. Therefore, the technical solution of the present application reduces the average latency and bit error rate required for each logic unit and unit simulation time, enabling the hardware simulation system to support more logic units and / or longer simulation time. For example, assuming that the existing hardware simulation system can accommodate a simulation scale of x (hundred million gates) × y (hours), where x and y are positive numbers, with the requirements for the total latency and total bit error rate of the hardware simulation system remaining unchanged, the technical solution of the present application can expand the simulation scale that the hardware simulation system can accommodate to n * x (hundred million gates) × m * y (hours), where n and m are positive numbers greater than 1.

[0188] As described above in conjunction with Figures 5 to 7 the embodiments of the encoding and decoding method provided by the present application, the embodiments of the encoding and decoding device provided by the present application will be described below in conjunction with Figures 8 to 10 for illustration.

[0189] Figure 8 FIG. shows a schematic structural block diagram of an encoder 800 provided by an embodiment of the present application. The encoder 800 can be disposed in a hardware simulation system, for example, disposed in the first PLD of the hardware simulation system. The hardware simulation system can include multiple PLDs. For example, the hardware simulation system can be the Figure 4 system 400 shown in Figure 8 As shown in

[0190] Specifically, the obtaining module 810 is configured to obtain an original data sequence, where the original data sequence includes 6N original data, and N is a positive integer.

[0191] Specifically, the encoding module 820 is configured to encode 6 of the 6N original data using an encoding matrix to obtain 4 encoded data, where the 6 original data are the 6i - 5th to 6ith original data in the original data sequence, and i is a positive integer less than or equal to N.

[0192] Optionally, the 6 original data and the 4 encoded data are used to be decoded by a decoding matrix in the second PLD to obtain 4 first decoded data, and the 4 first decoded data are 0.

[0193] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0194]

[0195] where G is the encoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0196] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0197]

[0198] where H is the decoding matrix, p0, p1, p2, and p3 are 4 encoded data, m0, m1, m2, m3, m4, and m5 are 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0199] Optionally, the encoding matrix and the decoding matrix satisfy:

[0200]

[0201]

[0202] where G is the encoding matrix and H is the decoding matrix.

[0203] Specifically, the sending module 830 is configured to send a first data sequence to the second PLD, where the first data sequence includes 10N first data, and the 10i−9 to 10i-th first data in the first data sequence include 6 original data and 4 encoded data.

[0204] Figure 9 FIG. shows a schematic structural block diagram of a decoder 900 provided by an embodiment of the present application. The decoder 900 can be disposed in a hardware simulation system, for example, disposed in the second PLD of the hardware simulation system. The hardware simulation system may include multiple PLDs. For example, the hardware simulation system may be Figure 4 the system 400 shown. As Figure 9 shown, the decoder 900 includes: a receiving module 910, a decoding module 920, and an error correction module 930.

[0205] Specifically, the receiving module 910 is configured to receive a second data sequence, where the second data sequence includes 10N second data, and N is a positive integer.

[0206] Specifically, the decoding module 920 is configured to decode 10 second data out of the 10N second data by using a decoding matrix to obtain 4 second decoded data, where the 10 second data are the 10i - 9th to 10ith second data in the second data sequence, and i is a positive integer less than or equal to N.

[0207] Specifically, the error correction module 930 is configured to determine 6 original data and 4 encoded data included in the 10 second data when the 4 second decoded data are 0, where the 6 original data are the 6i - 5th to 6ith original data in the original data sequence, the original data sequence includes 6N original data, and the 4 encoded data are obtained by encoding the 6 original data with the encoding matrix in the first PLD.

[0208] Optionally, the size of the decoding matrix is 4×10 and satisfies:

[0209]

[0210] where H is the decoding matrix, s0, s1, s2, and s3 are the 4 second decoded data, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are the 10 second data, and the operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0211] Optionally, the size of the encoding matrix is 4×6 and satisfies:

[0212]

[0213] where G is the encoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ), and k is the bit length of the original data, and k is a positive integer.

[0214] Optionally, the encoding matrix and the decoding matrix satisfy:

[0215]

[0216]

[0217] Among them, G is the encoding matrix and H is the decoding matrix.

[0218] Optionally, the error correction module 930 is further configured to determine the number of error data in the 10 second data decodings according to the 4 second decoded data when the 4 second decoded data are not all 0, where the error data are second data different from the 6 original data and the 4 encoded data.

[0219] Optionally, the error correction module 930 is specifically configured to determine that the number of error data is 1 when the 4 second decoded data meet the following conditions:

[0220]

[0221] Among them, s0, s1, s2, and s3 are the 4 second decoded data, and the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ). When the 4 second decoded data are not all 0 and do not meet the above conditions, it is determined that the number of error data is a positive integer greater than or equal to 2 and less than or equal to 10.

[0222] Optionally, the error correction module 930 is further configured to correct the error data according to the number of error data and the 4 second decoded data to obtain the 6 original data and the 4 encoded data.

[0223] Among them, the above modules can be implemented by software or by hardware.

[0224] As an example of a software functional unit, the above modules may include code running on a computing device. Among them, the above computing device may include a processor and a memory, and the above code may be stored in the memory of the above computing device. When the code is executed by the processor of the above computing device, the above computing device can execute the encoding method provided in the embodiments of the present application. The above processor may be an application-specific integrated circuit (ASIC), or any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), etc.

[0225] As an example of a hardware functional unit, the above-mentioned module can be implemented by combining logic units included in a PLD, or can be a computing device implemented using an ASIC. Among them, the PLD can include a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or any combination thereof. The logic units included in each functional module can be distributed in the same computing device or in multiple computing devices.

[0226] It should be noted that in other embodiments, the acquisition module 810, the encoding module 820, and the sending module 830 can be respectively used to execute any steps in the above encoding method. The steps to be implemented by the acquisition module 810, the encoding module 820, and the sending module 830 can be specified as needed. The encoder 800's full functionality is achieved by the acquisition module 810, the encoding module 820, and the sending module 830 respectively implementing different steps in the above encoding method.

[0227] In some other embodiments, the receiving module 910, the decoding module 920, and the error correction module 930 can be respectively used to execute any steps in the above decoding method. The steps to be implemented by the receiving module 910, the decoding module 920, and the error correction module 930 can be specified as needed. The decoder 900's full functionality is achieved by the receiving module 910, the decoding module 920, and the error correction module 930 respectively implementing different steps in the above decoding method.

[0228] This application also provides a computing device 100. Optionally, the computing device can be a programmable logic device or a part of a programmable logic device, such as the programmable logic device in a hardware emulation system. As Figure 10 shown, the computing device 100 includes: a bus 102, a processor 104, and a memory 106. The processor 104 and the memory 106 communicate through the bus 102. It should be understood that this application does not limit the number of processors and memories in the computing device 100.

[0229] The bus 102 can be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 10 only one line is used to represent it in Figure 10 , but it does not mean that there is only one bus or one type of bus. The bus 102 can include a path for transmitting information between various components of the computing device 100 (for example, the memory 106 and the processor 104).

[0230] The processor 104 can include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), a digital signal processor (DSP), or other processors, or an application-specific integrated circuit (ASIC).

[0231] The memory 106 can include volatile memory, such as random access memory (RAM). The memory 106 can also include non-volatile memory, such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0232] The memory 106 stores executable program code, and the processor 104 executes the executable program code to implement the functions of the foregoing acquisition module, encoding module, and sending module respectively, or to implement the functions of the foregoing receiving module, decoding module, and error correction module, so as to implement the foregoing encoding and decoding method. That is, the memory 106 stores instructions for executing the foregoing encoding method and / or decoding method.

[0233] An embodiment of the present application further provides a chip, which includes a processor and a data interface. The processor reads the instructions stored in the memory through the data interface to execute the foregoing encoding method and / or decoding method.

[0234] Embodiments of the present application also provide a computer program product containing instructions. The computer program product may be software or a program product containing instructions that can run on a computing device or be stored in any available medium. When the computer program product runs on at least one computing device, at least one computing device is caused to execute the above encoding method and / or decoding method.

[0235] Embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium may be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc. The computer-readable storage medium includes instructions that direct the computing device to execute the above encoding method and / or decoding method.

[0236] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0237] As mentioned above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A coding method, characterized in that, The method is applied to an encoder in a first programmable logic device (PLD) in a hardware simulation system. The hardware simulation system includes multiple PLDs. The method includes: Obtain an original data sequence, where the original data sequence includes 6N original data, and N is a positive integer; Encode 6 of the 6N original data using an encoding matrix to obtain 4 encoded data, where the 6 original data are the 6i - 5th to 6ith original data in the original data sequence, and i is a positive integer less than or equal to N; Send a first data sequence to a second PLD, where the first data sequence includes 10N first data, and the 10i - 9th to 10ith first data in the first data sequence include the 6 original data and the 4 encoded data.

2. The encoding method according to claim 1, wherein The 6 original data and the 4 encoded data are used to be decoded by a decoding matrix in the second PLD to obtain 4 first decoded data, and the 4 first decoded data are 0.

3. The encoding method according to claim 2, wherein The size of the encoding matrix is 4×6, and the encoding matrix satisfies: Among them, G is the encoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ).), k is the bit length of the original data, and k is a positive integer.

4. The encoding method according to claim 3, wherein The size of the decoding matrix is 4×10, and the decoding matrix satisfies: Among them, H is the decoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

5. The encoding method according to claim 4, characterized in that, The encoding matrix and the decoding matrix satisfy: where G is the encoding matrix and H is the decoding matrix.

6. A decoding method, characterized in that, The method is applied to a decoder in a second programmable logic device (PLD) in a hardware simulation system. The hardware simulation system includes multiple PLDs. The method includes: Receive a second data sequence, where the second data sequence includes 10N second data, and N is a positive integer; Decode 10 of the 10N second data using a decoding matrix to obtain 4 second decoded data, where the 10 second data are the 10i - 9th to 10ith second data in the second data sequence, and i is a positive integer less than or equal to N; When the 4 second decoded data are 0, determine the 6 original data and 4 encoded data included in the 10 second data, where the 6 original data are the 6i - 5th to 6ith original data in an original data sequence, the original data sequence includes 6N original data, and the 4 encoded data are obtained by encoding the 6 original data using an encoding matrix in a first PLD.

7. The decoding method according to claim 6, characterized in that The size of the decoding matrix is 4×10, and the decoding matrix satisfies: Wherein, H is the decoding matrix, s0, s1, s2, and s3 are the four second decoded data, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are the ten second data, and the operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ), k is the bit length of the original data, and k is a positive integer.

8. The decoding method according to claim 7, wherein The size of the encoding matrix is 4×6, and the encoding matrix satisfies: Among them, G is the encoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). Here, k is the bit length of the original data, and k is a positive integer.

9. The decoding method according to claim 8, wherein The encoding matrix and the decoding matrix satisfy: where G is the encoding matrix and H is the decoding matrix.

10. The decoding method according to claim 8 or 9, characterized in that, The method further includes: When the 4 second decoded data are not all 0, determine the number of error data in the decoding of the 10 second data according to the 4 second decoded data, where the error data are second data different from the 6 original data and the 4 encoded data.

11. The decoding method according to claim 10, characterized in that, The determining the number of error data in the 10 second data according to the 4 second decoded data includes: When the 4 second decoded data satisfy the following conditions, determine that the number of error data is 1: s0≠0, s1≠0, s2≠0, s3≠0, Among them, s0, s1, s2, and s3 are the four second decoded data, and the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ); When the four second decoded data are not all 0 and do not meet the above conditions, determine that the number of the error data is a positive integer greater than or equal to 2 and less than or equal to 10.

12. The decoding method according to claim 10 or 11, characterized in that, The method further includes: According to the number of the error data and the four second decoded data, correct the error data to obtain the six original data and the four encoded data.

13. An encoder, characterized in that, The encoder is disposed in a first programmable logic device (PLD) in a hardware simulation system. The hardware simulation system includes multiple PLDs. The encoder includes: An acquisition module, configured to acquire an original data sequence, where the original data sequence includes 6N original data, and N is a positive integer; An encoding module, configured to encode six original data among the 6N original data by using an encoding matrix to obtain four encoded data, where the six original data are the 6i - 5th to 6i - th original data in the original data sequence, and i is a positive integer less than or equal to N; A sending module, configured to send a first data sequence to a second PLD, where the first data sequence includes 10N first data, and the 10i - 9th to 10i - th first data in the first data sequence include the six original data and the four encoded data.

14. The encoder according to claim 13, wherein, The six original data and the four encoded data are used to be decoded by a decoding matrix in the second PLD to obtain four first decoded data, and the four first decoded data are 0.

15. The encoder according to claim 14, wherein, The size of the encoding matrix is 4×6, and the encoding matrix satisfies: Among them, G is the encoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ).), k is the bit length of the original data, and k is a positive integer.

16. The encoder according to claim 15, characterized in that, The size of the decoding matrix is 4×10, and the decoding matrix satisfies: Wherein, H is the decoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

17. The encoder according to claim 16, wherein The encoding matrix and the decoding matrix satisfy: Where G is the encoding matrix and H is the decoding matrix.

18. A decoder, characterized in that, The decoder is disposed in a second programmable logic device (PLD) in a hardware simulation system. The hardware simulation system includes multiple PLDs. The decoder includes: A receiving module, configured to receive a second data sequence, where the second data sequence includes 10N second data, and N is a positive integer; A decoding module, configured to decode ten second data among the 10N second data by using a decoding matrix to obtain four second decoded data, where the ten second data are the 10i - 9th to 10i - th second data in the second data sequence, and i is a positive integer less than or equal to N; An error correction module, configured to, when the four second decoded data are 0, determine the six original data and the four encoded data included in the ten second data, where the six original data are the 6i - 5th to 6i - th original data in the original data sequence, the original data sequence includes 6N original data, and the four encoded data are obtained by encoding the six original data by the encoding matrix in the first PLD.

19. The decoder according to claim 18, wherein, The size of the decoding matrix is 4×10, and the decoding matrix satisfies: Among them, H is the decoding matrix, s0, s1, s2, and s3 are the 4 second decoded data, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 are the 10 second data, and the operations of s0, s1, s2, s3, r0, r1, r2, r3, r4, r5, r6, r7, r8, and r9 conform to the operation rules in the finite field GF(2 k ).), k is the bit length of the original data, and k is a positive integer.

20. The decoder according to claim 19, characterized in that, The size of the encoding matrix is 4×6, and the encoding matrix satisfies: Among them, G is the encoding matrix, p0, p1, p2, and p3 are the 4 encoded data, m0, m1, m2, m3, m4, and m5 are the 6 original data, and the operations of p0, p1, p2, p3, m0, m1, m2, m3, m4, and m5 conform to the operation rules in the finite field GF(2 k ). k is the bit length of the original data, and k is a positive integer.

21. The decoder according to claim 20, wherein The encoding matrix and the decoding matrix satisfy: Where G is the encoding matrix and H is the decoding matrix.

22. The decoder according to claim 20 or 21, characterized in that, The error correction module is further configured to: When the four second decoded data are not all 0, determine the number of error data in the ten second data decodings according to the four second decoded data, where the error data are second data different from the six original data and the four encoded data.

23. The decoder according to claim 22, characterized in that, The error correction module is configured to: When the four second decoded data meet the following conditions, determine that the number of error data is 1: s0≠0, s0≠0, s0≠0, s0≠0, Among them, s0, s1, s2, and s3 are the four second decoded data, and the operations of s0, s1, s2, and s3 conform to the operation rules in the finite field GF(2 k ); When the four second decoded data are not all 0 and do not meet the above conditions, determine that the number of error data is a positive integer greater than or equal to 2 and less than or equal to 10.

24. The decoder according to claim 22 or 23, characterized in that, The error correction module is further configured to: Correct the error data according to the number of error data and the four second decoded data to obtain the six original data and the four encoded data.

25. A computing device, characterized in that, Comprising a processor and a memory, the processor is configured to execute instructions stored in the memory so that the computing device executes the method according to any one of claims 1 to 5, and / or execute the method according to any one of claims 6 to 12.

26. A computer program product, characterized in that, Comprising instructions, when the instructions are run by a computing device, the computing device is caused to execute the method according to any one of claims 1 to 5, and / or execute the method according to any one of claims 6 to 12.

27. A computer-readable storage medium, characterized in that, Comprising computer program instructions, when the computer program instructions are executed by a computing device, the computing device is caused to execute the method according to any one of claims 1 to 5, and / or execute the method according to any one of claims 6 to 12.

28. A hardware simulation system, characterized in that, Comprising at least one first programmable logic device (PLD) and at least one second PLD, the first PLD is configured to execute the method according to any one of claims 1 to 5, and the second PLD is configured to execute the method according to any one of claims 6 to 12.

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