Display device, display driving integrated circuit and operation method

Abstract

The invention provides a display device, a display driving integrated circuit and an operation method. The display driving integrated circuit receives a data stream and an external horizontal synchronization signal from the processor, wherein the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The display driving integrated circuit generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information. The display driving integrated circuit dynamically updates the delay value based on a phase relationship of the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal. The display driving integrated circuit delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal. The display driving integrated circuit drives the display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

Description

Technical Field

[0001] The present invention relates to an electronic device, and particularly to a display device, a display driving integrated circuit, and an operation method of the display driving integrated circuit. Background Art

[0002] An application processor (AP) can carry display frame data, vertical synchronization information, and horizontal synchronization information in a data stream, and then provide the data stream to a display driving integrated circuit through a data lane of a Mobile Industry Processor Interface (MIPI). The vertical synchronization information can be a Vertical Sync Start flag defined by the MIPI specification, and the horizontal synchronization information can be a Horizontal Sync Start flag defined by the MIPI specification. The display driving integrated circuit can drive a display panel based on the display frame data, vertical synchronization information, and horizontal synchronization information provided by the application processor. In some operation scenarios, in each display frame, after the application processor outputs data of a valid display frame to the display driving integrated circuit, it then outputs data of multiple blank frames to the display driving integrated circuit. For example, assuming the original frame rate is 120 Hz, in order to achieve a frame rate of 1 Hz, after the application processor outputs data of a valid display frame (including horizontal synchronization information of 1 frame) to the display driving integrated circuit each time, it then outputs invalid data and horizontal synchronization information of 199 blank frames to the display driving integrated circuit.

[0003] In the MIPI video mode, the display driving integrated circuit needs to count the horizontal synchronization information of these 199 blank frames to know the timing of the next display frame. However, the output of the horizontal synchronization information of these 199 blank frames consumes power. How to reduce the power consumption of the MIPI data lane is one of many technical problems in this field. Summary of the Invention

[0004] The present invention provides a display device, a display driving integrated circuit, and an operation method of the display driving integrated circuit to drive a display panel.

[0005] In an embodiment according to the present invention, the above-mentioned display driving integrated circuit includes an interface circuit, a synchronization signal generation circuit, and a driving circuit. The interface circuit receives a data stream and an external horizontal synchronization signal from a processor, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The synchronization signal generation circuit is coupled to the interface circuit to receive the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal. The synchronization signal generation circuit generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information. The synchronization signal generation circuit dynamically updates a delay value based on the phase relationship among the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal. The synchronization signal generation circuit delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal. The driving circuit is coupled to the interface circuit to receive the display frame data, and is coupled to the synchronization signal generation circuit to receive the internal vertical synchronization signal and the internal horizontal synchronization signal. The driving circuit drives a display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

[0006] In an embodiment according to the present invention, the above-mentioned operation method includes: receiving, by the interface circuit of the display driving integrated circuit, a data stream and an external horizontal synchronization signal from a processor, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information; generating, by the synchronization signal generation circuit of the display driving integrated circuit, an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information; dynamically updating, by the synchronization signal generation circuit, a delay value based on the phase relationship among the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal; delaying, by the synchronization signal generation circuit, the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal; and driving, by the driving circuit of the display driving integrated circuit, a display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

[0007] In an embodiment according to the present invention, the above-mentioned display device includes a processor, a display driving integrated circuit, and a display panel. The display driving integrated circuit is coupled to the processor to receive a data stream and an external horizontal synchronization signal, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The display driving integrated circuit generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information. The display driving integrated circuit dynamically updates a delay value based on the phase relationship among the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal. The display driving integrated circuit delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal. The display panel is coupled to the display driving integrated circuit. The display driving integrated circuit drives the display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

[0008] Based on the above, the display driver integrated circuit according to the embodiments of the present invention generates an internal horizontal synchronization signal by using an external horizontal synchronization signal, and then uses the internal horizontal synchronization signal to drive the display panel. In the MIPI video mode, the display driver integrated circuit can count the internal horizontal synchronization signal to know the timing of the next display frame. Therefore, in each display frame of the MIPI video mode, after the processor outputs the data of a valid display frame (including the horizontal synchronization information of one frame) to the display driver integrated circuit, the processor then stops the data stream (no longer outputs redundant horizontal synchronization information) until the end of a display frame. Since the processor does not need to output redundant horizontal synchronization information, and the display driver integrated circuit does not need to receive and process (such as unpacking) redundant horizontal synchronization information, the power consumption can be reduced. In addition, the display driver integrated circuit can dynamically update the delay value of the internal horizontal synchronization signal based on the phase relationship between the horizontal synchronization information and the external horizontal synchronization signal, so that the phase of the internal horizontal synchronization signal can match the phase of the horizontal synchronization information provided by the processor. Description of the Drawings

[0009] Figure 1 FIG. is a schematic diagram of a circuit block of a display device according to an embodiment of the present invention.

[0010] Figure 2 FIG. is a schematic flowchart of an operation method of a display driver integrated circuit according to an embodiment of the present invention.

[0011] Figure 3 FIG. is a timing / phase diagram of vertical synchronization information and an external horizontal synchronization signal shown according to an embodiment of the present invention.

[0012] Figure 4 FIG. is a timing / phase diagram of vertical synchronization information, horizontal synchronization information, external horizontal synchronization signal, internal vertical synchronization signal and internal horizontal synchronization signal shown according to an embodiment of the present invention.

[0013] Description of Reference Numerals

[0014] 100: Display device

[0015] 110: Processor

[0016] 120: Display driver integrated circuit

[0017] 121: Interface circuit

[0018] 122: Synchronization signal generation circuit

[0019] 123: Driver circuit

[0020] 130: Display panel

[0021] AP_CLK: Clock signal

[0022] AP_D1: Data stream

[0023] AP_D2: Display frame data

[0024] EHs1, EHs2: External synchronization time points

[0025] EXT_HSYNC: External horizontal synchronization signal

[0026] HSS: Horizontal synchronization information

[0027] HSS11, HSS21, IHs1, IHs2: Horizontal synchronization time points

[0028] Int_Hs: Internal horizontal synchronization signal

[0029] Int_Vs: Internal vertical synchronization signal

[0030] IVs1, IVs2, VSS1, VSS2: Vertical synchronization time points

[0031] S210, S220, S230, S240, S250: Steps

[0032] Skew1, skew2: Skew

[0033] TL1, TL2: Durations

[0034] VSS: Vertical synchronization information Detailed implementation manners

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0036] As used throughout the specification (including the claims) of this application, the term "coupled (or connected)" may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some means of connection. The terms "first", "second", etc. mentioned throughout the specification (including the claims) of this application are used to name elements or to distinguish different embodiments or scopes, rather than to limit the upper or lower limit of the number of elements, nor to limit the order of the elements. Additionally, wherever possible, components / elements / steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / elements / steps with the same reference numerals or the same terms used in different embodiments can be referred to each other for relevant descriptions.

[0037] Figure 1 FIG. 4 is a schematic diagram of a circuit block of a display device 100 according to an embodiment of the present invention. Figure 1 The illustrated display device 100 includes a processor 110, a display driver integrated circuit 120, and a display panel 130. The display driver integrated circuit 120 is coupled to the processor 110 to receive a data stream AP_D1 and an external horizontal synchronization signal EXT_HSYNC. The specific transmission method of the data stream AP_D1 is not limited herein. For example (but not limited to), the display driver integrated circuit 120 can receive a clock signal AP_CLK and a data stream AP_D1 from the processor 110 through a Mobile Industry Processor Interface (MIPI) or other interfaces. The display driver integrated circuit 120 can sample / latch the data in the data stream AP_D1 based on the clock signal AP_CLK.

[0038] The display driving integrated circuit 120 can unpack the data stream AP_D1. The data stream AP_D1 includes display frame data AP_D2, vertical synchronization information VSS, and horizontal synchronization information HSS. The vertical synchronization information VSS may include a Vertical Sync Start flag defined by the MIPI specification, and the horizontal synchronization information HSS may include a Horizontal Sync Start flag defined by the MIPI specification. The display driving integrated circuit 120 can generate an internal vertical synchronization signal Int_Vs based on the vertical synchronization information VSS and the horizontal synchronization information HSS. Based on the phase relationship between the vertical synchronization information VSS, the horizontal synchronization information HSS, and the external horizontal synchronization signal EXT_HSYNC, the display driving integrated circuit 120 can dynamically determine / update the delay value. The display driving integrated circuit 120 can delay the external horizontal synchronization signal EXT_HSYNC based on this delay value to generate an internal horizontal synchronization signal Int_Hs. The display panel 130 is coupled to the display driving integrated circuit 120. The display driving integrated circuit 120 can drive the display panel 130 based on the display frame data AP_D2, the internal vertical synchronization signal Int_Vs, and the internal horizontal synchronization signal Int_Hs.

[0039] In Figure 1 In the illustrated embodiment, the display driving integrated circuit 120 includes an interface circuit 121, a synchronization signal generation circuit 122, and a driving circuit 123. According to different designs, in some embodiments, the above-mentioned processor 110, display driving integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and (or) driving circuit 123 may be implemented as hardware circuits. In other embodiments, the processor 110, display driving integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and (or) driving circuit 123 may be implemented as firmware or software (i.e., programs) or a combination of the foregoing two. In still other embodiments, the processor 110, display driving integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and (or) driving circuit 123 may be implemented as a combination of hardware, firmware, and software.

[0040] In terms of hardware, the related functions of the above-mentioned processor 110, display driver integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and / or driving circuit 123 can be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or various logic blocks, modules, and circuits in other processing units. The related functions of the processor 110, display driver integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and / or driving circuit 123 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, by using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages.

[0041] In terms of software and / or firmware, the related functions of the above-mentioned processor 110, display driver integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and / or driving circuit 123 can be implemented as programming codes. For example, the processor 110, display driver integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and / or driving circuit 123 are implemented by using general programming languages (such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (such as a CPU, controller, microcontroller, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the related functions of the processor 110, display driver integrated circuit 120, interface circuit 121, synchronization signal generation circuit 122, and / or driving circuit 123.

[0042] Figure 2FIG. 0 is a schematic flowchart of an operation method of a display driving integrated circuit 120 according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , in step S210, the interface circuit 121 can receive the data stream AP_D1 and the external horizontal synchronization signal EXT_HSYNC from the processor 110, where the data stream AP_D1 includes display frame data, vertical synchronization information, and horizontal synchronization information. Based on the actual design, the interface circuit 121 can receive the clock signal AP_CLK and the data stream AP_D1 from the processor 110 through MIPI or other interfaces. The interface circuit 121 can sample / latch the data in the data stream AP_D1 based on the clock signal AP_CLK. The data stream AP_D1 includes display frame data AP_D2, vertical synchronization information VSS, and horizontal synchronization information HSS. The interface circuit 121 can unpack the data stream AP_D1 to output the display frame data AP_D2, the vertical synchronization information VSS, and the horizontal synchronization information HSS.

[0043] The synchronization signal generation circuit 122 is coupled to the interface circuit 121 to receive the vertical synchronization information VSS, the horizontal synchronization information HSS, and the external horizontal synchronization signal EXT_HSYNC. In step S220, the synchronization signal generation circuit 122 generates an internal vertical synchronization signal Int_Vs based on the vertical synchronization information VSS and the horizontal synchronization information HSS. In step S230, based on the phase relationship of the vertical synchronization information VSS, the horizontal synchronization information HSS, and the external horizontal synchronization signal EXT_HSYNC, the synchronization signal generation circuit 122 can dynamically determine / update the delay value. In step S240, the synchronization signal generation circuit 122 can delay the external horizontal synchronization signal EXT_HSYNC based on the delay value to generate an internal horizontal synchronization signal Int_Hs.

[0044] The driving circuit 123 is coupled to the interface circuit 121 to receive the display frame data AP_D2. The driving circuit 123 is also coupled to the synchronization signal generation circuit 122 to receive the internal vertical synchronization signal Int_Vs and the internal horizontal synchronization signal Int_Hs. In step S250, the driving circuit 123 can drive the display panel 130 based on the display frame data AP_D2, the internal vertical synchronization signal Int_Vs, and the internal horizontal synchronization signal Int_Hs. The implementation manner of the display panel 130 and the driving details of the display panel 130 are not limited in this embodiment. For example, the display panel 130 can be a well-known display panel or other display panels, and the driving circuit 123 can use a well-known driving method or other driving methods to drive the display panel 130.

[0045] In summary, the display driver integrated circuit 120 generates an internal horizontal synchronization signal Int_Hs by using an external horizontal synchronization signal EXT_HSYNC, and then uses the internal horizontal synchronization signal Int_Hs to drive the display panel 130. In the MIPI video mode, the display driver integrated circuit 120 can count the internal horizontal synchronization signal Int_Hs to know the timing of the next display frame. Therefore, in each display frame of the MIPI video mode, after the processor 110 outputs the valid data of a display frame (including the horizontal synchronization information HSS of 1 frame) to the display driver integrated circuit 120, the processor 110 can pause the data transmission of the data stream (no longer output redundant horizontal synchronization information HSS) until the end of a display frame. Since the processor 110 does not need to output redundant horizontal synchronization information HSS, and the display driver integrated circuit 120 also does not need to receive and process (such as unpacking) redundant horizontal synchronization information HSS, the power consumption can be reduced.

[0046] Figure 3 is a timing / phase schematic diagram of the vertical synchronization information VSS and the external horizontal synchronization signal EXT_HSYNC according to an embodiment of the present invention. Please refer to Figure 1 and Figure 3 , Figure 3 The upper part shows two vertical synchronization time points of the vertical synchronization information VSS, where the vertical line represents the "vertical synchronization time point". The "vertical synchronization time point" can be the time point where the vertical synchronization start (Vertical Sync Start) mark defined by the MIPI specification is located. Figure 3 The lower part shows multiple external synchronization time points of the external horizontal synchronization signal EXT_HSYNC, where the vertical line represents the "external synchronization time point". According to the actual design, in some embodiments, the "external synchronization time point" can be the rising edge time point of the external horizontal synchronization signal EXT_HSYNC. In other embodiments, the "external synchronization time point" can be the falling edge time point of the external horizontal synchronization signal EXT_HSYNC.

[0047] Generally speaking, once the vertical synchronization information VSS and the external horizontal synchronization signal EXT_HSYNC are not aligned, that is, there is a skew, the display driver integrated circuit 120 may not be able to receive the image normally. Figure 3The left part shows that there is a skew1 between the vertical synchronization information VSS and the external horizontal synchronization signal EXT_HSYNC. The display driving integrated circuit 120 needs to process the external horizontal synchronization signal EXT_HSYNC to generate an internal horizontal synchronization signal Int_Hs that matches the vertical synchronization information VSS and the horizontal synchronization information HSS. Based on the internal horizontal synchronization signal Int_Hs that matches the phase of the horizontal synchronization information HSS, the driving circuit 123 can correctly sample / latch the display frame data AP_D2.

[0048] However, due to one or more reasons, the skew between the synchronization information (VSS and HSS) of each display frame and the external horizontal synchronization signal EXT_HSYNC may not be fixed. For example, after the processor 110 performs MIPI frequency hopping, the skew between the synchronization information and the external horizontal synchronization signal EXT_HSYNC may be changed. Or, when the processor 110 performs MIPI mode switching, such as switching between the MIPI command mode and the MIPI video mode, it may also change the skew between the synchronization information and the external horizontal synchronization signal EXT_HSYNC. Or, the interference of electrostatic discharge (ESD) may change the skew between the synchronization information and the external horizontal synchronization signal EXT_HSYNC. Figure 3 The right part shows that there is a skew2 between the vertical synchronization information VSS and the external horizontal synchronization signal EXT_HSYNC. Due to one or more reasons, the skew1 between the synchronization information and the external horizontal synchronization signal EXT_HSYNC in the previous display frame may be different from the skew2 between the synchronization information and the external horizontal synchronization signal EXT_HSYNC in the subsequent display frame. Since the skew between the synchronization information (VSS and HSS) and the external horizontal synchronization signal EXT_HSYNC may not be fixed, even if the display driving integrated circuit 120 has performed compensation based on the skew1, the compensation based on the skew1 may not be applicable to the skew2 in the subsequent display frame.

[0049] Figure 4 It is a timing / phase schematic diagram of the vertical synchronization information VSS, the horizontal synchronization information HSS, the external horizontal synchronization signal EXT_HSYNC, the internal vertical synchronization signal Int_Vs, and the internal horizontal synchronization signal Int_Hs shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 4 , Figure 4The upper part shows the vertical synchronization time points of the vertical synchronization information VSS and the horizontal synchronization time points of the horizontal synchronization information HSS. Among them, the longer vertical lines represent the "vertical synchronization time points" of the vertical synchronization information VSS, and the shorter vertical lines represent the "horizontal synchronization time points" of the horizontal synchronization information HSS. The "vertical synchronization time point" can be the time point where the vertical sync start mark defined by the MIPI specification is located. Figure 4 Shows the vertical synchronization time points VSS1 and VSS2 of the vertical synchronization information VSS, and the vertical synchronization time points VSS1 and VSS2 of the vertical synchronization information VSS define a display frame. The "horizontal synchronization time point" (such as Figure 4 the shown horizontal synchronization time points HSS11 and HSS21) can be the time point where the horizontal sync start mark defined by the MIPI specification is located.

[0050] Figure 4 The middle part shows multiple external synchronization time points of the external horizontal synchronization signal EXT_HSYNC, where the "external synchronization time points" are represented by vertical lines (such as Figure 4 the shown external synchronization time points EHs1 and EHs2). According to the actual design, in some embodiments, the "external synchronization time point" can be the rising edge time point of the external horizontal synchronization signal EXT_HSYNC. In other embodiments, the "external synchronization time point" can be the falling edge time point of the external horizontal synchronization signal EXT_HSYNC. As Figure 3 the related description, due to one or more reasons, there may be a skew between the synchronization information VSS and HSS and the external horizontal synchronization signal EXT_HSYNC, and the skew between the synchronization information VSS and HSS and the external horizontal synchronization signal EXT_HSYNC for each display frame may not be fixed. If the display driving integrated circuit 120 directly uses the external horizontal synchronization signal EXT_HSYNC to sample / latch the display frame data AP_D2, the display driving integrated circuit 120 may sample incorrect data.

[0051] Figure 4The lower part shows the internal vertical synchronization points of the internal vertical synchronization signal Int_Vs and the internal horizontal synchronization points of the internal horizontal synchronization signal Int_Hs, where the longer vertical lines represent the "internal vertical synchronization points" of the internal vertical synchronization signal Int_Vs, and the shorter vertical lines represent the "internal horizontal synchronization points" of the internal horizontal synchronization signal Int_Hs. According to the actual design, in some embodiments, the "internal vertical synchronization points" and the "internal horizontal synchronization points" can be the rising edge points of the internal vertical synchronization signal Int_Vs and the internal horizontal synchronization signal Int_Hs. In other embodiments, the "internal vertical synchronization points" and the "internal horizontal synchronization points" can be the falling edge points of the internal vertical synchronization signal Int_Vs and the internal horizontal synchronization signal Int_Hs.

[0052] The synchronization signal generation circuit 122 can check the synchronization points belonging to the current frame in the vertical synchronization information VSS (e.g., Figure 4 the vertical synchronization point VSS1 shown). After the occurrence of the vertical synchronization point VSS1, the synchronization signal generation circuit 122 can check the first horizontal synchronization point following the vertical synchronization point VSS1 in the external horizontal synchronization signal EXT_HSYNC (e.g., Figure 4 the external synchronization point EHs1 shown), and check the first horizontal synchronization point following the vertical synchronization point VSS1 in the horizontal synchronization information HSS (e.g., Figure 4 the horizontal synchronization point HSS11 shown). The synchronization signal generation circuit 122 can generate the vertical synchronization point IVs1 in the internal vertical synchronization signal Int_Vs based on the horizontal synchronization point HSS11.

[0053] The synchronization signal generation circuit 122 can count the duration TL1 from the external synchronization point EHs1 to the horizontal synchronization point HSS11, and dynamically update the delay value of the current frame based on the duration TL1. Next, the synchronization signal generation circuit 122 can delay the external horizontal synchronization signal EXT_HSYNC based on the updated delay value (the delay value corresponding to the duration TL1) to generate multiple horizontal synchronization points of the current frame in the internal horizontal synchronization signal Int_Hs (e.g., Figure 4 the horizontal synchronization point IHs1 shown). The occurrence of the vertical synchronization point VSS2 indicates the end of the current frame and the start of the next frame.

[0054] Similarly, it can be deduced that the synchronization signal generation circuit 122 can count the duration TL2 from the external synchronization time point EHs2 (the first horizontal synchronization time point following the vertical synchronization time point VSS2 in the external horizontal synchronization signal EXT_HSYNC) to the horizontal synchronization time point HSS21 (the first horizontal synchronization time point following the vertical synchronization time point VSS2 in the horizontal synchronization information HSS), and dynamically update the delay value based on the duration TL2. The synchronization signal generation circuit 122 can generate the vertical synchronization time point IVs2 in the internal vertical synchronization signal Int_Vs based on the horizontal synchronization time point HSS21, and delay the external horizontal synchronization signal EXT_HSYNC based on the updated delay value (the delay value corresponding to the duration TL2) to generate multiple horizontal synchronization time points in the internal horizontal synchronization signal Int_Hs (for example Figure 4 the horizontal synchronization time point IHs2 shown).

[0055] Therefore, the update of the delay value of the current frame is independent of the update of the previous delay value of the previous frame. The display driving integrated circuit 120 can dynamically update the delay value of the internal horizontal synchronization signal Int_Hs based on the phase relationship between the horizontal synchronization information HSS and the external horizontal synchronization signal EXT_HSYNC, so that the phase of the internal horizontal synchronization signal Int_Hs can match the phase of the horizontal synchronization information HSS provided by the processor 110. Based on the internal horizontal synchronization signal Int_Hs with the phase matching the horizontal synchronization information HSS, the driving circuit 123 can correctly sample / latch the display frame data AP_D2.

[0056] However, due to one or more reasons, such as the interference of ESD or other reasons, the MIPI Horizontal Sync Start mark may be lost. For example, the horizontal synchronization time point HSS21 (the horizontal sync start mark) may not exist. Once the horizontal synchronization time point HSS21 does not exist, the duration TL2 counted by the synchronization signal generation circuit 122 will be incorrect. When the duration TL2 exceeds a certain threshold duration, the synchronization signal generation circuit 122 can discard the currently counted duration TL2 and use the previous delay value of the previous frame (for example, the delay value corresponding to the duration TL1) as the delay value of the current frame. The threshold duration can be any real number determined according to the actual design.

[0057] Due to one or more reasons, such as interference from ESD or other reasons, one or more pulses of the external horizontal synchronization signal EXT_HSYNC may be lost. For example, the external synchronization point EHs2 (a pulse of the external horizontal synchronization signal EXT_HSYNC) between the vertical synchronization point VSS2 and the horizontal synchronization point HSS21 may not exist. When the external synchronization point EHs2 does not exist between the vertical synchronization point VSS2 and the horizontal synchronization point HSS21, the synchronization signal generation circuit 122 may use the previous delay value of the previous frame (for example, the delay value corresponding to the duration TL1) as the delay value of the current frame.

[0058] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display driving integrated circuit, characterized in that, The display driving integrated circuit includes: An interface circuit that receives a data stream and an external horizontal synchronization signal from a processor, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information; A synchronization signal generation circuit coupled to the interface circuit to receive the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal, where the synchronization signal generation circuit generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information, the synchronization signal generation circuit dynamically updates a delay value based on the phase relationship of the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal, and the synchronization signal generation circuit delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal; and A driving circuit coupled to the interface circuit to receive the display frame data, and coupled to the synchronization signal generation circuit to receive the internal vertical synchronization signal and the internal horizontal synchronization signal, where the driving circuit drives a display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

2. The display driving integrated circuit according to claim 1, wherein The interface circuit receives the data stream from the processor through a Mobile Industry Processor Interface.

3. The display driving integrated circuit according to claim 1, wherein The synchronization signal generation circuit counts the duration from an external synchronization time point to a horizontal synchronization time point, the external synchronization time point being the first horizontal synchronization time point following a vertical synchronization time point in the external horizontal synchronization signal, the vertical synchronization time point being the synchronization time point of the current frame in the vertical synchronization information, the horizontal synchronization time point being the first horizontal synchronization time point following the vertical synchronization time point in the horizontal synchronization information, and the synchronization signal generation circuit dynamically updates the delay value of the current frame based on the duration.

4. The display driving integrated circuit according to claim 3, characterized in that, In response to the duration exceeding a threshold duration, the synchronization signal generation circuit discards the duration and uses a previous delay value of a previous frame before the current frame as the delay value of the current frame.

5. The display driving integrated circuit according to claim 3, characterized in that, In response to there being no external synchronization time point between the vertical synchronization time point and the horizontal synchronization time point, the synchronization signal generation circuit uses a previous delay value of a previous frame before the current frame as the delay value of the current frame.

6. The display driving integrated circuit according to claim 1, wherein The update of the delay value of the current frame is independent of the update of the previous delay value of a previous frame before the current frame.

7. A method for operating a display driving integrated circuit, characterized in that, The operation method includes: Receiving, by an interface circuit of the display driving integrated circuit, a data stream and an external horizontal synchronization signal from a processor, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information; Generating, by a synchronization signal generation circuit of the display driving integrated circuit, an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information; Dynamically updating, by the synchronization signal generation circuit, a delay value based on the phase relationship of the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal; Delaying, by the synchronization signal generation circuit, the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal; and The driving circuit of the display driving integrated circuit drives the display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

8. The operating method according to claim 7, characterized in that The interface circuit receives the data stream from the processor through the Mobile Industry Processor Interface.

9. The operating method according to claim 7, characterized in that, The operation method further includes: counting the duration from an external synchronization time point to a horizontal synchronization time point, where the external synchronization time point is the first horizontal synchronization time point following the vertical synchronization time point in the external horizontal synchronization signal, the vertical synchronization time point is the synchronization time point of the current frame in the vertical synchronization information, and the horizontal synchronization time point is the first horizontal synchronization time point following the vertical synchronization time point in the horizontal synchronization information; and dynamically updating the delay value of the current frame based on the duration.

10. The operating method according to claim 9, characterized in that, The operation method further includes: in response to the duration exceeding a threshold duration, discarding the duration and using the previous delay value of the previous frame before the current frame as the delay value of the current frame.

11. The operating method according to claim 9, characterized in that, The operation method further includes: in response to there being no external synchronization time point between the vertical synchronization time point and the horizontal synchronization time point, using the previous delay value of the previous frame before the current frame as the delay value of the current frame.

12. The operating method according to claim 7, characterized in that, The update of the delay value of the current frame is independent of the update of the previous delay value of the previous frame before the current frame.

13. A display device, characterized in that, The display device includes: a processor; a display driving integrated circuit, coupled to the processor to receive a data stream and an external horizontal synchronization signal, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information, the display driving integrated circuit generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information, the display driving integrated circuit dynamically updates a delay value based on the phase relationship of the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal, and the display driving integrated circuit delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal; and a display panel, coupled to the display driving integrated circuit, where the display driving integrated circuit drives the display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

14. The display device according to claim 13, wherein The display driving integrated circuit includes: an interface circuit, receiving the data stream and the external horizontal synchronization signal from the processor; a synchronization signal generation circuit, coupled to the interface circuit to receive the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal, where the synchronization signal generation circuit generates the internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information, the synchronization signal generation circuit dynamically updates the delay value based on the phase relationship of the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal, and the synchronization signal generation circuit delays the external horizontal synchronization signal based on the delay value to generate the internal horizontal synchronization signal; and A driving circuit is coupled to the interface circuit to receive the display frame data, and is coupled to the synchronization signal generation circuit to receive the internal vertical synchronization signal and the internal horizontal synchronization signal, wherein the driving circuit drives the display panel based on the display frame data, the internal vertical synchronization signal, and the internal horizontal synchronization signal.

15. The display device according to claim 14, wherein The interface circuit receives the data stream from the processor through a Mobile Industry Processor Interface.

16. The display device according to claim 14, wherein The synchronization signal generation circuit counts the duration from an external synchronization time point to a horizontal synchronization time point, where the external synchronization time point is the first horizontal synchronization time point following a vertical synchronization time point in the external horizontal synchronization signal, the vertical synchronization time point is the synchronization time point of the current frame in the vertical synchronization information, the horizontal synchronization time point is the first horizontal synchronization time point following the vertical synchronization time point in the horizontal synchronization information, and the synchronization signal generation circuit dynamically updates the delay value of the current frame based on the duration.

17. The display device according to claim 16, characterized in that, In response to the duration exceeding a threshold duration, the synchronization signal generation circuit discards the duration and uses the previous delay value of the previous frame before the current frame as the delay value of the current frame.

18. The display device according to claim 16, wherein In response to there being no external synchronization time point between the vertical synchronization time point and the horizontal synchronization time point, the synchronization signal generation circuit uses the previous delay value of the previous frame before the current frame as the delay value of the current frame.

19. The display device according to claim 14, wherein The update of the delay value of the current frame is independent of the update of the previous delay value of the previous frame before the current frame.

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