Display device

Abstract

A display device is disclosed. One aspect of the present disclosure relates to providing a display device capable of supplying an auxiliary voltage to a floating node between a first transistor and a second transistor constituting a pull-up transistor of a gate driver. The display device includes a pixel configured to be connected to a gate line, and a stage configured to output a gate signal to the gate line, in which the stage includes a pull-up transistor disposed between a clock line provided with a gate clock and the gate line, the pull-up transistor including a first transistor and a second transistor connected to each other, and an auxiliary capacitor is connected to a floating node between the first transistor and the second transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0194613, filed on December 28, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] A light - emitting display device is mounted on or provided in an electronic product to display an image, such as a television, a monitor, a laptop computer, a smartphone, a tablet computer, an electronic tablet, a wearable device, a watch phone, a portable information device, a navigation device, or a vehicle control display device, etc.

[0005] The display device may be a liquid - crystal display device or a light - emitting display device, and the display device includes a display panel on which an image is output.

[0006] A gate driver provided in the display panel includes a pull - up transistor connected to a gate line.

[0007] If the pull - up transistor is continuously stressed, the gate pulse output to the gate line may not be normally output, and thus, horizontal banding defects may occur in the display panel. Summary of the invention

[0008] Accordingly, the present disclosure aims to provide a light - emitting display device that substantially eliminates one or more problems due to the limitations and disadvantages of the related art.

[0009] One aspect of the present disclosure relates to providing a display device capable of providing an auxiliary voltage to a floating node between a first transistor and a second transistor of a pull - up transistor constituting a gate driver.

[0010] Additional advantages and features of the present disclosure will be partially set forth in the following description, and will partially become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the present disclosure. The objectives and other advantages of the present disclosure may be realized and attained by the structures particularly pointed out in the written description and the drawings.

[0011] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, there is provided a display device including pixels configured to be connected to gate lines and a stage configured to output a gate signal to the gate lines, wherein the stage includes a pull-up transistor disposed between a clock line provided with a gate clock and the gate lines, the pull-up transistor includes a first transistor and a second transistor connected to each other, and an auxiliary capacitor is connected to a floating node between the first transistor and the second transistor.

[0012] It should be understood that the foregoing summary and the following detailed description of the present disclosure are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings included to provide a further understanding of the present disclosure and incorporated herein and constituting a part of this application illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0014] Figure 1 is an exemplary diagram showing the configuration of a display device according to an embodiment of the present disclosure;

[0015] Figure 2A and 2B is an exemplary diagram showing the structure of a pixel applied to a display device according to an embodiment of the present disclosure;

[0016] Figure 3 is an exemplary diagram showing the structure of a control driver applied to a display device according to an embodiment of the present disclosure;

[0017] Figure 4 is an exemplary diagram showing the structure of a gate driver applied to a display device according to an embodiment of the present disclosure;

[0018] Figure 5 is an exemplary diagram showing the structure of a data driver applied to a display device according to an embodiment of the present disclosure;

[0019] Figure 6 schematically shows Figure 4 the configuration of the stage shown;

[0020] Figure 7 shows Figure 6 the structure of the pull-up transistor shown;

[0021] Figure 8 is an exemplary diagram for explaining the driving principle of a display device according to an embodiment of the present disclosure;

[0022] Figure 9is an exemplary diagram showing signals applied to a display device according to an embodiment of the present disclosure;

[0023] Figure 10 is an exemplary diagram showing the floating node voltage and the Q node voltage of a display device according to an embodiment of the present disclosure; and

[0024] Figure 11 is an exemplary cross-sectional view of a display panel applied to a display device according to an embodiment of the present disclosure. Detailed Description

[0025] Now, reference will be made in detail to exemplary embodiments of the present disclosure, which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0026] The advantages and features of the present disclosure and the method of realizing them will be clarified by the following embodiments described with reference to the drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0027] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and thus, the present disclosure is not limited to the details shown. The same reference numerals always denote the same elements. In the following description, when a detailed description of related known functions or configurations is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. When using "comprising", "having", and "including" described in the present disclosure, another part may be added unless "only" is used. Unless otherwise stated, terms in the singular form may include the plural form.

[0028] When interpreting an element, the element is interpreted as including an error or tolerance range, although such an error or tolerance range is not explicitly described.

[0029] When describing a positional relationship, for example, when the positional relationship between two parts is described as, for example, "on", "above", "below", and "next to", one or more other parts may be provided between the two parts unless more restrictive terms such as "exactly" or "directly" are used.

[0030] When describing a time relationship, for example, when a time sequence is described as, for example, "after", "subsequently", "next", and "before", a discontinuous situation may be included unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0031] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0032] When describing the elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", "(b)", etc. may be used. These terms are intended to identify the corresponding elements from other elements, and the basis, order, or numbering of the corresponding elements should not be limited by these terms. The expressions of an element "connected", "coupled", or "adhered" to another element or layer mean that, unless otherwise specified, the element or layer is not only directly connected or adhered to another element or layer, but also indirectly connected or adhered to another element or layer, and one or more intermediate elements or layers are "disposed" or "inserted" between the element or layer.

[0033] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents a combination of two or more of the first item, the second item, and the third item and all items proposed from the first item, the second item, or the third item.

[0034] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, and can operate differently from each other and be technically driven. The embodiments of the present disclosure can be carried out independently of each other, or can be carried out together in a mutually dependent relationship.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is an exemplary diagram showing the configuration of a display device according to an embodiment of the present disclosure, Figure 2A and 2B is an exemplary diagram showing the structure of a pixel applied to a display device according to an embodiment of the present disclosure, Figure 3 is an exemplary diagram showing the structure of a control driver applied to a display device according to an embodiment of the present disclosure, Figure 4 is an exemplary diagram showing the structure of a gate driver applied to a display device according to an embodiment of the present disclosure, Figure 5 is an exemplary diagram showing the structure of a data driver applied to a display device according to an embodiment of the present disclosure.

[0037] The display device according to an embodiment of the present disclosure can be used as various electronic devices. The electronic device can be, for example, a television, a monitor, etc.

[0038] As Figure 1 , Figure 2A and Figure 2B shown, a display device according to an embodiment of the present disclosure may include a display panel 100, a gate driver 200, a data driver 300, a control driver 400, and a power supply unit 500. The display panel 100 includes a display area DA for displaying an image and a non-display area NDA provided outside the display area DA. The gate driver 200 supplies a gate signal GS to a plurality of gate lines GL1 to GLg provided in the display area DA of the display panel 100. The data driver 300 supplies a data voltage Vdata to a plurality of data lines DL1 to DLd provided in the display area DA of the display panel 100. The control driver 400 controls the driving of the gate driver 200 and the data driver 300. The power supply unit 500 supplies power to the control driver 400, the gate driver 200, the data driver 300, and the display panel 100.

[0039] First, the display panel 100 may include a display area DA and a non-display area NDA. Gate lines GL1 to GLg, data lines DL1 to DLd, and pixels P may be provided in the display area DA. Accordingly, an image may be displayed in the display area DA. Here, g and d are natural numbers. The non-display area NDA may surround the outer periphery of the display area DA.

[0040] When the display device according to an embodiment of the present disclosure is a light-emitting display device, as Figure 2A shown, a pixel P included in the display panel 100 may include a pixel driving circuit PDC and a light-emitting device ED connected to the pixel driving circuit PDC. The pixel driving circuit PDC includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2.

[0041] A first terminal of the driving transistor Tdr may be connected to a first voltage supply line PLA through which a first voltage EVDD is provided, and a second terminal of the driving transistor Tdr may be connected to the light-emitting device ED.

[0042] A first terminal of the switching transistor Tsw1 may be connected to the data line DL, a second terminal of the switching transistor Tsw1 may be connected to the gate of the driving transistor Tdr, and a gate of the switching transistor Tsw1 may be connected to the gate line GL.

[0043] The data voltage Vdata may be provided from the data driver 300 through the data line DL. The gate signal GS may be provided from the gate driver 200 through the gate line GL. The gate signal GS may include a gate pulse GP for turning on the switching transistor Tsw1 (seeFigure 4 ) and a gate cut-off signal for the cut-off switch transistor Tsw1.

[0044] A sense transistor Tsw2 may be provided to measure the threshold voltage of the drive transistor Tdr or the mobility of charges (e.g., electrons), or a reference voltage Vref may be provided to the pixel drive circuit PDC. A first terminal of the sense transistor Tsw2 may be connected to a second terminal of the drive transistor Tdr and the light-emitting device ED, a second terminal of the sense transistor Tsw2 may be connected to the sense line SL, the reference voltage Vref may be provided through the sense line SL, and a gate of the sense transistor Tsw2 may be connected to the sense control line SCL, and a sense control signal SCS may be provided through the sense control line SCL.

[0045] The sense line SL may be connected to the data driver 300 and may be connected to the power supply unit 500 through the data driver 300. For example, the reference voltage Vref provided from the power supply unit 500 may be provided to the pixel through the sense line SL, the sense signal transmitted from the pixel P may be converted into a digital sense signal in the data driver 300, and the digital sense signal may be transmitted to the control driver 400.

[0046] The light-emitting device ED may include a first electrode provided with a first voltage EVDD through the drive transistor Tdr, a second electrode connected to a second voltage supply line PLB through which a second voltage is provided, and a light-emitting layer provided between the first electrode and the second electrode. The first electrode may be an anode and the second electrode may be a cathode.

[0047] When the display device according to an embodiment of the present disclosure is a liquid crystal display device, as Figure 2B shown, the pixel P provided in the display panel 100 may include a pixel drive circuit PDC and a light-emitting unit, the pixel drive circuit PDC includes a switch transistor Tsw1 and a common electrode, and the light-emitting unit includes liquid crystal.

[0048] For example, in Figure 2B , the reference numeral Clc denotes liquid crystal provided between the common electrode and the pixel electrode connected to the switch transistor Tsw1, and the reference numeral Vcom denotes the common voltage provided to the common electrode. That is, the pixel electrode is connected to the switch transistor Tsw1, and the common voltage Vcom is provided to the common electrode.

[0049] In this case, the display device may further include a backlight that outputs light to the display panel 100.

[0050] The structure of the pixel P applied to the display device according to an embodiment of the present disclosure is not limited to Figure 2A and 2BThe structure shown. Therefore, the structure of pixel P can be changed into various shapes.

[0051] The control driver 400 can realign the input image data Ri, Gi, and Bi transmitted from an external system by using the timing synchronization signal TSS (see Figure 3 ), and can generate a data control signal DCS to be provided to the data driver 300 and a gate control signal GCS to be provided to the gate driver 200.

[0052] For this purpose, as Figure 3 shown, the control driver 400 can include a data aligner 430 that realigns the input image data Ri, Gi, and Bi to generate image data Data, a control signal generator 420 that generates the gate control signal GCS and the data control signal DCS by using the timing synchronization signal TSS, an input unit 410 that transmits the timing synchronization signal TSS transmitted from the external system 600 to the control signal generator 420 and transmits the input image data Ri, Gi, and Bi transmitted from the external system 600 to the data aligner 430, and an output unit 440 that provides the image data Data generated by the data aligner 430 and the data control signal DCS generated by the control signal generator 420 to the data driver 300, and provides the gate control signal GCS generated by the control signal generator 420 to the gate driver 200.

[0053] The control signal generator 420 can generate a power control signal PCS to be provided to the power supply unit 500.

[0054] The control driver 400 can also include a storage unit 450 for storing various information. The storage unit 450 can be included in the control driver 400, as Figure 3 shown, but can also be separated from the control driver 400 and set independently.

[0055] The external system 600 can perform the functions of driving the control driver 400 and the electronic device.

[0056] For example, when the electronic device is a television (TV), the external system 600 can receive various sound information, image information, and text information through a communication network, and can transmit the received image information to the control driver 400. For example, the external system 600 can convert the image information into input image data Ri, Gi, and Bi, and transmit the input image data Ri, Gi, and Bi to the control driver 400.

[0057] The power supply unit 500 may generate various electric powers and supply the generated electric powers to the control driver 400, the gate driver 200, the data driver 300, and the display panel 100.

[0058] The gate driver 200 may be directly embedded in the non-display area NDA in the panel in a gate (GIP) type, or the gate driver 200 may be disposed in the display area DA where the pixels P are provided, or the gate driver 200 may be disposed on a film chip scale package mounted in the non-display area NDA.

[0059] The gate driver 200 may supply gate pulses GP1 to GPg to the gate lines GL1 to GLg.

[0060] When a gate pulse GP generated by the gate driver 200 is supplied to the gate of the switching transistor Tsw1 included in the pixel P, the switching transistor Tsw1 may be turned on. When the switching transistor Tsw1 is turned on, a data voltage Vdata supplied through the data line DL may be supplied to the pixel P.

[0061] When a gate cut-off signal generated by the gate driver 200 is supplied to the switching transistor Tsw1, the switching transistor Tsw1 may be turned off. When the switching transistor Tsw1 is turned off, the data voltage cannot be supplied to the pixel P any longer.

[0062] The gate signal GS supplied to the gate line GL may include a gate pulse GP and a gate cut-off signal.

[0063] In order to supply gate pulses GP1 to GPg to the gate lines GL1 to GLg, as Figure 4 shown, the gate driver 200 may include stages ST1 to STg connected to the gate lines GL1 to GLg.

[0064] Each of the stages ST1 to STg may be connected to one gate line GL, but may also be connected to at least two gate lines GL.

[0065] In order to generate gate pulses GP1 to GPg, a gate start signal VST generated by the control signal generator 420 and at least one gate clock GCLK may be transmitted to the gate driver 200. For example, the gate start signal VST and at least one gate clock GCLK may be included in the gate control signal GCS.

[0066] One of the stages ST1 to STg may be driven by the gate start signal VST to output a gate pulse GP to the gate line GL. The gate pulse GP may be generated by the gate clock GCLK.

[0067] At least one of the signals output from the stage ST that outputs the gate pulse can be provided to another stage ST to drive the other stage. Therefore, the gate pulse can be output in the other stage ST. For example, the stages ST can be driven in sequence to sequentially provide the gate pulse GP to the gate lines GL.

[0068] In the following description, when it is necessary to distinguish between the stages, reference numerals ST1 to STg may be used, and when referring to the stages collectively, the reference numeral ST may be used.

[0069] The data driver 300 can provide data voltages Vdata to the data lines DL1 to DLd.

[0070] For this purpose, as Figure 5 shown, the data driver 300 can include a shift register 310 that outputs a sampling signal; a latch 320 that latches the image data Data received from the control driver 400; a digital-to-analog converter 330 that converts the image data Data transmitted from the latch 320 into a data voltage Vdata and outputs the data voltage Vdata; and an output buffer 340 that outputs the data voltage transmitted from the digital-to-analog converter 330 to the data lines DL based on the source output enable signal SOE.

[0071] The shift register 310 can output a sampling signal by using the data control signal DCS received from the control signal generator 420. For example, the data control signal DCS transmitted to the shift register 310 can include a source start pulse SSP and a source shift clock signal SSC.

[0072] The latch 320 can latch the image data Data received sequentially from the control driver 400, and then output the image data Data to the digital-to-analog converter 330 simultaneously based on the sampling signal.

[0073] The digital-to-analog converter 330 can convert the image data Data transmitted from the latch 320 into a data voltage Vdata and output the data voltage Vdata.

[0074] The output buffer 340 can output the data voltage Vdata transmitted from the digital-to-analog converter 330 to the data lines DL1 to DLd of the display panel 100 simultaneously based on the source output enable signal SOE transmitted from the control signal generator 420.

[0075] For this purpose, the output buffer 340 can include a buffer 341 and a switch 342. The buffer 341 stores the data voltage Vdata transmitted from the digital-to-analog converter 330, and the switch 342 outputs the data voltage Vdata stored in the buffer 341 to the data lines DL based on the source output enable signal SOE.

[0076] For example, when the switch 342 is turned on based on the source output enable signal SOE simultaneously provided to the switch 342, the data voltage Vdata stored in the buffer 341 can be provided to the data lines DL1 to DLd through the switch 342.

[0077] The data voltage Vdata provided to the data lines DL1 to DLd can be provided to the pixel P connected to the gate line GL provided with the gate pulse GP.

[0078] Figure 6 is schematically shown Figure 4 an example diagram showing the configuration of the stage shown. For example, Figure 6 the stage shown can be Figure 4 any one of the stages ST1 to STg shown. In the following description, details that are the same as or similar to the details described with reference to Figures 1 to 5 will be omitted or simply described.

[0079] As described above, by using the gate (GIP) type in the panel, the gate driver 200 can be directly embedded in the non-display area NDA or the display area DA.

[0080] In this case, the transistors constituting the gate driver 200 can be provided in the non-display area NDA or the display area by the same process as the transistors provided in the pixel P in the display area DA.

[0081] The gate driver 200 provides the gate pulse GP to the gate lines GL1 to GLg. The gate signal GS can include the gate pulse GP and the gate cut-off signal Goff.

[0082] To provide the gate signal GS to the gate lines GL1 to GLg, the gate driver 200 includes stages ST1 to STg connected to the gate lines GL1 to GLg, as Figure 4 shown. Each of the stages ST1 to STg can be connected to one gate line GL, but can also be connected to at least two gate lines GL.

[0083] Hereinafter, for convenience of description, the gate driver 200 in which each of the stages ST1 to STg is connected to one gate line GL as Figure 4 and 6 shown is described as an example of the gate driver applied to the display device according to an embodiment of the present disclosure.

[0084] The stage ST provided in the gate driver 200 includes a plurality of transistors.

[0085] For example, to describe the schematic configuration of the stage ST, in Figure 6Shown is a stage ST having four transistors Tst, Trs, Tu, and Td as an example of a stage ST applied to a display device according to an embodiment of the present disclosure.

[0086] The start transistor Tst is turned on by a gate start signal VST to supply a first driving voltage VDD to the gate of the pull-up transistor Tu via a circuit unit I and a Q node Q.

[0087] As Figure 6 shown, when the pull-up transistor Tu is an N-type transistor, the first driving voltage VDD can be a voltage higher than a 2a driving voltage VSS1 and a 2b driving voltage VSS2. For example, the first driving voltage VDD can be a voltage having a high level, and the 2a driving voltage VSS1 and the 2b driving voltage VSS2 can be voltages having a low level.

[0088] The gate start signal VST can be a signal transmitted from a control signal generator 420, a gate pulse GP transmitted from a previous stage, or another signal transmitted from a previous stage.

[0089] Here, the previous stage can be a stage directly adjacent to the current stage or a stage spaced apart from the current stage with at least one stage inserted therebetween.

[0090] The pull-up transistor Tu is turned on by the first driving voltage VDD supplied via the start transistor Tst to output a gate clock GCLK to a gate line GL. In this case, a gate pulse GP having a high level, for example, is output to the gate line GL.

[0091] That is, the gate clock GCLK is changed to the gate pulse GP by the pull-up transistor Tu and output to the gate line GL. Therefore, when the pull-up transistor Tu remains in a turned-on state for at least a period corresponding to the pulse width of the gate clock GCLK, the gate pulse GP has the same shape as the gate clock GCLK.

[0092] The switching transistor Tsw1 can be turned on by a gate pulse GP supplied to the gate of the switching transistor Tsw1 provided in a pixel driving circuit PDC.

[0093] When the first driving voltage VDD is supplied to the gate of the pull-up transistor Tu and the pull-up transistor Tu is turned on, a voltage having a low level and supplied to a Qb node of the circuit unit I can be supplied to the gate of the pull-down transistor Td.

[0094] The pull-down transistor Td is turned off by the low-level Qb node voltage supplied to the gate of the pull-down transistor Td. As Figure 6As shown, when the pull-down transistor Td is an N-type transistor, the voltage of the Qb node can be a voltage lower than the first driving voltage VDD. The voltage of the Qb node can be the 2a driving voltage VSS1, but it can also be another voltage provided by the power supply unit 500.

[0095] In the following description, the high level refers to the level that can turn on the N-type transistor as shown Figure 6 and the low level refers to the level that can turn off the N-type transistor as shown Figure 6 .

[0096] As described above, when the first driving voltage VDD with a high level is provided to the gate of the pull-up transistor Tu and the pull-up transistor Tu is turned on, the pull-down transistor Td is turned off by the voltage of the Qb node with a low level.

[0097] Therefore, only the gate pulse GP passing through the pull-up transistor Tu is output to the gate line GL.

[0098] When the start transistor Tst is turned off and the reset transistor Trs is turned on by the reset signal Rest, the 2a driving voltage VSS1 with a low level is provided to the pull-up transistor Tu via the reset transistor Trs and the circuit unit I, so the pull-up transistor Tu is turned off.

[0099] When the 2a driving voltage VSS1 is provided to the gate of the pull-up transistor Tu and the pull-up transistor Tu is turned off, the voltage of the Qb node with a high level provided to the circuit unit I can be provided to the gate of the pull-down transistor Td. The high-level Qb node voltage can be the first driving voltage VDD, but it can also be another voltage provided by the power supply unit 500.

[0100] The pull-down transistor Td is turned on by the high-level Qb node voltage provided to the gate of the pull-down transistor Td.

[0101] When the pull-down transistor Td is turned on by the high-level Qb node voltage, the 2b driving voltage VSS2 with a low level is provided to the gate line GL via the pull-down transistor Td.

[0102] Therefore, the gate cut-off signal Goff with a low level is output to the gate line GL.

[0103] That is, the gate cut-off signal Goff with a low level is output to the gate line GL via the pull-down transistor Td.

[0104] The switching transistor Tsw1 can be turned off by the gate cut-off signal Goff provided to the gate of the switching transistor Tsw1 provided in the pixel driving circuit PDC.

[0105] As described above, when the second a driving voltage VSS1 having a low level is provided to the gate of the pull-up transistor Tu and the pull-up transistor Tu is turned off, the pull-down transistor Td is turned on by the high-level Qb node voltage.

[0106] Therefore, only the gate cut-off signal Goff passing through the pull-down transistor Td is output to the gate line GL.

[0107] Through the above operations, the switching transistor Tsw1 provided in the pixel driving circuit PDC can repeat the on-operation and the off-operation.

[0108] As described above, the stage ST includes a pull-up transistor Tu for outputting a gate pulse GP and a pull-down transistor Td for outputting a gate cut-off signal Goff, and in order to turn on or off the pull-up transistor Tu and turn off or on the pull-down transistor Td, the circuit unit I can be changed into various structures.

[0109] Figure 7 is a diagram showing Figure 6 an example of the structure of the pull-up transistor shown.

[0110] As described above, the pull-up transistor Tu can perform the function of outputting a gate pulse GP, and the pull-down transistor Td can perform the function of outputting a gate cut-off signal Goff.

[0111] In this case, each of the pull-up transistor Tu and the pull-down transistor Td can be composed of one transistor, but as Figure 7 shown, it can also be composed of two transistors connected to each other.

[0112] For example, as Figure 6 and 7 shown, when the pull-up transistor Tu is provided between the gate line GL and the clock line CL supplied with the gate clock GCLK, the pull-up transistor Tu can include a first transistor T1 and a second transistor T2 connected to each other. In this case, the auxiliary capacitor AC can be connected to the floating node FN between the first transistor T1 and the second transistor T2.

[0113] For example, since the pull-up transistor Tu performs a switching function, the pull-up transistor Tu should be turned on or off quickly. This function can be achieved by using a transistor of low-temperature polycrystalline silicon (LTPS).

[0114] Therefore, the pull-up transistor Tu can be formed of LTPS.

[0115] For example, since the charge mobility of a transistor using LTPS is higher than that of amorphous silicon (amorphous silicon, a-Si), a transistor using LTPS can be used as a high-speed switching transistor.

[0116] However, in transistors using LTPS, the leakage current is larger than that of amorphous silicon. That is, generally, when a transistor is turned off, current cannot flow through the transistor. However, in transistors using LTPS, leakage current occurs when the transistor is turned off.

[0117] To prevent such leakage current, a transistor for switching can be formed by using two transistors using LTP.

[0118] Therefore, the pull-up transistor Tu used as a switch uses LTP. In particular, to prevent leakage current, as Figure 7 shown, the pull-up transistor Tu can use two transistors T1 and T2 using LTP.

[0119] In this case, the first terminal of the first transistor T1 can be connected to the clock line CL, the second terminal of the first transistor T1 can be connected to the floating node FN, and the gate of the first transistor T1 can be connected to the Q node Q.

[0120] In addition, the first terminal of the second transistor T2 can be connected to the floating node FN, the second terminal of the second transistor T2 can be connected to the gate line GL, and the gate of the second transistor T2 can be connected to the Q node Q.

[0121] Therefore, the gates of the first transistor T1 and the second transistor T2 can be commonly connected to the Q node Q.

[0122] Due to the above structure, the first transistor T1 and the second transistor T2 can perform the function of the pull-up transistor Tu.

[0123] For example, as described above, when a high-level first drive voltage VDD is provided to the Q node Q, a high-level first drive voltage VDD is also provided to the gates of the first transistor T1 and the second transistor T2.

[0124] In this case, since the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 can be turned on by the high-level first drive voltage VDD.

[0125] When the first transistor T1 and the second transistor T2 are turned on, the gate clock GCLK is provided to the gate line GL via the first transistor T1 and the second transistor T2. In this case, the signal provided to the gate line GL can be the gate pulse GP.

[0126] In addition, as described above, when a low-level 2a drive voltage VSS1 is provided to the Q node Q, a low-level 2a drive voltage VSS1 is also provided to the gates of the first transistor T1 and the second transistor T2.

[0127] In this case, since the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 can be turned off by the low-level second driving voltage VSS1.

[0128] When the first transistor T1 and the second transistor T2 are turned off, the pull-down transistor Td can be turned on. When the pull-down transistor Td is turned on, the second driving voltage VSS2 is provided to the gate line GL via the pull-down transistor Td. At this time, the signal provided to the gate line GL can be a gate cut-off signal Goff.

[0129] The node between the first transistor T1 and the second transistor T2 is referred to as a floating node FN. That is, the floating node FN refers to the node to which the second terminal of the first transistor T1 and the first terminal of the second transistor T2 are connected.

[0130] The auxiliary capacitor AC is connected to the floating node FN.

[0131] For example, the auxiliary capacitor AC is connected between the auxiliary line AL supplied with the auxiliary voltage AV and the floating node FN.

[0132] A direct current voltage (hereinafter referred to as a DC voltage) is used as the auxiliary voltage.

[0133] The auxiliary voltage AV can be the same voltage as the common voltage commonly provided to all the pixels P provided in the display panel 100.

[0134] For example, the auxiliary voltage AV can be the same as the voltage provided to the common electrode provided in the pixel P.

[0135] For additional description, when the display device according to an embodiment of the present disclosure is a liquid crystal display device, as described in the reference Figure 2B The pixel driving circuit PDC is provided with a pixel electrode and a common electrode, and a liquid crystal is disposed between the pixel electrode and the common electrode.

[0136] In this case, the common electrodes provided in all the pixels P can be electrically connected to each other, and the common voltage Vcom can be provided to the common electrodes.

[0137] Therefore, when the display device according to an embodiment of the present disclosure is a liquid crystal display device, the auxiliary voltage AV can be the common voltage Vcom commonly provided to the common electrodes provided in the pixels P.

[0138] In addition, the auxiliary voltage AV can be the same as the voltage provided to the cathode provided in the pixel P.

[0139] In addition, when the display device according to an embodiment of the present disclosure is a light-emitting display device, as described in the reference Figure 2AAs described above, the light-emitting device ED includes an anode, a light-emitting layer, and a cathode.

[0140] In this case, the cathodes provided in all pixels P can be electrically connected to each other, and a cathode voltage can be supplied to the cathodes. That is, the same voltage (cathode voltage) can be supplied to all cathodes.

[0141] Therefore, when the display device according to an embodiment of the present disclosure is a light-emitting display device, the auxiliary voltage AV can be the cathode voltage commonly supplied to the cathodes provided in the pixels P.

[0142] Figure 8 It is an example diagram for explaining the driving principle of the display device according to an embodiment of the present disclosure.

[0143] As described above, the pull-up transistor Tu can be formed using LTPS. In particular, it can be constituted by a first transistor T1 and a second transistor T2 using LTPS. The gates of the first transistor T1 and the second transistor T2 share the Q node Q.

[0144] In this case, as Figure 7 and 8 shown, when a high-level Q node voltage VQ is supplied to the Q node Q and a gate clock GCLK is supplied through the clock line CL, the voltage of the floating node FN (hereinafter, simply referred to as the floating node voltage VFN) rises to the high level of the gate clock GCLK.

[0145] In this case, the high-level Q node voltage VQ is coupled to the floating node voltage VFN and further increases together with the high-level floating node voltage VFN.

[0146] That is, the floating node voltage VFN increases due to the gate clock GCLK supplied through the first transistor T1. Therefore, a high-level gate pulse GP can be output through the gate line GL.

[0147] In this case, the voltage having a high level in the Q node voltage VQ supplied to the Q node Q is a voltage capable of turning on the first transistor T1 and the second transistor T2. In the following description, specifically, the voltage in the Q node voltage VQ capable of turning on the first transistor T1 and the second transistor T2 is referred to as a pull-up pulse PU. For example, as Figure 8 shown, the voltage having a high level in the Q node voltage VQ is referred to as a pull-up pulse PU.

[0148] For example, as Figure 8 shown, the width of the pull-up pulse PU having a high level in the Q node voltage VQ supplied to the Q node Q is greater than the width of the gate clock GCLK.

[0149] In addition, the floating node voltage VFN is caused by the gate clock GCLK. Therefore, Figure 8 the width of the region where the floating node voltage VFN has a high level in Figure 8 is the same as or similar to the width of the gate clock GCLK.

[0150] Therefore, when the width of the gate clock GCLK is 1H, the width of the pull-up pulse PU provided to the Q node Q can be 3H.

[0151] To provide additional description, as Figure 7 and Figure 8 shown, the width of the pull-up pulse PU provided to the Q node Q can be three times the width of the gate clock GCLK.

[0152] For example, if a period corresponding to 1H has elapsed after the pull-up pulse PU is provided to the Q node Q, the gate clock GCLK is provided to the first terminal of the first transistor T1 in 1H.

[0153] In this case, the floating node voltage VFN is coupled to the gate clock GCLK and rises, and the pull-up pulse PU, which is the voltage of the Q node Q, is also coupled to the gate clock GCLK and rises.

[0154] When a period corresponding to 2H has elapsed after the pull-up pulse PU is provided to the Q node Q, the gate clock GCLK is no longer provided. Therefore, the floating node voltage VFN drops to a low level, and the coupled and rising pull-up pulse PU also drops to the original high level.

[0155] When a period corresponding to 3H has elapsed after the pull-up pulse PU is provided to the Q node Q, the pull-up pulse PU is no longer provided to the Q node Q. Here, 1H can be the period during which the gate pulse GP is output, and thus can be the period during which the data voltage provided through the data line DL is provided to the pixel through the switching transistor Tsw1.

[0156] As described above, the pull-up pulse PU can be provided to the Q node Q during 3H.

[0157] In the first period A of the 3H period, only the pull-up pulse PU is provided to the Q node Q.

[0158] In the second period B of the 3H period, the pull-up pulse PU is provided to the Q node Q, and the gate clock GCLK is provided to the first terminal of the first transistor T1. Therefore, the high-level gate clock GCLK is provided to the floating node FN via the first transistor T1. Therefore, the floating node voltage VFN increases to a high level. The high level of the gate clock GCLK can be, for example, 15.5V. Therefore, the floating node voltage VFN can have a value similar to 15.5V.

[0159] In this case, the Q-node voltage VQ can be coupled to the floating-node voltage VFN to further increase.

[0160] In the third period C of the 3H period, the gate clock GCLK is not provided, and only the pull-up pulse PU is provided to the Q-node Q. Therefore, the Q-node voltage VQ returns to its original high level, and the floating-node voltage VFN also returns to the low level LL. Here, the low level LL of the floating-node voltage VFN can be, for example, -4V.

[0161] After passing through the third period C, in the fourth period D, the high-level pull-up pulse PU is not provided to the Q-node Q, and the low-level Q-node voltage VQ is provided to the Q-node Q.

[0162] That is, the Q-node voltage VQ drops from the high level to the low level. Here, the low level of the Q-node voltage VQ can be, for example, -4V.

[0163] The floating-node voltage VFN that has dropped to the low level LL in the third period C can be coupled to the Q-node voltage VQ that drops to the low level in the fourth period D, and can drop to a voltage lower than the low level LL, such as -5.5V.

[0164] Therefore, the difference X between the coupling voltage CV of the floating node FN, which is reduced by coupling to the Q-node Q during the fourth period D, and the low level LL of the floating node can be 1.5V.

[0165] The above process can be repeated once in each frame period (1 frame period), where the gate pulse GP is output to the gate line GL through the pull-up transistor Tu.

[0166] When this process is repeated, for example, the performance of the first terminal serving as the drain of the first transistor T1 may degrade. This phenomenon is called hot carrier stress.

[0167] In particular, in the first transistor T1 using LTPS with a high charge mobility, the above hot carrier stress phenomenon may occur severely.

[0168] For additional description, when the first transistor T1 and the second transistor T2 using LTPS are used as the pull-up transistor Tu, the voltage of the floating node FN between the first transistor T1 and the second transistor T2 can be coupled to the Q-node voltage VQ. Therefore, when the Q-node voltage VQ drops from the high level to the low level, the floating-node voltage VFN can drop to the coupling voltage CV lower than the low level LL.

[0169] The difference between the low level LL in the floating node FN and the coupling voltage CV can form a differential voltage Vgs between the gate and the source of the first transistor T1, and can also form a differential voltage Vgs between the gate and the source of the second transistor T2.

[0170] In this case, hot carrier stress can be generated in the first transistor T1 by the gate clock GCLK continuously supplied to the gate of the first terminal of the first transistor T1. Hot carrier stress can also be generated in the second transistor T2.

[0171] When hot carrier stress is continuously generated in the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor T2 may deteriorate, and thus, the quality of the first transistor T1 and the second transistor T2 may decrease.

[0172] If the quality of the first transistor T1 and the second transistor T2 decreases, the falling period of the gate pulse GP output through the first transistor T1 and the second transistor T2 may be delayed.

[0173] For example, under normal circumstances, the first gate pulse GP1 should be output to the first gate line GL1 in the first stage ST1 during the 1H period, and the second gate pulse GP2 should be output to the second gate line GL2 in the second stage ST1 to STg2 during another 1H period. However, if the quality of the first transistor T1 and the second transistor T2 decreases and the falling period of the first gate pulse GP1 is delayed, the first gate pulse GP1 may remain at the high level during the 2H period.

[0174] Therefore, while the second gate pulse GP2 is supplied to the second gate line GL2, the first gate pulse GP1 may be continuously supplied to the first gate line GL1.

[0175] Therefore, abnormal light may be output from the pixel connected to the first gate line GL1, and due to this abnormal light, horizontal banding defects may occur.

[0176] In addition, the above-mentioned horizontal banding defects are caused by the phenomenon that the floating node voltage VFN is coupled to the Q node voltage that drops to the low level and the coupling voltage CV that drops below the low level LL during the fourth period D.

[0177] Therefore, in the display device according to the embodiment of the present disclosure, in order to prevent the floating node voltage VFN from being coupled to the Q node voltage that drops to the low level and the coupling voltage CV that drops below the low level LL during the fourth period D, an auxiliary capacitor AC is connected to the floating node FN, and a DC voltage can be supplied to the auxiliary capacitor AC.

[0178] Figure 9It is an exemplary diagram showing signals applied to a display device according to an embodiment of the present disclosure. Figure 10 It is an exemplary diagram showing the floating node voltage and Q node voltage of a display device according to an embodiment of the present disclosure. Specifically, Figure 9 It shows a vertical synchronization signal Vsync that defines one frame period (1 frame period) for a display panel to display an image, the Q node voltage VQ in the first stage ST1, the gate clock GCLK provided to the first stage ST1, the floating node voltage VFN of the first stage ST1, the auxiliary voltage AV provided to the auxiliary capacitor AC of the first stage ST1, and the first gate signal GS1 output from the first stage ST1. In Figure 10 it, the solid line represents the Q node voltage VQ, and the dashed line represents the floating node voltage VFN. In addition, in the following description, the gate clock GCLK may represent the signal indicated by Figure 10 GCLK in, but may also only represent the pulse with a high level among the signals indicated by Figure 10 GCLK in.

[0179] Hereinafter, a method of driving a display device according to an embodiment of the present disclosure will be described with reference to Figure 9 and 10 Description.

[0180] In the following description, details that are the same as or similar to those described with reference to Figures 1 to 8 will be omitted or simply described.

[0181] As described above, when the pull-up transistor Tu is provided between the clock line CL provided with the gate clock GCLK and the gate line GL, the pull-up transistor Tu may include a first transistor T1 and a second transistor T2 connected to each other. In this case, the auxiliary capacitor AC may be connected to the floating node FN between the first transistor T1 and the second transistor T2.

[0182] Each of the first transistor T1 and the second transistor T2 may be formed of LTPS.

[0183] In this case, the first terminal of the first transistor T1 may be connected to the clock line CL, the second terminal of the first transistor T1 may be connected to the floating node FN, and the gate of the first transistor T1 may be connected to the Q node Q.

[0184] In addition, the first terminal of the second transistor T2 may be connected to the floating node FN, the second terminal of the second transistor T2 may be connected to the gate line GL, and the gate of the second transistor T2 may be connected to the Q node Q.

[0185] Therefore, the gates of the first transistor T1 and the second transistor T2 may be commonly connected to the Q node Q.

[0186] Due to the above structure, the first transistor T1 and the second transistor T2 can perform the function of the pull-up transistor Tu.

[0187] The auxiliary capacitor AC is connected to the floating node FN.

[0188] For example, the auxiliary capacitor AC is connected between the auxiliary line AL supplied with the auxiliary voltage AV and the floating node FN.

[0189] A DC voltage is used as the auxiliary voltage.

[0190] The auxiliary voltage AV may be the same voltage as the common voltage commonly supplied to all the pixels P provided in the display panel 100.

[0191] For example, the auxiliary voltage AV may be the same as the voltage supplied to the common electrode provided in the pixel P.

[0192] To provide additional description, when the display device according to an embodiment of the present disclosure is a liquid crystal display device, the auxiliary voltage AV may be the common voltage Vcom commonly supplied to the common electrode provided in the pixel P.

[0193] In addition, when the display device according to an embodiment of the present disclosure is a light-emitting display device, the auxiliary voltage AV may be the cathode voltage commonly supplied to the cathode provided in the pixel P.

[0194] In the following description, the voltage with a high level in the Q-node voltage VQ supplied to the Q node Q represents a voltage capable of turning on the first transistor T1 and the second transistor T2, and is referred to as a pull-up pulse PU.

[0195] For example, as Figure 9 shown, the voltage with a high level in the Q-node voltage VQ is referred to as a pull-up pulse PU.

[0196] In addition, the voltage with a low level in the Q-node voltage VQ supplied to the Q node Q represents a voltage capable of turning off the first transistor T1 and the second transistor T2.

[0197] In this case, the low level of the Q-node voltage VQ supplied to the Q node Q may be the same as the low level of the gate clock GCLK. For example, the low level of the Q-node voltage VQ and the low level of the gate clock GCLK may be -4V, as Figure 10 shown.

[0198] In addition, the auxiliary voltage AV supplied to the auxiliary capacitor AC may be equal to the low level of the gate clock GCLK. For example, the auxiliary voltage AV and the low level of the gate clock GCLK may be -4V, as Figure 10 shown.

[0199] That is, in the display device according to an embodiment of the present disclosure, in order to minimize the difference between the low level LL of the floating node FN and the coupling voltage CV, the low level of the Q node voltage VQ, the low level of the gate clock GCLK, and the auxiliary voltage AV can be set equally.

[0200] As Figure 9 shown, the width of the pull-up pulse PU having a high level in the Q node voltage VQ provided to the Q node Q is greater than the width of the gate clock GCLK.

[0201] For example, when the width of the gate clock GCLK is 1H, the width of the pull-up pulse PU provided to the Q node Q can be 3H.

[0202] First, in the first period A of the 3H period, only the pull-up pulse PU is provided to the Q node Q, as Figure 9 and Figure 10 shown.

[0203] In the first period A, since the gate clock GCLK is not provided to the floating node FN, the floating node FN is in a floating state.

[0204] In this case, since the auxiliary voltage AV is provided to the auxiliary capacitor AC connected to the floating node FN, the voltage of the floating node FN can be the auxiliary voltage AV.

[0205] Next, in the second period B of the 3H period, the pull-up pulse PU is provided to the Q node Q, and the gate clock GCLK is provided to the first terminal of the first transistor T1. In this case, the Q node voltage VQ can be coupled to the floating node voltage VFN, and thus can be further increased, as referred to Figure 8 described.

[0206] The gate clock GCLK provided to the first terminal of the first transistor T1 is output to the first gate line GL1 via the floating node FN and the second transistor T2.

[0207] That is, the gate clock GCLK provided in the second period B becomes the first gate pulse GP1 output to the first gate line GL1.

[0208] In this case, since the gate clock GCLK is provided to the floating node FN, the floating node voltage VFN can become the high level of the gate clock GCLK.

[0209] Next, in the third period C of the 3H period, the gate clock GCLK is not provided, and only the pull-up pulse PU is provided to the Q node Q. Therefore, the voltage VQ of the Q node returns to its original high level, as referred to Figure 8As described above, the floating node voltage VFN also returns to the low level LL. Here, the low level LL can be, for example, -4V.

[0210] Next, after the third period C, in the fourth period D, a high-level pull-up pulse PU is not provided to the Q node Q, and a low-level Q node voltage VQ is provided to the Q node Q.

[0211] That is, the Q node voltage VQ drops from the high level to the low level. Here, the low level of the Q node voltage VQ can be, for example, -4V.

[0212] The floating node voltage VFN that has dropped to the low level LL in the third period C can be coupled to the Q node voltage VQ that has dropped to the low level in the fourth period D and can drop to a voltage lower than the low level LL.

[0213] However, an auxiliary capacitor AC provided with an auxiliary voltage AV is connected to the floating node FN.

[0214] The auxiliary capacitor AC can be set to a voltage equal to the low level of the Q node voltage VQ and the low level of the gate clock GCLK.

[0215] Therefore, in the fourth period D, even if the floating node FN is coupled to the Q node voltage VQ, the floating node voltage FN drops less than in the case without the auxiliary capacitor AC.

[0216] For example, when the floating node FN is not connected to the auxiliary capacitor AC, the floating node voltage FN can drop to a level 1.5V lower than the low level LL of the floating node, as referred to Figure 8 described.

[0217] However, in the display device according to an embodiment of the present disclosure, the floating node FN is connected to the auxiliary capacitor AC provided with the auxiliary voltage AC, and thus, even if the floating node FN is coupled to the Q node voltage VQ, the floating node voltage VFN drops to a level less than 1.5V.

[0218] For example, in the fourth period D, the floating node voltage VFN can drop to a level 0.6V less than the low level LL of the floating node, as Figure 10 shown.

[0219] To provide additional description, when there is no auxiliary capacitor AC in the floating node FN, the difference X between the coupling voltage CV of the floating node FN and the low level LL of the floating node in the fourth period D can be 1.5V.

[0220] However, when the auxiliary capacitor AC is connected to the floating node FN and an auxiliary voltage AV having the same level as the low level of the gate clock GCLK is provided to the auxiliary capacitor AC, the difference Y between the coupling voltage CV of the floating node FN and the low level LL of the floating node in the fourth period D may be 0.6V.

[0221] As described above, the hot carrier stress that delays the falling period of the gate pulse by deteriorating the first transistor T1 is caused by the phenomenon that the difference between the low level LL and the coupling voltage CV in the floating node FN increases.

[0222] However, in the display device according to an embodiment of the present disclosure, as described above, compared with the prior art, by the auxiliary voltage AV provided to the auxiliary capacitor AC, the difference between the low level LL and the coupling voltage CV in the floating node FN can be reduced.

[0223] Therefore, the first transistor T1 may not be affected by the hot carrier stress, or may be affected by a smaller hot carrier stress than the prior art.

[0224] Therefore, compared with the prior art, the degree of deterioration of the first transistor T1 can be reduced, and thus, the delay of the falling period of the first gate pulse GP1 can be reduced.

[0225] Since the delay of the falling period of the first gate pulse GP1 is reduced, the first gate pulse GP1 can be provided to the first gate line GL1 only during 1H.

[0226] Therefore, when the second gate pulse GP2 is output from the second stage ST1 to the second gate line GL2 in the third period C, the first gate pulse GP1 is not provided to the first gate line GL1.

[0227] Therefore, the data voltage Vdata to be provided to the pixel P connected to the second gate line GL2 is not provided to the pixel P connected to the first gate line GL1.

[0228] Therefore, horizontal stripe defects do not occur in the display panel 100, and thus an image can be output normally.

[0229] Finally, for example, the gate clock GCLK provided to the first stage ST1 can be provided to the first terminal of the first transistor T1 every 4H. Therefore, in Figure 10 is shown the gate clock GCLK provided to the first terminal of the first transistor T1 3H after the second period B.

[0230] The gate clock GCLK provided in the second period B can be output to the first gate line GL1 through the first transistor T1 and the second transistor T2 turned on by the pull-up pulse PU.

[0231] However, when the gate clock GCLK is supplied to the first terminal of the first transistor T1 after 3H from the second period B, the pull-up pulse PU is not supplied to the Q node Q. Accordingly, the first transistor T1 and the second transistor T2 are not turned on.

[0232] Therefore, the gate clock GCLK supplied to the first terminal of the first transistor T1 after 3H from the second period B is not output to the first gate line GL1.

[0233] Hereinafter, with reference to Figure 11 , a cross-sectional structure of the display panel 10 applied to a display device according to an embodiment of the present disclosure is described, and a method of calculating the capacitance of the auxiliary capacitor AC is described.

[0234] Figure 11 is an exemplary diagram showing a cross-section of a display panel applied to a display device according to an embodiment of the present disclosure. Specifically, it is an exemplary diagram showing a cross-section of a non-display area provided with Figure 7 the pull-up transistor Tu, the floating node FN, and the auxiliary capacitor AC as shown.

[0235] As described above with reference to Figure 6 and Figure 7 , the pull-up transistor Tu includes the first transistor T1 and the second transistor T2, and the auxiliary capacitor AC may be connected to the floating node FN between the first transistor T1 and the second transistor T2.

[0236] For example, as Figure 11 shown, the display panel 100 applied to a display device according to an embodiment of the present disclosure may include a substrate 101, a floating node connection electrode 102 provided on the substrate 101, a buffer layer 103 covering the floating node connection electrode 102, an active layer 104 provided on the buffer layer 103, a gate insulating layer 105 covering the active layer 104, two gate electrodes G and a connection electrode 106 provided on the gate insulating layer 105, a first passivation layer 107 covering the two gate electrodes G and the connection electrode 106, a clock line CL, a gate line GL, and an auxiliary line AL provided on the first passivation layer 107, and a second passivation layer 108 covering the clock line CL, the gate line GL (not shown), and the auxiliary line AL.

[0237] First, the substrate 101 may be any one of a glass substrate, a plastic substrate, a thin film, and a semiconductor substrate.

[0238] Next, the floating node connection electrode 102 may be provided on the substrate 101 and may be the first terminal of the auxiliary capacitor AC. The floating node connection electrode 102 may be formed by using at least one of various metals.

[0239] Next, an active layer 104 is provided on a buffer layer 103 covering the floating node connection electrode 102. The region between two gate electrodes G in the active layer 104 can be a floating node FN.

[0240] A first contact hole is formed in a region of the buffer layer 103 corresponding to the floating node FN, and the floating node FN can be connected to the floating node connection electrode 102 through the first contact hole.

[0241] Next, two gate electrodes G and a connection electrode 106 can be provided on a gate insulating layer 105 covering the active layer 104.

[0242] Figure 7 The first transistor T1 and the second transistor T2 shown in can be formed by two gate electrodes G and the active layer 104.

[0243] The connection electrode 106 is arranged to overlap with the floating node connection electrode 102.

[0244] The connection electrode 106 can be the second terminal of an auxiliary capacitor AC, and the floating node connection electrode 102 can be the first terminal of the auxiliary capacitor AC.

[0245] Next, two gate electrodes G and the connection electrode 106 are covered by a first passivation layer 107, and a clock line CL, a gate line GL, and an auxiliary line AL can be provided on the first passivation layer 107.

[0246] A gate clock GCLK is provided to the clock line CL, and a gate signal GS is output to the gate line GL.

[0247] An auxiliary voltage AV is provided to the auxiliary line AL.

[0248] The auxiliary line AL can be connected to the connection electrode 106 through a second contact hole formed in the first passivation layer 107.

[0249] As described above, the connection electrode 106 overlaps with the floating node connection electrode 102, and the floating node connection electrode 102 is connected to the floating node FN through the first contact hole.

[0250] Therefore, an auxiliary capacitor AC can be formed between the auxiliary line AL and the floating node FN.

[0251] For example, the floating node connection electrode 102, which is the first terminal of the auxiliary capacitor AC, can be connected to the floating node FN through the first contact hole, and the connection electrode 106, which is the second terminal of the auxiliary capacitor AC, can be connected to the auxiliary line AL through the second contact hole.

[0252] Then, the clock line CL, the gate line GL, and the auxiliary line AL can be covered by a second passivation layer 108.

[0253] Finally, when Figure 11 the display panel 100 shown is a liquid crystal display panel, liquid crystal can be provided on the second passivation layer 108. When Figure 11 the display panel 100 shown is a light-emitting display panel, a light-emitting device can be provided on the second passivation layer 108.

[0254] The structure of the display panel 100 applied to the display device according to the embodiments of the present disclosure is not limited to Figure 11 the structure shown and can be changed into various structures.

[0255] In this case, the capacitance of the auxiliary capacitor AC (hereinafter simply referred to as the auxiliary capacitance) can be set through various simulations and tests.

[0256] For example, based on various simulations and tests, the auxiliary capacitance is proportional to the voltage between the gate of the first transistor T1 and the floating node FN (hereinafter simply referred to as the gate-source voltage Vgs).

[0257] The gate-source voltage Vgs can be expressed by Equation 1 below.

[0258] [Equation 1]

[0259]

[0260] In [Equation 1], ΔVg is the difference between the high level and the low level of the gate clock GCLK, Cgs is the capacitance between the gate and the source of the first transistor T1, Cgd is the capacitance between the gate and the drain of the first transistor T1, and C_Floating is the capacitance applied to the floating node FN. In addition, Recovery refers to the period during which the difference X between the coupling voltage CV and the low level LL of the floating node becomes 0. In this case, the difference X between the coupling voltage CV and the low level LL of the floating node has been described with reference to Figure 8 Recovery is proportional to the initial threshold voltage of the first transistor T1.

[0261] Therefore, referring to [Equation 1], as the difference ΔVg between the high level and the low level of the gate clock GCLK increases, the gate-source voltage Vgs increases, and thus the auxiliary capacitance should also increase.

[0262] In addition, as the width of the active layer 104 of the first transistor T1 increases, the gate-source voltage Vgs increases, and thus the auxiliary capacitance should also increase.

[0263] In addition, the initial threshold voltage of the first transistor T1 is proportional to Recovery, and as Recovery increases, the gate-source voltage Vgs increases, and thus the auxiliary capacitance should also increase.

[0264] Therefore, considering the above conditions, the size and capacitance of the auxiliary capacitor AC can be set differently.

[0265] The features of the display device according to an embodiment of the present disclosure are briefly summarized as follows.

[0266] The display device according to an embodiment of the present disclosure includes pixels configured to be connected to gate lines, and stages configured to output gate signals to the gate lines, wherein each stage includes a pull-up transistor provided between a clock line supplied with a gate clock and the gate line, the pull-up transistor includes a first transistor and a second transistor connected to each other, and an auxiliary capacitor is connected to a floating node between the first transistor and the second transistor.

[0267] The gate of the first transistor and the gate of the second transistor are commonly connected to the Q node.

[0268] A first terminal of the first transistor is connected to the clock line, a second terminal of the first transistor is connected to the floating node, a first terminal of the second transistor is connected to the floating node, and a second terminal of the second transistor is connected to the gate line.

[0269] Each of the first transistor and the second transistor is formed of low-temperature polycrystalline silicon (LTPS).

[0270] The auxiliary capacitor is provided between an auxiliary line supplied with an auxiliary voltage and the floating node.

[0271] The auxiliary voltage is a direct current (DC) voltage.

[0272] The auxiliary voltage is the same as the common voltage commonly supplied to the pixels.

[0273] The auxiliary voltage is the same as the voltage supplied to a common electrode provided in the pixel, or the same as the voltage supplied to a cathode provided in the pixel.

[0274] The width of a pull-up pulse having a high level in the Q node voltage supplied to the Q node is greater than the width of the gate clock.

[0275] When the width of the pull-up pulse supplied to the Q node is 3H, the width of the gate clock is 1H.

[0276] The low level of the Q node voltage supplied to the Q node is the same as the low level of the gate clock.

[0277] The auxiliary voltage is the same as the low level of the gate clock.

[0278] The display device according to the present disclosure can be applied to all electronic devices including a display panel. For example, the light-emitting display device according to the present disclosure can be applied to virtual reality (VR) devices, augmented reality (AR) devices, mobile devices, video phones, smart watches, watch phones or wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, car navigation, vehicle display devices, TVs, wallpaper display devices, signage devices, game devices, laptop computers, monitors, cameras, video cameras, and household appliances.

[0279] The display device according to an embodiment of the present disclosure can supply an auxiliary voltage to a floating node between a first transistor and a second transistor of a pull-up transistor constituting a gate driver through an auxiliary capacitor.

[0280] The hot carrier stress applied to the first transistor and the second transistor can be reduced by the auxiliary voltage supplied to the floating node.

[0281] Therefore, the falling delay of the gate pulse output through the pull-up transistor can be reduced.

[0282] Therefore, the display device according to an embodiment of the present disclosure can reduce the horizontal banding defects that appear in the display panel.

[0283] The above features, structures, and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. In addition, the features, structures, and effects described in at least one embodiment of the present disclosure can be achieved by those skilled in the art through combinations or modifications of other embodiments. Therefore, the content related to combinations and modifications should be interpreted as being within the scope of the present disclosure.

[0284] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the present disclosure.

Claims

1. A display device, comprising: a pixel configured to be connected to a gate line; as well as a stage configured to output a gate signal to the gate line, wherein the stage includes a pull-up transistor, the pull-up transistor being arranged between a clock line provided with a gate clock and the gate line, The pull-up transistor includes a first transistor and a second transistor connected to each other, and An auxiliary capacitor is connected to a floating node between the first transistor and the second transistor.

2. The display device according to claim 1, wherein: The gate of the first transistor and the gate of the second transistor are commonly connected to a Q node.

3. The display device according to claim 2, wherein: A first terminal of the first transistor is connected to the clock line, a second terminal of the first transistor connected to the floating node, A first terminal of the second transistor is connected to the floating node, and A second terminal of the second transistor is connected to the gate line.

4. The display device according to claim 1, wherein: Each of the first transistor and the second transistor is formed of low temperature polysilicon (LTPS).

5. The display device according to claim 1, wherein: The auxiliary capacitor is provided between an auxiliary line supplied with an auxiliary voltage and the floating node.

6. The display device according to claim 5, wherein: The auxiliary voltage is a direct current (DC) voltage.

7. The display device according to claim 5, wherein: The auxiliary voltage is the same as a common voltage commonly supplied to the pixels.

8. The display device according to claim 5, wherein: The auxiliary voltage is the same as a voltage supplied to a common electrode provided in the pixel, or the same as a voltage supplied to a cathode provided in the pixel.

9. The display device according to claim 2, wherein: A width of a pull-up pulse having a high level in a Q-node voltage supplied to the Q-node is greater than a width of the gate clock.

10. The display device according to claim 2, wherein: When the width of the pull-up pulse provided to the Q node is 3H, the width of the gate clock is 1H.

11. The display device according to claim 2, wherein: The low level of the Q-node voltage supplied to the Q-node is the same as the low level of the gate clock.

12. The display device according to claim 5, wherein: The auxiliary voltage is the same as a low level of the gate clock.

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