Method for controlling display screen and display driving circuit thereof

Abstract

The invention discloses a method for controlling a display screen and a display driving circuit thereof, the method is used for the display driving circuit, and the display driving circuit is provided with a frame buffer. The method comprises the following steps of: receiving first frame display data, and bypassing the frame buffer to transmit the first frame display data to the display screen; starting timing in a time interval for receiving the first frame display data to determine whether a timeout occurs; receiving a second frame of display data after the timeout occurs; and writing the second frame display data into the frame buffer.

Description

Technical Field

[0001] The present invention relates to a method for controlling a display screen, and more particularly to a method for controlling a display screen in a hybrid mode. Background Art

[0002] In a display system, an Application Processor (AP) can transmit display data to a display driving circuit through a Mobile Industry Processor Interface (MIPI). There are two common transmission modes on the Mobile Industry Processor Interface: command mode and video mode. To obtain the benefits of both the command mode and the video mode simultaneously, the industry has proposed a hybrid mode for the specification of the Mobile Industry Processor Interface, which is equivalent to a combination of the command mode and the video mode.

[0003] In the prior art, a display driving circuit supporting the hybrid mode is required to perform mode switching according to the usage scenario of the display system, and the usage scenario is determined by the application processor. Specifically, the application processor should first determine the usage scenario and then transmit an instruction to notify the display driving circuit to change its operating mode. However, the application processor may not be able to determine the most suitable way of sending images in every usage scenario, so the power-saving effect achieved by the hybrid mode is limited. Summary of the Invention

[0004] Therefore, the main object of the present invention is to provide a method for controlling a display screen supporting a hybrid mode and its related display driving circuit to solve the above problems.

[0005] An embodiment of the present invention discloses a method for controlling a display screen for a display driving circuit having a frame buffer. The method includes the following steps: receiving a first frame of display data and bypassing the frame buffer to transmit the first frame of display data to the display screen; starting timing within a time interval for receiving the first frame of display data to determine whether a timeout occurs; after the timeout occurs, receiving a second frame of display data; and writing the second frame of display data into the frame buffer.

[0006] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen, and the display driving circuit has a frame buffer. The display driving circuit is further configured to receive a first frame of display data, bypass the frame buffer, and transmit the first frame of display data to the display screen; start timing within a time interval for receiving the first frame of display data to determine whether a timeout occurs; after the timeout occurs, receive a second frame of display data; and write the second frame of display data into the frame buffer.

[0007] Another embodiment of the present invention discloses a method for controlling a display screen for a display driving circuit that has a frame buffer. The method includes the following steps: receiving a first frame of display data and writing the first frame of display data into the frame buffer; after receiving the first frame of display data, receiving a second frame of display data without responding to a control signal of the display driving circuit; and bypassing the frame buffer and outputting the second frame of display data to the display screen.

[0008] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen, and the display driving circuit has a frame buffer. The display driving circuit is further configured to receive a first frame of display data and write the first frame of display data into the frame buffer; after receiving the first frame of display data, receive a second frame of display data without responding to a control signal of the display driving circuit; and bypassing the frame buffer and outputting the second frame of display data to the display screen.

[0009] Another embodiment of the present invention discloses a method for controlling a display screen for a display driving circuit that has a frame buffer. The method includes the following steps: receiving a plurality of display data; determining a frequency of the plurality of display data; and based on the frequency, writing the plurality of display data into the frame buffer or bypassing the frame buffer and outputting the plurality of display data to the display screen.

[0010] Another embodiment of the present invention discloses a display driving circuit for controlling a display screen, and the display driving circuit has a frame buffer. The display driving circuit is further configured to receive a plurality of display data; determine a frequency of the plurality of display data; and based on the frequency, write the plurality of display data into the frame buffer or bypassing the frame buffer and outputting the plurality of display data to the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of a display system according to Embodiment 1 of the present invention.

[0012] Figure 2 It is a schematic diagram of a display system for performing display data transmission using a general hybrid mode.

[0013] Figure 3 Waveform diagram of signal transmission between the main processor and the display driver circuit in the general hybrid mode.

[0014] Figure 4 Waveform diagram of signal transmission between the main processor and the display driver circuit in another scenario of the general hybrid mode.

[0015] Figure 5 Schematic diagram of a display system for transmitting display data in the hybrid mode according to an embodiment of the present invention.

[0016] Figure 6 And Figure 7 Waveform diagram of signal transmission between the main processor and the display driver circuit in the hybrid mode according to an embodiment of the present invention.

[0017] Figure 8 Waveform diagram of signal transmission between the main processor and the display driver circuit in the hybrid mode according to another embodiment of the present invention.

[0018] Figure 9 Flowchart of a control process of the display driver circuit according to an embodiment of the present invention.

[0019] Figure 10 Illustrates a detailed implementation manner in which the display driver circuit determines whether to switch to the read / write mode according to the timeout judgment.

[0020] Figure 11 Waveform diagram of signal transmission when the display driver circuit of the embodiment of the present invention switches from the read / write mode to the bypass mode.

[0021] Figure 12 Flowchart of a control process of the display driver circuit according to an embodiment of the present invention.

[0022] Figure 13 Illustrates another implementation manner in which the display driver circuit switches from the read / write mode to the bypass mode.

[0023] Figure 14 Illustrates another implementation manner in which the display driver circuit switches from the bypass mode to the read / write mode.

[0024] Figure 15 Illustrates another alternative embodiment in which the display driver circuit switches from the bypass mode to the command mode.

[0025] Figure 16 Flowchart of a control process according to an embodiment of the present invention.

[0026] Among them, the reference numerals are explained as follows:

[0027] 10, 20, 50 Display system

[0028] 102, 202, 502 Main processors

[0029] 104, 204, 504 Display driver circuits

[0030] 106 Display screen

[0031] 112 Memory

[0032] SI Static indication

[0033] CMD Instruction

[0034] VS Vertical synchronization signal

[0035] HS Horizontal synchronization signal

[0036] VFP Vertical front edge

[0037] VBP Vertical back porch

[0038] 90, 120, 160 Control flows

[0039] Steps 902 - 912, 1202 - 1208, 1602 - 1606

[0040] IMGA, IMGB1, IMGB2, IMGB, Display data

[0041] IMGC, IMGD, IMGE, IMGFTE1, TE2 Control signals

[0042] TLA, TLB Timeout lengths

[0043] VFP_EXT Extended vertical front edge interval Detailed implementation manners

[0044] According to the specification of the Mobile Industry Processor Interface (MIPI), a display driver circuit supporting the command mode includes a frame buffer. When the display driver circuit operates in the command mode, the display data from the Mobile Industry Processor Interface can be first written into the frame buffer and then read out from the frame buffer at an appropriate time point to refresh the panel. The video mode is applied to a display driver circuit that does not include a frame buffer. When the display driver circuit receives display data through the Mobile Industry Processor Interface, it can directly transfer the display data to the display screen for refreshing. In the hybrid mode, the main processor sends images in a manner similar to the video mode, but the display driver circuit can choose to write the received display data into the frame buffer or control the display data to bypass the frame buffer and directly output it to the display screen for refreshing.

[0045] A Low Temperature Polycrystalline Oxide (LTPO) panel supports extremely low frame rates such as 1 Hz. If the display screen directly switches from a high frame rate display of 120 Hz to an extremely low frame rate of 1 Hz, visual effects problems such as screen flickering are likely to occur. Therefore, the Mobile Industry Processor Interface Association has proposed an Adaptive Refresh Panel (ARP) mechanism. By gradually reducing the frequency, the panel refresh can enter the extremely low frame rate from the high frame rate display, which can solve the above visual effects problems and achieve power-saving effects at the same time. Based on the operation of the adaptive refresh panel, when the screen is not updated, the main processor does not actively send images. It only sends images when it receives the control signal transmitted by the display driver circuit. At this time, the display driver circuit can transmit a control signal during the operation of the adaptive refresh panel to instruct the main processor to send images at a specific time point to achieve the purpose of gradually reducing the frequency.

[0046] Generally speaking, the image sending method of the main processor in the hybrid mode is similar to the video mode, but the display driver circuit can choose to write the display data into the frame buffer or control the display data to bypass the frame buffer and be directly transferred to the display screen. Therefore, for the operation of the adaptive refresh panel, the display driver circuit only needs to receive the updated display data from the main processor once and store this display data in the frame buffer. Subsequently, it can use the internal clock to control the display data to be read out from the frame buffer to perform the panel refresh with gradually reduced frequency. The display driver circuit does not need to trigger the main processor to send images multiple times, which can greatly reduce the power consumption of image sending on the Mobile Industry Processor Interface and improve the display efficiency at the same time.

[0047] Figure 1 FIG. 10 is a schematic diagram of a display system 10 according to Embodiment 1 of the present invention. The display system 10 includes a main processor 102, a display driver circuit 104, and a display screen 106. The main processor 102 can be a core processor of the display system 10 and can serve as a video source or video providing unit to provide display data to the display screen 106 for display. In one embodiment, the main processor 102 can be an Application Processor (AP) of a mobile phone or a Central Processing Unit (CPU) of a computer. Those skilled in the art should understand that the main processor mentioned in this specification represents any type of processor or processing device that can control the display operation and be implemented in any way.

[0048] The display driving circuit 104 can be used to process display data and convert the display data into a data voltage for output to the pixels on the display screen 106. In one embodiment, the display driving circuit 104 can be implemented in an integrated circuit (IC) to implement a display driver integrated circuit (DDIC). Those skilled in the art should understand that the display driving circuit mentioned in this specification represents a driving circuit that can be used to drive a display screen and can be implemented in any way.

[0049] Since the display driving circuit 104 supports a hybrid mode, the display driving circuit 104 can include a memory 112 for implementing a frame buffer. Examples of the memory 112 include, but are not limited to, random access memory (RAM).

[0050] The display screen 106 can be any type of display device, which can be an organic light emitting diode (OLED) panel, a liquid crystal display (LCD) panel, or any other panel that can perform display by receiving scan control, but is not limited thereto.

[0051] In an embodiment of the present invention, the display driving circuit 104 supports a hybrid mode, which can selectively write the received display data into the frame buffer in the memory 112, or bypass the frame buffer and transfer it to the display screen 106 for refreshing. The operation of writing the display data into the frame buffer means that the display data can be compressed by an appropriate method first, and then the compressed display data is stored in the memory 112. The operation of transferring the display data to the display screen 106 means that the processing circuit in the display driving circuit 104 can process the display data and convert the display data into a corresponding data voltage, and then the output driving device in the display driving circuit 104 outputs the data voltage to the display screen 106. In this case, neither the display data nor the data voltage needs to be stored in the memory 112.

[0052] Figure 2 FIG. 13 is a schematic diagram of a display system 20 using a general hybrid mode for display data transmission. The display system 20 includes a main processor 202, a display driving circuit 204, and a display screen (omitted in Figure 2For simplicity. The main processor 202 can determine whether the picture to be displayed has more static pictures or more dynamic pictures according to the application scenario (for example, by the logic unit in the main processor 202). Therefore, the transmitter in the main processor 202 can send an instruction CMD carrying a static indication SI to the display driving circuit 204 through the mobile industry processor interface. In this example, it is assumed that the static indication SI being 1 represents a scenario with more static pictures, such as a user interface, a web page, etc.; while the static indication SI being 0 represents a scenario with more dynamic pictures, such as a game, a movie, etc. Then, when the main processor 202 transmits display data to the display driving circuit 204, it can transmit the corresponding static indication SI, so that the display driving circuit 204 can perform appropriate processing on the received display data according to the static indication SI.

[0053] Specifically, the display driving circuit 204 can determine whether it operates in the read / write mode or the bypass mode according to the static indication SI. In the read / write mode, the display driving circuit 204 can write the display data received through the receiver into the frame buffer (which can be implemented in the built-in memory, such as Figure 1 the memory 112 as shown). Therefore, when subsequently updating the picture on the display screen, the display data can be read from the frame buffer for refreshing. In the bypass mode, the display driving circuit 204 can control the received display data to bypass the frame buffer and directly transmit it to the display screen for refreshing.

[0054] As can be seen from the above, the main processor 202 can use the upper-layer logic unit to determine the value of the static indication SI. Among them, the upper layer can first perform the judgment of the operation mode before performing image processing and generating the output display data at the graphics layer. For example, the algorithm of the main processor 202 can determine which type of application program (app) the mobile phone is about to enter, and judge the attribute of the picture content that this application program may display, and then instruct the main processor 202 to enter which mode (such as the static mode or the dynamic mode). The main processor 202 can also correspondingly transmit the static indication SI to the display driving circuit 204 to instruct the display driving circuit 204 to enter the read / write mode or the bypass mode. When this application program is running, the main processor 202 and the display driving circuit 204 are set to continuously operate in the predetermined mode and cannot be dynamically switched.

[0055] However, an application may not be entirely dynamic or entirely static, but only one of the operation modes can be selected for this application, resulting in limited benefits of the hybrid mode. Additionally, mobile phone manufacturers may not be able to correctly identify the attributes of each application and select the correct operation mode. For example, the main processor 202 may default to operating in the static mode when it cannot determine the application attributes. However, if the application has more dynamic screens but the display driver circuit 204 is instructed to operate in the read / write mode, the display driver circuit 204 still needs to perform a large number of read / write operations, resulting in a significant amount of power consumption.

[0056] Figure 3 FIG. 4 is a waveform diagram of signal transmission between the main processor 202 and the display driver circuit 204 in a general hybrid mode, which shows a vertical synchronization signal VS, a horizontal synchronization signal HS, and display data transmitted through the Mobile Industry Processor Interface. In addition, for ease of explanation, the operation modes of the main processor 202 and the display driver circuit 204, as well as the operations of the display screen and the frame buffer, are also shown in Figure 3 .

[0057] First, the main processor 202 is in the static mode and may be displaying a static screen, such as a background screen. Correspondingly, the display driver circuit 204 operates in the read / write mode and enables the frame buffer to store the previously received display data. At this time, the main processor 202 does not need to transmit the display data and the vertical synchronization signal VS to the display driver circuit 204. Instead, the display driver circuit 204 reads the frame buffer through an internal clock to output the display data to the display screen for refreshing. It should be noted that the horizontal synchronization signal HS can be a signal used by the display driver circuit 204 to synchronize various display operations. This signal can be received from the main processor 202 through the Mobile Industry Processor Interface or a General Purpose Output (GPO) interface, or generated internally by the display driver circuit 204.

[0058] In one embodiment, in the read / write mode, to meet the visual effect requirements under the adaptive refresh panel operation, the display driver circuit 204 can gradually reduce the refresh rate in a sequential frequency reduction manner, for example, gradually adjusting from 120 Hz to 1 Hz. Therefore, the display data used for refreshing can be read out from the frame buffer in a sequential frequency reduction manner.

[0059] When the user starts a certain application, triggering the main processor 202 to enter the dynamic mode, the main processor 202 can start continuously transmitting the vertical synchronization signal VS and display data to the display driving circuit 204. At the same time, the main processor 202 transmits an instruction CMD including a static indication SI to the display driving circuit 204 to instruct the display driving circuit 204 to enter the bypass mode. The instruction CMD can be transmitted through the vertical front porch (VFP) on the display data channel of the mobile industry processor interface, but is not limited to this. In the bypass mode, the display driving circuit 204 can control the received display data to bypass the frame buffer and directly transmit it to the display screen. The display driving circuit 204 continuously receives display data from the main processor 202 to refresh the panel, and deactivates the read and write functions of the frame buffer.

[0060] In Figure 3 the example, the operation mode of the display driving circuit 204 is completely controlled by the main processor 202 through the instruction CMD. That is to say, after the display driving circuit 204 enters the bypass mode due to receiving the instruction CMD from the main processor 202, it cannot leave the bypass mode by itself until it receives another instruction. In this case, the display driving circuit 204 must continuously refresh the display screen through the latest received display data. This display data is not stored in the frame buffer, and the mobile industry processor interface needs to continuously transmit display data from the main processor 202 to the display driving circuit 204, resulting in inevitable power consumption on the mobile industry processor interface.

[0061] Figure 4 FIG. is a waveform diagram of signal transmission between the main processor 202 and the display driving circuit 204 in another scenario of the general hybrid mode. Among them, the main processor 202 switches from the dynamic mode to the static mode and transmits an instruction CMD including a static indication SI to the display driving circuit 204 to instruct the display driving circuit 204 to enter the read / write mode from the bypass mode.

[0062] In the dynamic mode, the main processor 202 continuously transmits high-speed display data, for example, at a frame rate of 120 Hz. The display driver circuit 204 in the bypass mode can bypass the frame buffer to transfer the display data to the display screen for refreshing. When the display driver circuit 204 receives an instruction CMD that includes a static indication SI indicating the start of a static picture, it enters the read-write mode. In the read-write mode, the frame buffer of the display driver circuit 204 is continuously enabled, and as long as the main processor 202 transmits any display data through the mobile industry processor interface, the display driver circuit 204 will write the display data into the frame buffer. Since the display driver circuit 204 only switches modes based on the static indication SI from the main processor 202, in the case where no relevant instruction is received and the main processor 202 continuously transmits pictures, it will cause a large amount of power consumption for the read-write operations of the frame buffer.

[0063] Generally speaking, to save storage space, the display data needs to be compressed before being written into the frame buffer, and the operation of reading the display data from the frame buffer requires corresponding decompression. The compression / decompression operations require a large amount of computation and thus consume a large amount of power. For example, Figure 4 there are some periods during which the main processor 202 outputs high-speed display data but the display driver circuit 204 is in the read-write mode and performs read-write operations. In contrast, if the display data from the mobile industry processor interface can bypass the frame buffer and be directly transferred to the display screen for refreshing, a large amount of power consumption for the read-write operations can be saved, especially when the main processor 202 continuously transmits pictures.

[0064] Figure 5 FIG. is a schematic diagram of transmitting display data by a display system 50 adopting a hybrid mode according to an embodiment of the present invention. The display system 50 includes a main processor 502, a display driver circuit 504, and a display screen (omitted in Figure 5 for simplicity). Different from Figure 2 the operation mode, in this example, the main processor 502 does not need to judge the usage scenario or change the operation mode, nor does it need to transmit the static indication SI and the relevant instruction CMD to the display driver circuit 504. The display driver circuit 504 can judge and automatically switch the operation mode according to the frame rate of the display data from the main processor 502. In any usage scenario or situation, the display driver circuit 504 can judge the picture transmission frequency of the main processor 502 according to the display data received through the mobile industry processor interface, and accordingly decide whether it should switch to the read-write mode or the bypass mode.

[0065] For example, when the display driving circuit 504 receives display data at a high frequency, it can be determined that the main processor 502 sends images at a high frame rate, which means that the image sending frequency may be higher than a first critical value. At this time, the display driving circuit 504 can enter the bypass mode to bypass the frame buffer and directly output the display data to the display screen, thereby reducing the number of read and write operations of the frame buffer. The reduction of read and write operations can further reduce the power consumption required by the memory. When the display driving circuit 504 receives display data at a low frequency, it can be determined that the main processor 502 sends images at a low frame rate, which means that the image sending frequency may be lower than a second critical value (which may be the same as or different from the first critical value). At this time, the display driving circuit 504 can enter the read / write mode and write the received display data into the frame buffer, and then read the display data from the frame buffer at an appropriate time point for panel refreshing (e.g., through the control of an internal clock), thereby reducing the power consumption incurred by the Mobile Industry Processor Interface (MIPI) in sending images.

[0066] In one embodiment, the display driving circuit 504 can use a timer or a timeout counter to determine the image sending frequency of the main processor 502. As long as the image sending frequency drops to a specific critical value, a timeout can be triggered. At this time, the display driving circuit 504 can enter the read / write mode.

[0067] For the main processor 502, it only needs to send images at a variable frame rate according to the content of the display screen. That is, for dynamic images (such as when playing a movie), the main processor 502 can continuously update the display data at a high frame rate; for static images, the main processor 502 does not transmit the display data or only transmits a small amount of display data. The main processor 502 does not need to judge whether the transmitted image is a dynamic image or a static image in the upper-level logic unit, and the main processor 502 does not need to judge which scenario the application program that the user wants to start belongs to. Therefore, in any scenario, the main processor 502 only needs to send images according to a predetermined timing sequence, so there is no dynamic mode or static mode. In addition, the main processor 502 does not need to send an instruction CMD or a static indication SI to notify the display driving circuit 504 to change the operation mode. The display driving circuit 504 can switch between the read / write mode and the bypass mode by itself without receiving any instruction indication from the main processor 502.

[0068] The main processor and the display driving circuit in the following embodiments can be Figure 5 the main processor 502 and the display driving circuit 504 in the display system 50, and / or Figure 1 the main processor 102 and the display driving circuit 104 in the display system 10, but not limited thereto.

[0069] Figure 6This is a waveform diagram of signal transmission between the main processor and the display driver circuit in the hybrid mode of an embodiment of the present invention, which shows the waveforms of a vertical synchronization signal VS, a horizontal synchronization signal HS, and display data, the operation mode of the display driver circuit, and the operations of panel refreshing and frame buffer.

[0070] First, assume that the display system is playing an animation at a high refresh rate. At this time, the main processor continuously outputs display data at a high frequency using the Mobile Industry Processor Interface. Since the display driver circuit receives continuous full-speed display data transmitted by the main processor plus the vertical synchronization signal VS, it can operate in the bypass mode to disable / bypass the frame buffer, and the display driver circuit continuously refreshes the display screen according to a series of display data from the main processor. More specifically, both the read and write functions of the frame buffer included in the display driver circuit are disabled. In this case, the display driver circuit can control the display data to bypass the frame buffer and directly transfer the display data to the display screen for refreshing.

[0071] After the animation is played, the main processor no longer actively updates the screen and stops transmitting display data. At this time, the main processor can gradually reduce the image transmission frequency by, for example, sequential downclocking. When the image transmission frequency drops below a certain level, the display driver circuit can leave the bypass mode and enter the read / write mode to write the subsequent received display data into the frame buffer.

[0072] The display driver circuit can perform mode switching by timing. In one embodiment, the display driver circuit can start timing within each time interval for receiving a frame of display data. For example, the display driver circuit can start timing each time it receives the vertical synchronization signal VS from the main processor, where the vertical synchronization signal VS indicates the start of a time interval for transmitting a frame of display data. The display driver circuit can also set a timeout length to determine whether a timeout occurs based on the timing result. When it is determined that a timeout occurs, which means that no vertical synchronization signal VS has been received within a predetermined period exceeding the timeout length, the display driver circuit can leave the bypass mode and enter the read / write mode. The occurrence of a timeout represents that the main processor has not actively updated the screen for a period of time, indicating that the image transmission frequency of the main processor has dropped below a certain level. For example, the display driver circuit can set the timeout length to an appropriate value so that the display driver circuit is expected to enter the read / write mode when the output frequency of the vertical synchronization signal VS drops below 20 Hz, indicating that the image transmission frequency of the main processor has dropped below 20 Hz.

[0073] Through the above timeout mechanism, the display driver circuit does not need to receive any instructions from the main processor to indicate whether it enters the read / write mode. According to the frame rate or frequency of the received display data, the display driver circuit can leave the bypass mode and enter the read / write mode.

[0074] The above timing scheme for determining whether timeout occurs can be implemented in any way. In one embodiment, a timeout counter can be used to calculate the number of consecutive horizontal synchronization signals HS received after the display driving circuit receives the vertical synchronization signal VS, so as to determine whether timeout occurs. Therefore, when the accumulated number of horizontal synchronization signals HS exceeds a certain specific value, it means that the display driving circuit determines that timeout has occurred, and thus enters the read / write mode.

[0075] After the display driving circuit enters the read / write mode, the display screen can be refreshed by reading the display data in the frame buffer. As Figure 6 shown, the display driving circuit can refresh the display screen at a gradually decreasing refresh rate, for example, gradually decreasing from 120Hz to 1Hz. Therefore, in the case where the main processor does not update the screen, the display driving circuit can read the display data from the frame buffer at a gradually decreasing refresh rate to save the power consumption generated by data transmission of the Mobile Industry Processor Interface.

[0076] Next, when the main processor wants to update the displayed screen and the display driving circuit is in the read / write mode, the main processor will start continuously transmitting the updated display data. When the display driving circuit receives the continuously transmitted updated display data from the main processor, it can automatically return to the bypass mode. Similarly, the display driving circuit completely judges according to the way the main processor sends the picture, so it does not need to receive an additional command CMD or static indication SI from the main processor to indicate whether it enters the bypass mode.

[0077] Figure 7 shows a picture sending scenario similar to Figure 4 but adopting the mode switching method of the present invention. In Figure 4 , regardless of how the main processor sends the picture, the display driving circuit only switches the operation mode by identifying the command CMD and static indication SI from the main processor. In contrast, in Figure 7 , when the main processor continuously changes the picture sending frequency, the display driving circuit can correspondingly adjust to the read / write mode or bypass mode to process the display data in the most efficient way and achieve the most optimized power saving.

[0078] Figure 8 FIG. is a waveform diagram of signal transmission between the main processor and the display driving circuit in the hybrid mode of the embodiment of the present invention, which illustrates the detailed operation method of the display driving circuit for mode switching. Figure 9 FIG. is a flowchart of a control process 90 of the display driving circuit, which corresponds to the waveform of Figure 8 . As Figure 9 shown, the control process 90 includes the following steps:

[0079] Step 902: Receive a first frame of display data IMGB1, bypass the frame buffer, and use the display data IMGB1 to refresh the display screen.

[0080] Step 904: Start timing within a time interval for receiving the display data IMGB1 to determine whether a timeout occurs.

[0081] Step 906: When it is determined that a timeout occurs, output a control signal TE2 to instruct the main processor to transfer a second frame of display data IMGB2 to the display driver circuit.

[0082] Step 908: Receive the vertical synchronization signal VS in response to the control signal TE2.

[0083] Step 910: Exit the bypass mode and enter the read / write mode.

[0084] Step 912: Receive the display data IMGB2 during the frame defined by the vertical synchronization signal VS.

[0085] And write the display data IMGB2 into the frame buffer.

[0086] Please refer to Figure 8 the waveform matching Figure 9 For the control flow 90 of, the display driver circuit is initially in the bypass mode, which can transfer display data (such as IMGA, IMGB1, …) from the main processor to the display screen for refreshing and bypass the frame buffer. The display channel also includes a vertical front porch (VFP) and a vertical back porch (VBP) as blank intervals where no display data is transmitted. The display driver circuit can time within each frame and perform timeout detection. When the display driver circuit does not receive the vertical synchronization signal VS (and display data) from the main processor for a period of time, it can be determined that the main processor's image transfer frequency has dropped below a specific threshold and a timeout has occurred. As described above, the timeout length can be set to a suitable value. In this example, the timeout length is equal to TLA, which is the threshold value in the context for triggering the display driver circuit to switch from the bypass mode to the read / write mode. If the timing time reaches the timeout length TLA but no updated screen is received, it can be determined that a timeout has occurred. At this time, the display driver circuit can enter the read / write mode from the bypass mode and transmit the control signal TE2 to the main processor.

[0087] The main processor can transmit a vertical synchronization signal VS and display data (such as IMGB2) to the display driving circuit in response to the control signal TE2. Since the display driving circuit has entered the read / write mode, it can write the display data IMGB2 into the frame buffer. Generally speaking, the display data IMGB2 output according to the trigger of the control signal TE2 does not actively update the screen, so the screen content of the display data IMGB2 is the same as the screen content of the display data IMGB1 (for example, both are IMGB, as Figure 8 shown).

[0088] It should be noted that the main processor supports variable frame rate, and the frequency of the multi-frame display data continuously transmitted by it is variable, and the variable frame rate can be implemented in any way. For example, the main processor can reduce the image transmission frequency by extending the vertical front interval, and different vertical front lengths can correspond to different frame rates. As Figure 8 shown, the extended vertical front interval is represented by VFP_EXT.

[0089] According to the specification of the Mobile Industry Processor Interface, communication between the display driving circuit and the main processor needs to be carried out through a control signal TE1. The display driving circuit can transmit the control signal TE1 to the main processor to indicate whether the main processor is allowed to draw a picture at the current time. In this example, the control signal TE1 can be implemented by a control port connected between the main processor and the display driving circuit. When the control port is at a high level, it represents the writable state, and when it is at a low level, it represents the non-writable state. For example, when the display driving circuit reads (decompresses) the display data from the frame buffer to refresh the display screen, it will pull the control signal TE1 low to inform the main processor that it cannot draw a picture at this time. In addition, when the display driving circuit receives the vertical synchronization signal VS and starts to receive and process the display data from the main processor, it will also pull the control signal TE1 low until the display data reception is completed. Therefore, for the switching in the hybrid mode, the display driving circuit can use the additional control signal TE2 to communicate with the main processor to indicate the main processor to transmit a picture at the appropriate time point. In one embodiment, the control signal TE2 can be a control port connected between the main processor and the display driving circuit, such as a general-purpose output port. In one embodiment, this control port is usually at a low level. When the display driving circuit wants to transmit the control signal TE2, it can pull this control port to a high level to generate a signal pulse.

[0090] The purpose of the transfer control signal TE2 instructing the main processor to send a picture is that in the bypass mode, the display driver circuit directly transfers the display data to the display screen for refreshing without updating the data stored in the frame buffer. Therefore, when the display driver circuit enters the read / write mode from the bypass mode, the data stored in the frame buffer may be older display data. At this time, the display driver circuit needs to trigger the main processor to transfer a new set of display data to update the frame buffer, so as to ensure that the subsequent display data read from the frame buffer is correct. As described above, since the main processor has stopped updating the picture content, the display data transferred in response to the control signal TE2 is still the same as the previously transferred display data.

[0091] It should be noted that the implementation of using the general-purpose output port to transfer the control signal TE2 is only one exemplary embodiment of the present invention. In fact, the display driver circuit can transfer the control signal TE2 to the main processor in any way. In other embodiments, the control signal TE2 can be transferred through any interface connected between the main processor and the display driver circuit, such as an Inter-Integrated Circuit Interface (I2C Interface), a Serial Peripheral Interface (SPI), or a Mobile Industry Processor Interface, etc., but not limited thereto.

[0092] Figure 10 A detailed implementation of the display driver circuit determining whether to switch to the read / write mode based on timeout judgment is shown. As described above, the display driver circuit can start timing (such as through a timeout counter or timer) every time it receives the vertical synchronization signal VS. As Figure 10 shown, during the frame corresponding to the display data IMGB, the display driver circuit receives the vertical synchronization signal VS of the next frame of display data IMGC before the timeout occurs, that is, the timing time does not exceed the timeout length TLA. Therefore, the display driver circuit can determine that no timeout has occurred and stay in the bypass mode, so that the received display data IMGC bypasses the frame buffer and is output to the display screen. Then, during the frame corresponding to the display data IMGC, since the picture sending frequency of the main processor slows down, the display driver circuit determines that a timeout has occurred and executes a series of steps to enter the read / write mode, and instructs the main processor to send a picture through the control signal TE2. Subsequently, the received display data IMGD can be written into the frame buffer. For the detailed operation method of mode switching, please refer to the above description about Figure 8 and Figure 9 , which will not be elaborated here.

[0093] Figure 11 This is a waveform diagram of the signal transmission when the display driver circuit of the embodiment of the present invention switches from the read / write mode to the bypass mode.Figure 12 It is a flowchart of a control process 120 of a display driving circuit, corresponding to Figure 11 the waveform of. As Figure 12 shown, the control process 120 includes the following steps:

[0094] Step 1202: Receive a first frame of display data IMGB and write the display data IMGB into the frame buffer.

[0095] Step 1204: Receive the vertical synchronization signal VS without responding to a control signal of the display driving circuit.

[0096] Step 1206: Exit the read / write mode and enter the bypass mode.

[0097] Step 1208: Receive a second frame of display data IMGC during the frame defined by the vertical synchronization signal VS, and bypass the frame buffer with the display data IMGC to refresh the display screen.

[0098] Please refer to Figure 11 the waveform of Figure 12 and the control process 120 of

[0099] . Initially, the display driving circuit is in the read / write mode. At this time, the main processor does not update the screen and does not transmit new display data. Therefore, the display driving circuit reads the previously received display data IMGB from the frame buffer to perform a lower-frequency refresh of the display screen. In an exemplary embodiment, the display driving circuit can read the display data from the frame buffer in a sequential frequency-down manner to refresh the display screen.

[0100] Subsequently, the display driving circuit receives a vertical synchronization signal VS from the main processor, and the received vertical synchronization signal VS does not respond to the control signal TE2 of the display driving circuit, indicating that the main processor starts to actively send images through the Mobile Industry Processor Interface. At this time, the display driving circuit can determine that the main processor is about to start updating the screen and automatically switches from the read / write mode to the bypass mode. Then, the display driving circuit receives the display data IMGC during the frame defined by this vertical synchronization signal VS, and bypasses the frame buffer with the display data IMGC and outputs it to the display screen for refreshing. In fact, when the display driving circuit enters the bypass mode, it can bypass the frame buffer with the received display data and directly transmit it to the display screen until the display driving circuit returns to the read / write mode. It should be noted that since the screen content has been updated, there are at least partial differences or the entire surface is different in the received display data (such as IMGC, IMGD, IMGE...).

[0100] Thus, in addition to transmitting the vertical synchronization signal VS, the horizontal synchronization signal HS, and the display data, the main processor does not need to transmit other instructions or static indications to the display driving circuit. The display driving circuit only needs to determine whether to switch to the bypass mode according to the image-sending behavior of the main processor.

[0101] It should be noted that the main purpose of the present invention is to propose a timing control mechanism for switching a display driving circuit between a read / write mode and a bypass mode when the display system operates in a hybrid mode of a mobile industry processor interface. Those skilled in the art can make modifications or variations accordingly, and are not limited thereto. For example, Figure 8 or Figure 10 The timing of is only one implementation manner for the display driving circuit to switch from the bypass mode to the read / write mode, and Figure 11 The timing of is only one implementation manner for the display driving circuit to switch from the read / write mode to the bypass mode. Under the display architecture of the hybrid mode, the display control timing of the present invention can be adjusted or varied in multiple different aspects, and all of them should fall within the scope of the present invention.

[0102] Figure 13 Another implementation manner for the display driving circuit to switch from the read / write mode to the bypass mode is shown. In this example, when the display driving circuit in the read / write mode receives the vertical synchronization signal VS, it does not directly enter the bypass mode, but further determines whether the main processor continues to transmit new images, and / or determines the subsequent image transmission frequency of the main processor. If the main processor still transmits images at a lower frequency subsequently, the display driving circuit may determine that the power saving efficiency of refreshing the display data through the frame buffer is better, and thus remains in the read / write mode and performs read / write operations on the frame buffer for panel refreshing; conversely, if the main processor transmits display data at a faster frequency, the display driving circuit then switches to the bypass mode.

[0103] As Figure 13 shown, when the display driving circuit receives the vertical synchronization signal VS and its corresponding display data, it can start timing within the frame period and perform an overtime judgment. Similarly, the overtime length can be set according to system requirements. In this example, the set overtime length is equal to TLB, which is a critical value in the situation for triggering the display driving circuit to switch from the read / write mode to the bypass mode. If the timing time reaches the overtime length TLB but the next display data is not received, it can be determined that an overtime has occurred.

[0104] During the period of the frame corresponding to the display data IMGC, the display driving circuit does not receive the vertical synchronization signal VS of the next image frame before timeout occurs. Therefore, the display driving circuit determines that the main processor transmits the display data at a slower frequency (i.e., its image transmission frequency is lower than a specific threshold). Therefore, when the display driving circuit receives the next frame of display data IMGD after timeout, it can stay in the read / write mode and write the display data IMGD into the frame buffer. Then, during the period of the frame corresponding to the display data IMGD, the display driving circuit receives the vertical synchronization signal VS of the next frame of display data IMGE before timeout occurs (i.e., the timing time does not reach the timeout length TLB). Therefore, the display driving circuit can determine that the display data IMGE is received at a frequency greater than a specific threshold, and thus determines that the main processor is about to start high-speed image transmission. In this case, the display driving circuit can switch to the bypass mode.

[0105] In another embodiment, after the display driving circuit in the bypass mode enters the read / write mode due to the trigger of timeout, the display driving circuit does not output the control signal TE2 to instruct the main processor to transmit the image, but continues to wait until the main processor wants to update the screen content and actively transmits new display data to the display driving circuit, and then writes this new display data into the frame buffer. After the display driving circuit receives the new display data, it can update the frame buffer with this new display data and read the display data from the frame buffer to initiate subsequent panel refresh operations.

[0106] For example, as Figure 14 shown, after the display driving circuit receives the display data IMGB, it can enter the read / write mode from the bypass mode when timeout occurs. At this time, the display driving circuit does not transmit the control signal TE2, but waits for the reception of the next frame of display data IMGC, and writes the display data IMGC into the frame buffer, and then reads the display data IMGC from the frame buffer to refresh the display screen. Depending on whether the main processor updates the screen, the display data IMGC may be the same as or different from the display data IMGB. The control port for the control signal TE2 is omitted in this example.

[0107] Figure 15 Another alternative embodiment is shown. To further enhance the power-saving effect, the main processor can turn off the transmission interface on the mobile industry processor interface during the blank interval when no display data is transmitted, and instead transmit the horizontal synchronization signal HS through a general-purpose output interface. Or, the main processor can stop transmitting the horizontal synchronization signal HS when it does not update the display data for a long time. At this time, the display driving circuit can generate the horizontal synchronization signal HS internally by itself, so as to use the internal horizontal synchronization signal HS to perform necessary display timing control. As Figure 15As shown, after the display driving circuit determines that an overtime has occurred and exits the bypass mode, the display control can be switched to be performed by the internal horizontal synchronization signal HS.

[0108] In this example, when the display driving circuit exits the bypass mode, it enters the command mode of the Mobile Industry Processor Interface to read and write display data, so as to perform the read and write operations of display data according to the specifications of the Mobile Industry Processor Interface. The command mode is used to replace the read and write mode of the foregoing embodiments. When the display driving circuit enters the command mode, the main processor can also send a write memory packet (not shown) to control the operation of the display driving circuit to start writing to the frame buffer. In the command mode, the main processor does not transmit the vertical synchronization signal VS and the horizontal synchronization signal HS through the Mobile Industry Processor Interface. Therefore, the display driving circuit instead uses the internal horizontal synchronization signal HS.

[0109] The above operations of data transmission and panel refresh based on the operation mode can be summarized into a control flow 160, as Figure 16 shown. The control flow 160 can be implemented in a display driving circuit, such as the display driving circuit in any of the foregoing embodiments. As Figure 16 shown, the control flow 160 includes the following steps:

[0110] Step 1602: Receive a plurality of display data.

[0111] Step 1604: Determine a frequency of the plurality of display data.

[0112] Step 1606: According to the frequency, write the plurality of display data into the frame buffer, or bypass the frame buffer and output the plurality of display data to the display screen.

[0113] For the detailed operations and variation methods of the control flow 160, reference can be made to the descriptions in the above paragraphs, which will not be elaborated here.

[0114] In the present invention, the display driving circuit switches the operation mode according to the behavior of the main processor for transmitting display data, rather than being instructed by the main processor to transmit instructions, which can optimize the power saving effect. Generally speaking, many applications may display static images in most cases, but there are still some situations where the screen needs to be updated frequently. If the traditional method of determining whether to operate in the static mode or the dynamic mode according to the usage scenarios of individual applications is adopted, only one of the operation modes can be selected, and the power saving effect obtained is limited. The simulation results of the long-term operation of a mobile phone show that if the usage scenario is determined by the upper layer of the main processor and the display driving circuit is notified to switch the mode by static indication, the power consumption that can be saved is extremely small. In contrast, by the method of the present invention, the display driving circuit can adopt the bypass mode when the main processor transmits images at high speed, and adopt the read / write mode when the main processor stops outputting high-speed display data, and switch the operation mode automatically according to the image transmission behavior of the main processor. The power consumption that can be saved is about 10 times that of the traditional method.

[0115] In summary, the present invention proposes an operation method of a hybrid mode applied to a mobile industry processor interface, which can control the display driving circuit to switch between the bypass mode and the read / write mode. The display driving circuit does not need to receive any instructions or indications from the main processor, and only needs to switch the mode according to the image transmission behavior of the main processor. The display driving circuit in the bypass mode can, through the timeout mechanism, when a timeout occurs but the vertical synchronization signal is not received, determine that the image transmission frequency of the main processor is lower than a critical value and correspondingly switch to the read / write mode. In an embodiment, the display driving circuit in the read / write mode can switch to the bypass mode when receiving the image transmitted by the main processor, or switch to the bypass mode through another timeout mechanism when determining that the image transmission frequency of the main processor is higher than a critical value. In an embodiment, an additional transmission interface is added between the display driving circuit and the main processor for the display driving circuit to transmit a control signal to instruct the main processor to transmit an image when entering the read / write mode, so as to update the display data stored in the frame buffer. In another embodiment, the display driving circuit may also not transmit a control signal when entering the read / write mode, but wait for the main processor to update the screen and actively output the updated display data, and then write the display data into the frame buffer and perform subsequent self-refresh operations according to the display data stored in the frame buffer. In an embodiment, the display driving circuit may also support the command mode, and when the main processor stops transmitting the horizontal synchronization signal, the display driving circuit can generate an internal horizontal synchronization signal by itself to perform display control. Through the operation method of the present invention, the benefits of both the command mode and the video mode can be obtained simultaneously under the application of the hybrid mode, and the obtained power saving effect can be maximized.

[0116] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for controlling a display screen, for a display driving circuit, wherein the display driving circuit has a frame buffer, characterized in that: The method includes: receiving a first frame of display data, and transmitting the first frame of display data to the display screen by bypassing the frame buffer; Starting timing within a time interval for receiving the first frame of display data to determine whether a timeout occurs; After the timeout occurs, receiving a second frame of display data; and The second frame display data is written into the frame buffer.

2. The method according to claim 1, characterized in that Also includes: When the timeout occurs, a control signal is output to instruct a main processor to transmit the second frame display data to the display driving circuit.

3. The method according to claim 1, characterized in that The display driving circuit operates in a first operation mode, and the method further comprises: When the timeout occurs, the first operation mode is left and a second operation mode is entered.

4. The method according to claim 3, characterized in that Also includes: When the display driving circuit is in the first operation mode, a plurality of display data received by the display driving circuit is controlled to bypass the frame buffer.

5. The method according to claim 3, characterized in that Also includes: When the display driving circuit is in the second operation mode, the second frame display data is read out from the frame buffer to refresh the display screen.

6. The method according to claim 5, characterized in that The second frame display data is read out from the frame buffer in a sequentially down-clocked manner.

7. The method according to claim 3, characterized in that Also includes: Without receiving an instruction from a main processor, the first operation mode is left and the second operation mode is entered.

8. The method according to claim 1, characterized in that The second frame display data is the same as the first frame display data.

9. The method according to claim 1, characterized in that The step of starting timing within the time interval for receiving the first frame of display data comprises: The timing starts when a synchronization signal for the first frame of display data is received.

10. The method according to claim 1, characterized in that The step of starting timing within the time interval for receiving the first frame of display data comprises: The timing starts when the time interval for receiving the first frame of display data starts.

11. The method according to claim 1, characterized in that The step of starting timing within the time interval for receiving the first frame of display data to determine whether the timeout occurs comprises: When no vertical synchronization signal is received for a predetermined period of time, it is determined that the timeout occurs.

12. The method according to claim 1, characterized in that The display driving circuit includes a timeout counter for determining whether the timeout occurs.

13. The method according to claim 1, characterized in that Also includes: receiving a third frame of display data before the timeout occurs; as well as The frame buffer is bypassed to output the third frame of display data to the display screen.

14. A display driving circuit for controlling a display screen, the display driving circuit having a frame buffer, characterized in that: The display driver circuit is used to: receiving a first frame of display data, and transmitting the first frame of display data to the display screen by bypassing the frame buffer; Starting timing within a time interval for receiving the first frame of display data to determine whether a timeout occurs; After the timeout occurs, receiving a second frame of display data; as well as The second frame display data is written into the frame buffer.

15. A method for controlling a display screen, for use in a display driving circuit, the display driving circuit having a frame buffer, characterized in that: The method includes: receiving a first frame of display data, and writing the first frame of display data into the frame buffer; After receiving the first frame of display data, receiving a second frame of display data without responding to a control signal of the display driving circuit; and The frame buffer is bypassed to output the second frame display data to the display screen.

16. The method according to claim 15, characterized in that The second frame display data is different from the first frame display data.

17. The method according to claim 15, characterized in that Also includes: Timing is started within a time interval for receiving the first frame of display data to determine whether a timeout occurs.

18. The method according to claim 17, characterized in that The second frame of display data is received before the timeout occurs.

19. The method according to claim 17, characterized in that Also includes: receiving a third frame of display data after the timeout occurs; as well as The third frame display data is written into the frame buffer.

20. The method of claim 15, wherein: The display driving circuit operates in a first operation mode, and the method further comprises: When the second frame of display data is received, the first operation mode is left and a second operation mode is entered.

21. The method of claim 20, wherein: Also includes: When the display driving circuit is in the first operation mode, the first frame of display data is read out from the frame buffer to refresh the display screen.

22. The method according to claim 21, characterized in that The first frame of display data is read out from the frame buffer in a sequentially down-clocked manner.

23. The method of claim 20, wherein: Also includes: When the display driving circuit is in the second operation mode, a plurality of display data received by the display driving circuit is controlled to bypass the frame buffer.

24. The method of claim 23, wherein: The plurality of display data are received at a frequency greater than a predetermined threshold value.

25. The method of claim 20, wherein: Also includes: Without receiving an instruction from a main processor, the first operation mode is left and the second operation mode is entered.

26. A display driving circuit for controlling a display screen, the display driving circuit having a frame buffer, characterized in that: The display driver circuit is used to: receiving a first frame of display data, and writing the first frame of display data into the frame buffer; After receiving the first frame of display data, receiving a second frame of display data without responding to a control signal of the display driving circuit; as well as The frame buffer is bypassed to output the second frame display data to the display screen.

27. A method for controlling a display screen, for use in a display driving circuit, the display driving circuit having a frame buffer, characterized in that: The method includes: receiving a plurality of display data; Determining a frequency of the plurality of display data; and According to the frequency, the plurality of display data are written into the frame buffer, or the frame buffer is bypassed to output the plurality of display data to the display screen.

28. The method of claim 27, wherein: The step of writing the plurality of display data into the frame buffer or bypassing the frame buffer and outputting the plurality of display data to the display screen according to the frequency comprises: When the frequency is lower than a first critical value, the plurality of display data are written into the frame buffer.

29. The method of claim 27, wherein: The step of writing the plurality of display data into the frame buffer or bypassing the frame buffer and outputting the plurality of display data to the display screen according to the frequency comprises: When the frequency is higher than a second critical value, the frame buffer is bypassed to output the plurality of display data to the display screen.

30. A display driving circuit for controlling a display screen, the display driving circuit having a frame buffer, characterized in that: The display driver circuit is used to: receiving a plurality of display data; Determining a frequency of the plurality of display data; and According to the frequency, the plurality of display data are written into the frame buffer, or the frame buffer is bypassed to output the plurality of display data to the display screen.

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