Display device and method of driving the same

Abstract

The invention provides a display device and a method of driving the same. The display device includes: a display panel on which a display area including sub-pixels is formed; a first GIP and a second GIP disposed on both sides of the display area, each of the first GIP and the second GIP including a buffer circuit including a buffer TFT and outputting a scan signal to a scan line connected to the sub-pixel through the buffer circuit; a sensing switch configured to select a signal input to / output from the buffer circuit; a sensing unit configured to control the sensing switch to sense a threshold voltage of a buffer TFT of a second GIP connected to a scan line based on a charge voltage of the scan line charged by a scan signal output from the first GIP; and a compensation unit configured to generate a compensation value for a high potential voltage applied to the related GIP according to the sensed threshold voltage of the buffer TFT.

Description

Technical Field

[0001] The present disclosure relates to apparatuses and methods, and in particular, by way of example and not limitation, to a display device and a method of driving the display device. Background Art

[0002] With the development of information technology, the market for display devices as a communication medium between users and information is growing. Accordingly, display devices such as light emitting display (LED) devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices are increasingly used.

[0003] A display device may include a display panel including sub-pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates driving power. The driver includes a gate driver that supplies gate signals such as a scan signal and a light emission control signal to the display panel, and a data driver that supplies a data signal to the display panel.

[0004] The description provided in the background art section should not be assumed to be prior art merely because it is mentioned in or related to that section. The background art section may include information describing one or more aspects of the subject technology, and the description in that section does not limit the present disclosure. Summary of the Invention

[0005] The gate driver of such a display device may be composed of a plurality of thin film transistors (TFTs). Since the electrical characteristics of the TFTs change over time of operation, appropriate compensation needs to be performed according to the changed electrical characteristics to improve operation stability. Accordingly, a technique for accurately sensing the electrical characteristics of the TFTs constituting the gate driver is needed.

[0006] An object of embodiments of the present disclosure is to provide a display device and a method of driving the display device to improve operation stability by accurately sensing and compensating the electrical characteristics of the TFTs constituting the gate driver of the display device.

[0007] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel on which a display area including sub-pixels is formed; a first gate-in-panel (GIP) and a second GIP disposed on both sides of the display area, each of which includes a buffer circuit including a plurality of buffer thin film transistors (TFTs), and outputs a scan signal to a scan line connected to the sub-pixels through the buffer circuit; a sensing switch configured to select a signal input to the buffer circuit / a signal output from the buffer circuit; a sensing unit configured to control the sensing switch to sense a threshold voltage of a buffer TFT of the second GIP connected to the scan line based on a charging voltage of the scan line charged through the scan signal output from the first GIP; and a compensation unit configured to generate a compensation value for a high potential voltage GVDD applied to the relevant GIP according to the sensed threshold voltage of the buffer TFT.

[0008] The sensing unit may control the sensing switch so that the buffer TFT of the second GIP performs a source follower operation based on the charging voltage of the scan line to sense the threshold voltage of the buffer TFT.

[0009] When the first GIP operates in a driving mode in which the first GIP outputs a scan signal, the sensing unit may sense the threshold voltage of the buffer TFT of the second GIP.

[0010] The buffer circuit may include a pull-up buffer TFT and a pull-down buffer TFT. The pull-up buffer TFT is controlled by a Q node voltage input to the gate electrode to output a scan signal through a first electrode, and the pull-down buffer TFT is controlled by a QB node voltage input to the gate electrode to output a scan signal through the first electrode, and the buffer circuit may output a scan signal according to a clock signal.

[0011] The sensing switch may include: a pull-up sensing switch configured to connect a second electrode of the pull-up buffer TFT to one of an initialization line for transmitting an initialization voltage, a clock line for transmitting a clock signal, and a sensing line through which a sensed value is obtained, or float the second electrode of the pull-up buffer TFT under the control of the sensing unit; and a pull-down sensing switch configured to connect a second electrode of the pull-down buffer TFT to a low potential voltage line for transmitting a low potential voltage or a sensing line through which a sensed value is obtained, or float the second electrode of the pull-down buffer TFT under the control of the sensing unit.

[0012] The sensing unit can, while the first GIP outputs a scan signal to the scan line, connect the second electrode of the pull-up buffer TFT of the second GIP connected to the scan line to the initialization line, and when the output of the scan signal is completed, float the second electrode of the pull-up buffer TFT of the second GIP, and then obtain the threshold voltage of the pull-up buffer TFT of the second GIP according to the voltage of the second electrode of the pull-up buffer TFT of the second GIP sensed by connecting the second electrode of the pull-up buffer TFT of the second GIP to the sense line.

[0013] The pull-up buffer TFT of the second GIP can perform a source follower operation based on the charging voltage of the scan line reflected in the first electrode.

[0014] The pull-up buffer TFT of the second GIP can receive the high potential voltage GVDD applied to the gate electrode and operate in the saturation region.

[0015] The sensing unit can, while the first GIP outputs a scan signal to the scan line, connect the second electrode of the pull-down buffer TFT of the second GIP connected to the scan line to the low potential voltage line, and when the output of the scan signal is completed, float the second electrode of the pull-down buffer TFT of the second GIP, and then obtain the threshold voltage of the pull-down buffer TFT of the second GIP according to the voltage of the second electrode of the pull-down buffer TFT of the second GIP sensed by connecting the second electrode of the pull-down buffer TFT of the second GIP to the sense line.

[0016] The pull-down buffer TFT of the second GIP can perform a source follower operation based on the charging voltage of the scan line reflected in the first electrode.

[0017] The sensing unit can, while the first GIP outputs a scan signal to the scan line, connect the second electrode of the pull-up buffer TFT of the first GIP to the clock line and connect the second electrode of the pull-down buffer TFT of the first GIP to the low potential voltage line.

[0018] Another aspect of the present disclosure provides a method for driving a display device, the display device including a display panel on which a display area including sub-pixels is formed; a first GIP and a second GIP provided on both sides of the display panel, each of which includes a buffer circuit including a plurality of buffer TFTs and outputs a scan signal to a scan line connected to the sub-pixels through the buffer circuit, the method including: outputting a scan signal from the first GIP to the scan line; sensing the threshold voltage of the buffer TFT of the second GIP connected to the relevant scan line based on the charging voltage of the scan line charged through the scan signal; and generating a correction value for the high potential voltage GVDD applied to the relevant GIP according to the sensed threshold voltage of the buffer TFT.

[0019] The buffer circuit may include: a pull-up buffer TFT controlled by a Q node voltage input to a gate electrode to output a scan signal through a first electrode; and a pull-down buffer TFT controlled by a QB node voltage input to a gate electrode to output a scan signal through a first electrode.

[0020] Sensing the threshold voltage of the buffer TFT of the second GIP may include: while the first GIP outputs a scan signal to the scan line, applying an initialization voltage to a second electrode of the pull-up buffer TFT of the second GIP connected to the scan line, floating the second electrode of the pull-up buffer TFT of the second GIP when the output of the scan signal is completed, and obtaining the threshold voltage of the pull-up buffer TFT of the second GIP based on the voltage of the second electrode of the pull-up buffer TFT of the second GIP sensed by connecting the second electrode of the pull-up buffer TFT of the second GIP to the sense line.

[0021] Sensing the threshold voltage of the buffer TFT of the second GIP may include: while the first GIP outputs a scan signal to the scan line, applying a low potential voltage to a second electrode of the pull-down buffer TFT of the second GIP connected to the scan line, floating the second electrode of the pull-down buffer TFT of the second GIP when the output of the scan signal is completed, and obtaining the threshold voltage of the pull-down buffer TFT of the second GIP based on the voltage of the second electrode of the pull-down buffer TFT of the second GIP sensed by connecting the second electrode of the pull-down buffer TFT of the second GIP to the sense line.

[0022] Outputting a scan signal from the first GIP to the scan line may include: connecting a second electrode of the pull-up buffer TFT of the first GIP to a clock line, and connecting a second electrode of the pull-down buffer TFT of the first GIP to a low potential voltage line.

[0023] It should be understood that the foregoing general description and the following detailed description of the present disclosure are both exemplary and explanatory and are intended to provide further explanation of the claimed present disclosure. Brief Description of the Drawings

[0024] The included drawings are used to provide a further understanding of the present disclosure and are incorporated into and form a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0025] Figure 1 is a block diagram schematically showing the configuration of a display device;

[0026] Figure 2 briefly shows Figure 1 a sub-pixel of

[0027] Figure 3 schematically showsFigure 1 Block diagram of the configuration of the strobe driver;

[0028] Figure 4 and Figure 5 is a diagram showing a display device according to a comparative example;

[0029] Figure 6 is a diagram showing some components of a display device according to an embodiment of the present disclosure;

[0030] Figure 7 is a diagram showing a display device according to a first embodiment;

[0031] Figures 8 to 10 is a diagram showing a method of sensing a change in the threshold voltage of the pull-up buffer TFT;

[0032] Figures 11 to 13 is a diagram showing a method of sensing a change in the threshold voltage of the pull-down buffer TFT;

[0033] Figure 14 is a diagram showing the GIP circuit included in the display device according to the first embodiment;

[0034] Figure 15 and Figure 16 is a diagram showing a display device according to a second embodiment;

[0035] Figure 17 is a diagram showing the configuration of the sensing unit of the first embodiment of the display device according to the embodiment of the present disclosure;

[0036] Figure 18 is a diagram showing the configuration of the sensing unit of the second embodiment of the display device according to the embodiment of the present disclosure;

[0037] Figure 19 is a diagram showing the configuration of the sensing unit of the third embodiment of the display device according to the embodiment of the present disclosure;

[0038] Figure 20 is an analog result diagram showing that the voltage of the clock signal changes according to the change in the threshold voltage of the pull-up buffer TFT;

[0039] Figure 21 is an analog result diagram showing the difference between the normal voltage and the abnormal voltage detected by sensing when a strong short circuit occurs between the gate, drain, and source of the pull-up buffer TFT;

[0040] Figure 22 is an analog result diagram showing the difference between the normal voltage and the abnormal voltage detected by sensing when a short circuit occurs between the gate and source, gate and drain, and drain and source of the pull-down buffer TFT; and

[0041] Figure 23 It is an analog result diagram showing the difference between the normal voltage and the abnormal voltage detected by sensing when a short circuit occurs due to foreign matter in the display area. Detailed implementation manners

[0042] Referring to the implementation manners described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the manner of obtaining these advantages and features will become apparent. However, the present disclosure is not limited to the implementation manners disclosed below and can be embodied in many different forms. More precisely, these exemplary implementation manners are provided to make the present disclosure complete and to fully convey the scope to those skilled in the art.

[0043] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the various implementation manners of the present disclosure are only given by way of example, and thus, the present disclosure is not limited to the illustrations in the accompanying drawings. Throughout the specification, the same or extremely similar elements are denoted by the same reference numerals. In this specification, when using terms such as "comprising", "including", etc., unless the term "only" is used, other elements can be added. Unless the context clearly indicates otherwise, an element described in the singular form is intended to include a plurality of elements.

[0044] Throughout the accompanying drawings and the detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes of these elements may be exaggerated and depicted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and can be changed as known in the art, except in cases where the steps and / or operations must occur in a specific order. The same reference numerals always denote the same elements. The names of the various elements used in the following description are only selected for the convenience of writing the specification and may thus be different from the names used in actual products.

[0045] When explaining the constituent elements included in the various implementation manners of the present disclosure, even without its explicit description, the constituent elements are interpreted to include an error range.

[0046] In the description of the various implementation manners of the present disclosure, when describing the positional relationship (for example, when using descriptions such as "on...", "above...", "below...", "next to..." to describe the positional relationship between two components), unless the terms "directly" or "immediately" are used, one or more other components may be located between these two components.

[0047] Although terms such as "first" and "second" may be used to describe various elements, these terms are only used to distinguish the same or similar elements from each other. Therefore, in this specification, unless otherwise specified, within the scope of the technology of the present disclosure, an element modified by "first" may be the same as an element modified by "second".

[0048] The display device according to the present disclosure can be implemented as a television receiver, a video player, a personal computer (PC), a home theater, an automotive electronic device, a smartphone, etc., but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display device, a liquid crystal display device, etc. However, as an example, for ease of description, a display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode will be described below.

[0049] Throughout the specification, the same or extremely similar elements are denoted by the same reference numerals. In addition, in the description of the present disclosure, when a detailed description of related known technologies may make the subject matter of the present disclosure unclear, the detailed description will be omitted.

[0050] Figure 1 is a block diagram schematically showing the configuration of a display device, Figure 2 briefly shows Figure 1 a sub-pixel of, and Figure 3 is a block diagram schematically showing Figure 1 the configuration of a gate driver of.

[0051] As Figures 1 to 3 shown, the display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply 180.

[0052] In addition to the image data signal supplied from the outside or the image data signal stored in the internal memory, the image provider 110 may also output various driving signals. The image provider 110 may supply a data signal and various driving signals to the timing controller 120.

[0053] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 may supply the data signal DATA supplied from the image provider 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be formed as an integrated circuit IC and mounted on a printed circuit board, but is not limited thereto.

[0054] The power supply 180 can convert the power supplied from the outside into high-voltage first power and low-voltage second power under the control of the timing controller 120, and output the first power and the second power through the first power line EVDD and the second power line EVSS. In addition to the first power and the second power, the power supply 180 can also generate and output a gate voltage including a gate high voltage and a gate low voltage required to drive the gate driver 130, and a voltage required to drive the data driver 140.

[0055] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 can supply the data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 can be formed as an IC and mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0056] The display panel 150 can include a plurality of sub-pixels SP provided at the intersections of the gate lines GL and the data lines DL arranged in a matrix form. As Figure 2 shown, one sub-pixel SP can be connected to the first data line DL1, the first gate line GL1, the first power line EVDD, and the second power line EVSS. The first data line DL1 is a line for transmitting the data voltage, the first gate line GL1 is a line for transmitting the scan signal, the first power line EVDD is a line for transmitting the first power, and the second power line EVSS is a line for transmitting the second power. One sub-pixel SP can include a switching transistor SW that transmits the data voltage input through the data line in response to the scan signal input through the gate line, and a pixel circuit PC that emits light in response to the data voltage. The pixel circuit PC can include a driving transistor that generates a driving current, an organic light-emitting diode (OLED) that emits light in response to the driving current, and the like. An array of sub-pixels SP arranged on the same gate line is called a horizontal line. The sub-pixels SP of the same horizontal line are turned on by the same scan signal and receive the data voltage input to the data lines connected to each sub-pixel SP.

[0057] The gate driver 130 can supply at least one scan signal to the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 can be formed in the form of an IC, or can be directly formed on the display panel 150 in an in-panel-gate (GIP) structure. The gate driver 130 formed in the GIP structure can be provided at one edge of the display panel 150, or can be separated and provided at two edges of the display panel 150.

[0058] Figure 3is a block diagram schematically showing the configuration of the gate driver 130.

[0059] Referring Figure 3 , the gate driver 130 may output scan signals SCAN[1] to SCAN[N] in response to a gate timing control signal GDC supplied from the timing controller 120, where N is a positive integer. A high potential voltage GVDD and a low potential gate voltage GVSS may be supplied to the gate driver 130, and the scan signals SCAN[1] to SCAN[N] are output according to the gate timing control signal GDC.

[0060] The gate driver 130 may include a scan signal generation circuit 132 and a buffer circuit 134.

[0061] The scan signal generation circuit 132 may generate one or more clock signals and a start pulse signal based on a signal output from the timing controller 120. The scan signal generation circuit 132 may generate scan signals SCAN[1] to SCAN[N] to be supplied to the gate lines by shifting a scan pulse signal according to a clock timing using a shift register.

[0062] The buffer circuit 134 may output the scan signals SCAN[1] to SCAN[N] output from the scan signal generation circuit 132 to the gate lines GL1 to GLm. The buffer circuit 134 may sequentially output the scan signals SCAN[1] to SCAN[N] in synchronization with a scan clock signal output from the IC in the timing controller 120 or the gate driver 130.

[0063] Figure 4 and Figure 5 is a diagram showing a display device according to a comparative example.

[0064] As Figure 4 shown, the display device according to the comparative example may include a first circuit board C-PCB, a second circuit board S-PCB, a third circuit board F-PCB, and a display panel 150. The first circuit board C-PCB may include a timing controller 120 and a GVDD change circuit 125. The second circuit board S-PCB may be electrically connected to the first circuit board C-PCB and the third circuit board F-PCB. The third circuit board F-PCB may include a data driver SDIC mounted in the form of an IC, and may be electrically connected to the second circuit board S-PCB and the display panel 150.

[0065] A display area AA for displaying an image using a plurality of sub-pixels may be formed on the display panel 150. On both sides of the display area AA, a first GIP GIP_L and a second GIP GIP_R may be formed. An analog TFT 135 for sensing the deterioration degree of buffer TFTs for the first GIP GIP_L and the second GIP GIP_R may be formed adjacent to the first GIP GIP_L and the second GIP GIP_R.

[0066] Referring to Figure 5 , the first GIP GIP_L and the second GIP GIP_R may include a scan signal generation circuit 132 (also referred to as GIP logic 132) that generates a scan signal, and a buffer circuit 134. The first GIP GIP_L and the second GIP GIP_R may receive a high-potential gate drive voltage (GVDD) and a low-potential gate drive voltage (GVSS) as DC voltages, and output a scan signal. In order to reduce the stress caused by GVDD in this GIP structure, a GVDD change circuit 125 that changes the level of GVDD in response to a change in the threshold voltage Vth of the TFTs constituting the buffer circuit 134 is applied.

[0067] The buffer circuit 134 may include a pull-up buffer TFT T6 and a pull-down buffer TFT T7. In order to sense a change in the threshold voltage Vth of the pull-up buffer TFT T6 and the pull-down buffer TFT T7, an analog TFT 135 (TFB) may be formed on the edge of the panel 150.

[0068] Four analog TFTs 135 (TFB) may be formed on the edge of the panel corresponding to the positions where the first GIP GIP_L and the second GIP GIP_R are formed. The analog TFT 135 (TFB) may have a gate electrode connected to the QB node Qb of the scan signal generation circuit 132 (GIP logic), a first electrode connected to the Q node Q, and a second electrode connected to a low-potential voltage line that transmits a low-potential voltage GVSS. Therefore, the threshold voltage of the analog TFT 135 (TFB) can be measured and used as threshold voltage information of the TFTs constituting the buffer circuit 134.

[0069] The GVDD changing circuit 125 can change the high potential voltage GVDD supplied to the first GIP GIP_L and the second GIP GIP_R according to the threshold voltage of the analog TFT 135. The GVDD changing circuit 125 can be implemented based on a comparator. The GVDD changing circuit 125 can be configured to determine a voltage that allows the same current to flow in the analog TFT 135 (TFB) as GVDD by utilizing the equipotential characteristic of an operational amplifier (OP-AMP). That is, the GVDD changing circuit for maintaining a constant current amount can be configured by connecting the analog TFT 135 connected to the gate drivers GIP_L and GIP_R to the OP-AMP. In this way, the display device according to the comparative example measures the change in the threshold voltage of the analog TFT 135 (TFB) and uses it as the threshold voltage information of the buffer TFT.

[0070] Compared with the display device according to the comparative example, the display device according to an embodiment of the present disclosure can directly sense the threshold voltage of the buffer TFT included in the buffer circuit by driving the buffer TFT in a source follower manner. In the display device according to an embodiment of the present disclosure (where the first GIP GIP_L and the second GIP GIP_R are formed on both sides of the display area), when one side's GIP outputs a scan signal, the threshold voltage of the buffer TFT on the other side's GIP can be sensed. The display device according to an embodiment of the present disclosure can sense the threshold voltage based on the charging voltage of the scan line by driving the buffer TFT of the other side's GIP connected to the scan line charged by the scan signal output from one side's GIP in a source follower manner.

[0071] Figure 6 FIG. is a diagram showing a configuration for sensing the threshold voltage of a buffer TFT in a display device according to an embodiment of the present disclosure.

[0072] Referring to Figure 6 , the display device according to an embodiment of the present disclosure may include a buffer circuit 134, a pull-up sensing switch 210, a pull-down sensing switch 220, a sensing unit 200, and a compensation circuit 300.

[0073] The buffer circuit 134 may include a pull-up buffer TFT T6 and a pull-down buffer TFT T7. The pull-up buffer TFT T6 may be controlled by the Q node voltage input to the gate and output a scan signal through the first electrode. The pull-down buffer TFT T7 may be controlled by the QB node voltage input to the gate and output a scan signal through the first electrode. The buffer circuit 134 may output a scan signal according to a scan clock signal.

[0074] According to the first switch control signal SW1 applied by the sensing unit 200, the pull-up sensing switch 210 can connect the second electrode of the pull-up buffer TFT T6 to one of the initialization line IN for transmitting the initialization voltage, the clock line CLK for transmitting the clock signal, and the sensing line ADC for obtaining the sensed value. If the pull-up sensing switch 210 is not connected to any line, the second electrode of the pull-up buffer TFT T6 can be electrically floating. When the second electrode of the pull-up buffer TFT T6 is connected to the clock line CLK, the pull-up buffer TFT T6 can output a scan signal according to the Q-node voltage. When the threshold voltage of the pull-up buffer TFT T6 is sensed, the Q-node voltage at the conductive level can be applied to the gate electrode of the pull-up buffer TFT T6. When the threshold voltage is sensed, the Q-node voltage at the conductive level is applied to the gate electrode of the pull-up buffer TFT T6, and the second electrode of the pull-up buffer TFT T6 can be connected to the sensing line ADC after being connected to the initialization line IN and then be floated.

[0075] According to the second switch control signal SW2 applied by the sensing unit 200, the pull-down sensing switch 220 can connect the second electrode of the pull-down buffer TFT T7 to the ground voltage line GVSS0 for transmitting the low-potential voltage or the sensing line ADC for obtaining the sensed value. If the pull-down sensing switch 220 is not connected to any line, the second electrode of the pull-down buffer TFT T7 can be electrically floating. When outputting the scan signal, the second electrode of the pull-down buffer TFT T7 is connected to the ground voltage line GVSS0 to output the scan signal according to the Qb-node voltage. When the threshold voltage of the pull-down buffer TFT T7 is sensed, the Qb-node voltage at the conductive level can be applied to the gate electrode of the pull-down buffer TFT T7. When sensing the threshold voltage, the Qb-node voltage at the conductive level is applied to the gate electrode of the pull-down buffer TFT T7, and the second electrode of the pull-up buffer TFT T6 can be floated and then connected to the sensing line ADC. The sensing unit 200 can obtain the threshold voltage sensing information V_sen of the pull-up buffer TFT T6 and the pull-down buffer TFT T7 of the buffer circuit 134 by controlling the pull-up sensing switch 210 and the pull-down sensing switch 220.

[0076] When the GIP operates in a driving mode for outputting a scan signal, the sensing unit 200 may connect the second electrode of the pull-up buffer TFT T6 to the clock line CLK and connect the second electrode of the pull-down buffer TFT T7 to the low-potential voltage line GVSS0. When the GIP operates in a sensing mode for threshold voltage sensing, the sensing unit 200 may connect the second electrodes of the pull-up buffer TFT T6 and the pull-down buffer TFT T7 of the GIP to the initialization line IN, or float them and then connect them to the sensing line ADC. As described above, the sensing unit 200 may control the pull-up sensing switch 210 and the pull-down sensing switch 220 such that one of the two GIPs operates in the driving mode and the other GIP operates in the sensing mode.

[0077] When sensing the threshold voltage of the pull-up buffer TFT T6, the sensing unit 200 may connect the second electrode of the pull-up buffer TFT T6 to the initialization line IN while the scan line is charged by the scan signal output from the pull-up buffer TFT of the GIP on the other side. Thereafter, the sensing unit 200 may keep the pull-up sensing switch 210 in an off state so that the second electrode of the pull-up buffer TFT T6 is floated. When the Q-node voltage is applied while the second electrode of the pull-up buffer TFT T6 is floated, a source follower operation is performed based on the charging voltage of the scan signal reflected in the first electrode of the pull-up buffer TFT T6, so that the potential of the second electrode rises to a potential lower than the Q node by Vth. Accordingly, the sensing unit 200 may obtain the threshold voltage sensing information V_sen by connecting the second electrode of the pull-up buffer TFT T6 to the sensing line ADC.

[0078] When sensing the threshold voltage of the pull-down buffer TFT T7, the sensing unit 200 may connect the second electrode of the pull-down buffer TFT T7 to the low-potential voltage line GVSS0 while the scan line is charged by the scan signal. When the charging of the scan signal is completed, the sensing unit 200 keeps the pull-down sensing switch 220 in an off state so that the second electrode of the pull-down buffer TFT T7 is floated. When the Qb-node voltage is applied while the second electrode of the pull-down buffer TFT T7 is floated, a source follower operation is performed based on the charging voltage of the scan signal reflected in the first electrode of the pull-up buffer TFT T7, so that the potential of the second electrode rises to a potential lower than the Qb node by Vth. Accordingly, the sensing unit 200 may obtain the threshold voltage sensing information V_sen by connecting the second electrode of the pull-down buffer TFT T7 to the sensing line ADC.

[0079] The sensing unit 200 can sample and hold the threshold voltage sensing information V_sen using an ADC to obtain the threshold voltage information of the corresponding buffer TFT. The sensing unit 200 can send the GIP sensing information GIP_sen including the threshold voltages of the pull-up buffer TFT T6 and the pull-down buffer TFT T7 to the compensation circuit 300.

[0080] The compensation circuit 300 can generate a compensation value for the high potential voltage GVDD applied to the GIP including the corresponding buffer TFT according to the GIP sensing information GIP_sen.

[0081] Figure 7 FIG. is a diagram showing a display device according to the first embodiment.

[0082] Referring to Figure 7 , the first GIP GIP_L and the second GIP GIP_R can be provided at two edges (corresponding to the passive region) of the display area AA defined in the display panel. The first GIP GIP_L and the second GIP GIP_R can alternately output scan signals according to the gate timing control signal GDC of the timing controller. The driving mode or sensing mode operation of the first GIP GIP_L and the second GIP GIP_R can be determined by the operations of the pull-up sensing switch and the pull-down sensing switch controlled by the sensing unit. When both the first GIP GIP_L and the second GIP GIP_R are operating in the driving mode, they can alternately output scan signals. When sensing the threshold voltage of the sensing buffer TFT, only one side of the first GIP GIP_L and the second GIP GIP_R can operate in the driving mode to output a scan signal, while the other side can operate in the sensing mode.

[0083] The first GIP GIP_L and the second GIP GIP_R can respectively include a pull-up buffer TFT T6 L and a pull-down buffer TFT T7 L and a pull-up buffer T6 R and a pull-down buffer TFT T7 R .

[0084] The pull-up buffer TFT T6 L and T6 R and the pull-down buffer TFT T7 L and T7 R can be connected to the Nth gate line passing through the display area AA. The pull-up buffer TFT T6 L and T6 R and the pull-down buffer TFT T7 L and T7 R can be respectively connected to the Q node voltage Q L and Q Rand the Qb node voltage Qb L and Qb R Control. The pull-up buffer TFT T6 L and T6 R and the pull-down buffer TFT T7 L and T7 R can output a scan signal SCAN[N] at a conduction voltage (e.g., a high voltage) and a cut-off voltage (e.g., a low voltage). For example, the pull-up buffer TFT T6 L and T6 R can output a scan signal SCAN[N] at a conduction voltage, and the pull-down buffer TFT T7 L and T7 R can output a scan signal SCAN[N] at a cut-off voltage.

[0085] The first GIP GIP_L and the second GIP GIP_R may include a pull-up sensing switch SW_L and SW_R provided between signal lines of the pull-up buffer TFT T6 L and T6 R and a pull-down sensing switch SW_LL and SW_RL provided between power lines of the pull-down buffer TFT T7 L and T7 R The pull-up sensing switches SW_L and SW_R and the pull-down sensing switches SW_LL and SW_RL may be controlled by a sensing unit described below to perform a selective switching operation.

[0086] The pull-up sensing switches SW_L and SW_R may include a first pull-up sensing switch SW_L and a second pull-up sensing switch SW_R. The pull-down sensing switches SW_LL and SW_RL may include a first pull-down sensing switch SW_LL and a second pull-down sensing switch SW_RL.

[0087] The first pull-up sensing switch SW_L may be provided on a first pull-up line of a first pull-up buffer TFT T6 included in the first GIP GIP_L L and the second pull-up sensing switch SW_R may be provided on a second pull-up line of a second pull-up buffer TFT T6 included in the second GIP GIP_R R of.

[0088] The first pull-up sensing switch SW_L may be controlled to connect a second electrode of the first pull-up buffer TFT T6 L to a first initialization line IN provided outside the display panel L selected from, a first clock line CLK L and a first sensing line ADC LOne of them, or the first pull-up sensing switch SW_L can be controlled to be electrically floating.

[0089] When the first pull-up sensing switch SW_L is connected to the first initialization line IN L the first initialization voltage can be applied to the second electrode of the first pull-up buffer TFT T6 L When the first pull-up sensing switch SW_L is connected to the first clock line CLK L the first clock signal can be applied to the second electrode of the first pull-up buffer TFT T6 L When the first pull-up sensing switch SW_L is connected to the first sensing line ADC L the sensing of the threshold voltage of the first pull-up buffer TFT T6 can be performed through the first sensing line ADC L L

[0090] The second pull-up sensing switch SW_R can be controlled to connect the second electrode of the second pull-up buffer TFT T6 R to one selected from a second initialization line IN, a second clock line CLK, and a second sensing line ADC R which are provided outside the display panel, or the second pull-up sensing switch SW_R can be controlled to be electrically floating. R R

[0091] When the second pull-up sensing switch SW_R is connected to the second initialization line IN R the second initialization voltage can be applied to the second electrode of the second pull-up buffer TFT T6 R When the second pull-up sensing switch SW_R is connected to the second clock line CLK R the second clock signal can be applied to the second electrode of the second pull-up buffer TFT T6 R When the second pull-up sensing switch SW_R is connected to the second sensing line ADC R the sensing of the threshold voltage of the second pull-up buffer TFT T6 can be performed through the second sensing line ADC R R

[0092] The first pull-down sensing switch SW_LL can be disposed on the first pull-down line of the first pull-down buffer TFT T7 included in the first GIP GIP_L, and the second pull-down sensing switch SW_RL can be disposed on the second pull-down line of the second pull-down buffer TFT T7 included in the second GIP GIP_R. L R

[0093] The first pull-down sensing switch SW_LL can be controlled to connect the second electrode of the first pull-down buffer TFT T7 L to one selected from a first low-potential voltage line GVSS0 provided outside the display panel and a first sensing line ADC L , or the first pull-down sensing switch SW_LL can be controlled to be electrically floating.

[0094] When the first pull-down sensing switch SW_LL is connected to the first low-potential voltage line GVSS0, the first low-potential voltage GVSS can be applied to the second electrode of the first pull-down buffer TFT T7 L . When the first pull-down sensing switch SW_LL is connected to the first sensing line ADC L , sensing of the threshold voltage of the first pull-down buffer TFT T7 L can be performed through the first sensing line ADC L .

[0095] The second pull-down sensing switch SW_RL can be controlled to connect the second electrode of the second pull-down buffer TFT T7 R to one selected from a first low-potential voltage line GVSS0 provided outside the display panel and a second sensing line ADC R , or the second pull-down sensing switch SW_RL can be controlled to be electrically floating.

[0096] When the second pull-down sensing switch SW_RL is connected to the first low-potential voltage line GVSS0, the first low-potential voltage GVSS can be applied to the second electrode of the second pull-down buffer TFT T7 R . When the second pull-down sensing switch SW_RL is connected to the second sensing line ADC R , sensing of the threshold voltage of the second pull-down buffer TFT T7 R can be performed through the second sensing line ADCR.

[0097] Figures 8 to 10 is a diagram showing a method for sensing a pull-up buffer TFT.

[0098] As Figures 8 to 10 shown, a display device according to an embodiment can sense a change in the threshold voltage of a pull-up buffer TFT included in one selected from a first GIP GIP_L and a second GIP GIP_R through scan line charging, source following, and sampling and holding. To this end, one selected from the first GIP GIP_L and the second GIP GIP_R (the sensing target) can be in a non-driving state in which a scan signal is not output. Hereinafter, an example of a case where the second GIP GIP_R is unidirectionally driven to sense the first pull-up buffer TFT T6 L included in the first GIP GIP_L will be described.

[0099] During Figure 8 the scan line charging period shown, the first pull-up sensing switch SW_L included in the first GIP GIP_L can be connected to the first initialization line IN L , and the second pull-up sensing switch SW_R can be connected to the second clock line CLK R .

[0100] According to the operation of the first pull-up sensing switch SW_L included in the first GIP GIP_L, a first initialization voltage can be applied to the first pull-up line connected to the first pull-up buffer TFT T6 L . The line capacitor C CLK (or parasitic capacitor) of the first pull-up line can be initialized based on the first initialization voltage.

[0101] A second clock signal can be applied to the second pull-up line connected to the second pull-up buffer TFT T6 according to the operation of the second pull-up sensing switch SW_R included in the second GIP GIP_R R , and the second pull-up buffer TFT T6 R can be turned on in response to the voltage charged in the second Q node QR and output a scan signal SCAN[N] at the on voltage based on the second clock signal. When the scan signal SCAN[N] is output, the corresponding scan line can be charged to a high voltage. Therefore, a high voltage can be applied to the drain node of the first pull-up buffer TFT T6 L of the first GIP GIP_L. In addition, since the first GIP GIP_L and the second GIP GIP_R alternately output scan signals, at the moment when the second GIP GIP_R outputs the scan signal SCAN[N], the voltage Q L of the first Q node of the first GIP GIP_L L remains low, so the first pull-up buffer TFT T6 Figure 9 remains in the off state. During R the source follower stage shown, the first pull-up sensing switch SW_L can be electrically floated, and the second pull-up sensing switch SW_R can be kept in the state of being connected to the second clock line CLK L . After the second GIP GIP_R outputs the scan signal SCAN[N], the voltage Q LThe potential of the second electrode can rise to a potential lower than the Q node by Vth. According to the source-follower operation of the first pull-up buffer TFT T6 L a voltage corresponding to the threshold voltage of the first pull-up buffer TFT T6 L can be charged into the line capacitor C of the first pull-up line CLK .

[0102] During Figure 10 the sampling and holding phase shown, the first pull-up sensing switch SW_L can be connected to the first sensing line ADC L , and the second pull-up sensing switch SW_R can be electrically floated. During the sampling and holding phase, the voltage charged into the line capacitor C of the first pull-up line CLK can be sensed by an external device connected to the first sensing line ADC L and sampled and held.

[0103] Figures 11 to 13 is a diagram showing a method of sensing a pull-down buffer TFT.

[0104] As Figures 11 to 13 shown, a display device according to an embodiment can sense a change in the threshold voltage of a pull-down buffer TFT included in one of a first GIP GIP_L and a second GIP GIP_R through scan line charging, source-follower, and sampling and holding. To this end, one of the first GIP GIP_L and the second GIP GIP_R (a sensing target) can be in a non-driving state in which a scan signal is not output. Hereinafter, an example of sensing the first pull-down buffer TFT T7 L included in the first GIP GIP_L will be described.

[0105] During Figure 11 the scan line charging shown, the first pull-up sensing switch SW_L can be connected to the first initialization line IN L , and the second pull-up sensing switch SW_R can be connected to the second clock line CLK R . The first pull-down sensing switch SW_LL and the second pull-down sensing switch SW_RL can be connected to the first low potential voltage line GVSS0.

[0106] The first initialization voltage can be applied to the first pull-up line connected to the first pull-up buffer TFT T6 L according to the operation of the first pull-up sensing switch SW_L, and the line capacitor C CLK (or parasitic capacitor) of the first pull-up line can be initialized based on the first initialization voltage.

[0107] The second clock signal can be applied to the second pull-up line connected to the second pull-up buffer TFT T6 according to the operation of the second pull-up sense switch SW_R. R The second pull-up buffer TFT T6 R can be turned on in response to the voltage charged in the second Q node Q R and output a scan signal SCAN[N] at the on voltage based on the second clock signal.

[0108] During Figure 12 the source follower period shown, the first pull-down sense switch SW_LL can be electrically floated. After the second GIP GIP_R outputs the scan signal SCAN[N], the voltage Qb of the first Qb node of the first GIP GIP_L L can be switched to a high level. Therefore, since the first Qb node voltage Qb is applied while the second electrode is floated L , the first pull-down buffer TFT T7 can be driven by source follower based on the charge voltage of the scan signal of the first electrode. L During the source follower period, the potential of the second electrode of the first pull-down buffer TFT T7 L can rise to a potential lower than the Q node by Vth. According to the source follower operation of the first pull-down buffer TFT T7 L , the line capacitor C of the first pull-down line VSS can be charged with a voltage corresponding to the threshold voltage of the first pull-down buffer TFT T7 L .

[0109] During Figure 13 the sampling and holding period shown, the first pull-up sense switch SW_L can be electrically floated, and the second pull-up sense switch SW_R can be held in a state connected to the second clock line CLK R . The first pull-down sense switch SW_LL can be connected to the first sense line ADC L , and the second pull-down sense switch SW_RL can be electrically floated. During the sampling and holding period, the voltage charged in the line capacitor CVSS of the first pull-down line can be sensed by an external device connected to the first sense line ADCL and sampled and held.

[0110] Figure 14 is a diagram showing a stage circuit of a gate driver to which a compensation circuit according to an embodiment is applied.

[0111] As Figure 14As shown, a strobe driver applicable to a compensation circuit according to an embodiment can be implemented based on a stage circuit including a line selector 502, a Q-node controller 504, a Q-node and QH-node stabilizer 506, an inverter 508, a QB-node stabilizer 510, a carry signal output unit 512, and a scan signal output unit 514.

[0112] The line selector 502 can charge the M-node based on a previous carry signal C(k-2) in response to the input of a line sense ready signal LSP. The line selector 502 can charge the Q-node to the level of a first high voltage GVDD1 based on the voltage charged at the M-node in response to the input of a reset signal RESET. The line selector 502 can discharge or reset the Q-node to the level of a third low voltage GVSS3 in response to the input of a panel on signal POS.

[0113] The line selector 502 can include a first transistor T11 to a seventh transistor T17 and a precharge capacitor CA. The first transistor T11 and the second transistor T12 can be connected between the M-node and a first high voltage line that transmits a first high voltage GVDD1. The first transistor T11 and the second transistor T12 can be connected in series.

[0114] The first transistor T11 can output a previous carry signal C(k-2) to a first connection node NC1 in response to the input of a line sense ready signal LSP. The second transistor T12 can electrically connect the first connection node NC1 to the M-node in response to the input of a line sense ready signal LSP. For example, when a high voltage line sense ready signal LSP is input to the first transistor T11 and the second transistor T12, the first transistor T11 and the second transistor T12 are turned on simultaneously, so that the M-node can be charged to the level of the first high voltage GVDD1.

[0115] When the voltage level of the M-node is high, the third transistor T13 can be turned on to supply the first high voltage GVDD1 to the first connection node NC1. When the first high voltage GVDD1 is supplied to the first connection node NC1, the voltage difference between the gate voltage of the first transistor T11 and the first connection node NC1 may increase. Therefore, when a low level line sense ready signal LSP is input to the gate of the first transistor T11 to turn off the first transistor T11, due to the voltage difference between the gate voltage of the first transistor T11 and the first connection node NC1, the first transistor T11 can be maintained in a fully off state. Therefore, current leakage in the first transistor T11 and voltage drop generated at the M-node can be reduced or prevented, and the voltage of the M-node can be stably maintained.

[0116] The precharge capacitor CA is connected between the M node and the first high-voltage line that transmits the first high voltage GVDD1, and can store the differential voltage between the first high voltage GVDD1 and the voltage charged at the M node. When the first transistor T11, the second transistor T12, and the third transistor T13 are turned on, the precharge capacitor CA can store the high voltage of the previous carry signal C(k - 2). When the first transistor T11, the second transistor T12, and the third transistor T13 are turned off, the precharge capacitor CA can maintain the voltage of the M node for a certain period of time using the stored voltage.

[0117] The fourth transistor T14 and the fifth transistor T15 can be connected between the Q node and the first high-voltage line that transmits the first high voltage GVDD1. The fourth transistor T14 and the fifth transistor T15 can be connected in series.

[0118] The fourth transistor T14 and the fifth transistor T15 can charge the Q node to the first high voltage GVDD1 in response to the input of the voltage of the M node and the reset signal RESET. When the voltage of the M node is at a high level, the fourth transistor T14 is turned on to transmit the first high voltage GVDD1 to the shared node of the fourth transistor T14 and the fifth transistor T15. The fifth transistor T15 can be turned on by the high-level reset signal RESET to supply the voltage of the shared node to the Q node. Therefore, when the fourth transistor T14 and the fifth transistor T15 are turned on simultaneously, the Q node can be charged to the first high voltage GVDD1.

[0119] The sixth transistor T16 and the seventh transistor T17 can be connected between the Q node and the third low-voltage line that transmits the third low voltage GVSS3. The sixth transistor T16 and the seventh transistor T17 can be connected in series.

[0120] The sixth transistor T16 and the seventh transistor T17 can discharge the Q node to the third low voltage GVSS3 in response to the input of the panel turn-on signal POS. Discharging the Q node to the third low voltage GVSS3 can also be expressed as resetting the Q node. The seventh transistor T17 can be turned on in response to the input of the high-level panel turn-on signal POS to supply the third low voltage GVSS3 to the QH node. The sixth transistor T16 can be turned on in response to the input of the high-level panel turn-on signal POS to electrically connect the Q node and the QH node. Therefore, when the sixth transistor T16 and the seventh transistor T17 are turned on simultaneously, the Q node can be discharged or reset to the third low voltage GVSS3.

[0121] The Q-node controller 504 can charge the Q-node to the level of the first high voltage GVDD1 in response to the input of the previous carry signal C(k - 2), and discharge the Q-node to the level of the third low voltage GVSS3 in response to the input of the subsequent carry signal C(k + 2). The Q-node controller 504 can include the first transistor T21 to the eighth transistor T28.

[0122] The first transistor T21 and the second transistor T22 can be connected between the Q-node and the first high voltage line that transmits the first high voltage GVDD1. The first transistor T21 and the second transistor T22 can be connected in series.

[0123] The first transistor T21 and the second transistor T22 can charge the Q-node to the level of the first high voltage GVDD1 in response to the input of the previous carry signal C(k - 2). The first transistor T21 can be turned on in response to the input of the previous carry signal C(k - 2) to supply the first high voltage GVDD1 to the second connection node NC2. The second transistor T22 can be turned on in response to the input of the previous carry signal C(k - 2) to electrically connect the second connection node NC2 and the Q-node. Therefore, when the first transistor T21 and the second transistor T22 are turned on simultaneously, the first high voltage GVDD1 can be supplied to the Q-node.

[0124] The fifth transistor T25 and the sixth transistor T26 can be connected to the third high voltage line that transmits the third high voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 can supply the third high voltage GVDD3 to the second connection node NC2 in response to the third high voltage GVDD3.

[0125] By being turned on simultaneously by the third high voltage GVDD3, the fifth transistor T25 and the sixth transistor T26 can continuously supply the third high voltage GVDD3 to the second connection node NC2 to increase the voltage difference between the gate voltage of the first transistor T21 and the second connection node NC2. Therefore, when the low-level previous carry signal C(k - 2) is input to the gate of the first transistor T21 to turn off the first transistor T21, due to the voltage difference between the gate voltage of the first transistor T21 and the second connection node NC2, the first transistor T21 can be maintained in a fully off state. Therefore, the current leakage in the first transistor T21 and the voltage drop generated at the Q-node can be reduced or prevented, and the voltage at the Q-node can be stably maintained.

[0126] For example, when the threshold voltage of the first transistor T21 is negative (-), the gate-source voltage Vgs of the first transistor T21 can be maintained at a negative level (-) according to the third highest voltage GVDD3 supplied to the drain electrode. Therefore, when a low-level previous carry signal C(k - 2) is input to the gate of the first transistor T21 to turn off the first transistor T21, the first transistor T21 remains in a fully off state, thereby reducing or preventing the occurrence of leakage current. The third highest voltage GVDD3 can be set at a level lower than the first highest voltage GVDD1.

[0127] The third transistor T23 and the fourth transistor T24 can be connected between the Q node and a third low voltage line that transmits the third low voltage GVSS3. The third transistor T23 and the fourth transistor T24 can be connected in series.

[0128] The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the level of the third low voltage GVSS3 in response to the input of a subsequent carry signal C(k + 2). The fourth transistor T24 can conduct in response to the input of the subsequent carry signal C(k + 2) to discharge the QH node to the level of the third low voltage GVSS3. The third transistor T23 can conduct in response to the input of the subsequent carry signal C(k + 2) to electrically connect the Q node and the QH node. Therefore, when the third transistor T23 and the fourth transistor T24 are both conducting, the Q node and the QH node can be discharged or reset to the level of the third low voltage GVSS3.

[0129] The seventh transistor T27 and the eighth transistor T28 can be connected between a first high voltage line that transmits the first high voltage GVDD1 and the Q node, and between the first high voltage line that transmits the first high voltage GVDD1 and the QH node. The seventh transistor T27 and the eighth transistor T28 can be connected in series.

[0130] The seventh transistor T27 and the eighth transistor T28 can supply the first high voltage GVDD1 to the QH node in response to the voltage of the Q node. When the voltage of the Q node is at a high level, the seventh transistor T27 can conduct to supply the first high voltage GVDD1 to the shared node of the seventh transistor T27 and the eighth transistor T28. The eighth transistor T28 can conduct when the voltage of the Q node is at a high level to electrically connect the shared node and the QH node. Therefore, when the voltage of the Q node is at a high level, the seventh transistor T27 and the eighth transistor T28 can both conduct to supply the first high voltage GVDD1 to the QH node.

[0131] When the first high voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node may increase. Therefore, when a low-level carry signal C(k + 2) is input to the gate of the third transistor T23 to turn off the third transistor T23, due to the voltage difference between the gate voltage of the third transistor 23 and the voltage of the QH node, the third transistor 23 can be maintained in a fully off state. Therefore, the current leakage in the third transistor T23 and the resulting voltage drop at the Q node are reduced or prevented, so that the voltage of the Q node can be stably maintained.

[0132] The Q node and QH node stabilizer 506 can discharge the Q node and the QH node to the level of the third low voltage GVSS3 in response to the voltage of the QB node. The Q node and QH node stabilizer 506 can include a first transistor T31 and a second transistor T32.

[0133] The first transistor T31 and the second transistor T32 can be connected between the Q node and the third low voltage line that transmits the third low voltage GVSS3. The first transistor T31 and the second transistor T32 can be connected in series. The first transistor T31 and the second transistor T32 can discharge the Q node and the QH node to the level of the third low voltage GVSS3 in response to the voltage of the QB node. When the voltage of the QB node is at a high level, the second transistor T32 is turned on to supply the third low voltage GVSS3 to the shared node of the first transistor T31 and the second transistor T32. When the voltage of the QB node is at a high level, the first transistor T31 can be turned on to electrically connect the Q node and the QH node. Therefore, when the first transistor T31 and the second transistor T32 are turned on simultaneously in response to the voltage of the QB node, the Q node and the QH node can be discharged or reset to the level of the third low voltage GVSS3.

[0134] The inverter 508 can change the voltage level of the QB node in response to the voltage level of the Q node. The inverter 508 can include a first transistor T41 to a fifth transistor T45. The second transistor T42 and the third transistor T43 can be connected between the second high voltage line that transmits the second high voltage GVDD2 and the third connection node NC3. The second transistor T42 and the third transistor T43 can be connected in series.

[0135] The second transistor T42 and the third transistor T43 may supply the second high voltage GVDD2 to the third connection node NC3 in response to the second high voltage GVDD2. The second transistor T42 may be turned on by the second high voltage GVDD2 to supply the second high voltage GVDD2 to the shared node of the second transistor T42 and the third transistor T43. The third transistor T43 may be turned on by the second high voltage GVDD2 to electrically connect the shared node of the second transistor T42 and the third transistor T43 to the third connection node NC3. Accordingly, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high voltage GVDD2, the third connection node NC3 may be charged to the level of the second high voltage GVDD2.

[0136] The fourth transistor T44 may be connected between the third connection node NC3 and the second low voltage line that transmits the second low voltage GVSS2. The fourth transistor T44 may supply the second low voltage GVSS2 to the third connection node NC3 in response to the voltage of the Q node. When the voltage of the Q node is at a high level, the fourth transistor T44 may be turned on to discharge or reset the third connection node NC3 to the second low voltage GVSS2.

[0137] The first transistor T41 may be connected between the QB node and the second high voltage line that transmits the second high voltage GVDD2. The first transistor T41 may supply the second high voltage GVDD2 to the QB node in response to the voltage of the third connection node NC3. When the voltage of the third connection node NC3 is at a high level, the first transistor T41 may be turned on to charge the QB node to the level of the second high voltage GVDD2.

[0138] The fifth transistor T45 may be connected between the QB node and the third low voltage line that transmits the third low voltage GVSS3. The fifth transistor T45 may supply the third low voltage GVSS3 to the QB node in response to the voltage of the Q node. When the voltage of the Q node is at a high level, the fifth transistor T45 may be turned on to discharge or reset the QB node to the level of the third low voltage GVSS3.

[0139] The QB node stabilizer 510 may discharge the QB node to the level of the third low voltage GVSS3 in response to the input of the carry signal C(k - 2), the input of the reset signal, and the voltage charged at the M node. The QB node stabilizer 510 may include a first transistor T51 to a third transistor T53.

[0140] The first transistor T51 can be connected between the QB node and the second low-voltage line that transmits the third low voltage GVSS3. The first transistor T51 can supply the third low voltage GVSS3 to the QB node in response to the input of the carry signal C(k - 2). When the voltage of the Q node is at a high level, the fifth transistor T45 can conduct to discharge or reset the QB node to the level of the third low voltage GVSS3.

[0141] The second transistor T52 and the third transistor T53 can be connected between the QB node and the third low-voltage line that transmits the third low voltage GVSS3. The second transistor T52 and the third transistor T53 can be connected in series. The second transistor T52 and the third transistor T53 can discharge the QB node to the level of the third low voltage GVSS3 in response to the input of the reset signal and the voltage charged at the M node. When the voltage of the M node is at a high level, the third transistor T53 can conduct to supply the third low voltage GVSS3 to the common node of the second transistor T52 and the third transistor T53. The second transistor T52 can conduct in response to the input of the reset signal RESET to electrically connect the shared node of the second transistor T52 and the third transistor T53 to the QB node. Therefore, when the reset signal RESET is input while the voltage at the M node is at a high level, the second transistor T52 and the third transistor T53 conduct simultaneously, so that the QB node can be discharged or reset to the level of the third low voltage GVSS3.

[0142] The carry signal output unit 512 can output the carry signal C(k) based on the voltage level of the Q node or the voltage level of the QB node, and based on the voltage level of the carry clock signal CRCLK(k) or the level of the third low voltage GVSS3. The carry signal output unit 512 can include a first transistor T61, a second transistor T62, and a boost capacitor CC.

[0143] The first transistor T61 can be connected between the clock signal line that transmits the carry clock signal CRCLK(k) and the first output node NO1. The boost capacitor CC can be connected between the gate and the source of the first transistor T61.

[0144] The first transistor T61 can output the high-voltage carry signal C(k) through the first output node NO1 based on the carry clock signal CRCLK(k) in response to the voltage of the Q node. When the voltage of the Q node is at a high level, the first transistor T61 can conduct to supply the high-voltage carry clock signal CRCLK(k) to the first output node NO1. Therefore, the high-voltage carry signal C(k) can be output.

[0145] When the output carry signal C(k) is generated, the boost capacitor CC can bootstrap the voltage of the Q node to a boost voltage level higher than the level of the first high voltage GVDD1 synchronously with the high voltage carry clock signal CRCLK(k). When the voltage of the Q node is bootstrapped, the high voltage carry clock signal CRCLK(k) can be output quickly without distortion as the carry signal C(k).

[0146] The second transistor T62 can be connected between the first output node NO1 and the third low voltage line that transmits the third low voltage GVSS3. The second transistor T62 can output the low voltage carry signal C(k) to the first output node NO1 based on the third low voltage GVSS3 in response to the voltage of the QB node. When the voltage of the QB node is at a high level, the second transistor T62 can be turned on to supply the third low voltage GVSS3 to the first output node NO1. Accordingly, the low voltage carry signal C(k) can be output.

[0147] The scan signal output unit 514 can output a plurality of scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) based on the voltage levels of the plurality of scan clock signals SCCLK(i) (i is a positive integer), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3) or the levels of the first low voltages GVSS1A to GVSS1D transmitted through the first low voltage line according to the voltage level of the Q node or the voltage level of the QB node. The scan signal output unit 514 can include a first transistor T71 to an eighth transistor T78 and boost capacitors CS1, CS2, CS3, and CS4. The first transistor T71 to the eighth transistor T78 can be divided into a pull-up buffer TFT and a pull-down buffer TFT.

[0148] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can be respectively connected between the clock signal lines that transmit the scan clock signals SCCLK(i), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3) and the second output node NO2 to the fifth output node NO5. The boost capacitors CS1, CS2, CS3, and CS4 can be respectively connected between the gates and sources of the first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77.

[0149] The first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can output high-voltage scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) through the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5 respectively in response to the voltage of the Q node, based on the scan clock signals SCCLK(i), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3). When the voltage of the Q node is at a high level, the first transistor T71, the third transistor T73, the fifth transistor T75, and the seventh transistor T77 can be turned on to supply the high-voltage scan clock signals SCCLK(i), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3) to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5 respectively. Accordingly, the high-voltage scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) can be output.

[0150] When the scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) are output, the boost capacitors CS1, CS2, CS3, and CS4 can bootstrap or increase the voltage of the Q node to a boost voltage level higher than the level of the first high voltage GVDD1 synchronously with the high-voltage scan clock signals SCCLK(i), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3). When the voltage of the Q node is bootstrapped, the high-voltage scan clock signals SCCLK(i), SCCLK(i + 1), SCCLK(i + 2), and SCCLK(i + 3) can be output quickly without distortion as the scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3).

[0151] The second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can output low-voltage scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) through a second output node NO2, a third output node NO3, a fourth output node NO4, and a fifth output node NO5, respectively, in response to the voltage of the QB node, based on a first low voltage GVSS1. When the voltage of the QB node is at a high level, the second transistor T72, the fourth transistor T74, the sixth transistor T76, and the eighth transistor T78 can be turned on to supply the first low voltage GVSS1 to the second output node NO2, the third output node NO3, the fourth output node NO4, and the fifth output node NO5, respectively. Accordingly, the low-voltage scan signals SCOUT(i), SCOUT(i + 1), SCOUT(i + 2), and SCOUT(i + 3) can be output.

[0152] In Figure 14 three high voltages GVDD1, GVDD2, and GVDD3 set to different levels and three low voltages GVSS1A to GVSS1D, GVSS2, and GVSS3 set to different levels can be supplied to the stage circuit. For example, the first high voltage GVDD1 can be set to 20V, the second high voltage GVDD2 can be set to 16V, the third high voltage GVDD3 can be set to 14V, the first low voltages GVSS1A to GVSS1D can be set to -6V, the second low voltage GVSS2 can be set to -10V, and the third low voltage GVSS3 can be set to -12V. However, this is merely an example, and the levels of the high voltage and the low voltage can be set differently according to the driving method of the device, etc.

[0153] In addition, Figures 7 to 13 the configuration for sensing described in Figure 6 can be applied to the scan signal output unit 514. For example, Figure 6 the first pull-up sensing switch SW_L and the second pull-up sensing switch SW_R in

[0154] Figure 15 and Figure 16 are diagrams showing a display device according to the second embodiment. Figure 15 is a circuit diagram for describing the GIP driving method when sensing the threshold voltage of the sensing buffer TFT in the display device according to the second embodiment.Figure 16 FIG. is a diagram showing a hierarchical connection method of a display device according to a second embodiment.

[0155] The display device according to the first embodiment of the present disclosure can operate in a driving mode by connecting a buffer TFT to a clock line, or can operate in a sensing mode by connecting the buffer TFT to an initialization line IN or a sensing line ADC or floating it. Since the GIP outputs scan signals sequentially, the Q-node voltage is applied sequentially as a high-voltage signal. Using this principle, during the sensing mode operation in the first embodiment, the high-level Q-node voltage can be applied to the gate electrode of the pull-up buffer TFT. Therefore, during the sensing mode operation, the gate electrode of the pull-up buffer TFT can be floated with a high voltage. When sensing the threshold voltage of the pull-up buffer TFT, the display device according to the second embodiment of the present disclosure can further improve the accuracy of the sensed value by performing the process of sensing the threshold voltage of the pull-up buffer TFT in a state where the GVDD voltage is applied to the gate electrode of the pull-up buffer TFT.

[0156] Figure 15 FIG. shows a case of sensing the threshold voltage of the pull-up buffer TFT T6 of the second GIP GIP_R in a state where the first GIP GIP_L outputs a scan signal and the second GIP GIP_R is in a non-driving state R of the second GIP GIP_R.

[0157] Referring to Figure 15 FIG., when sensing the threshold voltage of the pull-up buffer TFT T6 R of the second GIP GIP_R, the threshold voltage of the buffer TFT of the second GIP GIP_R can be sensed in a state where the GVDD voltage is applied to the Q node to which the gate electrode of the pull-up buffer TFT T6 R of the second GIP GIP_R is connected.

[0158] The threshold voltage of the second pull-up buffer TFT T6 R can be sensed by scan line charging, source following, and sampling and holding.

[0159] The source following operation for sensing the threshold voltage of the second pull-up buffer TFT T6 R can be performed in the saturation region of the TFT. Therefore, in order to sense the threshold voltage Vth of the second pull-up buffer TFT T6 R of the second GIP GIP_R, it is necessary to satisfy Vgs-Vth>Vds of the second pull-up buffer TFT T6 R of the second GIP GIP_R. When applied to Figure 15When the second GIP GIP_R is involved, the strobe voltage can be represented by the Q-node voltage VQ, the clock voltage VCLK, and the scan voltage VSCAN. Therefore, if the Q-node voltage VQ is maintained at GVDD and VQ - VCLK - Vth < VSCAN - VCLK, the second pull-up buffer TFT T6 can be sensed through source follower operation. R The threshold voltage Vth. This formula can be reset to VQ - Vth > VSCAN. In the display device according to the second embodiment, during the sensing of the threshold voltage of the buffer TFT, the Q-node voltage VQ is fixed at GVDD, so the accuracy can be improved during Vth sensing and calculation.

[0160] Figure 15 shows in a stage with Figure 14 the circuit configuration, the clock input state when the Q-node voltage VQ is used as GVDD. As Figure 15 shown, when the carry start signal CRIN_Qstart(C(K - 2)) of the (n - 2)th stage is input to the line selector 502, during the threshold voltage sensing period of the second pull-up buffer TFT T6 R , the Q-node voltage VQ can be maintained at GVDD. Thereafter, when the carry end signal CRIN_Qend(C(K + 1)) of the (n - 1)th stage is input to the Q-node controller 504, the Q-node voltage VQ can be discharged to GVSS0. That is, as Figure 16 shown, by providing a configuration where a start carry pulse is input to the (n - 2)th stage and an end carry pulse is transmitted to the (n + 1)th stage, a GVDD voltage can be applied to the gate electrode of the pull-up buffer TFT when sensing the threshold voltage of the pull-up buffer TFT.

[0161] The second embodiment of the present disclosure shows a case where, when using Figure 14 the start carry pulse and the end carry pulse in the stage circuit shown to sense the threshold voltage of the pull-up buffer TFT, a GVDD voltage is applied to the gate electrode of the pull-up buffer TFT. However, the circuit configuration of the stage circuit and the method of connecting the start carry pulse and the end carry pulse are not limited thereto, and various circuits and connection methods can be applied so that a GVDD voltage can be applied to the gate of the pull-up buffer TFT when the threshold voltage of the pull-up buffer TFT is sensed.

[0162] Figure 17 is a diagram showing some components included in a display device according to an embodiment of the first example, Figure 18 is a diagram showing some components included in a display device according to an embodiment of the second example, and Figure 19 is a diagram showing some components included in a display device according to an embodiment of the third example.

[0163] As Figure 17 shown, according to the first example, a sensing unit (200, refer to Figure 6 ) that obtains a sensing voltage V_Sen from a buffer TFT included in the GIP and generates GIP sensing information GIP_sen can be implemented in the data driver SDIC. The data driver including the sensing unit can be defined as SDIC_sen. The data driver SDIC_sen including the sensing unit can be disposed on two edges of the third circuit board F-PCB, but the present disclosure is not limited thereto.

[0164] The data driver SDIC_sen including the sensing unit can generate GIP sensing information GIP_sen based on the sensing voltage V_Sen received from the buffer TFT included in the GIP, and send it to the compensation circuit 300. The data driver SDIC_sen including the sensing unit can include a sample-and-hold circuit that samples and holds the sensing voltage V_Sen and a digital-to-analog converter (DAC) that converts the sensing voltage V_Sen into a digital signal.

[0165] The compensation circuit 300 can generate a compensation value GIP_comp for compensating GVDD based on the GIP sensing information GIP_sen, and provide the generated compensation value GIP_comp to the GIP driving circuit 310. The compensation circuit 300 can include a compensation controller 320 and a look-up table 330. The look-up table 330 can store GVDD setting values according to the threshold voltage change of the buffer TFT. The compensation controller 320 can generate a compensation value GIP_comp corresponding to the GIP sensing information GIP_sen based on the look-up table 330, and provide the compensation value GIP_comp to the GIP driving circuit 310.

[0166] The GIP driving circuit 310 can output a GIP driving signal GIP_Drive by adjusting the voltage level of GVDD supplied to the GIP according to the compensation value GIP_comp received from the compensation circuit 300. The GIP driving signal GIP_Drive can include a control signal and a voltage signal for driving the GIP.

[0167] According to the above first example, a sensing unit that generates GIP sensing information GIP_sen can be implemented within the data driver SDIC to compensate the voltage level of GVDD according to the threshold voltage change of the buffer TFT.

[0168] As Figure 18 shown, according to the second example, a sensing unit (200, refer toFigure 6 )。200a represents the sensing unit included in the GIP driving circuit 310. The sensing unit 200a may include a sample-and-hold circuit that samples and holds the sensed voltage V_Sen and a DAC that converts the sensed voltage V_Sen into a digital signal. The GIP driving circuit 310 including the sensing unit 200a may be disposed on the first circuit board C-PCB, but the present disclosure is not limited thereto.

[0169] The data driver SDIC may receive the sensed voltage V_Sen from the buffer TFT included in the GIP and transmit the sensed voltage V_Sen to the GIP driving circuit 310 including the sensing unit 200a.

[0170] The sensing unit 200a included in the GIP driving circuit 310 may generate GIP sensing information GIP_sen based on the sensed voltage V_Sen received from the buffer TFT included in the GIP and transmit the sensing information GIP_Sen to the compensation circuit 300.

[0171] The compensation circuit 300 may generate a compensation value GIP_comp for compensating GVDD based on the GIP sensing information GIP_sen and provide the generated compensation value GIP_comp to the GIP driving circuit 310.

[0172] The GIP driving circuit 310 may output a GIP driving signal GIP_Drive by adjusting the voltage level supplied to the GIP according to the compensation value GIP_comp received from the compensation circuit 300.

[0173] As Figure 19 shown, according to the third example, a sensing unit 200b that obtains the sensed voltage V_Sen from the buffer TFT included in the GIP and generates GIP sensing information GIP_sen may be independently implemented. The sensing unit 200b may include a sample-and-hold circuit that samples and holds the sensed voltage V_Sen and a DAC that converts the sensed voltage V_Sen into a digital signal. The sensing unit 200b may be independently disposed on the first circuit board C-PCB in the form of a chip, but the present disclosure is not limited thereto.

[0174] The data driver SDIC may receive the sensed voltage V_Sen from the buffer TFT included in the GIP and transmit the sensed voltage V_Sen to the sensing unit 200b.

[0175] The sensing unit 200b may generate GIP sensing information GIP_sen based on the sensed voltage V_Sen received from the buffer TFT included in the GIP and transmit the sensing information GIP_Sen to the compensation circuit 300.

[0176] The compensation circuit 300 can generate a compensation value GIP_comp for compensating GVDD based on the GIP sensing information GIP_sen, and provide the generated compensation value GIP_comp to the GIP driving circuit 310.

[0177] The GIP driving circuit 310 can adjust the voltage level of GVDD supplied to GIP according to the compensation value GIP_comp received from the compensation circuit 300, and output a GIP driving signal GIP_Drive.

[0178] Figure 20 is an analog result showing that the voltage of the clock signal changes according to the change in the threshold voltage of the pull-up buffer TFT.

[0179] From Figure 20 it can be determined that although the voltages of the Q node and the clock signal line can be maintained at the threshold voltage T6 Vth of the pull-up buffer TFT, when the threshold voltage T6 Vth of the pull-up buffer TFT changes, the voltage of the Q node also changes.

[0180] Figure 21 is an analog result showing the difference between the normal voltage and the abnormal voltage detected by sensing when a strong short circuit occurs in the gate, drain, and source of the pull-up buffer TFT; Figure 22 is an analog result showing the difference between the normal voltage and the abnormal voltage detected by sensing when a short circuit occurs between the gate and the source, between the gate and the drain, and between the drain and the source of the pull-down buffer TFT; and Figure 23 is an analog result showing the difference between the normal voltage and the abnormal voltage detected by sensing when a short circuit occurs due to a foreign object in the display area.

[0181] As Figures 21 to 23 shown, the display device according to the embodiment can detect whether a short circuit has occurred in the buffer TFT, whether a defect has occurred after the short circuit, and whether a short circuit has occurred due to a foreign object based on the sensing value obtained from the buffer TFT included in the gate driver. Additionally, in Figures 21 to 23 the waveforms without the label "normal" indicate a short circuit or an abnormality. Furthermore, Figures 21 to 23 it should be understood as an example showing that the display device according to the embodiment can be used not only for sensing and compensation purposes but also for detecting and responding to defects.

[0182] As described above, by detecting the threshold voltage of the buffer TFT included in the gate driver and compensating at least one of the signals and voltages required to drive the gate driver, the present disclosure has the effect of improving driving reliability and driving stability and extending the lifespan of the device. In addition, the present disclosure has the effect of detecting whether there are defects in at least one of the signals and voltages applied to the gate driver by sensing the threshold voltage of the buffer TFT included in the gate driver and responding to the defects.

[0183] Embodiments of the present disclosure may provide a display device and a method of driving the display device, which can improve operational stability.

[0184] Embodiments of the present disclosure may provide a display device and a method of driving the display device, which can improve the operational reliability and operational stability of the gate driver by sensing and compensating the electrical characteristics of the TFTs constituting the gate driver.

[0185] Embodiments of the present disclosure may provide a display device and a method of driving the display device, which can ensure the operational reliability and operational stability of the gate driver by improving the sensing accuracy of the threshold voltage of the TFTs included in the gate driver.

[0186] The effects according to the present disclosure are not limited to the above description, and more various effects are included in the present disclosure.

[0187] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the technical concept or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

[0188] Cross - reference to related applications

[0189] This application claims the priority benefits of Korean Patent Application No. 10 - 2023 - 0197315, filed on December 29, 2023, and Korean Patent Application No. 10 - 2024 - 0130822, filed on September 26, 2024. The entire contents of these two Korean patent applications are incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, comprising: A display panel having a display area including sub-pixels formed thereon; a first panel gate GIP and a second GIP disposed on both sides of the display area, each of the first GIP and the second GIP including a buffer circuit including a plurality of buffer thin film transistors TFT and outputting a scan signal to a scan line connected to the sub-pixel through the buffer circuit; a sensing switch configured to select a signal input to / output from the buffer circuit; a sensing unit configured to control the sensing switch to sense a threshold voltage of a buffer TFT of the second GIP connected to the scan line based on a charged voltage of the scan line charged by the scan signal output from the first GIP; as well as A compensation unit is configured to generate a compensation value for a high potential voltage applied to a related GIP according to the sensed threshold voltage of the buffer TFT.

2. The display device according to claim 1, wherein: The sensing unit controls the sensing switch so that the buffer TFT of the second GIP performs a source follower operation based on the charged voltage of the scan line to sense the threshold voltage of the buffer TFT.

3. The display device according to claim 1, wherein: When the first GIP operates in a driving mode in which the first GIP outputs the scan signal, the sensing unit senses the threshold voltage of the buffer TFT of the second GIP.

4. The display device according to claim 1, wherein: The buffer circuit includes a pull-up buffer TFT and a pull-down buffer TFT, the pull-up buffer TFT is controlled by a Q node voltage input to a gate electrode of the pull-up buffer TFT to output a first scan signal through a first electrode of the pull-up buffer TFT, the pull-down buffer TFT is controlled by a QB node voltage input to a gate electrode of the pull-down buffer TFT to output a second scan signal through the first electrode of the pull-down buffer TFT, and the buffer circuit outputs the first scan signal or the second scan signal according to a clock signal.

5. The display device according to claim 4, wherein: The sensing switch comprises: a pull-up sensing switch, the pull-up sensing switch being used to connect the second electrode of the pull-up buffer TFT to one of an initialization line, a clock line, and a sensing line or to electrically float the second electrode of the pull-up buffer TFT under the control of the sensing unit, transmit an initialization voltage through the initialization line, transmit the clock signal through the clock line, and obtain a sensing value through the sensing line; and A pull-down sensing switch is used to connect the second electrode of the pull-down buffer TFT to a low potential voltage line or a sensing line or to electrically float the second electrode of the pull-down buffer TFT under the control of the sensing unit, transmit a low potential voltage through the low potential voltage line, and obtain a sensing value through the sensing line.

6. The display device according to claim 5, wherein: The sensing unit connects the second electrode of the pull-up buffer TFT of the second GIP connected to the scan line to the initialization line while the first GIP outputs the first scan signal or the second scan signal to the scan line; floats the second electrode of the pull-up buffer TFT of the second GIP when the output of the first scan signal or the second scan signal is completed; and then obtains a threshold voltage of the pull-up buffer TFT of the second GIP according to a voltage of the second electrode of the pull-up buffer TFT of the second GIP sensed by connecting the second electrode of the pull-up buffer TFT of the second GIP to the sensing line.

7. The display device according to claim 6, wherein: The pull-up buffer TFT of the second GIP performs a source follower operation based on the charged voltage of the scan line reflected in the first electrode of the pull-up buffer TFT of the second GIP.

8. The display device according to claim 7, wherein: The pull-up buffer TFT of the second GIP receives the high potential voltage applied to the gate electrode of the pull-up buffer TFT of the second GIP and operates in a saturation region.

9. The display device according to claim 5, wherein: The sensing unit connects the second electrode of the pull-down buffer TFT of the second GIP connected to the scan line to the low potential voltage line while the first GIP outputs the first scan signal or the second scan signal to the scan line; floats the second electrode of the pull-down buffer TFT of the second GIP when the output of the first scan signal or the second scan signal is completed; and then obtains a threshold voltage of the pull-down buffer TFT of the second GIP according to a voltage of the second electrode of the pull-down buffer TFT of the second GIP sensed by connecting the second electrode of the pull-down buffer TFT of the second GIP to the sensing line.

10. The display device according to claim 9, wherein: The pull-down buffer TFT of the second GIP performs a source follower operation based on the charged voltage of the scan line reflected in the first electrode of the pull-down buffer TFT of the second GIP.

11. The display device according to claim 5, wherein: The sensing unit connects the second electrode of the pull-up buffer TFT of the first GIP to the clock line and connects the second electrode of the pull-down buffer TFT of the first GIP to the low potential voltage line while the first GIP outputs the first scan signal or the second scan signal to the scan line.

12. A method for driving a display device, the display device comprising a display panel, a display area including sub-pixels formed on the display panel; a first GIP and a second GIP disposed on both sides of the display panel, each of the first GIP and the second GIP comprising a buffer circuit including a plurality of buffer TFTs, and outputting a scan signal to a scan line connected to the sub-pixel through the buffer circuit, the method comprising the following steps: Outputting a scan signal from the first GIP to a scan line; sensing a threshold voltage of a buffer TFT of the second GIP connected to the scan line based on a charged voltage of the scan line charged by the scan signal; as well as According to the sensed threshold voltage of the buffer TFT, a correction value is generated for a high potential voltage applied to a related GIP.

13. The method according to claim 12, wherein: The buffer circuit comprises: a pull-up buffer TFT, the pull-up buffer TFT being controlled by a Q-node voltage input to a gate electrode of the pull-up buffer TFT to output a first scan signal through a first electrode of the pull-up buffer TFT; and A pull-down buffer TFT is controlled by a QB node voltage input to a gate electrode of the pull-down buffer TFT to output a second scan signal through a first electrode of the pull-down buffer TFT.

14. The method according to claim 13, wherein: The step of sensing the threshold voltage of the buffer TFT of the second GIP comprises the following steps: applying an initialization voltage to a second electrode of a pull-up buffer TFT of the second GIP connected to the scan line while the first GIP outputs the first scan signal or the second scan signal to the scan line; When the output of the first scanning signal or the second scanning signal is completed, floating the second electrode of the pull-up buffer TFT of the second GIP; and A threshold voltage of the pull-up buffer TFT of the second GIP is obtained according to a voltage of the second electrode of the pull-up buffer TFT of the second GIP sensed by connecting the second electrode of the pull-up buffer TFT of the second GIP to a sensing line.

15. The method according to claim 13, wherein: The step of sensing the threshold voltage of the buffer TFT of the second GIP comprises the following steps: while the first GIP outputs the first scan signal or the second scan signal to the scan line, applying a low potential voltage to a second electrode of a pull-down buffer TFT of the second GIP connected to the scan line; When the output of the first scan signal or the second scan signal is completed, floating the second electrode of the pull-down buffer TFT of the second GIP; and A threshold voltage of the pull-down buffer TFT of the second GIP is obtained according to a voltage of the second electrode of the pull-down buffer TFT of the second GIP sensed by connecting the second electrode of the pull-down buffer TFT of the second GIP to a sensing line.

16. The method according to claim 13, wherein: Outputting a scan signal from the first GIP to a scan line includes connecting a second electrode of a pull-up buffer TFT of the first GIP to a clock line and connecting a second electrode of a pull-down buffer TFT of the first GIP to a low potential voltage line.

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