Variable frequency display device and flicker compensation method thereof

Abstract

A frequency variable display device includes: a display panel in which a plurality of sub-pixels are disposed; an image driving circuit configured to write an input image into the plurality of sub-pixels during a vertical activity period in which a data enable signal of one frame swings, to achieve a target brightness in the plurality of sub-pixels; and a flicker compensation circuit configured to cause a leakage current to flow from the plurality of sub-pixels to the signal lines corresponding thereto in a vertical blanking period in which the data enable signal of the one frame does not swing, to achieve flicker compensation brightness lower than the target brightness in the plurality of sub-pixels.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the benefit of Korean Patent Application No. 10 - 2023 - 0197157, filed on December 29, 2023, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a frequency - variable display device and a method for compensating for flicker thereof. Background art

[0004] A frequency - variable display device changes the frame rate of an image displayed on a screen based on the attributes of video data received from an external video source. The frequency - variable display device supports a variable refresh rate (VRR) function that changes the frame rate within a predetermined frequency range.

[0005] When the frame rate is rapidly changed from a low - speed frame to a high - speed frame or vice versa through VRR operation, a user can recognize a flicker phenomenon caused by a recognition brightness deviation. To reduce the recognition brightness deviation, a brightness algorithm technique that adjusts data gain using the frame rate is known.

[0006] However, in the VRR mode, frequency information about the current frame may not be known until the end of the current frame. Therefore, conventional brightness algorithm techniques determine the data gain of the current frame based on the frequency information of the previous frame, and for this reason, there are limitations in reducing the recognition brightness deviation between the first frame immediately after a rapid change in the frame rate and the frame immediately before the first frame. Summary of the invention

[0007] To overcome the above problems of the prior art, the present disclosure can provide a frequency - variable display device and a method for compensating for flicker thereof, which can reduce the recognition brightness deviation that occurs under conditions of rapid change in the frame rate.

[0008] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a frequency - variable display device includes: a display panel in which a plurality of sub - pixels are provided; an image driving circuit configured to write an input image into the plurality of sub - pixels during a vertical active period in which a data enable signal of a frame swings, to achieve a target brightness in the plurality of sub - pixels; and a flicker compensation circuit configured to cause leakage current to flow from the plurality of sub - pixels to corresponding signal lines during a vertical blanking period in which the data enable signal of the frame does not swing, to achieve a flicker - compensated brightness lower than the target brightness in the plurality of sub - pixels.

[0009] In another aspect of the present disclosure, a method for flicker compensation of a variable-frequency display device, the variable-frequency display device including a display panel provided with a plurality of sub-pixels, the method including: writing an input image into the plurality of sub-pixels during a vertical active period in which a data enable signal of a frame swings, to achieve a target brightness in the plurality of sub-pixels, and causing leakage current to flow from the plurality of sub-pixels to corresponding signal lines during a vertical blanking period in which the data enable signal of the frame does not swing, to achieve a flicker compensation brightness lower than the target brightness in the plurality of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0011] Figure 1 is a block diagram showing a variable-frequency display device according to the present embodiment;

[0012] Figure 2 is a view showing a connection configuration of a pixel according to the present embodiment;

[0013] Figure 3 is a view showing a vertical active period and a vertical blanking period constituting a frame time;

[0014] Figure 4 is a view showing an example in which the length of a vertical front edge included in a vertical blanking period varies based on the level of a frame frequency;

[0015] Figure 5 is a view showing an example of changing a recognition brightness based on the level of a frame frequency;

[0016] Figure 6 is a view showing a recognition brightness deviation occurring under a condition of a rapid change in frame frequency;

[0017] Figure 7 and Figure 8 is a view showing an example in which the visibility of a recognition brightness deviation occurring under a condition of a rapid change in frame frequency at a high gray level is higher than that at a low gray level;

[0018] Figure 9 is a view showing a configuration of a flicker compensation circuit according to the present embodiment;

[0019] Figure 10 and Figure 11 is a driving timing diagram for describing a brightness control operation of a flicker compensation circuit;

[0020] Figure 12is a view for describing the operation of a sub - pixel in a vertical front according to the present embodiment;

[0021] Figure 13 is a view showing a setting range of a gate - cut - off control voltage that allows leakage current to flow in a switching transistor of a sub - pixel in a vertical front;

[0022] Figure 14 is a view showing the relative magnitude of identifying a luminance deviation in the case of implementing a luminance control operation in a vertical front or the like;

[0023] Figure 15 is a view showing an example of proportionally and gradually adjusting the level of a gate - cut - off control voltage in real - time with respect to the length of a vertical front;

[0024] Figure 16 is a view showing an example of proportionally and linearly adjusting the level of a gate - cut - off control voltage in real - time with respect to the length of a vertical front; and

[0025] Figure 17 is a view showing a method of compensating for flicker of a frequency - variable display device according to the present embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0027] The advantages and features of the present disclosure and methods for realizing them will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is defined only by the scope of the claims.

[0028] The various embodiments disclosed in the accompanying drawings for describing the present disclosure, such as the shapes, sizes, ratios, angles, quantities, etc. of the embodiments of the present disclosure, are merely exemplary, and the present disclosure is not limited thereto. The same reference numerals always denote the same elements. Throughout the specification, the same elements are denoted by the same reference numerals. As used herein, terms such as "comprising", "having", "including", etc. indicate that other parts may be added, unless the term "only" is used. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0029] Elements in the various embodiments of the present disclosure will be construed to include a margin of error even if not explicitly stated.

[0030] When describing positional relationships, for example, when the positional relationship between two parts is described as "on", "above", "below", and "next to", one or more other parts may be provided between the two parts unless the terms "exactly" or "directly" are used.

[0031] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0032] In the following description, when a detailed description of related known functions or configurations is determined to unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram showing a frequency variable display device according to the present embodiment.

[0034] Referring to Figure 1 , the display panel 100 may include a screen AA for displaying an input image. The screen AA may include a pixel array for displaying pixel data (hereinafter referred to as "image data") DATA of the input image. The pixel array may include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, a plurality of reference voltage lines, and a plurality of pixels.

[0035] The pixels may be arranged on the screen AA in a matrix type defined by the data lines DL, the gate lines GL, and the reference voltage lines. The pixels may be arranged on the screen AA in various types, such as a stripe type, a diamond type, and a matrix type.

[0036] The pixel array may include a plurality of pixel columns and a plurality of pixel rows L1 to Ln intersecting the pixel columns. Each pixel column may include pixels arranged in the Y-axis direction. The pixel rows may include pixels arranged in the X-axis direction. One vertical period may be one frame period required to write image data DATA of one frame in all pixels of the screen. One horizontal period may be a time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period may be a time required to write image data DATA of one pixel row sharing a gate line GL in the pixels of one pixel row.

[0037] Each pixel may include a red (R) sub-pixel 101, a green (G) sub-pixel 101, a blue (B) sub-pixel 101, and a white (W) sub-pixel 101 for implementing colors.

[0038] The frequency-variable display device according to the present embodiment may be implemented as an electroluminescent display device. In this case, the pixel circuit of the frequency-variable display device may include a light-emitting device, a driving element, one or more switching elements, and a capacitor. The light-emitting device may be implemented as an organic light-emitting diode (OLED) or an inorganic light-emitting diode. The driving current that allows the light-emitting device to emit light may be adjusted based on the gate-source voltage of the driving element. Each of the driving element and the switching element may be implemented as a transistor. The semiconductor layer of the transistor may include amorphous silicon or polycrystalline silicon. The semiconductor layer of at least some of the transistors may include an oxide. The pixel circuit may be connected to a data line DL and a gate line GL. In Figure 1 the figure, “D1 to D3” shown in the circle may be data lines, and “Gn-2 to Gn” may be gate lines. Additionally, each of the sub-pixels 101 may include the same pixel circuit.

[0039] A touch sensor may be provided on the display panel 100. The touch sensor may be arranged in an on-cell or add-on type on the screen AA of the display panel 100, or may be implemented as an in-cell type touch sensor embedded in the pixel array. Touch input may be sensed through the touch sensor, or may be sensed only through the pixels even without a touch sensor.

[0040] The source driver 110 may convert the image data DATA received from the timing controller 130 into a gamma-compensated voltage by using a digital-to-analog converter (DAC) to generate a data voltage. The source driver 110 may provide the data voltage to the data lines DL. The data voltage may be provided to the data lines DL and may be applied to the gate electrodes of the driving elements through the switching elements of the sub-pixels 101. The source driver 110 may supply a reference voltage received from the power supply circuit 200 to the reference voltage line. The reference voltage may be provided to the reference voltage line and may be applied to the source electrodes of the driving elements through the switching elements of each sub-pixel 101.

[0041] The source driver 110 may be implemented by using one or more source driver integrated circuits (ICs). The source driver IC may be connected to the timing controller 130 through an internal interface circuit. The internal interface circuit may be implemented as an embedded clock point-to-point interface (EPI). The source driver IC may further include a touch driver. The touch driver may generate a touch sensor driving signal and may convert the charge change of the touch sensor into touch raw data. The touch driver may transmit the touch raw data to a host system (not shown) through a separate interface circuit. The separate interface circuit may be implemented as a serial peripheral interface (SPI).

[0042] The gate driver 120 may be disposed in the border area BZ that is located outside the screen and does not display an image on the display panel 100. The gate driver 120 may sequentially provide gate signals synchronized with the data voltage to the gate lines GL according to the control of the timing controller 130. The gate signals may simultaneously activate the pixel rows into which the data voltage is charged. The gate driver 120 may output the gate signals by using one or more shift registers and may shift the gate signals. The gate signals may include one or more scan signals and emission control signals. The gate signals (or scan signals) may include a gate-on voltage VON and a gate-off voltage VOFF received from the power supply circuit 200, and a three-level scan signal based on the gate-off control voltage received from the flicker compensation circuit 150.

[0043] The timing controller 130 may receive video data DATA and a timing signal synchronized with the video data DATA from a host system (not shown). The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync may define a vertical period (i.e., one frame). The horizontal synchronization signal Hsync may define a horizontal period. The data enable signal DE may define the time for transmitting the video data DATA during the vertical period (i.e., the vertical active period). Another time of the vertical period other than the vertical active period may be a vertical blanking period. The data enable signal DE may swing during the vertical active period and may not swing during the vertical blanking period.

[0044] The timing controller 130 may generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0045] The host system is one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an in-vehicle display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and the level shifter 140 may be integrated into one driving IC.

[0046] The level shifter 140 may shift the logic voltage of the gate timing control signal GDC output from the timing controller 130 to a gate-on voltage VON or a gate-off voltage VOFF to be provided to the gate driver 120. The low logic voltage of the gate timing control signal GDC may be shifted to the gate-off voltage VOFF, and the high logic voltage of the gate timing control signal GDC may be shifted to the gate-on voltage VON.

[0047] The source driver 110 and the gate driver 120 may constitute an image driving circuit. The image driving circuit may write an input image into the sub-pixels 101 during the vertical active period of one frame to achieve a target luminance in the sub-pixels 101.

[0048] The flicker compensation circuit 150 can cause the leakage current to flow from the sub-pixel 101 to its corresponding signal lines (i.e., the data line and the reference voltage line) during the vertical blanking period of one frame, so as to achieve a flicker compensation brightness lower than the target brightness in the sub-pixel 101. When the frame frequency changes, the length of the vertical active period can be fixed, but the length of the vertical blanking period can change. The flicker compensation circuit 150 can cause the leakage current during the vertical blanking period to reduce the brightness achieved in the sub-pixel 101, and thus, can reduce the recognition brightness deviation between frames that occurs under the condition of a rapid change in the frame frequency.

[0049] The flicker compensation circuit 150 can cause the leakage current during the vertical blanking period to output a gate cut-off control voltage between the gate-on voltage VON and the gate-off voltage VOFF to the gate driver 120. Therefore, the gate-on voltage VON, the gate-off voltage VOFF, and a three-level scan signal based on the gate cut-off control voltage can be generated from the gate driver 120. The flicker compensation circuit 150 can adjust the level of the gate cut-off control voltage based on the change in the length of the vertical blanking period.

[0050] The flicker compensation circuit 150 can also output a first fixed voltage to the data line DL, and can also output a second fixed voltage to the reference voltage line, so as to reduce the brightness achieved by the sub-pixel during the vertical blanking period. During the vertical blanking period, the gate-source voltage of the driving element can be relatively reduced by the first fixed voltage, and thus, the current flowing in the driving element can be reduced. Based on the second fixed voltage, the leakage current flowing to the reference voltage line can increase, and thus, the current flowing in the light-emitting device can be reduced.

[0051] The flicker compensation circuit 150 can be integrated into the power supply circuit 200.

[0052] The power supply circuit 200 can generate various source voltages required for panel driving. The power supply circuit 200 can generate the gate-on voltage VON and the gate-off voltage VOFF required for generating the scan signal, generate the high-level source voltage EVDD and the low-level source voltage EVSS to be provided to each sub-pixel 101, and generate the reference voltage Vref to be provided to the reference voltage line.

[0053] Figure 2 is a view showing the connection configuration of one pixel PXL according to the present embodiment.

[0054] Reference Figure 2, a pixel PXL may include four sub-pixels SP1 to SP4 sharing a reference voltage line RL. The four sub-pixels SP1 to SP4 may be R, G, B, and W sub-pixels for forming the same pixel. Each of the sub-pixels SP1 to SP4 may include, for example, a light-emitting device EL, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1, and a second switching transistor ST2.

[0055] The light-emitting device EL may emit light using a driving current provided from the driving transistor DT to achieve brightness. The anode electrode of the light-emitting device EL may be connected to the second node N2, and its cathode electrode may be connected to the input terminal of a low-level source voltage EVSS. In the same frame, the amount of current flowing through the light-emitting device EL may be reduced more in the vertical blanking period than in the vertical active period. This may be caused by a leakage current occurring in the vertical blanking period.

[0056] The driving transistor DT may generate a driving current based on its gate-source voltage to supply to the light-emitting device EL. The gate electrode of the driving transistor DT may be connected to the first node N1, its drain electrode may be connected to the input terminal of a high-level source voltage EVDD, and its source electrode may be connected to the second node N2. In the same frame, the gate-source voltage of the driving transistor DT may be reduced more in the vertical blanking period than in the vertical active period. This may be caused by a leakage current occurring in the vertical blanking period.

[0057] The gate electrode of the first switching transistor ST1 may be connected to the gate line GL. The first electrode of the first switching transistor ST1 may be connected to the data line DL, and its second electrode may be connected to the first node N1.

[0058] The gate electrode of the second switching transistor ST2 may be connected to the gate line GL. The first electrode of the second switching transistor ST2 may be connected to the reference voltage line RL, and its second electrode may be connected to the second node N2.

[0059] The first electrode of the storage capacitor Cst may be connected to the first node N1, and its second electrode may be connected to the second node N2.

[0060] The first switching transistor ST1 and the second switching transistor ST2 may be turned on based on a scan signal SCAN of a gate conduction voltage in the vertical active period, and thus, the gate electrode of the driving transistor DT may be connected to the data line DL, and the source electrode of the driving transistor DT may be connected to the reference voltage line RL. Therefore, a display programming operation for writing image data may be performed. When the display programming operation is completed in the vertical active period, the first switching transistor ST1 and the second switching transistor ST2 may be turned off based on the scan signal SCAN of a gate cut-off voltage.

[0061] The first switching transistor ST1 and the second switching transistor ST2 can be turned on based on a scan signal SCAN of a gate conduction voltage in a vertical back porch VBP of a vertical blanking period (see Figure 3 ). Accordingly, the gate electrode of the driving transistor DT can be connected to the data line DL, and the source electrode of the driving transistor DT can be connected to the reference voltage line RL. Accordingly, a sensing programming operation for writing sensed data can be performed. When the sensing programming operation is completed in the vertical back porch VBP, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the scan signal SCAN of a gate cut-off voltage.

[0062] The first switching transistor ST1 and the second switching transistor ST2 can be slightly turned on based on a scan signal SCAN of a gate cut-off control voltage in a vertical front porch VFP of a vertical blanking period (see Figure 3 ). Accordingly, a leakage current can be caused between the gate electrode of the driving transistor DT and the data line DL, and a leakage current can be caused between the source electrode of the driving transistor DT and the reference voltage line RL. Accordingly, a flicker compensation operation for reducing an identification luminance deviation occurring under a condition of a rapid change in frame frequency can be performed.

[0063] In addition, in the vertical front porch VFP (see Figure 3 ), a first fixed voltage AFIX1 can be applied to the data line DL, and a second fixed voltage AFIX2 can be applied to the reference voltage line RL in order to effectively reduce luminance. In Figure 2 , "Vdata" can be a data voltage corresponding to image data or sensed data, and "Vref" can be a reference voltage for a display programming operation and a sensing programming operation. The first fixed voltage AFIX1 can be lower than the data voltage Vdata charged to the first node N1 of the sub-pixel during a vertical active period. In addition, the second fixed voltage AFIX2 can be lower than the reference voltage Vref charged to the second node N2 of the sub-pixel during a vertical active period.

[0064] The first switch SW1 and the second switch SW2 can also be connected to the reference voltage line RL. The first switch SW1 can connect an output terminal of the reference voltage Vref or an output terminal of the second fixed voltage AFIX2 to the reference voltage line RL. The second switch SW2 can connect the sensing circuit SU to the reference voltage line RL.

[0065] The first switch SW1 and the second switch SW2 can operate in opposite directions to each other. That is, when the first switch SW1 is connected to the reference voltage line RL, the electrical connection between the second switch SW2 and the reference voltage line RL can be disconnected. On the other hand, when the second switch SW2 is connected to the reference voltage line RL, the electrical connection between the first switch SW1 and the reference voltage line RL can be disconnected.

[0066] When the second switch SW2 is connected to the reference voltage line RL, the sensing operation of the sensing circuit SU can be enabled. The sensing operation of the sensing circuit SU can be performed after the sensing programming operation is completed in the vertical trailing edge, and thus, the change in the electrical characteristics of each sub-pixel (e.g., the change in the threshold voltage of the driving transistor and the change in the electron mobility) can be sensed.

[0067] Figure 3 is a view showing the vertical active period and the vertical blanking period that constitute one frame time. Figure 4 is a view showing an example in which the length of the vertical leading edge included in the vertical blanking period varies based on the level of the frame frequency.

[0068] Reference Figure 3 , one frame time (vertical period) can be defined by the vertical synchronization signal Vsync. One frame time (vertical period) can be defined as the time interval between adjacent falling edges (or rising edges) of the vertical synchronization signal Vsync.

[0069] The vertical active period ACT and the vertical blanking period BLK in one frame time (vertical period) can be defined by the data enable signal DE. The vertical active period ACT can be the period during which the data enable signal DE swings, and the vertical blanking period BLK can be the period during which the data enable signal DE does not swing.

[0070] In one frame, the vertical blanking period BLK can be arranged separately with the vertical active period ACT therebetween. The vertical blanking period BLK can include a vertical back porch VBP arranged before the vertical active period ACT and a vertical front porch VFP arranged immediately after the vertical active period ACT.

[0071] The frequency variable display device according to the present embodiment can have a VRR mode in which the length of one frame varies. In the VRR mode, as Figure 4As shown, the frame rate can be changed to A, B, and C Hz. When the frame rate is changed, the one-frame time can be changed accordingly. At this time, each of the length of the vertical back porch VBP and the length of the vertical active period ACT can be fixed to a predetermined constant value, and only the length of the vertical front porch VFP can be changed. Based on the frame rate of A Hz, the length of the vertical front porch VFP can be VFP1, based on the frame rate of B Hz, the length of the vertical front porch VFP can be VFP2, and based on the frame rate of C Hz, the length of the vertical front porch VFP can be VFP3. Here, when A > B > C, VFP1 < VFP2 < VFP3.

[0072] In the vertical active period ACT with a fixed length, a display programming operation for writing an image can be performed.

[0073] In the vertical front porch VFP with a variable length, a flicker compensation operation for reducing the brightness can be performed. The flicker compensation operation can be performed such that the amount of reduction in brightness increases as the length of the vertical front porch VFP increases.

[0074] The above-described sensing programming operation and sensing operation can be performed in the vertical back porch VBP with a fixed length. In the VRR mode, since the real-time (RT) sensing operation is performed in the vertical back porch VBP with a fixed length, the sensing line compensation algorithm can be applied in real time without error. The sensing line compensation algorithm can be a technique for differentially applying a compensation gain for brightness restoration based on the position of the pixel row where the sensing operation is performed, thereby improving the image quality. For example, when the sensing operation is performed in the blanking period whose length is changed based on the frame rate, it may be difficult to apply the sensing line compensation algorithm in real time. This may be because the length of the blanking period should be more reflected in the compensation gain, but the length of the blanking period may not be known until the blanking period ends. That is, this may be because the length of the blanking period may not be known when the sensing line compensation algorithm is performed.

[0075] Figure 5 is a view showing an example of identifying brightness based on a horizontal change in the frame rate. Figure 6 is a view showing the identification brightness deviation that occurs under the condition of a rapid change in the frame rate. Figure 7 and Figure 8 is a view showing an example in which the visibility of the identification brightness deviation that occurs under the condition of a rapid change in the frame rate at a high gray level is higher than that at a low gray level.

[0076] Figure 5 and Figure 6 The peak low point of can be the point where the display programming operation is performed. The emission operation can be performed after the display programming operation is performed. When the display programming operation is being performed, the emission operation can be stopped.

[0077] The display programming operation and the emission operation can be continuously performed in one frame. The number of display programming operations can increase as the number of frame arrangements within a predetermined time increases (i.e., the frame frequency increases), and thus, the recognition brightness can be reduced. For example, the number of display programming operations within a predetermined time at a frame frequency of 240 Hz can be twelve, the number of display programming operations within a predetermined time at a frame frequency of 120 Hz can be six, and the number of display programming operations within a predetermined time at a frame frequency of 60 Hz can be three. As a result, the real-time brightness integration value (i.e., the recognition brightness) of a frame frequency of 240 Hz can be L1, the real-time brightness integration value (i.e., the recognition brightness) of a frame frequency of 120 Hz can be L2 which is higher than L1, and the real-time brightness integration value (i.e., the recognition brightness) of a frame frequency of 60 Hz can be L3 which is higher than L2.

[0078] As described above, when assuming that the gray level of the displayed image is constant, the recognition brightness may be relatively higher in the case of a low frame frequency compared to the case of a high frame frequency. Therefore, when the frame frequency changes from high to low, a brightness deviation caused by the change in recognition brightness may occur.

[0079] As Figure 7 and Figure 8 shown, the frequency-based brightness deviation can be recognized relatively higher in the low gray level period than in the high gray level period. In the case where the time taken to reach the effective brightness saturation immediately after programming is defined as the brightness conversion rate, the brightness conversion rate of the high gray level image can be relatively higher than that of the low gray level image. Therefore, the recognition brightness deviation caused by the frequency change may not occur to a great extent in the high gray level image, but when a low gray level image is displayed, the recognition brightness deviation caused by the frequency change can be clearly recognized.

[0080] Figure 9 is a view showing the configuration of the flicker compensation circuit 150 according to the present embodiment. Figure 10 and Figure 11 are driving timing diagrams for describing the brightness control operation of the flicker compensation circuit 150. Figure 12 is a view for describing the operation of one sub-pixel in the vertical front edge according to the present embodiment. Figure 13 is a view showing the setting range of the gate cut-off control voltage that allows leakage current to flow in the switching transistor of the sub-pixel in the vertical front edge.

[0081] Referring Figures 9 to 13 to, the flicker compensation circuit 150 according to the present embodiment can cause the leakage current to flow from the sub-pixel to the corresponding signal line in the vertical front edge VFP to achieve a flicker compensation brightness lower than the target brightness in the sub-pixel.

[0082] The flicker compensation circuit 150 may output a gate-off control voltage AVOFF so that leakage current flows from the sub-pixel to its corresponding signal line during the vertical front porch VFP. The gate-off control voltage AVOFF may form a three-level scan signal SCAN together with the gate-on voltage VON and the gate-off voltage VOFF. The gate-off control voltage AVOFF may be set to be lower than the gate-on voltage VON and higher than the gate-off voltage VOFF. In Figure 13 the Vg-Id curve graph of Figure 13 when the gate-on voltage VON is set to a voltage of VG1 or greater and the gate-off voltage VOFF is set to a voltage of VG2 or less in the Vg-Id curve graph of

[0083] the gate-off control voltage AVOFF may be set in a specific voltage period between VG1 and VG2. Accordingly, the first switching transistor ST1 and the second switching transistor ST2 of each sub-pixel may be slightly turned on during the vertical front porch VFP. That is, during the vertical front porch VFP, a leakage current path may be formed through the first switching transistor ST1 and the second switching transistor ST2.

[0084] To this end, the flicker compensation circuit 150 may include a counter 152 and a voltage controller 154.

[0085] The length of the vertical front porch VFP defined by the vertical synchronization signal Vsync and the data enable signal DE may vary based on the frame frequency. The counter 152 may count the length of the vertical front porch VFP using a reference clock RCLK to continuously provide a real-time count value CNT to the voltage controller 154.

[0086] The voltage controller 154 may gradually increase the level of the gate-off control voltage AVOFF based on the real-time count value CNT corresponding to the length of the vertical front porch VFP. That is, the level of the gate-off control voltage AVOFF may be increased to a target value during the vertical front porch VFP.

[0087] The voltage controller 154 may also output a first fixed voltage AFIX1 to the data line DL during the vertical front porch VFP, and may also output a second fixed voltage AFIX2 to the reference voltage line RL during the vertical front porch VFP to achieve flicker compensation luminance in the sub-pixel during the vertical front porch VFP.

[0088] The first fixed voltage AFIX1 can be lower than the data voltage Vdata charged to the gate node N1 of the sub-pixel during the vertical active period ACT. As the potential difference between the first fixed voltage AFIX1 and the data voltage Vdata increases, the gate potential of the driving transistor DT (the potential of N1) can rapidly discharge from the data voltage Vdata to the first fixed voltage AFIX1. As a result, during the vertical front VFP, the gate-source voltage Vgs of the driving transistor DT can be relatively reduced, and thus, the driving current Ids flowing between the drain and source of the driving transistor DT can be reduced.

[0089] The second fixed voltage AFIX2 can be lower than the reference voltage Vref charged to the gate node N2 of the sub-pixel during the vertical active period ACT. During the vertical front VFP, the source potential of the driving transistor DT (the potential of N2) can be maintained at a voltage higher than the operating point voltage of the light-emitting device EL of the reference voltage Vref. At this time, when the second fixed voltage AFIX2 is sufficiently lower than the reference voltage Vref, the leakage current flowing to the reference voltage line RL can increase, and thus, the current Iel flowing through the light-emitting device EL can be reduced.

[0090] Reference Figure 10 and Figure 11 Moreover, the 3-level scan signal SCAN applied to each gate line can include a first pulse P1 corresponding to the vertical active period ACT and a second pulse P2 corresponding to the vertical front VFP.

[0091] Synchronized with the gate-on voltage VON of the first pulse P1, the data voltage Vdata can be applied to the data line DL, and the reference voltage Vref can be applied to the reference voltage line RL.

[0092] Synchronized with the gate-off control voltage AVOFF of the second pulse P2, the first fixed voltage AFIX1 can be applied to the data line DL, and the second fixed voltage AFIX2 can be applied to the reference voltage line RL.

[0093] The first pulse P1 can be sequentially applied to all gate lines GL#1 to GL#n during the vertical active period ACT, and the second pulse P2 can be simultaneously applied to all gate lines GL#1 to GL#n during the vertical front VFP. During the vertical front VFP, synchronized with the second pulse P2, the first fixed voltage AFIX1 can be simultaneously applied to all data lines DL, and the second fixed voltage AFIX2 can be simultaneously applied to all reference voltage lines RL.

[0094] Figure 14 It is a view showing the relative magnitude of the recognized luminance deviation in the case of implementing the luminance control operation during the vertical front and the like.

[0095] Reference Figure 14 In the vertical front edge VFP during the execution of the VRR operation, case B where the brightness control operation is implemented can represent a significantly reduced recognition brightness deviation ΔL compared to case A where the brightness control operation is not implemented.

[0096] Figure 15 is a view showing an example of proportionally and gradually adjusting the level of the gate cut-off control voltage in real time according to the length of the vertical front edge.

[0097] Reference Figure 15 According to the present embodiment, the flicker compensation circuit can proportionally and gradually increase the level of the gate cut-off control voltage AVOFF in real time according to the length of the vertical front edge VFP.

[0098] The flicker compensation circuit can pre-store a plurality of count thresholds TH1 to TH3 having different sizes respectively corresponding to a plurality of frame frequencies, and based on an order comparison operation between the plurality of count thresholds TH1 to TH3 and real-time count values of the length of the vertical front edge VFP, gradually increase the level of the gate cut-off control voltage AVOFF to a target value in real time.

[0099] That is, during the vertical front edge VFP of the first frame, the flicker compensation circuit can gradually increase the level of the gate cut-off control voltage AVOFF to a first target value (for example, AVOFF2) in real time based on the real-time count value of the first length of the vertical front edge VFP, and during the vertical front edge VFP of the second frame, the flicker compensation circuit can gradually increase the level of the gate cut-off control voltage AVOFF to a second target value (for example, AVOFF4) in real time based on the real-time count value of the second length of the vertical front edge VFP.

[0100] In this case, the second length of the vertical front edge VFP can be longer than the first length of the vertical front edge VFP, and the second target value of the gate cut-off control voltage AVOFF can be greater than the first target value of the gate cut-off control voltage AVOFF. Therefore, the leakage current can increase more in the second frame than in the first frame.

[0101] Figure 16 is a view showing an example of proportionally and linearly adjusting the level of the gate cut-off control voltage in real time according to the length of the vertical front edge.

[0102] Reference Figure 16 According to the present embodiment, the flicker compensation circuit can proportionally and linearly increase the level of the gate cut-off control voltage AVOFF in real time according to the length of the vertical front edge VFP.

[0103] During the vertical front porch (VFP) of the first frame, the flicker compensation circuit can linearly increase the level of the gate cutoff control voltage (AVOFF) in real time to a first target value (e.g., AVOFF2) based on the real-time count value of the first length of the vertical front porch (VFP), and during the vertical front porch (VFP) of the second frame, the flicker compensation circuit can linearly increase the level of the gate cutoff control voltage (AVOFF) in real time to a second target value (e.g., AVOFF4) based on the real-time count value of the second length of the vertical front porch (VFP).

[0104] In this case, the second length of the vertical front porch (VFP) can be longer than the first length of the vertical front porch (VFP), and the second target value of the gate cutoff control voltage (AVOFF) can be greater than the first target value of the gate cutoff control voltage (AVOFF). Therefore, the leakage current can increase more in the second frame than in the first frame.

[0105] Figure 17 is a view showing a flicker compensation method of a frequency variable display device according to the present embodiment.

[0106] Reference Figure 17 , the flicker compensation method of the frequency variable display device according to the present embodiment can write an input image in a sub-pixel during a vertical active period in which a data enable signal of a frame swings, so as to achieve a target luminance in the sub-pixel (S10).

[0107] Subsequently, the flicker compensation method of the frequency variable display device according to the present embodiment can cause the leakage current to flow from the sub-pixel to its corresponding signal line during a vertical blanking period in which a data enable signal of a frame does not swing, so as to achieve a flicker compensation luminance lower than the target luminance in the sub-pixel (S20).

[0108] The present embodiment can achieve the following effects.

[0109] The present embodiment can reduce the recognition luminance deviation occurring under the condition of a rapid change in the frame frequency, thereby significantly improving the display quality.

[0110] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in this specification.

[0111] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure defined by the appended claims.

Claims

1. A frequency variable display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; an image driving circuit configured to write an input image into the plurality of sub-pixels in a vertical active period of a frame in response to a data enable signal swing to achieve a target brightness in the plurality of sub-pixels; as well as A flicker compensation circuit is configured to cause leakage current to flow from the plurality of sub-pixels to the signal lines corresponding thereto during a vertical blanking period of the frame in response to the data enable signal not swinging, so as to achieve flicker compensation brightness lower than a target brightness in the plurality of sub-pixels.

2. The frequency variable display device according to claim 1, wherein: The vertical blanking period includes a vertical trailing edge arranged before the vertical active period in the frame and a vertical leading edge arranged immediately after the vertical active period in the frame, Regardless of the length of the frame, the length of the vertical back porch is a constant value, and The length of the vertical front porch varies in proportion to the length of the frame.

3. The frequency variable display device according to claim 2, wherein: The flicker compensation circuit is configured to cause the leakage current to flow from the plurality of sub-pixels to the signal lines corresponding thereto in the vertical front porch to achieve the flicker compensation luminance lower than the target luminance in the plurality of sub-pixels.

4. The frequency variable display device according to claim 3, wherein: The flicker compensation circuit is configured to output a gate-off control voltage so that leakage current flows from the plurality of sub-pixels to the signal lines corresponding thereto in the vertical front porch, The gate-off control voltage is configured as a 3-level scanning signal together with the gate-on voltage and the gate-off voltage, and The gate-off control voltage is lower than the gate-on voltage and higher than the gate-off voltage.

5. The frequency variable display device according to claim 4, wherein: The flicker compensation circuit is configured to increase the level of the gate-off control voltage in proportion to the length of the vertical front porch, and The leakage current increases as the level of the gate-off control voltage increases.

6. The frequency variable display device according to claim 5, wherein: The flicker compensation circuit is configured to step-by-step increase the level of the gate-off control voltage in real time in proportion to the length of the vertical front porch.

7. The frequency variable display device according to claim 6, wherein: The flicker compensation circuit is configured to: During a vertical front edge of a first frame, based on a real-time count value of a first length of the vertical front edge, the level of the gate-off control voltage is gradually increased to a first target value, During the vertical front edge of the second frame, based on the real-time count value of the second length of the vertical front edge, the level of the gate-off control voltage is gradually increased to a second target value, wherein the second length of the vertical front is longer than the first length of the vertical front, and the second target value of the gate cut-off control voltage is greater than the first target value of the gate cut-off control voltage, and The leakage current increases more in the second frame than in the first frame.

8. The frequency variable display device according to claim 5, wherein: The level of the gate-off control voltage increases linearly in real time in proportion to the length of the vertical front edge.

9. The frequency variable display device according to claim 8, wherein: The flicker compensation circuit is configured to: During a vertical front edge of a first frame, based on a real-time count value of a first length of the vertical front edge, the level of the gate-off control voltage is linearly increased to a first target value, During the vertical front edge of the second frame, based on the real-time count value of the second length of the vertical front edge, the level of the gate-off control voltage is linearly increased to a second target value, wherein the second length of the vertical front is longer than the first length of the vertical front, and the second target value of the gate cut-off control voltage is greater than the first target value of the gate cut-off control voltage, and The leakage current increases more in the second frame than in the first frame.

10. The frequency variable display device according to claim 4, wherein: The flicker compensation circuit is further configured to output a first fixed voltage to a data line of the signal line during the vertical front period, and to output a second fixed voltage to a reference voltage line of the signal line, so as to achieve the flicker compensation brightness in the plurality of sub-pixels during the vertical front period, The first fixed voltage is lower than a data voltage supplied to the plurality of sub-pixels in the vertical active period, and The second fixed voltage is lower than a reference voltage provided to the plurality of sub-pixels in the vertical active period.

11. The frequency variable display device according to claim 4, wherein: Each sub-pixel of the plurality of sub-pixels comprises: a driving transistor including a gate electrode connected to the first node, a drain electrode connected to the high-level source voltage, and a source electrode connected to the second node; a light emitting device including an anode electrode connected to the second node and a cathode electrode connected to a low-level source voltage; a first switching transistor configured to control a flow of current between the first node and a data line based on a 3-level scan signal from a gate line; and a second switching transistor configured to control a flow of current between the second node and a reference voltage line based on the 3-level scan signal from the gate line, The 3-level scanning signal swings between a gate-on voltage and a gate-off voltage in the vertical active period, and maintains a gate-off control voltage between the gate-on voltage and the gate-off voltage in the vertical front edge.

12. The frequency variable display device according to claim 11, wherein: The level of the gate-off control voltage is configured to increase in proportion to the length of the vertical front edge, and The leakage current is configured to increase as a level of the gate-off control voltage increases. 13 . The frequency variable display device according to claim 2 , further comprising a sensing circuit configured to sense an electrical characteristic of each of the plurality of sub-pixels in the vertical trailing porch.

14. A flicker compensation method for a variable frequency display device, the variable frequency display device comprising a display panel, the display panel comprising a plurality of sub-pixels, the flicker compensation method comprising: When the data enable signal swings, writing the input image into the plurality of sub-pixels in a vertical active period of a frame to achieve a target brightness in the plurality of sub-pixels; as well as When the data enable signal is not swinging, leakage current is caused to flow from the plurality of sub-pixels to signal lines corresponding thereto in a vertical blanking period of the frame to achieve flicker compensation luminance lower than the target luminance in the plurality of sub-pixels.

15. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; as well as a control circuit electrically coupled to a sub-pixel of the plurality of sub-pixels, Wherein, the sub-pixel comprises: Driver transistor, a first switch coupled between one of a data voltage or a first fixed voltage selectable by the control circuit and a gate node of the drive transistor, and A second switch is coupled between one of a reference voltage or a second fixed voltage selectable by the control circuit and a source node or a drain node of the drive transistor.

16. The display device according to claim 15, wherein: The first fixed voltage is lower than the data voltage, and the second fixed voltage is lower than the reference voltage.

17. The display device according to claim 15, wherein: The control circuit is configured to provide a gate voltage to a gate of the first switch coupled between a gate node of the driving transistor and the first fixed voltage, the gate voltage being variable based on a variable frame frequency of a display operation of the display device.

18. The display device according to claim 17, wherein: The gate voltage is configured to cause a leakage current to pass through the first switch.

19. The display device according to claim 17, wherein: The gate voltage increases in response to the variable frame rate decreasing.

20. The display device according to claim 15, wherein: The sub-pixel further includes a third switch coupled between the source node or the drain node and the sensing unit.

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