Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and optimizes winding design. The display panel comprises a light hole and a first non-display area surrounding the light hole. A data line, wherein a part of the data line comprises a first winding; each gating unit comprises at least two gating switches, the input ends of the at least two gating switches are electrically connected with one source signal line, the control ends of the at least two gating switches are electrically connected with the at least two control lines respectively, and the output ends of the at least two gating switches are electrically connected with the at least two data lines respectively; the control lines comprise a first control line and a second control line; the gating unit comprises a first gating unit and a second gating unit; in the first windings connected with the first gating units and the second gating units, the first windings corresponding to the same first control line are arranged in different layers and are overlapped; the first winding corresponding to the first control line and the first winding corresponding to the second control line are arranged in different layers and at least partially not overlapped.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Currently, to achieve a full-screen display, a display panel may be designed with a hole dug in the display area, and at least some signal lines are routed around the light-transmitting hole.

[0003] However, the existing routing design is difficult to simultaneously narrow the border and reduce signal interference between the routed lines, thereby affecting the overall performance of the display panel. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device, which can optimize the routing design.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including: A light-transmitting hole, a first non-display area surrounding the light-transmitting hole, and a display area surrounding the first non-display area; Data lines, where some of the data lines include a first line segment, a first routed line, and a second line segment. Among them, the first line segment and the second line segment are disconnected on both sides of the light-transmitting hole and are at least located in the display area, and the first routed line is connected between the first line segment and the second line segment and is located in the first non-display area; Multiple selection units, where each selection unit includes at least two selection switches; in the selection unit, the input ends of at least two of the selection switches are electrically connected to a source signal line, the control ends of at least two of the selection switches are respectively electrically connected to at least two control lines, and the output ends of at least two of the selection switches are respectively electrically connected to at least two of the data lines; Among them, the first routed line corresponding to the control line is the first routed line connected by the selection switch connected to the control line; The control lines include at least one first control line and at least one second control line; The selection unit includes a first selection unit and a second selection unit; among the first routed lines connected by the first selection unit and the second selection unit: the first routed lines corresponding to the same first control line are arranged in different layers and at least partially overlap in a direction perpendicular to the plane of the display panel; the first routed lines corresponding to the first control line and the first routed lines corresponding to the second control line are arranged in different layers, and the first routed lines corresponding to the first control line and the first routed lines corresponding to the second control line do not overlap at least partially in a direction perpendicular to the plane of the display panel.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above-mentioned display panel.

[0007] The technical solution provided by the embodiment of the present invention has the following beneficial effects: In the first winding connecting the first gating unit and the second gating unit, for the first windings corresponding to the same first control line, the writing of the data voltage on this part of the first windings is controlled by the same first control line. Therefore, the voltage jumps of this part of the first windings occur simultaneously, and the mutual interference between such first windings will be smaller. In the embodiment of the present invention, this part of the first windings is arranged in different layers and at least partially overlapped. While not generating significant interference in the first windings, the wiring width occupied by this part of the first windings in the first non-display area is compressed, thereby effectively achieving the purpose of narrowing the border.

[0008] In the first winding connecting the first gating unit and the second gating unit, for the first windings corresponding to the first control line and the first windings corresponding to the second control line, since different control lines provide enable levels in a time-division manner, therefore, the voltages on the first windings corresponding to the first control line and the first windings corresponding to the second control line jump in a time-division manner. In the embodiment of the present invention, the first windings corresponding to the first control line and the first windings corresponding to the second control line are arranged in different layers and at least partially non-overlapped. Furthermore, through their staggered arrangement, the mutual interference between the two parts of the first windings can be reduced.

[0009] The embodiment of the present invention provides a winding method for data lines for a panel structure adopting a gating design. From the above analysis, it can be seen that this winding method can enable the display panel to simultaneously achieve narrowing the border and reducing the signal interference between the windings, and the display panel can achieve better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 2 It is another schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 3 It is still another schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 4Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 5 is Figure 4 A cross-sectional view along the A1-A2 direction; Figure 6 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 7 A schematic diagram of a film layer structure of the display panel provided by the embodiment of the present invention; Figure 8 Another schematic diagram of a film layer structure of the display panel provided by the embodiment of the present invention; Figure 9 Another schematic diagram of a film layer structure of the display panel provided by the embodiment of the present invention; Figure 10 Another schematic diagram of a film layer structure of the display panel provided by the embodiment of the present invention; Figure 11 A schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 12 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 13 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 14 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 15 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 16 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 17 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 18 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 19 Another schematic diagram of a film layer position of the first winding provided by the embodiment of the present invention; Figure 20 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 21 A winding schematic diagram of scan lines and data lines in the related art; Figure 22 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 23Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 24 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 25 A schematic diagram of the film layer position of the first lead provided by the embodiment of the present invention; Figure 26 For Figure 23 A cross-sectional view along the B1-B2 direction; Figure 27 A structural schematic diagram of the pixel circuit provided by the embodiment of the present invention; Figure 28 A schematic diagram of the film layer position of the second winding provided by the embodiment of the present invention; Figure 29 Another schematic diagram of the film layer position of the second winding provided by the embodiment of the present invention; Figure 30 Another structural schematic diagram of the pixel circuit provided by the embodiment of the present invention; Figure 31 Another schematic diagram of the film layer position of the second winding provided by the embodiment of the present invention; Figure 32 Another structural schematic diagram of the display panel provided by the embodiment of the present invention; Figure 33 A timing diagram provided by the embodiment of the present invention; Figure 34 A structural schematic diagram of the display device provided by the embodiment of the present invention. Detailed implementation manners

[0012] For a better understanding of the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0014] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0015] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this text generally represents an "or" relationship between the preceding and following associated objects.

[0016] An embodiment of the present invention provides a display panel, as Figure 1 shown Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. The display panel includes a light-transmitting hole 1, a first non-display area 2, and a display area 3. Among them, an optical component such as a camera is correspondingly arranged at the light-transmitting hole 1; the first non-display area 2 surrounds the light-transmitting hole 1 and is a border area around the light-transmitting hole 1; the display area 3 surrounds the first non-display area 2 and is a conventional display area.

[0017] Combined with Figures 1 to 5 , Figure 2 is another schematic structural diagram of the display panel provided by an embodiment of the present invention. Figure 3 is still another schematic structural diagram of the display panel provided by an embodiment of the present invention. Figure 4 is yet another schematic structural diagram of the display panel provided by an embodiment of the present invention. Figure 5 is Figure 4 a cross-sectional view along the A1-A2 direction. The display panel further includes data lines D. Some of the data lines D include a first segment D1, a first winding D0, and a second segment D2. Among them, the first segment D1 and the second segment D2 are disconnected on both sides of the light-transmitting hole 1 and are at least located in the display area 3, and the first winding D0 is connected between the first segment D1 and the second segment D2 and is located in the first non-display area 2.

[0018] The display panel further includes a plurality of selection units 4. The selection unit 4 includes at least two selection switches 5. In the selection unit 4, the input ends of at least two selection switches 5 are electrically connected to a source signal line Source, the control ends of at least two selection switches 5 are respectively electrically connected to at least two control lines mux, and the output ends of at least two selection switches 5 are respectively electrically connected to at least two data lines D.

[0019] For ease of understanding, in the drawings of the embodiments of the present invention, at least two control lines mux are respectively represented by reference numerals mux(1)~mux(n), where n≥2.

[0020] For example, refer to Figure 3, the gating unit 4 includes four gating switches 5. Correspondingly, the display panel includes four control lines, namely control line mux(1) to control line mux(4). During the display driving process, the control lines mux(1) to mux(4) sequentially provide enable levels. Among them, when the control line mux(i) provides an enable level, the gating switches 5 connected to the control line mux(i) among the multiple gating units 4 are turned on, and the data voltage on the source signal line Source is written into the data line D connected to this part of the gating switches 5.

[0021] Among them, the first winding D0 corresponding to the control line mux is the first winding D0 connected to the gating switch 5 connected to the control line mux.

[0022] That is, each control line mux will be connected to a certain gating switch 5 among all the gating units 4. The gating switches 5 connected to the control line mux can be divided into two types. Among them, the data lines D connected to the first type of gating switch are conventional data lines, and these data lines do not include the first winding D0. The data lines D connected to the second type of gating switch include the first winding D0. The first winding D0 corresponding to the control line mux is the first winding D0 of this part corresponding to the second type of gating switch connected to the control line mux.

[0023] The control line mux includes at least one first control line mux1 and at least one second control line mux2.

[0024] The gating unit 4 includes a first gating unit 41 and a second gating unit 42.

[0025] Among the first windings D0 respectively connected to the first gating unit 41 and the second gating unit 42: the first windings D0 corresponding to the same first control line mux1 are arranged in different layers and at least partially overlap in the direction perpendicular to the plane of the display panel; the first windings D0 corresponding to the first control line mux1 and the first windings D0 corresponding to the second control line mux2 are arranged in different layers, and the first windings D0 corresponding to the first control line mux1 and the first windings D0 corresponding to the second control line mux2 do not overlap at least partially in the direction perpendicular to the plane of the display panel.

[0026] For easy understanding, in the drawings of the embodiments of the present invention, the data line connected to the first gating unit 41 and corresponding to the control line mux(i) is represented by the reference numeral D(1i), and the first winding in the data line D(1i) is represented by the reference numeral D0(1i); the data line connected to the second gating unit 42 and corresponding to the control line mux(i) is represented by the reference numeral D(2i), and the first winding in the data line D(2i) is represented by the reference numeral D0(2i).

[0027] For Figures 2 to 5For example, the first control line mux1 includes a control line mux(1) and a control line mux(3), and the second control line mux2 includes a control line mux(2) and a control line mux(4).

[0028] Regarding “in the first windings D0 connected to the first gating unit 41 and the second gating unit 42, the first windings D0 corresponding to the same first control line mux1 are arranged in different layers and at least partially overlap”, for example, in combination with Figure 4 and Figure 5 , the first winding D0 (11) and the first winding D0 (21) corresponding to the control line mux (1) are arranged in different layers and at least partially overlap; the first winding D0 (13) and the first winding D0 (23) corresponding to the control line mux (3) are arranged in different layers and at least partially overlap.

[0029] Among the first windings D0 connected to the first selection unit 41 and the second selection unit 42, for the first windings D0 corresponding to the same first control line mux1, the writing of the data voltage on this part of the first windings D0 is controlled by the same first control line mux1, so the voltage jump of this part of the first windings D0 occurs at the same time, for example, the voltage jump of the first windings D0 (11) and the first windings D0 (21) occurs at the same time, and the mutual interference between such first windings D0 will be smaller. In the embodiment of the present invention, this part of the first windings D0 is set to different layers and at least partially overlapped, so that this part of the first windings D0 will not generate greater interference, and the wiring width occupied by this part of the first windings D0 in the first non-display area 2 is compressed, thereby effectively achieving the purpose of narrowing the frame.

[0030] Regarding “among the first windings D0 connected to the first gating unit 41 and the second gating unit 42, the first windings D0 corresponding to the first control line mux1 and the first windings D0 corresponding to the second control line mux2 are arranged in different layers, and the first windings D0 corresponding to the first control line mux1 and the first windings D0 corresponding to the second control line mux2 at least partially do not overlap”, for example, in combination with Figure 4 and Figure 5, the first winding lines D0(11), D0(21) corresponding to the control line mux(1) and the first winding lines D0(12), D0(22) corresponding to the control line mux(2) are arranged on different layers, and the first winding lines D0(11), D0(21), D0(12) and D0(22) do not overlap at least partially; the first winding lines D0(13), D0(23) corresponding to the control line mux(3) and the first winding lines D0(14), D0(24) corresponding to the control line mux(4) are arranged on different layers, and the first winding lines D0(13), D0(23), D0(14) and D0(24) do not overlap at least partially.

[0031] Among the first winding lines D0 connected to the first gating unit 41 and the second gating unit 42, for the first winding lines D0 corresponding to the first control line mux1 and the first winding lines D0 corresponding to the second control line mux2, since different control line muxes provide enabling levels at different times, the voltages on the first winding lines D0 corresponding to the first control line mux1 and the first winding lines D0 corresponding to the second control line mux2 jump at different times. For example, after the data voltage is written to the first winding lines D0(11), D0(21), they are in a floating state, and then the data voltage starts to be written to the first winding lines D0(12), D0(22). In the embodiment of the present invention, the first winding lines D0 corresponding to the first control line mux1 and the first winding lines D0 corresponding to the second control line mux2 are set on different layers and do not overlap at least partially, and thus, through their staggered arrangement, the signal interference between the two parts of the first winding lines D0 can be reduced.

[0032] The embodiment of the present invention provides a winding method for data lines for a panel structure adopting a gating design. From the above analysis, it can be seen that this winding method can simultaneously narrow the border and reduce the signal interference between the windings, and the display panel can achieve better performance.

[0033] In a feasible implementation manner, refer to Figure 2 and Figure 3 , the display panel includes alternately arranged first data line groups 6 and second data line groups 7, and the first data line groups 6 and the second data line groups 7 each include at least two adjacent data lines D.

[0034] Among them, the first gating unit 41 is electrically connected to the first data line group 6, and the second gating unit 42 is electrically connected to the second data line group 7.

[0035] The first gating unit 41 and the second gating unit 42 are respectively connected to the first data line group 6 and the second data line group 7, which means that the data lines D connected by the first gating unit 41 and the second gating unit 42 are adjacent. Then, when the above design is carried out for the first winding D0 in this part of the data lines D, the overall wiring of the first winding D0 will be relatively simple, and the wiring difficulty in the first non-display area 2 can be reduced.

[0036] In a feasible implementation manner, combined with Figures 2 to 5 , the gating unit 4 includes 2m gating switches 5, and the control line mux includes m first control lines mux1 and m second control lines mux2, where m≥1. Among them, when m>1, the first control line mux1 and the second control line mux2 alternately provide enable levels. For example, when m = 2, a first control line mux1, a second control line mux2, another first control line mux1, and another second control line mux2 sequentially provide enable levels.

[0037] The first winding D0 includes a first sub-winding 8 corresponding to the first control line mux1 and a second sub-winding 9 corresponding to the second control line mux2.

[0038] Among them, the first sub-winding 8 electrically connected to the first gating unit 41 is located on the tenth metal layer 10, the first sub-winding 8 electrically connected to the second gating unit 42 is located on the eleventh metal layer 11, the second sub-winding 9 electrically connected to the first gating unit 41 is located on the twelfth metal layer 12, and the second sub-winding 9 electrically connected to the second gating unit 42 is located on the thirteenth metal layer 13.

[0039] Moreover, in the first winding D0 connected by the same gating unit 4, there is a projection of a second sub-winding 9 on the plane of the display panel between the projections of two adjacent first sub-windings 8 on the plane of the display panel, and there is a projection of a first sub-winding 8 on the plane of the display panel between the projections of two adjacent second sub-windings 9 on the plane of the display panel.

[0040] For example, the first control line mux1 includes a control line mux(1) and a control line mux(3), and the second control line mux2 includes a control line mux(2) and a control line mux(4).

[0041] The first sub-winding 8 includes a first winding D0(11), a first winding D0(13), a first winding D0(21), and a first winding D0(23), and the second sub-winding 9 includes a first winding D0(12), a first winding D0(14), a first winding D0(22), and a first winding D0(24).

[0042] Among the first windings D0(11), D0(12), D0(13), and D0(14) connected to the first gating unit 41, between the orthographic projections of two adjacent first windings D0(11) and D0(13), there is either the orthographic projection of the first winding D0(12) or the orthographic projection of the first winding D0(14); between the orthographic projections of two adjacent first windings D0(12) and D0(14), there is either the orthographic projection of the first winding D0(11) or the orthographic projection of the first winding D0(13).

[0043] Among the first windings D0(21), D0(22), D0(23), and D0(24) connected to the second gating unit 42, between the orthographic projections of two adjacent first windings D0(21) and D0(23), there is either the orthographic projection of the first winding D0(22) or the orthographic projection of the first winding D0(24); between the orthographic projections of two adjacent first windings D0(22) and D0(24), there is either the orthographic projection of the first winding D0(21) or the orthographic projection of the first winding D0(23).

[0044] In the panel structure of the gating unit 4 driving 2m, with the above design, on the premise of narrowing the border and reducing the mutual interference of the first winding D0, the first winding D0 only needs to occupy a total of four metal layers. Currently, the number of metal layers in the panel film layer structure can meet the requirement of four-layer wiring for the first winding D0, and thus there is no need to additionally add other metal layers for the first winding D0 in the panel film layer structure.

[0045] Further, m = 2, that is, the gating unit 4 performs a one-driving-four design on the data line D.

[0046] In one structure, as Figure 6 shown, Figure 6 FIG. is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The display panel includes a first circuit column 14 and a second circuit column 15 arranged alternately along the first direction x. Among them, the first circuit column 14 includes a first pixel circuit 16 and a second pixel circuit 17 arranged alternately along the second direction y, and the second circuit column 15 includes a third pixel circuit 18 arranged along the second direction y. Moreover, in two adjacent first circuit columns 14, the first pixel circuit 16 in one first circuit column 14 and the second pixel circuit 17 in the other first circuit column 14 are arranged opposite to each other.

[0047] Among them, the first pixel circuit 16 is electrically connected to a red light-emitting element, the second pixel circuit 17 is electrically connected to a blue light-emitting element, and the third pixel circuit 18 is electrically connected to a green light-emitting element.

[0048] Each circuit column is electrically connected to two data lines D respectively. One of the data lines D is electrically connected to the pixel circuits in the odd rows, and the other data line D is electrically connected to the pixel circuits in the even rows. The data lines D corresponding to two adjacent circuit columns are connected to a selection unit 4.

[0049] Under this design, the number of data lines D is relatively large, and accordingly, the number of the first winding D0 is also relatively large. By adopting the above design for the first winding D0, the border width occupied by the first winding D0 in the first non-display area 2 can be reduced, and the signal interference between the first windings D0 can also be reduced.

[0050] The subsequent embodiments will describe the optional film layer positions of the first winding D0. For a clearer understanding of the solution, the present invention first introduces several film layer structures of the display panel.

[0051] As Figures 7 to 10 shown, Figure 7 is a schematic diagram of a film layer structure of the display panel provided by an embodiment of the present invention, Figure 8 is another schematic diagram of a film layer structure of the display panel provided by an embodiment of the present invention, Figure 9 is still another schematic diagram of a film layer structure of the display panel provided by an embodiment of the present invention, Figure 10 is yet another schematic diagram of a film layer structure of the display panel provided by an embodiment of the present invention. The display panel further includes a substrate 20, a transistor 21, a storage capacitor Cst, and a connection electrode 22. Among them, the connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23.

[0052] In a feasible setting manner, referring to Figure 7 and Figure 8 , the display panel includes three source-drain metal layers, namely a first source-drain metal layer sd1, a second source-drain metal layer sd2, and a third source-drain metal layer sd3. This kind of display panel is also called a "3SD structure". Among them, the first source-drain metal layer sd1 includes the connection electrode 22. The second source-drain metal layer sd2 is located on the side of the first source-drain metal layer sd1 away from the substrate 20, and the third source-drain metal layer sd3 is located on the side of the second source-drain metal layer sd2 away from the substrate 20. Moreover, a planarization layer 19 is respectively provided between the first source-drain metal layer sd1 and the second source-drain metal layer sd2, and between the second source-drain metal layer sd2 and the third source-drain metal layer sd3. The planarization layer 19 is usually an organic film layer and has a relatively large thickness.

[0053] In the "3SD structure", the number of source-drain metal layers is relatively large, which is more suitable for the situation where the number of signal lines is relatively large and the number of metal layers required to be occupied is relatively large.

[0054] In another feasible setting manner, referring to Figure 9 andFigure 10 The display panel only includes two source-drain metal layers, namely the first source-drain metal layer sd1 and the second source-drain metal layer sd2. Such a display panel is also referred to as having a "2SD structure". Among them, the first source-drain metal layer sd1 includes a connection electrode 22. The second source-drain metal layer sd2 is located on the side of the first source-drain metal layer sd1 away from the substrate 20. And there is a planarization layer 19 between these two source-drain metal layers.

[0055] In the "2SD structure", the number of source-drain metal layers is small, which is more suitable for the case where the number of signal lines is small and the number of metal layers required is not much.

[0056] In a feasible setting method, referring to Figure 7 and Figure 9 the transistor 21 includes a first transistor 27 and a second transistor 28. Among them, the active layer of the first transistor 27 includes a metal oxide semiconductor material. For example, the first transistor 27 is an Indium Gallium Zinc Oxide (IGOZ) transistor; the active layer of the second transistor 28 includes a silicon material. For example, the second transistor 28 is a Low Temperature Poly Si (LTPS) transistor. Such a display panel is also referred to as having an "LTPO structure".

[0057] In this structure, the display panel further includes a first semiconductor layer al1, a first gate metal layer m1, a first electrode metal layer mc, a second semiconductor layer al2, and a second gate metal layer mg arranged in sequence along the direction away from the substrate 20.

[0058] Among them, the first semiconductor layer a1 includes the active layer of the second transistor 28; the first gate metal layer m1 includes the gate of the second transistor 28 and the second electrode plate c2 of the storage capacitor Cst; the first electrode metal layer mc includes the first electrode plate c1 of the storage capacitor Cst; the second semiconductor layer al2 includes the active layer of the first transistor 27; the second gate metal layer mg includes the gate of the first transistor 27. The first source-drain metal layer sd1 is located on the side of the second gate metal layer mg away from the substrate 20. Among the above-mentioned film layers, there are inorganic insulating layers 29 between adjacent two film layers respectively.

[0059] In another setting method, referring to Figure 8 and Figure 10 the transistor 21 only includes one type of transistor, namely the second transistor 28. Such a display panel is also referred to as having an "LTPS structure".

[0060] In this structure, the display panel further includes a first semiconductor layer al1, a first gate metal layer m1, and a first electrode metal layer mc arranged in sequence along the direction away from the substrate 20.

[0061] Among them, the first semiconductor layer a1 includes the active layer of the second transistor 28; the first gate metal layer m1 includes the gate of the second transistor 28 and the second electrode plate c2 of the storage capacitor Cst; the first electrode metal layer mc includes the first electrode plate c1 of the storage capacitor Cst. The first source-drain metal layer sd1 is located on the side of the first electrode metal layer mc away from the substrate 20. Among the above-mentioned film layers, an inorganic insulating layer 29 is respectively provided between two adjacent film layers.

[0062] Then, the optional film layer positions of the first winding D0 will be described below.

[0063] In a feasible implementation manner, as Figures 11 to 14 shown, Figure 11 is a schematic diagram of a film layer position of the first winding provided by an embodiment of the present invention, Figure 12 is another schematic diagram of a film layer position of the first winding provided by an embodiment of the present invention, Figure 13 is still another schematic diagram of a film layer position of the first winding provided by an embodiment of the present invention, Figure 14 is yet another schematic diagram of a film layer position of the first winding provided by an embodiment of the present invention. The first winding D0 includes a first sub-winding 8 corresponding to the first control line mux1.

[0064] Among them, the first sub-winding 8 electrically connected to the first gating unit 41 is located in the first metal layer 10, and the first sub-winding 8 electrically connected to the second gating unit 42 is located in the second metal layer 11. That is, the first winding D0(11) and the first winding D0(13) are located in the first metal layer 10, and the first winding D0(21) and the first winding D0(23) are located in the second metal layer 11. Among them, a planarization layer is provided between the first metal layer 10 and the second metal layer 11.

[0065] Combined with the foregoing introduction, it can be known that among the first sub-windings 8 corresponding to the same first control line mux1, the first sub-winding 8 connected to the first gating unit 41 and the first sub-winding 8 connected to the second gating unit 42 overlap. That is, the first winding D0(11) and the first winding D0(21) overlap, and the first winding D0(13) and the first winding D0(23) overlap.

[0066] By providing a planarization layer 19 between the first metal layer 10 where the first sub-winding 8 connected to the first gating unit 41 is located and the second metal layer 11 where the first sub-winding 8 connected to the second gating unit 42 is located, the relatively thick planarization layer 19 can be used to increase the longitudinal distance between these two parts of the first sub-windings 8, so as to avoid generating a large parasitic capacitance when they overlap and further avoid mutual influence between them.

[0067] In addition, as can be seen from the previous analysis of the film layer structure of the display panel, a planarization layer 19 is provided between the first metal layer 10 and the second metal layer 11, which means that at least one of the first metal layer 10 and the second metal layer 11 is a source / drain metal layer. For example, when only the planarization layer 19 is provided between the first metal layer 10 and the second metal layer 11, both the first metal layer 10 and the second metal layer 11 are source / drain metal layers. Generally, due to reasons such as the material resistance of the source / drain metal layer, its impedance is relatively small. Therefore, when the first sub-wire 8 is located in the source / drain metal layer, it can also have a smaller load, which helps to balance the load difference from the conventional data line.

[0068] Further, referring to Figure 11 and Figure 12 , the display panel further includes a substrate 20, a transistor 21, and a connection electrode 22, wherein the connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23.

[0069] The planarization layer 19 includes a first planarization layer 24 and a second planarization layer 25. The first planarization layer 24 is located on the side of the connection electrode 22 away from the substrate 20, and the second planarization layer 25 is located on the side of the first planarization layer 24 away from the substrate 20.

[0070] Among them, the first metal layer 10 is located on the side of the second planarization layer 25 away from the substrate 20, and the second metal layer 11 is located between the first planarization layer 24 and the second planarization layer 25.

[0071] This setting method is more suitable for the "3SD structure", where the first metal layer 10 is the third source / drain metal layer sd3, and the second metal layer 11 is the second source / drain metal layer sd2. With this setting, the parasitic capacitance between the overlapping first sub-wires 8 can be reduced by using the second planarization layer 25, and the load of the first sub-wire 8 can be reduced by using the characteristic of the lower impedance of the source / drain metal layer.

[0072] In a feasible implementation, referring to Figure 13 and Figure 14 , the display panel further includes a substrate 20, a transistor 21, and a connection electrode 22, and the connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23.

[0073] The planarization layer 19 includes a first planarization layer 24, and the first planarization layer 24 is located on the side of the connection electrode 22 away from the substrate 20.

[0074] Among them, the first metal layer 10 is located on the side of the first planarization layer 24 away from the substrate 20, and the second metal layer 11 includes the connection electrode 22.

[0075] This setting method is more applicable to the "2SD structure", where the first metal layer 10 is the second source / drain metal layer sd2, and the second metal layer 11 is the first source / drain metal layer sd1. With this setting, the first planarization layer 24 can be used to reduce the parasitic capacitance between the overlapping first sub-wires 8, and the characteristic of the lower impedance of the source / drain metal layer can be used to reduce the load of the first sub-wires 8.

[0076] In a feasible implementation, referring to Figures 11 to 14 , the first wire D0 includes a second sub-wire 9 corresponding to the second control line mux2.

[0077] The second sub-wire 9 electrically connected to the first gating unit 41 is located on the third metal layer 12, and the second sub-wire 9 electrically connected to the second gating unit 42 is located on the fourth metal layer 13. That is, the first wire D0(12) and the first wire D0(14) are located on the third metal layer 12, and the first wire D0(22) and the first wire D0(24) are located on the fourth metal layer 13. Among them, an inorganic insulating layer 29 is provided between the third metal layer 12 and the fourth metal layer 13.

[0078] Combined with the previous analysis of the film layer structure of the display panel, when there is an inorganic insulating layer 29 between the third metal layer 12 and the fourth metal layer 13, it means that at least one of the third metal layer 12 and the fourth metal layer 13 is the first source / drain metal layer sd1 or a metal layer below it.

[0079] For example, in the "3SD structure", when the first sub-wire 8 is located on the uppermost third source / drain metal layer sd3 and the second source / drain metal layer sd2, the second sub-wire 9 can be selected to be located on the first source / drain metal layer sd1 or the second gate metal layer mg, the first electrode metal layer mc, the first gate metal layer m1, etc. below it. In the "2SD structure", when the first sub-wire 8 is located on the uppermost second source / drain metal layer sd2 and the first source / drain metal layer sd1, the second sub-wire 9 can be selected to be located on the second gate metal layer mg, the first electrode metal layer mc, the first gate metal layer m1, etc. below the first source / drain metal layer sd1. Furthermore, the film layer positions are reasonably configured for the first sub-wire 8 and the second sub-wire 9 in the "3SD structure" and the "2SD structure".

[0080] In a feasible implementation, referring to Figures 11 to 13 , there are also other metal layers between the third metal layer 12 and the fourth metal layer 13. Among them, in the second sub-wires 9 connected to the first gating unit 41 and the second gating unit 42, the second sub-wires 9 corresponding to the same second control line mux2 overlap at least partially in the direction perpendicular to the plane of the substrate 20.

[0081] For example, referring to Figure 11, the third metal layer 12 is the first source / drain metal layer sd1, the fourth metal layer 13 is the first gate metal layer m1, and there are a second gate metal layer mg and a first electrode metal layer mc between the third metal layer 12 and the fourth metal layer 13. The first winding D0(12) and the first winding D0(22) overlap, and the first winding D0(14) and the first winding D0(24) overlap.

[0082] As described above, in the first sub-winding 8 connected to the first gating unit 41 and the second gating unit 42, the first sub-windings 8 corresponding to the same first control line mux1 overlap to compress the border width occupied by the first sub-winding 8. In this embodiment, when there are other metal layers between the third metal layer 12 where the second sub-winding 9 connected to the first gating unit 41 is located and the fourth metal layer 13 where the second sub-winding 9 connected to the second gating unit 42 is located, it means that the longitudinal distance between the third metal layer 12 and the fourth metal layer 13 is large. In this regard, it can be selected to also set the second sub-windings 9 corresponding to the same second control line mux2 to overlap, so as to compress the border width occupied by the second sub-windings 9 synchronously on the premise that no large parasitic capacitance is generated between these second sub-windings 9. For example, see Figure 4 , the eight first windings D0 connected to the first gating unit 41 and the second gating unit 42 occupy at least only four wiring widths, and further narrow the border to a greater extent.

[0083] It should be noted that the above setting method is more applicable to Figure 11 and Figure 12 the "3SD structure" shown in Figure 13 and the "2SD+LTPO structure" shown in

[0084] . In these film layer structures, the number of metal layers is relatively large, which is more convenient to select two non-adjacent metals to set the second sub-winding 9. Figure 11 and Figure 12 , the display panel further includes a substrate 20, a transistor 21, and a connection electrode 22. The connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23.

[0085] The third metal layer 12 includes the connection electrode 22, and the fourth metal layer 13 is located on the side of the third metal layer 12 close to the substrate 20.

[0086] This setting method is more applicable to the "3SD structure". Among them, the first metal layer 10 is the third source / drain metal layer sd3, the second metal layer 11 is the second source / drain metal layer sd2, the third metal layer 12 is the first source / drain metal layer sd1, and the fourth metal layer 13 is located on the side of the first source / drain metal layer sd1 close to the substrate 20.

[0087] The third metal layer 12 described above is the first source / drain metal layer sd1. On the one hand, the characteristic of the source / drain metal layer with lower impedance can be utilized to reduce the load of this part of the second sub-wire 9 connected to the first selection unit 41. On the other hand, the film layer position of the first source / drain metal layer sd1 is relatively upper. When selecting a metal layer that is not adjacent to it below as the fourth metal layer 13, the position selection of the fourth metal layer 13 will be more flexible, and it also helps to increase the vertical distance between the third metal layer 12 and the fourth metal layer 13 to a greater extent, so as to reduce the parasitic capacitance between the second sub-wire 9 connected to the overlapping first selection unit 41 and the second sub-wire 9 connected to the second selection unit 42 to a greater extent, and reduce the mutual influence of signals between the two.

[0088] When there are other metal layers between the third metal layer 12 and the fourth metal layer 13, in another feasible implementation, refer to Figure 13 , the display panel further includes a substrate 20 and a transistor 21, and the transistor 21 includes a first transistor 27, and the active layer of the first transistor 27 includes a metal oxide material.

[0089] The third metal layer 12 includes the gate of the first transistor 27, and the fourth metal layer 13 is located on the side of the third metal layer 12 close to the substrate 20.

[0090] This setting method is more suitable for the "2SD structure + LTPO structure". Among them, the first metal layer 10 is the second source / drain metal layer sd2, the second metal layer 11 is the first source / drain metal layer sd1, the third metal layer 12 is the second gate metal layer mg, and the fourth metal layer 13 is located on the side of the second gate metal layer mg close to the substrate 20.

[0091] The third metal layer 12 described above is the second gate metal layer mg. The film layer position of the second gate metal layer mg is relatively upper. When selecting a metal layer that is not adjacent to it below as the fourth metal layer 13, the position selection of the fourth metal layer 13 will be more flexible, and it also helps to increase the vertical distance between the third metal layer 12 and the fourth metal layer 13 to a greater extent, so as to reduce the parasitic capacitance between the second sub-wire 9 connected to the overlapping first selection unit 41 and the second sub-wire 9 connected to the second selection unit 42 to a greater extent.

[0092] In a feasible implementation, refer to Figures 11 to 13 , the transistor 21 includes a second transistor 28, the active layer of the second transistor 28 includes silicon material, and the fourth metal layer 13 includes the gate of the second transistor 28. That is, the fourth metal layer 13 is the first gate metal layer m1.

[0093] For example, in Figure 11 and Figure 12In the "3SD structure", the third metal layer 12 is the first source / drain metal layer sd1, and the fourth metal layer 13 is the first gate metal layer m1. Alternatively, in Figure 13 the "2SD structure + LTPO structure", the third metal layer 12 is the second gate metal layer mg, and the fourth metal layer 13 is the first gate metal layer m1.

[0094] Alternatively, as Figure 15 and Figure 16 shown, Figure 15 FIG. Figure 16 FIG. is another schematic diagram of the film layer positions of the first winding provided by the embodiment of the present invention. The display panel further includes a shielding metal 30. The shielding metal 30 is located between the transistor 21 and the substrate 20. In the direction perpendicular to the plane where the substrate 20 is located, the shielding metal 30 overlaps with the channel of the transistor 21. The fourth metal layer 13 includes the shielding metal 30.

[0095] In this structure, the display panel further includes a shielding metal layer m0. The shielding metal layer m0 is located between the first semiconductor layer al1 and the substrate 20. There is an inorganic insulating layer 29 between the shielding metal layer m0 and the first semiconductor layer al1. The fourth metal layer 13 is the shielding metal layer m0. For example, in Figure 15 the "3SD structure", the third metal layer 12 is the first source / drain metal layer sd1, and the fourth metal layer 13 is the shielding metal layer m0. Alternatively, in Figure 16 the "2SD structure + LTPO structure", the third metal layer 12 is the second gate metal layer mg, and the fourth metal layer 13 is the shielding metal layer m0.

[0096] In the film layer structure of the display panel, the positions of the first gate metal layer m1 and the shielding metal layer m0 are both relatively close to the substrate 20. When the fourth metal layer 13 is the first gate metal layer m1 or the shielding metal layer m0, the longitudinal distance between the fourth metal layer 13 and the third metal layer 12 is greater, the parasitic capacitance between the second sub-winding 9 connected to the first gating unit 41 and the second sub-winding 9 connected to the second gating unit 42 is smaller, and the signal influence between the two is smaller.

[0097] In a feasible implementation manner, referring again to Figure 14 , the third metal layer 12 and the fourth metal layer 13 are two adjacent metal layers. Among them, in the second sub-winding 9 connected to the first gating unit 41 and the second gating unit 42, the second sub-windings 9 corresponding to the same second control line mux2 do not overlap at least partially in the direction perpendicular to the plane where the substrate 20 is located.

[0098] For example, referring to Figure 14, the third metal layer 12 is the first electrode metal layer mc, the fourth metal layer 13 is the first gate metal layer m1, the third metal layer 12 and the fourth metal layer 13 are adjacent, and there is no other metal layer in between. The first winding D0(12) and the first winding D0(22) do not overlap at least partially, and the first winding D0(14) and the first winding D0(24) do not overlap at least partially.

[0099] When the third metal layer 12 where the second sub-winding 9 connected to the first gating unit 41 is located and the fourth metal layer 13 where the second sub-winding 9 connected to the second gating unit 42 is located are adjacent metal layers, it means that the longitudinal distance between the third metal layer 12 and the fourth metal layer 13 is small. In this regard, among the second sub-windings 9 connected to the first gating unit 41 and the second gating unit 42, it is possible to select the second sub-windings 9 corresponding to the same second control line mux2 to be at least partially non-overlapping and stagger them from each other, thereby reducing the parasitic capacitance between these second sub-windings 9 and reducing the mutual influence of their signals.

[0100] It should be noted that the above setting method will be more applicable to Figure 14 the "2SD+LTPS structure" shown. In this film layer structure, the number of metal layers is small, so two adjacent metals can be selected to set the second sub-winding 9.

[0101] When the third metal layer 12 and the fourth metal layer 13 are two adjacent metal layers, in a feasible implementation manner, referring to Figure 14 again, the display panel further includes a substrate 20, a storage capacitor Cst, and a transistor 21. Among them, the transistor 21 includes a second transistor 28, and the active layer of the second transistor 28 includes a silicon material.

[0102] The third metal layer 12 includes the first electrode plate c1 of the storage capacitor Cst, and the fourth metal layer 13 includes the gate of the second transistor 28 and the second electrode plate c2 of the storage capacitor Cst.

[0103] Among them, the first metal layer 10 is the second source-drain metal layer sd2, the second metal layer 11 is the first source-drain metal layer sd1, the third metal layer 12 is the first electrode metal layer mc, and the fourth metal layer 13 is the first gate metal layer m1. Thus, under the "2SD structure+LTPS structure", the film layer positions of the four metal layers where the first sub-winding 8 and the second sub-winding 9 are located are reasonably configured, and the parasitic capacitance between the second sub-windings 9 connected to the first gating unit 41 and the second sub-windings 9 connected to the second gating unit 42 is reduced, and the mutual influence of their signals is reduced.

[0104] In a feasible implementation manner, as shown in Figure 17 and Figure 18 shown, Figure 17Another structural schematic diagram of the display panel provided by the embodiment of the present invention Figure 18 Another schematic diagram of the film layer position of the first winding D0 provided by the embodiment of the present invention. The selection unit 4 includes 3 selection switches 5. The control line mux includes n first control lines mux1 and 3 - n second control lines mux2, where n = 1 or n = 2.

[0105] More specifically, in one structure, refer to Figure 17 , the display panel includes a first circuit column 14, a second circuit column 15, and a third circuit column 31 that are alternately arranged in sequence along the first direction x. Among them, the first circuit column 14 includes a plurality of first pixel circuits 16 arranged along the second direction y, the second circuit column 15 includes a plurality of third pixel circuits 18 arranged along the second direction y, and the third circuit column 31 includes a plurality of second pixel circuits 17 arranged along the second direction y.

[0106] Among them, one circuit column is connected to one data line D. The data lines D corresponding to three adjacent circuit columns are connected to one selection unit 4.

[0107] Among them, in the first winding D0 corresponding to the first control line mux, the first windings D0 electrically connected to the first selection unit 41 and the second selection unit 42 are respectively located in the first metal layer 10 and the second metal layer 11. That is, the first winding D0(11) corresponding to the control line mux(1) and connected to the first selection unit 41 is located in the first metal layer 10, and the first winding D0(21) corresponding to the control line mux(1) and connected to the second selection unit 42 is located in the second metal layer 11.

[0108] In the first winding D0 corresponding to the second control line mux, the first windings D0 electrically connected to the first selection unit 41 and the second selection unit 42 are respectively located in the third metal layer 12 and the fourth metal layer 13. That is, the first winding D0(12) corresponding to the control line mux(2) and connected to the first selection unit 41 is located in the third metal layer 12, and the first winding D0(22) corresponding to the control line mux(2) and connected to the second selection unit 42 is located in the fourth metal layer 13.

[0109] In the first winding D0 corresponding to the third control line mux, the first windings D0 electrically connected to the first selection unit 41 and the second selection unit 42 are respectively located in the fifth metal layer 32 and the sixth metal layer 33. That is, the first winding D0(13) corresponding to the control line mux(3) and connected to the first selection unit 41 is located in the fifth metal layer 32, and the first winding D0(23) corresponding to the control line mux(3) and connected to the second selection unit 42 is located in the sixth metal layer 33.

[0110] This structure is more applicable to the "3SD structure". In the "3SD structure", the number of metal layers is relatively large, which can meet the requirement of the first winding D0 using six-layer wiring. The first winding D0 only needs to be located in the original metal layers without the need to additionally provide other metal layers for the first winding D0. For example, the first metal layer 10 is the third source-drain metal layer sd3, the second metal layer 11 is the second source-drain metal layer sd2, the third metal layer 12 is the first source-drain metal layer sd1, the fourth metal layer 13 is the second gate metal layer mg, the fifth metal layer 32 is the first electrode metal layer mc, and the sixth metal layer 33 is the first gate metal layer m1.

[0111] Further, as Figure 19 shown, Figure 19 FIG. is another schematic diagram of the film layer position of the first winding provided by the embodiment of the present invention. n = 2, that is, two of the three control lines mux are the first control lines mux1, and one is the second control line mux2. Among them, the second control line mux2 provides an enable level between the two first control lines mux1.

[0112] The display panel further includes a substrate 20, and the distances between the first metal layer 10, the second metal layer 11, the third metal layer 12, the fourth metal layer 13, the fifth metal layer 32, and the sixth metal layer 33 and the substrate 20 decrease.

[0113] In the first winding D0 electrically connected to the first gating unit 41 and the second gating unit 42, the first winding D0 corresponding to one of the first control lines mux1 is respectively located in the first metal layer 10 and the second metal layer 11, and the first winding D0 corresponding to the other first control line mux1 is respectively located in the fifth metal layer 32 and the sixth metal layer 33. Moreover, the first windings D0 corresponding to the two first control lines mux1 at least partially overlap in the direction perpendicular to the plane of the display panel. That is, the first winding D0(11), the first winding D0(21), the first winding D0(13), and the first winding D0(23) overlap.

[0114] The first windings D0 corresponding to the two first control lines mux1 are set to overlap, and the six windings corresponding to the first gating unit 41 and the second gating unit 42 occupy at least only two wiring widths, which can further narrow the border.

[0115] In a feasible implementation manner, as Figure 20 shown, Figure 20Another structural schematic diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a first scan line S, and part of the first scan line S includes a third line segment S1, a second winding S0, and a fourth line segment S2. Among them, the third line segment S1 and the fourth line segment S2 are disconnected on both sides of the light-transmitting hole 1 and are at least located in the display area 3. The extending directions of the third line segment S1 and the fourth line segment S2 intersect with the extending directions of the first line segment D1 and the second line segment D2. The second winding S0 is connected between the third line segment S1 and the fourth line segment S2 and is located in the first non-display area 2.

[0116] In the embodiment of the present invention, the second winding S0 of the first scan line S is located on the side of the first winding D0 away from the light-transmitting hole 1.

[0117] In the related art, when arranging the windings of the scan line and the data line, the two windings overlap each other. However, the inventor's research found that under this design, the coupling between the two windings is very large, which easily leads to XX mura, heavy-load picture splitting and other problems.

[0118] For example, as Figure 21 shown, Figure 21 is a winding schematic diagram of the scan line and the data line in the related art. Taking the scan line including the emission control scan line Emit as an example, the winding of the innermost data line D has the largest overlap with the winding of the emission control scan line Emit. When the emission control scan signal jumps, the voltage on the winding of this part of the data line D is affected, forming a point (bright point or dark point). The winding of the outermost data line D has the smallest overlap with the winding of the emission control scan line Emit. And the two emission control scan lines Emit overlapping with the winding of the outermost data line D are far apart. When the emission control scan signal jumps, the two farthest points (bright points or dark points) are formed, thereby generating XX mura phenomenon.

[0119] In the embodiment of the present invention, referring to Figure 20 , the second winding S0 of the first scan line S is located on the side of the first winding D0 away from the light-transmitting hole 1, and the two windings are arranged separately. Therefore, the jump of the scan signal has less interference on the data signal on the winding, so as to effectively improve XX mura, heavy-load picture splitting and other bad display problems.

[0120] In a feasible implementation manner, as Figure 22 shown, Figure 22 is another structural schematic diagram of the display panel provided by the embodiment of the present invention. The first winding D0 is connected to the first line segment D1 and the first winding D0 is connected to the second line segment D2 respectively through the first lead 34.

[0121] On a plane perpendicular to the plane where the display panel is located, the first lead 34 overlaps with the second winding S0, and the first lead 34 extends in the same direction as the first line segment D1 and the second line segment D2.

[0122] The first lead 34 directly longitudinally crosses the second winding S0 and is connected to the first winding D0. The extension distance of the first lead 34 is small, so the coupling with the second winding S0 is small, which can further reduce the interference of the scanning signal jump on the data signal.

[0123] In a feasible implementation, as Figure 23 and Figure 24 shown, Figure 23 is another schematic structural diagram of the display panel provided by the embodiment of the present invention. Figure 24 is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The first lead 34 is arranged on the same layer as the first line segment D1 and the second line segment D2, so there is no need to punch holes for connection between the first lead 34 and the first line segment D1 and the second line segment D2.

[0124] And / or, as Figure 25 shown, Figure 25 is a schematic diagram of the film layer position of the first lead provided by the embodiment of the present invention. The display panel further includes a substrate 20, a transistor 21, and a connection electrode 22. The connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23. The metal layer where the first lead 34 is located is on the side of the metal layer where the connection electrode 22 is located away from the substrate 20, that is, the first lead 34 is located in the second source-drain metal layer sd2 or the third source-drain metal layer sd3. In this way, the impedance of the source-drain metal layer can be used to reduce the load of the first lead 34 and weaken the load difference between the data line D with windings and the conventional data line D.

[0125] In a feasible implementation, combining Figure 23 and Figure 26 , Figure 26 is Figure 23 a cross-sectional view along the B1-B2 direction. The first lead 34 includes a first sub-lead 35 and a second sub-lead 36.

[0126] Among them, the first sub-lead 35 and the first winding D0 connected thereto are arranged on different layers and are connected through a first connection portion 37. The second sub-lead 36 and the first winding D0 connected thereto are arranged on the same layer and are connected through a second connection portion 38. The first connection portion 37 and the second connection portion 38 are arranged on the same layer, for example, they can be located in the second source-drain metal layer sd2. And further, the first connection portion 37 and the second connection portion 38 are arranged on different layers from the second sub-lead 36.

[0127] There are multiple possibilities for the film layer position of the first winding D0. Therefore, when the first sub-lead 35 and the first winding D0 connected thereto are arranged in different layers, regardless of which layer the first winding D0 is located in, the two can be wire-changed and connected through the first connection part 37 located in the same layer to simplify the punching design. At the same time, when the first sub-lead 35 and the first winding D0 connected thereto are arranged in the same layer, in order to improve the distribution uniformity of the connection parts in the first non-display area 2, the two can also be wire-changed and connected through the second connection part 38 in the same layer as the first connection part 37.

[0128] In a feasible implementation manner, referring again to Figure 23 , at least part of the first lead 34 and the first winding D0 connected thereto are arranged in different layers and are connected through the connection part 39, and the connection part 39 is located between the first winding D0 and the second winding S0.

[0129] The connection part 39 does not overlap with the second winding S0. Therefore, the end of the first winding D0 does not need to overlap with the second winding S0 either. The selection of the film layer positions of the first winding D0 and the second winding S0 will not affect each other. Even if part of the first winding D0 and the second winding S0 are in the same layer, the two will not be short-circuited, thus making greater use of the film layer wiring.

[0130] In a feasible implementation manner, referring to Figures 27 to 29 , the display panel includes at least two types of first scanning lines S, and different types of first scanning lines S are used to provide different types of scanning signals. For example, one of the first scanning lines S is used to provide a gate reset scanning signal, and one of the first scanning lines S is used to provide a light emission control scanning signal, etc.

[0131] The second windings S0 of the same type of first scanning line S are arranged in the same layer, and the second windings S0 of different types of first scanning lines S are arranged in different layers. And, in the direction perpendicular to the plane of the display panel, there are at least two second windings S0 of the first scanning lines S overlapping.

[0132] Such an arrangement can compress the wiring width required by the second winding S0 in the first non-display area 2, which helps to further narrow the border.

[0133] In a feasible implementation manner, as Figures 27 to 29 shown, Figure 27 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention, Figure 28 is a schematic diagram of a film layer position of a second winding provided by an embodiment of the present invention, Figure 29Another schematic diagram of the film layer position of the second winding provided by the embodiment of the present invention. The display panel includes a pixel circuit 40, and the pixel circuit 40 includes a storage capacitor Cst and multiple transistors 21. Among them, the transistor 21 includes a first transistor 27 and a second transistor 28. The active layer of the first transistor 27 includes a metal oxide material, and the active layer of the second transistor 28 includes a silicon material.

[0134] Among them, the display panel further includes a connection electrode 22. The connection electrode 22 is electrically connected to the doped region of the active layer in the transistor 21 through a via 23. The second winding S0 of one of the first scan lines S is disposed on the same layer as the connection electrode 22. That is, the second winding S0 of the first scan line S is located in the first source-drain metal layer sd1.

[0135] And / or, the second winding S0 of one of the first scan lines S is disposed on the same layer as the gate of the first transistor 27. That is, the second winding S0 of the first scan line S is located in the second gate metal layer mg.

[0136] And / or, the second winding S0 of one of the first scan lines S is disposed on the same layer as the first electrode plate c1 of the storage capacitor Cst. That is, the second winding S0 of the first scan line S is located in the first electrode metal layer mc.

[0137] And / or, the second winding S0 of one of the first scan lines S is disposed on the same layer as the gate of the second transistor 28 and the second electrode plate c2 of the storage capacitor Cst. That is, the second winding S0 of the first scan line S is located in the first gate metal layer m1.

[0138] And / or, the display panel further includes a shielding metal 30. The shielding metal 30 is located between the transistor 21 and the substrate 20. In the direction perpendicular to the plane where the substrate 20 is located, the shielding metal 30 overlaps with the channel of the transistor 21. The second winding S0 of one of the first scan lines S is disposed on the same layer as the shielding metal 30. That is, the second winding S0 of the first scan line S is located in the shielding metal layer m0.

[0139] This setting method is applied to a panel with an "LTPO structure". There are more metal layers in this type of display panel, so more optional film layer positions can be provided for the second windings S0 of multiple first scan lines S to achieve a reasonable setting of the second winding S0.

[0140] In a feasible embodiment, referring to Figures 27 to 29 , the multiple transistors 21 include a driving transistor T0, a gate reset transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a bias transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and an anode reset transistor T7.

[0141] Among them, the gate reset transistor T1 is electrically connected to the gate reset scan line s1n, the gate reset line ref1, and the gate of the driving transistor T0, respectively.

[0142] The data writing transistor T2 is electrically connected to the data writing scan line sp, the data line D, and the first pole of the driving transistor T0, respectively.

[0143] The threshold compensation transistor T3 is electrically connected to the compensation scan line s2n, the second pole of the driving transistor T0, and the gate of the driving transistor T0, respectively.

[0144] The bias transistor T4 is electrically connected to the bias scan line spx, the bias signal line DVH, and the driving transistor T0, respectively. Exemplarily, the bias transistor T4 is electrically connected to the first pole of the driving transistor T0.

[0145] The first light emission control transistor T5 is electrically connected to the light emission control scan line Emit, the power supply line pvdd, and the first pole of the driving transistor T0, respectively.

[0146] The second light emission control transistor T6 is electrically connected to the light emission control scan line Emit, the second pole of the driving transistor T0, and the light emitting element 50, respectively.

[0147] The anode reset transistor T7 is electrically connected to the data writing scan line sp, the anode reset line ref2, and the light emitting element 50, respectively; or, the anode reset transistor T7 is electrically connected to the bias scan line spx, the anode reset line ref2, and the light emitting element 50, respectively.

[0148] Among them, the first transistor 27 includes at least one of the gate reset transistor T1 and the threshold compensation transistor T3, and the second transistor 28 includes at least one of the driving transistor T0, the data writing transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the anode reset transistor T7.

[0149] The first scan line S includes at least two of the gate reset scan line s1n, the compensation scan line s2n, the bias scan line spx, and the light emission control scan line Emit.

[0150] For example, in one structure, the first scan line S includes the gate reset scan line s1n, the compensation scan line s2n, the bias scan line spx, and the light emission control scan line Emit.

[0151] In a feasible setting manner, in the "3SD structure + LTPO structure", refer to Figure 28, the first sub-wire 8 connected to the first gating unit 41 is located in the third source-drain metal layer sd3, the first sub-wire 8 connected to the second gating unit 42 is located in the second source-drain metal layer sd2, the second sub-wire 9 connected to the first gating unit 41 is located in the first source-drain metal layer sd1, and the second sub-wire 9 connected to the second gating unit 42 is located in the first gate metal layer m1.

[0152] The second wire S0 in the gate reset scan line s1n is located in the first source-drain metal layer sd1, the second wire S0 in the compensation scan line s2n is located in the second gate metal layer mg, the second wire S0 in the light emission control scan line Emit is located in the first electrode metal layer mc, and the second wire S0 in the bias scan line spx is located in the first gate metal layer m1. In the gate reset scan line s1n, the compensation scan line s2n, the bias scan line spx, and the light emission control scan line Emit, the second wires S0 of at least two first scan lines S overlap in a direction perpendicular to the plane of the substrate 20.

[0153] Alternatively, in another feasible setting method, in the "2SD structure + LTPO structure", see Figure 29 , the first sub-wire 8 connected to the first gating unit 41 is located in the second source-drain metal layer sd2, the first sub-wire 8 connected to the second gating unit 42 is located in the first source-drain metal layer sd1, the second sub-wire 9 connected to the first gating unit 41 is located in the second gate metal layer mg, and the second sub-wire 9 connected to the second gating unit 42 is located in the first gate metal layer m1.

[0154] The second wire S0 in the compensation scan line s2n is located in the second gate metal layer mg, the second wire S0 in the light emission control scan line Emit is located in the first electrode metal layer mc, the second wire S0 in the bias scan line spx is located in the first gate metal layer m1, and the second wire S0 in the gate reset scan line s1n is located in the shielding metal layer m0. In the gate reset scan line s1n, the compensation scan line s2n, the bias scan line spx, and the light emission control scan line Emit, the second wires S0 of at least two first scan lines S overlap in a direction perpendicular to the plane of the substrate 20.

[0155] In addition, in this structure, the data write scan line sp can be bilaterally driven by the shift register. Therefore, the segments of the data write scan line sp that are disconnected on both sides of the light-transmitting hole 1 can be connected without using wires, and the two disconnected segments are respectively connected to a shift register.

[0156] In a feasible implementation manner, as Figure 30 and Figure 31 shown, Figure 30 is another schematic structural diagram of the pixel circuit provided by the embodiment of the present invention. Figure 31A schematic diagram of the position of the film layer of the second winding provided by the embodiment of the present invention. The display panel includes a pixel circuit 40, and the pixel circuit 40 includes a plurality of transistors 21. The active layers of the plurality of transistors 21 all include silicon materials.

[0157] The plurality of transistors 21 include a driving transistor T0, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. Among them, the first light-emitting control transistor T5 is electrically connected to the light-emitting control scan line Emit, the power supply line pvdd, and the first pole of the driving transistor T0 respectively, and the second light-emitting control transistor T6 is electrically connected to the light-emitting control scan line Emit, the second pole of the driving transistor T0, and the light-emitting element 50 respectively.

[0158] The first scan line S includes the light-emitting control scan line Emit, and the second winding S0 of the light-emitting control scan line Emit is arranged on the same layer as the gate of the transistor 21, that is, the second winding S0 of the light-emitting control scan line Emit is located in the first gate metal layer m1.

[0159] When the types of the first scan line S are relatively few, for example, only including one type of light-emitting control scan line Emit, the second winding S0 in the light-emitting control scan line Emit can be arranged in the first gate metal layer m1 closer to the substrate 20. In this way, the longitudinal distance between the second winding S0 and the first lead 34 can be increased, the coupling between the two can be reduced, and further the influence of the light-emitting control scan signal jump on the data signal can be reduced, improving the display quality.

[0160] In addition, the above pixel circuit 40 may further include a gate reset transistor T1, a data writing transistor T2, a threshold compensation transistor T3, and an anode reset transistor T7.

[0161] Among them, the gate reset transistor T1 is electrically connected to the gate reset scan line scan1, the gate reset line ref1, and the gate of the driving transistor T0 respectively.

[0162] The data writing transistor T2 is electrically connected to the data writing scan line scan2, the data line D, and the first pole of the driving transistor T0 respectively.

[0163] The threshold compensation transistor T3 is electrically connected to the data writing scan line scan2, the second pole of the driving transistor T0, and the gate of the driving transistor T0 respectively.

[0164] The anode reset transistor T7 is electrically connected to the data writing scan line scan2, the anode reset line ref2, and the light-emitting element 50 respectively.

[0165] In addition, in this structure, the data write scan line scan2 connected to the pixel circuit 40 in the previous row and the gate reset scan line scan1 connected to the pixel circuit 40 in the next row can be electrically connected to the same-stage shift register, and the shift register can perform bilateral driving on the gate reset scan line scan1 and the data write scan line scan2. The line segments disconnected on both sides of the light-transmitting hole 1 in the gate reset scan line scan1 and the data write scan line scan2 do not need to be connected by wire winding, and the line segments disconnected on both sides can be respectively connected to a shift register.

[0166] In a feasible implementation manner, the display panel includes a pixel circuit 40. Taking Figure 27 the shown pixel circuit 40 as an example, the pixel circuit 40 includes a data write transistor T2, and the data write transistor T2 is electrically connected to the data write scan line sp, the data line D, and the first pole of the driving transistor T0 respectively.

[0167] Wherein, in combination with Figure 3 、 Figure 27 、 Figure 28 、 Figure 32 and Figure 33 , Figure 32 FIG. is another structural schematic diagram of the display panel provided by the embodiment of the present invention, Figure 33 FIG. is a timing diagram provided by the embodiment of the present invention. The enable level of the first control line mux1 does not overlap with the enable level of the data write scan line sp, and the first winding D0 and the second winding S0 corresponding to the first control line mux1 are arranged in different layers. The enable level of the second control line mux2 overlaps with the enable level of the data write scan line sp, and at least part of the first winding D0 and at least part of the second winding S0 corresponding to the second control line mux2 are arranged in the same layer.

[0168] For example, referring to Figure 28 ,the metal layers where the second winding S0 is located are the first source-drain metal layer sd1, the first electrode metal layer mc, the first gate metal layer m1, and the shielding metal layer m0.

[0169] The first windings D0(11), D0(13), D0(21), and D0(23) corresponding to the first control line mux1 are located in the third source-drain metal layer sd3 and the second source-drain metal layer sd2, and this part of the first winding D0 is in a different layer from the second winding S0.

[0170] The first windings D0(12), D0(14), D0(22), and D0(24) corresponding to the second control line mux2 are located in the first source-drain metal layer sd1 and the first gate metal layer m1, and this part of the first winding D0 is in the same layer as part of the second winding S0.

[0171] When the strobe unit 4 performs a one - to - four design on the data line D, one data write scan line sp is electrically connected to two rows of pixel circuits 40.

[0172] The control line mux(1) and the control line mux(3) are the first control line mux1, and the control line mux(2) and the control line mux(4) are the second control line mux2.

[0173] Combined with Figure 6 , taking the i - th row pixel circuit and the (i + 1)-th row pixel circuit as an example for illustration. Among them, Figure 33 each signal corresponding to the i - th row pixel circuit in [] is represented by adding (i) to its corresponding reference numeral, and each signal corresponding to the (i + 1)-th row pixel circuit 40 is represented by adding (i + 1) to its corresponding reference numeral.

[0174] During the driving process of the i - th row pixel circuit and the (i + 1)-th row pixel circuit, referring to Figure 33 , first, the control line mux(1) provides a low level (enable level), and the source signal line Source writes a data voltage to the data line D corresponding to the control line mux(1). However, since the data write scan line sp(i) corresponding to the i - th row pixel circuit does not provide a low level during this period, therefore, during this period, the data line D corresponding to the control line mux(1) does not charge the first pixel circuit 16 and the second pixel circuit 17 in the i - th row pixel circuit, and the data voltage is only transmitted in the data line D.

[0175] Then, the control line mux(2) provides a low level. At the same time, the data write scan line sp(i) also starts to provide a low level. During this period, on the one hand, the data voltage on the data line D corresponding to the control line mux(1) starts to be written into the first pixel circuit 16 and the second pixel circuit 17 in the i - th row pixel circuit to charge the first pixel circuit 16 and the second pixel circuit 17. On the other hand, the data line D corresponding to the control line mux(2) receives the data voltage provided by the source signal line Source and simultaneously writes the data voltage into the third pixel circuit 18 in the i - th row pixel circuit.

[0176] Then again, the control line mux(3) provides a low level (enable level), and the source signal line Source writes a data voltage to the data line D corresponding to the control line mux(3). However, since the data write scan line sp(i + 1) corresponding to the (i + 1)-th row pixel circuit does not provide a low level during this period, therefore, during this period, the data line D corresponding to the control line mux(3) does not charge the first pixel circuit 16 and the second pixel circuit 17 in the (i + 1)-th row pixel circuit, and the data voltage is only transmitted in the data line D.

[0177] Finally, the control line mux (4) provides a low level. At the same time, the data write scan line sp(i + 1) also starts to provide a low level. During this period, on the one hand, the data voltage on the data line D corresponding to the control line mux (4) starts to be written into the first pixel circuit 16 and the second pixel circuit 17 in the (i + 1)-th row pixel circuit, charging the first pixel circuit 16 and the second pixel circuit 17. On the other hand, the data line D corresponding to the control line mux (4) receives the data voltage provided by the source signal line Source and simultaneously synchronously writes the data voltage into the third pixel circuit 18 in the (i + 1)-th row pixel circuit.

[0178] In summary, the charging method of the data line D corresponding to the first control line mux1 is only "line charging". Before charging the pixel circuit 40, there will be a floating state for a period of time, and its signal is more likely to be affected by other signal jumps and fluctuate, thus affecting the charging effect. Therefore, the first winding D0 in this part of the data line D can be set to a different layer from the second winding S0 to reduce the coupling between the two and avoid the influence of the scan signal jump to a greater extent. The charging method of the data line D corresponding to the second control line mux2 is "line charging + direct charging", and its charging is less affected by other signals. Considering that the overall number of metal layers occupied by the first winding D0 and the second winding S0 is relatively large, the first winding D0 in this part of the data line D can be set to the same layer as part of the second winding S0 to make the number of original metal layers in the display panel meet the wiring requirements of the windings.

[0179] Based on the same inventive concept, an embodiment of the present invention further provides a display device, as Figure 34 shown, Figure 34 is a schematic structural diagram of the display device provided by the embodiment of the present invention. The display device includes the above-mentioned display panel 100. Of course, Figure 34 the display device shown is only for illustrative purposes. The display device can be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book reader or a television.

[0180] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A light-transmitting hole, a first non-display area surrounding the light-transmitting hole, and a display area surrounding the first non-display area; A data line, part of which includes a first line segment, a first winding line, and a second line segment, wherein the first line segment and the second line segment are disconnected at both sides of the light-transmitting hole and are at least located in the display area, and the first winding line is connected between the first line segment and the second line segment and is located in the first non-display area; A plurality of gating units, each of which includes at least two gating switches; in each of the gating units, input ends of at least two of the gating switches are electrically connected to a source signal line, control ends of at least two of the gating switches are electrically connected to at least two control lines, and output ends of at least two of the gating switches are electrically connected to at least two of the data lines; Wherein, the first winding corresponding to the control line is the first winding connected to the selection switch connected to the control line; The control lines include at least one first control line and at least one second control line; The gating unit includes a first gating unit and a second gating unit; in the first winding connected to the first gating unit and the second gating unit: the first winding corresponding to the same first control line is arranged in different layers, and at least partially overlaps in a direction perpendicular to the plane where the display panel is located; the first winding corresponding to the first control line and the first winding corresponding to the second control line are arranged in different layers, and the first winding corresponding to the first control line and the first winding corresponding to the second control line at least partially do not overlap in a direction perpendicular to the plane where the display panel is located.

2. The display panel according to claim 1, characterized in that: The display panel comprises a first data line group and a second data line group which are alternately arranged, wherein the first data line group and the second data line group respectively comprise at least two adjacent data lines; The first gating unit is electrically connected to the first data line group, and the second gating unit is electrically connected to the second data line group.

3. The display panel according to claim 1, characterized in that: The gating unit includes 2m gating switches, the control lines include m first control lines and m second control lines, and m≥1; The first winding includes a first sub-winding corresponding to the first control line and a second sub-winding corresponding to the second control line; The first sub-winding electrically connected to the first gating unit is located at a first metal layer, the first sub-winding electrically connected to the second gating unit is located at a second metal layer, the second sub-winding electrically connected to the first gating unit is located at a third metal layer, and the second sub-winding electrically connected to the second gating unit is located at a fourth metal layer; Furthermore, among the first windings connected to the same selection unit, the orthographic projections of two adjacent first sub-windings on the plane where the display panel is located are separated by an orthographic projection of the second sub-winding on the plane where the display panel is located, and the orthographic projections of two adjacent second sub-windings on the plane where the display panel is located are separated by an orthographic projection of the first sub-winding on the plane where the display panel is located.

4. The display panel according to claim 3, characterized in that: m=2。 5. The display panel according to claim 1, characterized in that: The first winding includes a first sub-winding corresponding to the first control line; The first sub-winding electrically connected to the first gating unit is located at a first metal layer, and the first sub-winding electrically connected to the second gating unit is located at a second metal layer; Wherein, a planarization layer is provided between the first metal layer and the second metal layer.

6. The display panel according to claim 5, characterized in that: The display panel further comprises a substrate, a transistor and a connecting electrode, wherein the connecting electrode is electrically connected to a doping region of an active layer in the transistor through a via hole; The planarization layer comprises a first planarization layer and a second planarization layer, wherein the first planarization layer is located on a side of the connection electrode away from the substrate, and the second planarization layer is located on a side of the first planarization layer away from the substrate; The first metal layer is located on a side of the second planarization layer away from the substrate, and the second metal layer is located between the first planarization layer and the second planarization layer.

7. The display panel according to claim 5, characterized in that: The display panel further comprises a substrate, a transistor and a connecting electrode, wherein the connecting electrode is electrically connected to a doped region of an active layer in the transistor through a via hole; The planarization layer comprises a first planarization layer, and the first planarization layer is located on a side of the connection electrode away from the substrate; The first metal layer is located on a side of the first planarization layer away from the substrate, and the second metal layer includes the connecting electrode.

8. The display panel according to claim 1, characterized in that: The first winding includes a second sub-winding corresponding to the second control line; The second sub-winding electrically connected to the first gating unit is located at a third metal layer, and the second sub-winding electrically connected to the second gating unit is located at a fourth metal layer; Wherein, an inorganic insulating layer is spaced between the third metal layer and the fourth metal layer.

9. The display panel according to claim 8, characterized in that: Another metal layer is provided between the third metal layer and the fourth metal layer; In the second sub-windings connected to the first gating unit and the second gating unit, the second sub-windings corresponding to the same second control line at least partially overlap in a direction perpendicular to the plane where the display panel is located.

10. The display panel according to claim 9, characterized in that: The display panel further comprises a substrate, a transistor and a connecting electrode, wherein the connecting electrode is electrically connected to a doped region of an active layer in the transistor through a via hole; The third metal layer includes the connecting electrode, and the fourth metal layer is located on a side of the third metal layer close to the substrate.

11. The display panel according to claim 9, characterized in that: The display panel further comprises a substrate and a transistor, wherein the transistor comprises a first transistor, and an active layer of the first transistor comprises a metal oxide material; The third metal layer includes a gate of the first transistor, and the fourth metal layer is located on a side of the third metal layer close to the substrate.

12. The display panel according to claim 10 or 11, characterized in that: The transistor includes a second transistor, an active layer of the second transistor includes a silicon material, and the fourth metal layer includes a gate of the second transistor; Alternatively, the display panel further includes a blocking metal, the blocking metal is located between the transistor and the substrate, the blocking metal overlaps with a channel of the transistor in a direction perpendicular to a plane where the substrate is located, and the fourth metal layer includes the blocking metal.

13. The display panel according to claim 8, characterized in that: The third metal layer and the fourth metal layer are two adjacent metal layers; In the second sub-windings connected to the first gating unit and the second gating unit, the second sub-windings corresponding to the same second control line at least partially do not overlap in a direction perpendicular to the plane where the display panel is located.

14. The display panel according to claim 13, characterized in that: The display panel further comprises a substrate, a storage capacitor and a transistor, wherein the transistor comprises a second transistor, and an active layer of the second transistor comprises a silicon material; The third metal layer includes a first plate of the storage capacitor, and the fourth metal layer includes a gate of the second transistor and a second plate of the storage capacitor.

15. The display panel according to claim 1, characterized in that: The gating unit includes three gating switches, and the control lines include n first control lines and 3-n second control lines, where n=1 or n=2; Wherein, in the first winding corresponding to the first control line, the first winding electrically connected to the first gating unit and the second gating unit is located in the first metal layer and the second metal layer respectively; In the first winding corresponding to the second control line, the first winding electrically connected to the first gating unit and the second gating unit is located in the third metal layer and the fourth metal layer respectively; In the first winding corresponding to the third control line, the first winding electrically connected to the first gating unit and the second gating unit are located in the fifth metal layer and the sixth metal layer, respectively.

16. The display panel according to claim 15, characterized in that: n=2； The display panel further includes a substrate, and the distances between the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the fifth metal layer and the sixth metal layer and the substrate decrease gradually; Among the first windings electrically connected to the first selection unit and the second selection unit, the first windings corresponding to one of the first control lines are respectively located in the first metal layer and the second metal layer, and the first windings corresponding to another first control line are respectively located in the fifth metal layer and the sixth metal layer, and the first windings corresponding to the two first control lines at least partially overlap in a direction perpendicular to the plane where the display panel is located.

17. The display panel according to claim 1, characterized in that: The display panel further includes a first scan line, part of which includes a third line segment, a second winding line and a fourth line segment, wherein the third line segment and the fourth line segment are disconnected at both sides of the light-transmitting hole and are at least located in the display area, the extension direction of the third line segment and the fourth line segment intersects with the extension direction of the first line segment and the second line segment, and the second winding line is connected between the third line segment and the fourth line segment and is located in the first non-display area; Wherein, the second winding is located on a side of the first winding away from the light-transmitting hole.

18. The display panel according to claim 17, characterized in that: The first winding and the first line segment, and the first winding and the second line segment are respectively connected via a first lead wire; On a plane perpendicular to the display panel, the first lead line overlaps the second winding line, and the first lead line and the first line segment and the second line segment extend in the same direction.

19. The display panel according to claim 18, characterized in that: The first lead is arranged in the same layer as the first line segment and the second line segment; And / or, the display panel also includes a substrate, a transistor and a connecting electrode, the connecting electrode is electrically connected to the doped region of the active layer in the transistor through a via, and the metal layer where the first lead is located is located on a side of the metal layer where the connecting electrode is located away from the substrate.

20. The display panel according to claim 18, characterized in that: The first lead includes a first sub-lead and a second sub-lead; The first sub-lead and the first winding connected thereto are arranged in different layers and are connected through a first connecting portion, the second sub-lead and the first winding connected thereto are arranged in the same layer and are connected through a second connecting portion, and the first connecting portion and the second connecting portion are arranged in the same layer.

21. The display panel according to claim 18, characterized in that: At least part of the first lead and the first winding connected thereto are arranged in different layers and are connected via a connecting portion, and the connecting portion is located between the first winding and the second winding.

22. The display panel according to claim 17, characterized in that: The display panel includes at least two types of the first scanning lines, the second windings of the same type of the first scanning lines are arranged in the same layer, and the second windings of different types of the first scanning lines are arranged in different layers, and in a direction perpendicular to the plane where the display panel is located, the second windings of at least two types of the first scanning lines overlap.

23. The display panel according to claim 22, characterized in that: The display panel includes a pixel circuit, and the pixel circuit includes a storage capacitor and a plurality of transistors; wherein the transistor includes a first transistor and a second transistor, an active layer of the first transistor includes a metal oxide material, and an active layer of the second transistor includes a silicon material; The display panel further comprises a connecting electrode, the connecting electrode is electrically connected to a doping region of an active layer in the transistor through a via hole, wherein the second winding of the first scanning line is arranged in the same layer as the connecting electrode; And / or, the second winding of the first scanning line is arranged in the same layer as the gate of the first transistor; And / or, wherein the second winding of the first scanning line is arranged in the same layer as the first electrode plate of the storage capacitor; And / or, the second winding of the first scanning line is arranged in the same layer as the gate of the second transistor and the second plate of the storage capacitor; And / or, the display panel also includes a substrate and a shielding metal, the shielding metal is located between the transistor and the substrate, the shielding metal overlaps with the channel of the transistor in a direction perpendicular to the plane of the substrate, and the second winding of the first scanning line is arranged on the same layer as the shielding metal.

24. The display panel according to claim 23, characterized in that: The plurality of transistors include: Driver transistor; A gate reset transistor, electrically connected to the gate reset scan line, the gate reset line and the gate of the driving transistor respectively; A data writing transistor is electrically connected to the data writing scanning line, the data line and the first electrode of the driving transistor respectively; a threshold compensation transistor, electrically connected to the compensation scan line, the second electrode of the driving transistor and the gate of the driving transistor respectively; A bias transistor, electrically connected to the bias scan line, the bias signal line and the driving transistor respectively; A first light emitting control transistor is electrically connected to the light emitting control scanning line, the power supply line and the first electrode of the driving transistor respectively; A second light emitting control transistor is electrically connected to the light emitting control scanning line, the second electrode of the driving transistor and the light emitting element respectively; The first transistor includes at least one of the gate reset transistor and the threshold compensation transistor, and the second transistor includes at least one of the drive transistor, the data write transistor, the first light emission control transistor and the second light emission control transistor; The first scan lines include at least two of the gate resetting scan lines, the compensation scan lines, the bias scan lines, and the light emission control scan lines.

25. The display panel according to claim 17, characterized in that: The display panel comprises a pixel circuit, the pixel circuit comprises a plurality of transistors, and active layers of the plurality of transistors each comprise silicon material; The plurality of transistors include a driving transistor, a first light-emitting control transistor, and a second light-emitting control transistor, wherein the first light-emitting control transistor is electrically connected to a light-emitting control scan line, a power line, and a first electrode of the driving transistor, respectively, and the second light-emitting control transistor is electrically connected to the light-emitting control scan line, a second electrode of the driving transistor, and a light-emitting element, respectively; The first scan line includes the light emission control scan line, and the second winding of the light emission control scan line is arranged at the same layer as the gate of the transistor.

26. The display panel according to claim 17, characterized in that: The display panel comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor and a data writing transistor, wherein the data writing transistor is electrically connected to a data writing scanning line, the data line and a first electrode of the driving transistor respectively; Wherein, the enable level of the first control line does not overlap with the enable level of the data writing scan line, and the first winding and the second winding corresponding to the first control line are arranged in different layers; The enable level of the second control line overlaps with the enable level of the data writing scan line, and at least a portion of the first winding and at least a portion of the second winding corresponding to the second control line are arranged in the same layer.

27. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 26.

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