Display device

Abstract

There is provided a display device including: a display panel including sub-pixels connected to a power line, a data line, and a reference line; a power supply device configured to supply power to the display panel through the power line; a data driver including a driving circuit configured to supply a data voltage to the display panel through the data lines and a sensing circuit configured to sense the display panel through the reference lines; and a timing controller configured to control the power supply device and the data driver, in which the sensing circuit has a variable sampling point for sensing the display panel in response to a change in a level of the power.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0197869, filed on Dec. 29, 2023, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] With the development of information technology, the market for display devices as a connection medium between users and information has been growing. Accordingly, display devices such as light-emitting display (LED) devices, quantum dot displays (QDDs), and liquid crystal displays (LCDs) have been increasingly used.

[0004] Each of the above display devices includes: a display panel including sub-pixels; a driver configured to output a driving signal for driving the display panel; and a power supply device configured to generate power to be supplied to the display panel or the driver.

[0005] In such a display device, when a driving signal such as a scan signal and a data signal is supplied to sub-pixels formed in the display panel, one of the selected sub-pixels in the sub-pixels may thereby transmit light or may directly emit light, thereby displaying an image. Summary of the Invention

[0006] Accordingly, the present disclosure relates to a display device that substantially avoids one or more problems caused by limitations and disadvantages of the related art.

[0007] The present disclosure changes a sampling point in response to a change in the level of a first power or reflects the change in the level of the first power in a sense voltage to increase the probability of obtaining a constant (uniform) sense voltage, thereby improving compensation accuracy and minimizing the occurrence of a sense error due to a change in the level of the first power.

[0008] Additional advantages, objects, and features of the present disclosure will be partly set forth in the description that follows, and partly will be obvious to those of ordinary skill in the art after examination of the following, or may be learned from practice of the present disclosure. The objects and other advantages of the present disclosure may be realized and obtained by the structure particularly pointed out in the written description and claims of the present disclosure and the drawings.

[0009] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a display device includes: a display panel including sub-pixels connected to a power line, a data line, and a reference line; a power supply device configured to supply power to the display panel through the power line; a data driver including a driving circuit and a sensing circuit, the driving circuit being configured to supply a data voltage to the display panel through the data line, the sensing circuit being configured to sense the display panel through the reference line; and a timing controller configured to control the power supply device and the data driver, wherein the sensing circuit has a variable sampling point for sensing the display panel in response to a change in the level of the power.

[0010] The sensing circuit may advance the sampling time from a reference sampling time when the level of the power becomes higher than a reference level, and may delay the sampling time from the reference sampling time when the level of the power becomes lower than the reference level.

[0011] The sensing circuit may include a sampling circuit configured to sense the reference line, and the sampling time may correspond to the on-time of the sampling circuit.

[0012] The timing controller may be configured to: calculate a level of a first power required to drive the display panel based on a data signal to prepare a first power calculation value, and generate a sampling control signal for changing the sampling time based on the first power calculation value.

[0013] The timing controller may generate a sampling control signal for changing the sampling time based on one of the first power calculation value and a first power sensing value prepared by sensing the first power output from the power supply device.

[0014] In another aspect of the present disclosure, a display device includes: a display panel including sub-pixels connected to a power line, a data line, and a reference line; a power supply device configured to supply power to the display panel through the power line; a data driver including a driving circuit and a sensing circuit, the driving circuit being configured to supply a data voltage to the display panel through the data line, the sensing circuit being configured to sense the display panel through the reference line to prepare a sensing voltage; and a timing controller configured to control the power supply device and the data driver, wherein the timing controller prepares a corrected sensing voltage by reflecting a change in the level of the power in the sensing voltage transmitted from the sensing circuit, and compensates the data signal based on the corrected sensing voltage to generate a compensated data signal.

[0015] The timing controller may be configured to: calculate a level of a first power required to drive a display panel based on a data signal to prepare a first power calculation value; and predict a change in the level of the first power based on the first power calculation value, and reflect the predicted change in a sense voltage to prepare a corrected sense voltage.

[0016] The timing controller may predict a change in the level of the first power based on one of the first power calculation value and a first power sense value prepared by sensing the first power output from a power supply device, and may reflect the predicted change in the sense voltage to prepare a corrected sense voltage.

[0017] The timing controller may generate a sampling control signal for changing a sampling time for sensing the display panel based on one of the first power sense value and the first power calculation value.

[0018] The sensing circuit may include a sampling circuit configured to sense a reference line to prepare a sense voltage, and the sampling time may correspond to an on-time of the sampling circuit.

[0019] The timing controller may include a look-up table including a data table for preparing a corrected sense voltage in response to a change in the level of the first power.

[0020] It should be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings included to provide a further understanding of the present disclosure and incorporated in and constituting a part of this application illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0022] Figure 1 is a block diagram schematically showing an LED device, Figure 2 is schematically showing Figure 1 a configuration diagram of sub-pixels shown in, and Figure 3 is an example diagram of a pixel including sub-pixels;

[0023] Figure 4 and Figure 5 is a diagram for describing a configuration of a gate-in-panel (GIP) type scan driver, and Figure 6 is a diagram showing an arrangement example of the GIP type scan driver;

[0024] Figure 7 is a schematic diagram briefly showing sub-pixels and a data driver according to a first embodiment, Figure 8is a waveform diagram for describing a sensing period and a display period according to a first embodiment, Figure 9 and Figure 10 is a diagram for describing an output change of a power supply device according to a first embodiment, Figure 11 is a diagram for describing a method of changing sampling points in response to an output change of a power supply device according to a first embodiment, and Figure 12 is a diagram for describing an advantage according to a first embodiment;

[0025] Figure 13 is an exemplary diagram showing in more detail a sub-pixel and a data driver according to a second embodiment, Figure 14 and Figure 15 is a waveform diagram for describing a sampling method according to a second embodiment, and Figure 16 and Figure 17 is a diagram for describing a change of sampling points in response to a change in first power;

[0026] Figure 18 is an exemplary diagram showing in more detail a main configuration included in an LED device according to a third embodiment, and Figure 19 is an exemplary diagram showing a modification of a third embodiment; and

[0027] Figure 20 is an exemplary diagram showing in more detail a main configuration included in an LED device according to a fourth embodiment, and Figure 21 is an exemplary diagram showing a modification of a fourth embodiment. Detailed Description of the Embodiments

[0028] Reference will now be made in detail to the preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0029] The present disclosure can be implemented as a television, a video player, a personal computer (PC), a home theater, an automotive electrical device, or a smart phone, but is not limited thereto. The present disclosure can be implemented as an LED device, a QDD, or an LCD. For ease of description, hereinafter, an LED device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be taken as an example.

[0030] Figure 1 is a block diagram schematically showing an LED device, Figure 2 is schematically showing Figure 1 a configuration diagram of a sub-pixel shown in Figure 3 is an example diagram of a pixel including sub-pixels.

[0031] As Figures 1 to 3As shown, the LED device may include an image supply device 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, a power supply device 180, etc.

[0032] The image supply device (complete system or host system) 110 may output various driving signals together with the image data signal supplied from the outside or the image data signal stored in the internal memory. The image supply device 110 may supply the data signal and various driving signals to the timing controller 120.

[0033] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, various synchronization signals, etc. The timing controller 120 may supply the data signal DATA supplied from the image supply device 110 to the data driver 140 together with the data timing control signal DDC. The timing controller 120 may be in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0034] The scan driver 130 may output a scan signal (or scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 may supply the scan signal to each of the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The scan driver 130 may be in the form of an IC, or may be directly formed on the display panel 150 in a GIP manner, but is not limited thereto.

[0035] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the obtained digital data signal into an analog data voltage based on the gamma reference voltage, and output the converted analog data voltage. The data driver 140 may supply the data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be in the form of an IC and mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0036] The power supply device 180 may generate a first power at a high potential and a second power at a low potential based on an external input voltage supplied from the outside. The power supply device 180 may output the first power through a first power line EVDD, and may output the second power through a second power line EVSS. The power supply device 180 may not only generate and output the first power and the second power, but also generate and output a voltage required to drive the scan driver 130 (e.g., a scan high voltage and a scan low voltage) or a voltage required to drive the data driver 140 (a drain voltage and a semi-drain voltage). Under the control of the timing controller 120, the power supply device 180 may generate and change the first power at a high potential and the second power at a low potential. However, the present disclosure is not limited thereto.

[0037] The display panel 150 may display an image in response to a scan signal, a driving signal including a data voltage, a first power, a second power, etc. Sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, polyimide, etc. For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a pixel circuit having a switching transistor, a driving transistor, a capacitor, an organic light emitting diode, etc.

[0038] The sub-pixel SP used in the LED device directly emits light and thus has a complex circuit configuration. In addition, there are various compensation circuits that not only compensate for the deterioration of the organic light emitting diode that emits light, but also compensate for the deterioration of the driving transistor that supplies the driving current required to drive the organic light emitting diode. Therefore, note that the sub-pixel SP is shown only in the form of a block.

[0039] The sub-pixels that emit light may include pixels having colors of red, green, and blue or pixels having colors of red, green, blue, and white. For example, one pixel P may include a red sub-pixel SPR connected to a first data line DL1, a white sub-pixel SPW connected to a second data line DL2, a green sub-pixel SPG connected to a third data line DL3, and a blue sub-pixel SPB connected to a fourth data line DL4. In addition, the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB may be commonly connected to a first reference line VREF1. The first reference line VREF1 may be used to sense the deterioration of an element included in one of the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB, which will be discussed below.

[0040] Meanwhile, the timing controller 120, the scan driver 130, the data driver 140, etc. have been described above as having separate configurations. However, according to the implementation of the LED device, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC. In addition, the pixel P in which the red sub-pixel SPR, the white sub-pixel SPW, the green sub-pixel SPG, and the blue sub-pixel SPB are arranged in this order has been shown above as an example. However, the arrangement order and direction of the sub-pixels may be changed according to the implementation of the LED device.

[0041] Figure 4 and Figure 5 is a diagram for describing the configuration of the GIP type scan driver, and Figure 6 is a diagram showing an arrangement example of the GIP type scan driver.

[0042] As Figure 4 shown, the GIP type scan driver may include a shift register 131 and a level shifter 135. The level shifter 135 may generate driving clock signals Clks, start signals Vst, etc. based on the signals and voltages output from the timing controller 120 and the power supply device 180.

[0043] The shift register 131 may operate based on the signals Clks and Vst output from the level shifter 135, and output scan signals Scan[1] to Scan[m] capable of turning on or off the transistors formed on the display panel. The shift register 131 may be in the form of a thin film and formed on the display panel using the GIP method.

[0044] As Figure 4 and Figure 5 shown, different from the shift register 131, the level shifter 135 may independently be in the form of an IC or be included in the power supply device 180. However, this is only an example, and the present disclosure is not limited thereto.

[0045] As Figure 6 shown, in the GIP type scan driver, the first shift register 131a and the second shift register 131b configured to output scan signals may be provided in the non-active area NA of the display panel 150. As an example, the shift registers 131a and 131b are shown as being provided in the non-active areas NA on the right and left sides of the display panel 150. However, the shift registers 131a and 131b may be provided in the non-active areas NA on the upper and lower sides of the display panel 150, or may be provided in the active area AA of the display panel 150.

[0046] Figure 7is an exemplary diagram briefly showing a sub-pixel and a data driver according to a first embodiment, Figure 8 is a waveform diagram for describing a sensing period and a display period according to a first embodiment, Figure 9 and Figure 10 is a diagram for describing an output change of a power supply device according to a first embodiment, Figure 11 is a diagram for describing a method of changing a sampling point in response to an output change of a power supply device according to a first embodiment, and Figure 12 is a diagram for describing an advantage according to a first embodiment.

[0047] As Figure 7 shown, according to a first embodiment, one sub-pixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light-emitting diode OLED.

[0048] The driving transistor DT may have a gate electrode connected to a first electrode of the capacitor CST, a first electrode connected to a first power line EVDD, and a second electrode connected to an anode of the organic light-emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may have an anode connected to the second electrode of the driving transistor DT and a cathode connected to a second power line EVSS.

[0049] The switching transistor SW may have a gate electrode connected to a first scan line Gate1 included in a first gate line GL1, a first electrode connected to a first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The sensing transistor ST may have a gate electrode connected to a second scan line Gate2 included in the first gate line GL1, a first electrode connected to a first reference line VREF1, and a second electrode connected to the anode of the organic light-emitting diode OLED.

[0050] The sensing transistor ST is a compensation circuit added to compensate for deterioration (deterioration in threshold voltage, mobility, etc.) of the driving transistor DT or the organic light-emitting diode OLED. The sensing transistor ST may implement physical threshold voltage sensing based on a source follower operation of the driving transistor DT. The sensing transistor ST may operate to obtain a sensing voltage through a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED. At the same time, the first gate line GL1 may be integrated without being divided into the first scan line Gate1 and the second scan line Gate2. That is, the switching transistor SW and the sensing transistor ST may be commonly connected to the first gate line GL1 and turned on or off simultaneously.

[0051] In addition, according to the first embodiment, the data driver 140 may include a driving circuit 141 for driving the sub-pixel SP and a sensing circuit 145 for sensing the sub-pixel SP. The driving circuit 141 may be connected to the first data line DL1 through the first data channel DCH1. The driving circuit 141 may output a data voltage Vdata for driving the sub-pixel SP through the first data channel DCH1.

[0052] The sensing circuit 145 may be connected to the first reference line VREF1 through the first sensing channel SCH1. The sensing circuit 145 may obtain a sensing voltage Vsen sensed from the sub-pixel SP through the first sensing channel SCH1. The sensing circuit 145 may obtain the sensing voltage Vsen based on a current sensing or voltage sensing method. The sensing circuit 145 may include a sampling circuit SAM that operates to obtain the sensing voltage Vsen and the like. The sampling circuit SAM is shown only as a switch, but is not limited thereto.

[0053] As Figure 8 shown, the LED device according to the first embodiment may drive the display panel for a sensing period PSP and a display period DSP respectively based on a vertical synchronization signal Vsync and a data enable signal DE. As an example, the sensing period PSP occurs in response to a vertical blanking period Vblank included in the vertical synchronization signal Vsync, but is not limited thereto.

[0054] As Figure 7 and Figure 8 shown, the LED device according to the first embodiment may drive the sensing circuit 145 during the sensing period PSP to sense the sub-pixel SP included in the display panel. In addition, the LED device according to the first embodiment may drive the driving circuit 141 during the display period DSP to display an image based on the sub-pixel SP included in the display panel.

[0055] As Figures 8 to 10 shown, the LED device according to the first embodiment may change the first power output from the power supply device 180 during at least one of the sensing period PSP or the display period DSP. For example, the power supply device 180 may output a first power Evdd1 at a first level and then output a first power Evdd2 at a higher second level, or may conversely change the first power.

[0056] The LED device according to the first embodiment may change the first power output from the power supply device 180 to reduce power consumption or improve color reproduction ability. The level of the first power is not limited to Figure 9 and Figure 10level, and can be changed to different levels according to the characteristics of the image displayed on the display panel.

[0057] As Figures 7 to 11 shown, the LED device according to the first embodiment can change the sampling point (specifically, the starting point) of the sampling circuit SAM in response to the change in the first power during the sensing period PSP to obtain the sensing voltage Vsen. For example, when the first power Evdd1 at the first level is output from the power supply device 180, the second time SAM_On@T2 can be selected as the sampling point of the sampling circuit SAM. In contrast, when the first power Evdd2 at the second level higher than the first power Evdd1 at the first level is output from the power supply device 180, the first time SAM_On@T1 earlier than the second time SAM_On@T2 can be selected as the sampling point of the sampling circuit SAM.

[0058] Figure 12 is a reference diagram showing the following: using the compensation method of the first embodiment to solve the problem of the deviation ΔV existing in the sensing voltage Vsen when the first power Evdd changes between 18V and 24V, so that a constant (uniform) sensing voltage Vsen can be obtained.

[0059] As in the first embodiment, by changing the sampling point of the sampling circuit SAM in response to the change in the first power Evdd output from the power supply device 180, even when the current value changes in response to the change in the first power Evdd, the probability of obtaining a constant (uniform) sensing voltage Vsen can be increased. Therefore, the first embodiment can improve the compensation accuracy and minimize the occurrence of sensing errors because a constant (uniform) sensing voltage (sensing voltage value) Vsen can be obtained even when the level of the first power Evdd changes.

[0060] Figure 13 is an exemplary diagram showing the sub-pixel and the data driver according to the second embodiment in more detail, Figure 14 and Figure 15 is a waveform diagram for describing the sampling method according to the second embodiment, and Figure 16 and Figure 17 is a diagram for describing changing the sampling point in response to the change in the first power.

[0061] As Figure 13As shown, according to the second embodiment, the driving circuit 141 may include a digital-to-analog converter (DAC) to output a sense data voltage and a blank data voltage in addition to the display data voltage Vdata. The sensing circuit 145 may include a first voltage circuit SPRE, a second voltage circuit RPRE, a sampling circuit SAM, an analog-to-digital converter (ADC), etc., to output a voltage and a sense voltage to the sub-pixel SP and the first reference line VREF1.

[0062] The first voltage circuit SPRE and the second voltage circuit RPRE may perform a voltage output operation to initialize a node or a circuit included in the sub-pixel SP, or to charge the node or the circuit with a voltage at a specific level. The first voltage circuit SPRE and the second voltage circuit RPRE may include a first reference voltage source VPRES and a second reference voltage source VPRER, respectively. The first voltage circuit SPRE may output a first reference voltage based on the first reference voltage source VPRES, and the second voltage circuit RPRE may output a second reference voltage based on the second reference voltage source VPRER. The first reference voltage is a voltage for degradation compensation in the sensing mode (compensation mode), and the second reference voltage may be defined as a voltage for image display in the driving mode (normal mode). In addition, the first reference voltage may be set to a voltage lower than the second reference voltage.

[0063] The sampling circuit SAM may perform a sampling operation to obtain a sense voltage through the first reference line VREF1. The analog-to-digital converter ADC may convert the analog sense voltage obtained by the sampling circuit SAM into a digital sense voltage and output the converted sense voltage. The analog-to-digital converter ADC may change the ratio (amplify or reduce) to easily convert the sense voltage stored in the sampling capacitor SCAP.

[0064] The sensing circuit 145 may obtain a sense voltage Vsen through a sensing capacitor PCAP formed on the first reference line to compensate for the degradation of the driving transistor DT or the organic light-emitting diode OLED included in the sub-pixel SP. The sensing circuit 145 may obtain a sense voltage Vsen through a sampling capacitor SCAP formed in the sampling circuit SAM, convert the analog sense voltage Vsen obtained through the analog-to-digital converter ADC into a digital sense voltage VSEN, and output the converted sense voltage. The digital sense voltage VSEN output from the sensing circuit 145 may be sent to the timing controller 120. The digital sense voltage VSEN may be transmitted and received through a communication interface (e.g., LVDS) connected between the data driver 140 and the timing controller 120.

[0065] The timing controller 120 may determine whether the driving transistor DT or the organic light emitting diode OLED included in the sub-pixel SP has deteriorated based on the digital sensing voltage VSEN, and perform a compensation operation to compensate for the deterioration. For example, the timing controller 120 may output the data signal DATA supplied from the image supply device without change, or output the compensated data signal CDATA obtained by performing the compensation operation.

[0066] The timing controller 120 may output a sampling control signal SAMC that can turn on or off the sampling circuit SAM included in the sensing circuit 145. The sampling control signal SAMC may change the on / off time of the sampling circuit SAM in response to a change in the first power supplied through the first power line EVDD. The timing controller 120 may output a gate control signal GCS that can change the second scan signal applied to the second scan line Gate2. The gate control signal GCS may change the on / off time of the second scan signal in response to a change in the first power supplied through the first power line EVDD. The scan driver may change the on / off time of the second scan signal in response to the gate control signal GCS.

[0067] As Figures 13 to 15 shown, according to the second embodiment, the sensing periods PSP1 to PSP3 for sensing the sub-pixels SP included in the display panel may include a first period PSP1, a second period PSP2, and a third period PSP3.

[0068] The first scan signal Scan applied to the first scan line Gate1 may be in a high H state (the on time of the first scan signal) during the first period PSP1. Therefore, the switching transistor SW may be turned on in response to the first scan signal Scan in the high H state during the first period PSP1.

[0069] The second scan signal Sense applied to the second scan line Gate2 may be in a high H state (the on time of the second scan signal) during the first period PSP1 and the second period PSP2. Therefore, the sensing transistor ST may be turned on in response to the second scan signal Sense in the high H state during the first period PSP1 and the second period PSP2.

[0070] The first voltage control signal Sp re applied to the first voltage circuit SPRE may be in a high H state (the on time of the first voltage control signal) during the first period PSP1. Therefore, the first voltage circuit SPRE may output the first reference voltage required for the sensing mode through the first reference line VREF1 in response to the first voltage control signal Sp re in the high H state during the first period PSP1.

[0071] The digital-to-analog converter DAC included in the drive circuit 141 can operate during the first period PSP1. Accordingly, the digital-to-analog converter DAC can output the sensed data voltage Vdata required for the sensing mode through the first data line DL1 during the first period PSP1.

[0072] The sampling control signal SAMC applied to the sampling circuit SAM can be in the high H state (the conduction time of the sampling control signal) during the third period PSP3. Accordingly, the sampling circuit SAM can acquire the sensed voltage Vsen stored in the first reference line VREF1 in response to the sampling control signal SAMC being in the high H state during the third period PSP3.

[0073] Figure 14 is an exemplary diagram showing the following: when a first power Evdd2 at a second level higher than the first power Evdd1 is applied, the sampling point for acquiring the sensed voltage Vsen is advanced to the first time SAM_On@T1. In addition, Figure 15 shows the following: when a first power Evdd1 at a first level lower than the first power Evdd2 at the second level is applied, the sampling point for acquiring the sensed voltage Vsen is delayed to a second time SAM_On@T2 later than the first time SAM_On@T1. Accordingly, Figure 14 and Figure 15 the waveform diagrams of need to be interpreted as examples to describe that the sampling point can change in response to a change in the level of the first power.

[0074] As Figure 16 and Figure 17 shown, the sensed voltage Vsen can be related to the current applied to the sensing capacitor formed on the reference line. The sensed voltage Vsen can change in response to a change in voltage ΔV and a change in time Δt. Accordingly, by changing the sampling point corresponding to the element that changes the time Δt among the elements that determine the sensed voltage Vsen, the difference caused by the change in the first power can be compensated.

[0075] Based on this, in the second embodiment, the sampling points prepared differently from the first time SAM_On@T1 to the Nth time SAM_On@Tn in response to the change of the first power from the first power Evdd1 at the first level to the first power Evddn at the Nth level (N is an integer greater than or equal to 2) can be defined as the range of sampling points. In addition, by using one of the sampling points set within the range of sampling points in response to the change of the first power, the probability of obtaining a constant (uniform) sensed voltage (sensed voltage value) Vsen can be increased.

[0076] As can be seen from the description of the second embodiment, the sampling points for obtaining the sensed voltage Vsen can change in response to a change in the first power. However, a specific level of the first power can be defined as a reference sampling point, and the sampling point can be set to change from the reference sampling point in response to a change in the level of the first power when the level decreases or increases. In this case, in order to define the reference sampling point, the reference level of the first power can be determined based on experiments or simulations. However, the present disclosure is not limited thereto.

[0077] Therefore, in the second embodiment, even when the level of the first power Evdd is variable, a constant (uniform) sensed voltage (sensed voltage value) Vsen can be obtained. Accordingly, the compensation accuracy can be improved and the occurrence of sensing errors can be minimized.

[0078] Figure 18 is an exemplary diagram showing in more detail the main configurations included in the LED device according to the third embodiment, and Figure 19 is an exemplary diagram showing a modification of the third embodiment.

[0079] As Figure 18 shown, according to the third embodiment, the timing controller 120 may include a first power calculator 121, a first power controller 122, a sensed voltage corrector 124, a data compensator 126, a signal output circuit 129, etc.

[0080] The first power calculator 121 may calculate the level of the first power required to drive the display panel 150 based on the data signal DATA supplied from the outside, and prepare a first power calculation value EPV. The first power calculator 121 may prepare the first power calculation value EPV such that the level of the first power output from the power supply device 180 can increase or decrease according to the characteristics of the data signal DATA.

[0081] The first power controller 122 may output a power control signal VCS for determining or changing the level of the first power output from the power supply device 180 based on the first power calculation value EPV sent from the first power calculator 121.

[0082] The sensed voltage corrector 124 may prepare a corrected sensed voltage VSEN' based on the first power calculation value EPV (which may also be referred to as the calculation result value of the first power) provided from the first power calculator 121 and the sensed voltage VSEN sent from the data driver 140. The sensed voltage corrector 124 may output the sensed voltage VSEN without change when the level of the first power does not change and remains constant, and generate a corrected sensed voltage VSEN' by reflecting the change in the level of the first power in the sensed voltage VSEN when the level of the first power changes.

[0083] The data compensator 126 may compensate the data signal DATA supplied from the outside based on the sensed voltage VSEN or the corrected sensed voltage VSEN'. The data compensator 126 may determine whether there is deterioration (deterioration in threshold voltage, mobility, etc.) of elements included in the sub-pixels SP of the display panel 150 based on the sensed voltage VSEN or the corrected sensed voltage VSEN'. The data compensator 126 may output the data signal DATA supplied from the outside without change in response to the presence or absence of deterioration of elements included in the sub-pixels SP, or may compensate the data signal DATA based on the sensed voltage VSEN or the corrected sensed voltage VSEN' and output the compensated data signal CDATA.

[0084] The signal output circuit 129 may output the data signal DATA or the compensated data signal CDATA transmitted from the data compensator 126. The signal output circuit 129 may output the data signal DATA or the compensated data signal CDATA through a communication interface (e.g., EPI) connected to the data driver 140.

[0085] Meanwhile, Figure 18 The following is shown: The sampling circuit SAM and the analog-to-digital converter ADC included in the sensing circuit 145 of the data driver 140 sense the sub-pixels SP through the first reference line VREF1 of the display panel 150. However, note that Figure 18 the first reference line VREF1 shown corresponds to any reference line existing on the display panel 150.

[0086] According to the third embodiment, the timing controller 120 may predict (detect) a change in the first power based on the first power calculation value EPV, correct the sensed voltage VSEN transmitted from the data driver 140 in response to the change in the first power, and prepare the corrected sensed voltage VSEN'. Even when the level of the first power changes, the third embodiment may perform correction by reflecting the change in the level of the first power in the sensed voltage (sensed voltage value) VSEN, and thus may improve the compensation accuracy and minimize the occurrence of sensing errors.

[0087] As Figure 19 shown, according to a modification of the third embodiment, the timing controller 120 may include a first power calculator 121, a first power controller 122, a voltage sensor 123, a sensed voltage corrector 124, a data compensator 126, a signal output circuit 129, etc. Hereinafter, in the modification of the third embodiment, the description will focus on the parts different from the third embodiment.

[0088] The voltage sensor 123 may sense the first power output from the power supply device 180 and output a first power sensed value ESV. For example, the voltage sensor 123 may convert an analog first power sensed value into a digital first power sensed value ESV and output the converted first power sensed value.

[0089] Meanwhile, Figure 19 An example in which the voltage sensor 123 is included inside the timing controller 120 is shown. However, the voltage sensor 123 may be included inside the power supply device 180. In this case, the power supply device 180 may send the digital first power sensed value ESV through a communication interface connected to the timing controller 120.

[0090] The sensed voltage corrector 124 may prepare a corrected sensed voltage VSEN' by correcting the sensed voltage VSEN based on one of a predicted value such as a first power calculated value EPV and an actual measured value such as a first power sensed value ESV. The sensed voltage corrector 124 may include a selector SEL and a look-up table LUT. The selector SEL may select one of the first power sensed value ESV and the first power calculated value EPV output from the first power calculator 121, and send the selected value to the look-up table LUT. The look-up table LUT may include a data table (correction data values for each level of EVDD) that can prepare a corrected sensed voltage VSEN' by correcting the sensed voltage VSEN in response to a change in the level of the first power.

[0091] According to a modification of the third embodiment, the timing controller 120 may predict (detect) a change in the first power based on one of a predicted value and an actual measured value, correct the sensed voltage VSEN sent from the data driver 140 in response to the change in the first power, and prepare a corrected sensed voltage VSEN'. The modification of the third embodiment is similar to the third embodiment. However, since the corrected sensed voltage (sensed voltage value) VSEN' is prepared by detecting a change in the first power based on one of a predicted value and an actual measured value, it has the advantage of being able to adaptively respond to the driving characteristics or driving environment of the device.

[0092] Figure 20 is an exemplary diagram showing in more detail the main configurations included in the LED device according to the fourth embodiment, and Figure 21 is an exemplary diagram showing a modification of the fourth embodiment.

[0093] As Figure 20As shown, according to the fourth embodiment, the timing controller 120 may include a first power calculator 121, a first power controller 122, a sensed voltage corrector 124, a data compensator 126, a signal output circuit 129, etc. Hereinafter, the fourth embodiment will mainly describe the parts different from the third embodiment.

[0094] The sensed voltage corrector 124 may prepare a corrected sensed voltage VSEN' by correcting the sensed voltage VSEN based on the first power calculation value EPV. The sensed voltage corrector 124 may generate a sampling control signal SAMC for controlling the sampling time of a sampling circuit SAM included in the sensing circuit 145 based on the first power calculation value EPV in response to a change in the level of the first power.

[0095] According to the fourth embodiment, the timing controller 120 may obtain a sensed voltage (sensed voltage value) by changing a sampling point in response to a change in the level of the first power, and thus may improve the compensation accuracy and minimize the occurrence of sensing errors.

[0096] As Figure 21 As shown, according to a modification of the fourth embodiment, the timing controller 120 may include a first power calculator 121, a first power controller 122, a voltage sensor 123, a sensed voltage corrector 124, a data compensator 126, a signal output circuit 129, etc. Hereinafter, in the modification of the fourth embodiment, the description will focus on the parts different from the fourth embodiment.

[0097] The first power calculator 121 may calculate the level of the first power required to drive the display panel 150 based on the data signal DATA supplied from the outside, and prepare a first power calculation value EPV. The first power calculator 121 may prepare the first power calculation value EPV such that the level of the first power output from the power supply device 180 may increase or decrease according to the characteristics of the data signal DATA.

[0098] The voltage sensor 123 may sense the first power output from the power supply device 180 and output a first power sensed value ESV. For example, the voltage sensor 123 may convert an analog first power sensed value into a digital first power sensed value ESV and output the converted first power sensed value.

[0099] Meanwhile, Figure 21 An example is shown in which the voltage sensor 123 is included inside the timing controller 120. However, the voltage sensor 123 may be included inside the power supply device 180. In this case, the power supply device 180 may send the digital first power sensed value ESV through a communication interface connected to the timing controller 120.

[0100] The sensed voltage corrector 124 can prepare a corrected sensed voltage VSEN' by correcting the sensed voltage VSEN based on one of a predicted value such as a first power calculation value EPV and an actually measured value such as a first power sensed value ESV. The sensed voltage corrector 124 can include a selector SEL and a look-up table LUT. The selector SEL can select one of the first power sensed value ESV and the first power calculation value EPV output from the first power calculator 121, and send the selected value to the look-up table LUT. The look-up table LUT can include a data table that can prepare a corrected sensed voltage VSEN' by correcting the sensed voltage VSEN in response to a change in the level of the first power.

[0101] The sensed voltage corrector 124 can generate a sampling control signal SAMC for controlling the sampling time of a sampling circuit SAM included in the sensing circuit 145 based on one of the first power calculation value EPV and the first power sensed value EVS in response to a change in the level of the first power.

[0102] According to a modification of the fourth embodiment, the timing controller 120 can detect a change in the first power based on one of a predicted value and an actually measured value, and prepare a sampling control signal SAMC and a corrected sensed voltage VSEN' in response to the change in the first power. The modification of the fourth embodiment is similar to the fourth embodiment. However, since the sampling control signal SAMC and the corrected sensed voltage (sensed voltage value) VSEN' are prepared by detecting a change in the first power based on one of a predicted value and an actually measured value, there is an advantage in that it can adaptively respond to the driving characteristics or driving environment of the device.

[0103] Meanwhile, for ease of description, Figure 20 and Figure 21 the following is shown: the sampling control signal SAMC prepared from the sensed voltage corrector 124 is directly applied to the sampling circuit SAM included in the sensing circuit 145 of the data driver 140. However, the sampling control signal SAMC can be transmitted and received through a communication interface provided between the timing controller 120 and the data driver 140.

[0104] The present disclosure has the following effects: it can improve the compensation accuracy by changing the sampling point in response to the change in the level of the first power, and can increase the probability of obtaining a constant (uniform) sensed voltage even when the level of the first power changes. Additionally, the present disclosure has the following effects: it can improve the compensation accuracy even when the level of the first power changes, because the change in the level of the first power can be reflected in the sensed voltage. Furthermore, the present disclosure has the following effects: it can minimize the occurrence of sensing errors even when the level of the first power changes.

[0105] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a display panel including sub-pixels connected to power lines, data lines, and reference lines; a power supply device configured to supply power to the display panel through the power line; a data driver, the data driver comprising a driving circuit and a sensing circuit, the driving circuit being configured to supply a data voltage to the display panel through the data line, the sensing circuit being configured to sense the display panel through the reference line; as well as a timing controller configured to control the power supply device and the data driver, The sensing circuit has a variable sampling point for sensing the display panel in response to a change in the level of the power.

2. The display device according to claim 1, wherein: The sensing circuit advances a sampling time from a reference sampling time when the level of the power becomes higher than a reference level, and delays the sampling time from the reference sampling time when the level of the power becomes lower than the reference level.

3. The display device according to claim 1, wherein: The sensing circuit includes a sampling circuit configured to sense the reference line, and The sampling time corresponds to the on-time of the sampling circuit.

4. The display device according to claim 1, wherein: The timing controller is configured to: calculating a level of first power required to drive the display panel based on the data signal to prepare a first power calculation value, and A sampling control signal for changing a sampling time is generated based on the first power calculation value.

5. The display device according to claim 4, wherein: The timing controller generates a sampling control signal for changing the sampling time based on one of the first power calculation value and a first power sensing value prepared by sensing the first power output from the power supply device.

6. A display device, comprising: a display panel including sub-pixels connected to power lines, data lines, and reference lines; a power supply device configured to supply power to the display panel through the power line; a data driver including a driving circuit configured to supply a data voltage to the display panel through the data line and a sensing circuit configured to sense the display panel through the reference line to prepare a sensing voltage; as well as a timing controller configured to control the power supply device and the data driver, The timing controller prepares a corrected sensing voltage by reflecting a change in the level of the power in the sensing voltage transmitted from the sensing circuit, and compensates a data signal based on the corrected sensing voltage to generate a compensated data signal.

7. The display device according to claim 6, wherein: The timing controller is configured to: calculating a level of first power required to drive the display panel based on the data signal to prepare a first power calculation value; as well as A change in the level of the first power is predicted based on the first power calculation value, and the predicted change is reflected in the sensing voltage to prepare a corrected sensing voltage.

8. The display device according to claim 7, wherein: The timing controller predicts a change in the level of the first power based on one of the first power calculation value and a first power sensing value prepared by sensing the first power output from the power supply device, and reflects the predicted change in the sensing voltage to prepare a corrected sensing voltage.

9. The display device according to claim 8, wherein: The timing controller generates a sampling control signal that changes a sampling time for sensing the display panel based on one of the first power sensing value and the first power calculation value.

10. The display device according to claim 9, wherein: The sensing circuit includes a sampling circuit configured to sense the reference line to prepare the sensing voltage, and The sampling time corresponds to the on-time of the sampling circuit.

11. The display device according to claim 7, wherein: The timing controller includes a lookup table including a data table for preparing a corrected sensing voltage in response to a change in a level of the first power.

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