Gate driver and display device including the same

Abstract

The present specification discloses a gate driver and a display device including the same. The gate driver includes: first and second pull-up transistors; first and second pull-down transistors; a first output terminal configured to output a carry signal; an A-th transistor disposed between the first and second pull-up transistors and configured to electrically isolate the Q node in response to a control signal; a B-th transistor disposed between the A-th transistor and the second pull-up transistor, and configured to supply a low potential voltage to the second pull-up transistor in response to a control bar signal; and a C-th transistor connected to the second output terminal to supply a low potential voltage in response to the control bar signal. According to the present specification, a capacitance can be quickly charged and accurate sensing can be realized by reducing a capacitive load compared to the prior art when sensing for electrical characteristic compensation of a pixel circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0197819, filed on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a gate driver and a display device including the gate driver. Background Art

[0004] Electroluminescent display devices can be classified into inorganic light - emitting display devices and organic light - emitting display devices according to the material of the light - emitting layer. A display - matrix type organic light - emitting diode display device includes an organic light - emitting diode (hereinafter referred to as "OLED"), which emits light by itself and has the advantages of a fast response time, high luminous efficiency and brightness, and a wide viewing angle. Each of the OLED display devices includes an OLED formed in each pixel. Since the OLED display device has a fast response time, excellent luminous efficiency and brightness, and a wide viewing angle, and can express black grayscale with perfect black, the OLED display device has excellent contrast and color gamut.

[0005] The driving elements should have uniform electrical characteristics in all pixels. However, due to process variations and differences in device characteristics, there may be differences in electrical characteristics between pixels, and the differences in electrical characteristics between driving elements may increase as the driving time of the display device elapses. The differences in the electrical characteristics of pixels may lead to deterioration of image quality and shortening of lifespan. To reduce the deterioration of pixels and extend the lifespan of pixels, the change in characteristics can be compensated by sensing the electrical characteristics of pixels. When there are many pixels electrically connected to the sensing path when sensing the electrical characteristics of pixels, the sensing time may increase and the sensing result may be inaccurate due to the resistance and capacitive load (RC) connected to the sensing path. Summary of the Invention

[0006] This specification aims to fulfill the needs described above and / or solve the problems of the related art.

[0007] The object of this specification is not limited to the object described above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] The gate driver according to this specification may include a plurality of signal transmission units, which are cascaded with each other and are configured to receive a clock signal and sequentially output gate signals.

[0009] At least one of the plurality of signal transmission units includes: a first pull-up transistor that is turned on based on the potential of the Q node; a second pull-up transistor that is turned on based on the potential of the Q node; a first pull-down transistor that is turned on based on the potential of the Qb node; a second pull-down transistor that is turned on based on the potential of the Qb node; and an A transistor that is disposed between the first pull-up transistor and the second pull-up transistor and is configured to electrically isolate the Q node in response to a control signal.

[0010] The gate driver according to the present specification includes an nth signal transmission unit and an (n + 1)th signal transmission unit, the nth signal transmission unit and the (n + 1)th signal transmission unit are cascade-connected to each other and are configured to receive a clock signal and sequentially output gate signals (n is a positive integer greater than or equal to 1), wherein each of the nth signal transmission unit and the (n + 1)th signal transmission unit may include: a first pull-up transistor that is turned on based on the potential of the Q node; a second pull-up transistor that is turned on based on the potential of the Q node; a first pull-down transistor that is turned on based on the potential of the Qb node; a second pull-down transistor that is turned on based on the potential of the Qb node; a first output terminal that is configured to output a carry signal according to the operation of the first pull-up transistor and the operation of the first pull-down transistor; a second output terminal that is configured to output a gate signal according to the operation of the second pull-up transistor and the operation of the second pull-down transistor; an A transistor that is disposed between the first pull-up transistor and the second pull-up transistor and is configured to electrically isolate the Q node in response to a control signal; a Bth transistor that is disposed between the Ath transistor and the second pull-up transistor and is configured to supply a second low potential voltage to the second pull-up transistor in response to a control bar signal; and a Cth transistor that is connected to the second output terminal to supply a first low potential voltage in response to the control bar signal.

[0011] The display device according to the present specification may include: a gate driver including an nth signal transmission unit and an (n + 1)th signal transmission unit (n is a positive integer greater than or equal to 1) connected in cascade with each other; an nth pixel row group including an nth odd pixel row receiving an nth gate signal output from the nth signal transmission unit and an nth even pixel row receiving the nth gate signal output from the nth signal transmission unit; and an (n + 1)th pixel row group including an (n + 1)th odd pixel row receiving an (n + 1)th gate signal output from the (n + 1)th signal transmission unit and an (n + 1)th even pixel row receiving the (n + 1)th gate signal output from the (n + 1)th signal transmission unit, and for a sensing time for external compensation, when the nth gate signal is a gate-on voltage, the (n + 1)th gate signal is a gate-off voltage, and when the (n + 1)th gate signal is a gate-on voltage, the nth gate signal is a gate-off voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a block diagram showing a display device according to an embodiment of the present specification.

[0013] Figure 1B is a block diagram showing a display device according to another embodiment of the present specification.

[0014] Figure 2 is showing Figure 1A a cross-sectional view of a cross-sectional structure of the display panel shown.

[0015] Figure 3 is a view showing the time when the display device enters a sensing mode in a driving sequence of the display device.

[0016] Figure 4 is a circuit diagram schematically showing a pixel circuit and a sensing circuit according to the present specification.

[0017] Figure 5 is schematically showing the application to Figure 4 a waveform diagram of signals applied to the pixel circuit shown.

[0018] Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present specification.

[0019] Figure 7 is a waveform diagram showing a method of driving a pixel circuit according to an embodiment of the present specification.

[0020] Figures 8A to 8D is showing in relation to Figure 7The circuit diagram of the operation state of the pixel circuit corresponding to each operation.

[0021] Figure 9 It is a waveform diagram showing a method of driving a pixel circuit according to another embodiment of the present specification.

[0022] Figure 10 It is shown in the second initialization operation Figure 6 The circuit diagram of the current flowing in the pixel circuit shown.

[0023] Figure 11A It is a view showing an embodiment in which the output signals of the pixel and the gate driver are shared in the present specification.

[0024] Figure 11B It is a view showing another embodiment in which the output signals of the pixel and the gate driver are shared in the present specification.

[0025] Figure 12 It is a view schematically showing the shift register of the gate driver.

[0026] Figure 13 It is a circuit diagram showing a pixel circuit according to an embodiment of the present specification.

[0027] Figure 14 It is shown during the sensing time for external compensation of the display device and input to Figure 13 The waveform diagram of the voltage level of the signal of the shown switching element.

[0028] Figure 15 It is a circuit diagram showing the operation state of the pixel circuit during the sensing time for external compensation of the display device.

[0029] Figure 16 It is a view schematically showing the shift register of the gate driver according to an embodiment of the present specification.

[0030] Figure 17 It is a circuit diagram specifically showing the signal transmission unit included in the gate driver according to an embodiment of the present specification.

[0031] Figure 18 It is a waveform diagram showing the input / output waveform during the display time in the gate driver according to an embodiment of the present specification.

[0032] Figure 19 It is shown in connection with Figure 18 The view of the operation state of the signal transmission unit corresponding to the DA section to the DC section.

[0033] Figures 20A to 20F It is shown in connection withFigure 18 The circuit diagram of the operating state of the signal transmission unit corresponding to the DA section to the DC section.

[0034] Figure 21 It is a waveform diagram showing the input / output waveforms during the sensing time for external compensation in a gate driver according to an embodiment of the present specification.

[0035] Figure 22 It shows Figure 21 The view of the operating state of the signal transmission unit corresponding to the SA section to the SC section.

[0036] Figures 23A to 23F It shows Figure 21 The circuit diagram of the operating state of the signal transmission unit corresponding to the SA section to the SC section.

[0037] Figure 24 It is a waveform diagram showing the voltage level of the signal input to the Figure 13 switching element shown during the sensing time for external compensation of a display device according to an embodiment of the present specification.

[0038] Figure 25 It is a circuit diagram showing the operating state of the pixel circuit during the sensing time for external compensation of a display device according to an embodiment of the present specification. Detailed Embodiments

[0039] Referring to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present specification and the methods for achieving these advantages and features will become clear. The present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. These embodiments are provided only to make the disclosure of the present disclosure complete and fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the appended claims.

[0040] When describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

[0041] When using the terms "comprising", "including", "having", and "consisting of" described in this specification, unless "only" is used, other parts can be added. When a component is expressed in the singular, it can be interpreted as multiple components unless otherwise specifically stated.

[0042] When describing the positional relationship and interconnection relationship between two components, such as "above", "over", "below", "adjacent", "connected or coupled", "crossed or intersected", etc., unless the terms "immediately" or "directly" are described, one or more other components may be disposed between the components.

[0043] When using terms such as "after", "subsequently", "then", "before", etc. to describe the time relationship, unless the terms "immediately" or "directly" are used, non - consecutive cases may be included.

[0044] Although terms such as "first", "second", etc. may be used to distinguish components, the function or structure of the components is not limited by the ordinal number or component name added in front of the component.

[0045] The following embodiments may be partially or wholly coupled or combined, and various technical interconnections and drivings are possible. The embodiments may be implemented independently of each other and also implemented together in an associated relationship.

[0046] In addition, unless explicitly and specifically defined and described, the terms (including technical terms and scientific terms) used in the embodiments of this specification may be interpreted as the meanings that may be generally understood by those skilled in the art to which this specification pertains, and the meanings of commonly used terms, such as the terms defined in a dictionary, may be interpreted in consideration of the context of the related technology.

[0047] In the display device according to this specification, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be oxide thin - film transistors (TFTs) containing an oxide semiconductor or LTPS TFTs containing low - temperature polycrystalline silicon (LTPS).

[0048] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. Carriers start to flow from the source in the transistor. The drain is an electrode through which carriers move from the transistor to the outside. In the transistor, carriers flow from the source to the drain.

[0049] In the case of an n - channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, so that electrons can flow from the source to the drain. In an n - channel transistor, the current flows from the drain to the source. In the case of a p - channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may change depending on the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as "the first electrode and the second electrode".

[0050] The gate signal can swing between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage (VGH), and the gate-off voltage can be a gate low voltage (VGL). In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage (VGL), and the gate-off voltage can be a gate high voltage (VGH).

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0052] Figure 1A is a block diagram showing a display device according to an embodiment of the present specification. Figure 1B is a block diagram showing a display device according to another embodiment of the present specification. Figure 2 is showing Figure 1A a cross-sectional view of the cross-sectional structure of the shown display panel.

[0053] Referring to Figure 1A , Figure 1B and Figure 2 , the display device may include: a display panel 100; a display panel driving unit for writing pixel data on the pixels of the display panel 100; and a power supply unit 140 for generating power required to drive the pixels and the display panel driving circuit.

[0054] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 may include a pixel array for displaying an input image on the screen. The pixel array may include a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels. The power lines may supply a constant voltage required to drive the pixels 101 to the pixels 101. For example, the display panel 100 may include a VDD line to which a pixel driving voltage ELVDD is applied and a VSS line to which a low-potential power voltage ELVSS is applied. In addition, the power lines may further include a REF line to which a reference voltage Vref is applied and an INIT line to which an initialization voltage Vinit is applied.

[0055] As Figure 2 shown, the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and a packaging layer 16 stacked on a substrate 10.

[0056] The circuit layer 12 may include a TFT array, a gate driver 120, etc. The TFT array includes pixel circuits connected to lines such as data lines, gate lines, and power lines. The circuit elements and lines of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers interposed with insulating layers therebetween, and a display layer including a semiconductor material. All transistors formed on the circuit layer 12 may be implemented as n-channel oxide TFTs.

[0057] The light-emitting element layer 14 may include light-emitting elements EL driven by the pixel circuits. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer including an organic film and a protective film.

[0058] The encapsulation layer 16 may cover the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may have a multi-insulating film structure formed by alternately stacking an organic film and an inorganic film. The inorganic film may block the penetration of moisture or oxygen. The organic film may flatten the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen may be longer than that of a single layer, thereby effectively blocking the influence of the penetration of moisture and oxygen on the light-emitting element layer 14.

[0059] A touch sensor layer (omitted in the drawing) may be formed on the encapsulation layer 16, and a polarizer or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a change in capacitance before and after the touch input. The touch sensor layer may include a metal wire pattern and an insulating film that generate the capacitance of the touch sensor. The insulating film may insulate the intersections of the metal wire pattern and flatten the surface of the touch sensor layer. The polarizer may increase visibility and contrast by converting the polarization of external light reflected by the metals of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer or a circular polarizer joined with a linear polarizer and a phase retardation film. A cover glass may be joined to the polarizer. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may further include a black matrix pattern. The color filter layer may absorb light of a part of wavelengths reflected from the circuit layer and the touch sensor layer to be used as a polarizer and improve the color purity of the image displayed in the pixel array.

[0060] The pixel array may include a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln may include a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels provided in one pixel row may share the gate line 103. The sub-pixels arranged in the column direction Y in the data line direction may share the same data line 102. One horizontal period (1H) is the time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln. The pixel rows L1 to Ln may be classified into odd pixel rows PXLO and even pixel rows PXLE.

[0061] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on the screen and real objects in the background are visible. The display panel 100 may be manufactured as a flexible display panel.

[0062] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color display. Each of the pixels may further include a white sub-pixel. Each sub-pixel may include a pixel circuit. Hereinafter, "pixel" may be interpreted to have the same meaning as "sub-pixel". Each pixel circuit may be connected to a data line, a gate line, and a power line.

[0063] The pixels may be set as true color pixels and pentile pixels. The pentile pixels may achieve a higher resolution than the true color pixels by driving two sub-pixels of different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for the insufficient color representation in each pixel with the color of the light emitted from adjacent pixels.

[0064] The power supply unit 140 can generate the DC voltage (or constant voltage) required to drive the pixel array of the display panel 100 and the display panel driving unit using a DC-DC converter. The DC-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit 140 can generate a DC voltage (or constant voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH / VEH, a gate-off voltage VGL / VEL, a pixel driving voltage ELVDD, a low-potential power voltage ELVSS, an initialization voltage Vinit, and a reference voltage Vref, by adjusting the level of the DC input voltage applied from a host system (not shown). The gamma reference voltage VGMA can be supplied to the data driver 110. The gate-on voltage VGH / VEH and the gate-off voltage VGL / VEL can be applied to the gate driver 120. Constant voltages such as the pixel driving voltage ELVDD, the low-potential power voltage ELVSS, the initialization voltage Vinit, and the reference voltage Vref can be supplied to the pixel 101 through power lines commonly connected to the pixel 101. The constant voltages applied to the pixel circuit can have different voltage levels.

[0065] The display panel driving unit can write the pixel data of the input image on the pixels of the display panel 100 under the control of the timing controller 130.

[0066] The display panel driving unit can include a data driver 110 and a gate driver 120.

[0067] The display panel driving unit can also include a touch sensor driver for driving the touch sensor. The touch sensor driver is omitted from Figure 1A and Figure 1B The data driver 110 and the touch sensor driver can be integrated into one driving IC. In a mobile device or a wearable device, the timing controller 130, the power supply unit 140, the data driver 110, etc. can be integrated into one driving IC.

[0068] The data driver 110 can receive the pixel data of the input image received as a digital signal from the timing controller 130 and output a data voltage. The data driver 110 can convert the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC) during each frame period and output a data voltage Vdata. The gamma reference voltage VGMA can be divided into gamma-compensated voltages for each gray level through a voltage-dividing circuit. The gamma-compensated voltages for each gray level can be provided to the DAC of the data driver 110. The data voltage Vdata can be output from each of the channels of the data driver 110 through an output buffer.

[0069] The gate driver 120 may be implemented as an in-panel gate (GIP) circuit formed together with the TFT array and lines of the pixel array on a circuit layer 12 provided on the display panel 100. The gate driver 120 may be disposed on the border area BZ which is a non-display area of the display panel 100, or at least some of the gate driver 120 may be disposed by being distributed in the pixel array for displaying an input image. The gate driver 120 may sequentially output gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply gate signals to the gate lines 103 by shifting the gate signals using a shift register. The gate signals may include various gate pulses, such as scan pulses and emission control pulses (hereinafter referred to as "EM pulses").

[0070] The gate driver 120 may be disposed on either the left non-display area BZ or the right non-display area BZ outside the display area on the display panel 100, and supply gate signals to the gate lines 103 by a single-feed method. In the single-feed method, the gate signals may be applied at one end of the gate lines 103.

[0071] Referring to Figure 1B , the gate driver 120 may be disposed in the left non-display area BZ and the right non-display area BZ of the display panel 100, and apply gate signals to the gate lines 103 by a dual-feed method. In the dual-feed method, the gate signals may be applied at both ends of the gate lines 103 simultaneously.

[0072] The timing controller 130 may receive digital video data DATA of an input image and timing signals synchronized with the digital video data from a host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. Since the vertical period and the horizontal period may be known in a method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE may have a period of 1 horizontal period (1H).

[0073] The host system may be any one of a television system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale an image signal from a video source according to the resolution of the display panel 100, and transmit the scaled image signal together with the timing signals to the timing controller 130.

[0074] The timing controller 130 can control the operation timing of the display panel driving unit at a frame frequency of input frame frequency × i Hz by multiplying the input frame frequency by i (i is a natural number) in the normal driving mode. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) type and 50 Hz in the Phase Alternating Line (PAL) type.

[0075] The timing controller 130 can provide a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system. The timing controller 130 can synchronize the data driver 110, the touch sensor driver, and the gate driver 120 by controlling the operation timing of the display panel driving unit.

[0076] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 through a level shifter. The level shifter can receive the gate timing control signal, generate a start pulse and a shift clock that swing between a gate high voltage and a gate low voltage, and provide the start pulse and the shift clock to the shift register of the gate driver 120.

[0077] The display mode (or display time) for writing pixel data of the input image to the pixels can be classified into a normal driving mode and a low-speed driving mode. In the low-speed driving mode, the power consumption of the display panel 100 and the display panel driving circuit can be reduced, and thus the display device can be driven with low power. The low-speed driving mode can be set to analyze the input image to reduce the power consumption of the display device when the input image does not change for a preset number of frames. When a still image is input for a predetermined time or longer, the low-speed driving mode can reduce the power consumption of the display panel driving circuit and the display panel 100 by reducing the frame frequency (i.e., the refresh rate) at which pixel data is written to the pixels. The low-speed driving mode is not limited to when a still image is input. For example, when the display device is operating in the standby mode, or when no user command or input image is input to the display panel driving circuit for a predetermined time or longer, the display panel driving circuit can operate in the low-speed driving mode.

[0078] Compared with the normal driving mode, the timing controller 130 can reduce the refresh frame frequency at which pixel data is written to the pixels in the low-speed driving mode. For example, in the normal driving mode, the refresh frame frequency at which pixel data is written to the pixels can be a frequency of 60 Hz or higher, such as any one of 60 Hz, 120 Hz, 144 Hz, and 240 Hz, and the refresh frame frequency in the low-speed driving mode can be lower than the refresh frame frequency in the normal driving mode. The timing controller 130 can reduce the driving frequencies of the display panel driving circuit and the pixels by setting a plurality of holding frames after the refresh frame to reduce the refresh rate of the pixels in the low-speed driving mode. In the refresh frame, the pixel data of the input image can be written to the pixels. In the holding frame, the sub-pixels can hold the data voltage stored in the capacitor since the previous refresh frame.

[0079] The display panel driving circuit can scan the pixels in the display mode under the control of the timing controller 130 and write the pixel data of the input image to the pixels 101. In the display mode, the input image can be displayed on the display area AA. The sensing circuit can sense the threshold voltage of the driving element DT from all the sub-pixels by sequentially sensing the sub-pixels of the display area AA row by row in the sensing mode.

[0080] Figure 3 is a view showing the time when the display device enters the sensing mode in the driving sequence of the display device.

[0081] Referring to Figure 3 , the display device can enter the sensing mode in at least one of the power-on sequence in which power starts to be applied to the display device, the vertical blanking time VB during the display time, and the power-off sequence in which the disconnect switch of the display device is turned on. The vertical blanking time VB is the blanking time other than the activation time AT, during which the pixel data of the input image is written to the pixels within one frame period. During the vertical blanking time VB, the pixel data may not be input to the data driver, and the pixel data may not be written to the sub-pixels. During the activation time AT, the pixel data DATA can be input to the data driver, and the data voltage output from the data driver can be charged to the sub-pixels so that the pixel data can be written to the sub-pixels.

[0082] In the power-off sequence, the sensing circuit can be further driven for a predetermined time after the power-off switch is turned on to sense the threshold voltage of the driving element in each sub-pixel. Then, when the power is cut off, the sensing circuit can stop operating. During the sensing time, the sensing data output from the sensing channel of the data driver can be transmitted to the timing controller.

[0083] Figure 4is a circuit diagram schematically showing a pixel circuit and a sensing circuit according to the present specification. Figure 5 is a waveform diagram schematically showing signals applied to Figure 4 the pixel circuit shown. The pixel circuit according to the present specification is not limited to Figure 4 .

[0084] Referring to Figure 4 and Figure 5 , the pixel circuit may include a light-emitting element EL, a driving element DT, a capacitor Cst, a first switching element MA, a second switching element MB, etc. The sensing circuit may include an analog-to-digital converter ADC and an external compensation circuit unit YB including a third switching element MC and a fourth switching element MD. The driving element DT and the switching elements MA to MD may be implemented as n-channel transistors, but are not limited thereto. The switching elements MC and MD of the sensing circuit and the ADC may be provided in a sensing channel of the data driver.

[0085] The pixel circuit may be connected to a constant voltage node. For example, a first constant voltage node PLA to which a pixel driving voltage EVDD is applied, a second constant voltage node PLB to which a low-potential power voltage EVSS is applied, a third constant voltage node PLC to which a reference voltage Vref’ is applied, etc. The constant voltage nodes PLA, PLB, and PLC may be commonly connected to a power line for pixels. The pixel driving voltage EVDD may be set to a voltage at which the driving element DT operates in a saturation region. The pixel driving voltage EVDD may be higher than the maximum voltage of the data voltage Vdata (or white grayscale voltage). The low-potential power voltage EVSS and the reference voltage Vref may be lower than the pixel driving voltage EVDD and lower than the minimum voltage of the data voltage Vdata (or black grayscale voltage).

[0086] The pixel circuit may be connected to a data line DL to which a data voltage Vdata is applied, a first gate line GLA to which a first gate signal SCAN is applied, a second gate line GLB to which a second gate signal SENSE is applied, and a sensing line SL.

[0087] During a sensing time SET, the data driver may output a pulse whose voltage gradually increases under the control of the timing controller. The timing controller may transmit a pulse whose data value increases independently of the pixel data of the input image to the data driver during the sensing time SET. The data driver may convert the data received from the timing controller into a data voltage Vdata through a digital-to-analog converter (DAC) of the data channel.

[0088] During the sensing time SET, a pulse of the data voltage Vdata can be applied to the first node DTG while the first switching element MA and the second switching element MB are turned on. In this case, the gate-source voltage (Vgs) of the driving element DT is the difference between the gate voltage of the data voltage Vdata applied to the first node DTG and the voltage at the second node DTS, i.e., the sensing voltage Vsen. When the pulse voltage of the data voltage Vdata is applied to the first node DTG to turn on the driving element DT, the threshold voltage (Vth) of the driving element DT can be sensed as the sensing voltage Vsen that increases rapidly.

[0089] During the display time DRT, the data channel of the data driver can convert the pixel data of the input image received from the timing controller into the data voltage Vdata and output the data voltage Vdata.

[0090] The gate driver can control the first switching element MA and the second switching element MB within the sensing time SET by outputting a first gate signal SCAN and a second gate signal SENSE under the control of the timing controller. The control circuit in the timing controller or the data driver can control the switching elements MC and MD of the sensing circuit by generating a C gate signal SPRE and a D gate signal SAM for controlling the third switching element MC and the fourth switching element MD. The C gate signal SPRE and the D gate signal SAM can include pulses that swing between a high voltage H and a low voltage L of the digital signal voltage level.

[0091] The first gate signal SCAN can include a pulse that remains at the gate high voltage VGH for a preset time (e.g., 20 horizontal periods of the sensing time SET). The first switching element MA can be turned on in response to the gate high voltage VGH of the first gate signal SCAN and turned off when the voltage of the first gate signal SCAN is the gate low voltage VGL.

[0092] The second gate signal SENSE can include a pulse of the gate high voltage VGH generated within the sensing time SET. The second switching element MB can be turned on in response to the gate high voltage VGH of the second gate signal SENSE. After the first switching element MA is turned on, when the voltage of the second gate signal SENSE is the gate low voltage VGL, the second switching element MB can be turned on and off. For the sensing time SET, after the voltage of the first gate signal SCAN is changed to the gate high voltage VGH, the voltage of the second gate signal SENSE can increase to the gate high voltage VGH. For the sensing time SET, the voltage of the second gate signal SENSE can be decreased to the gate low voltage VGL, and then the voltage of the first gate signal SCAN can be decreased to the gate low voltage VGL.

[0093] The C gate signal SPRE may include a pulse of a high voltage H generated within a sensing time SET. The C switching element MC may be turned on in response to the high voltage H of the C gate signal SPRE and turned off when the voltage of the C gate signal SPRE is a low voltage L. The C switching element MC may be turned on earlier than the B switching element MB. The voltage of the C gate signal SPRE may increase to the high voltage H when the voltage of the A gate signal SCAN changes to the gate high voltage VGH and may decrease to the low voltage L when the voltage of the B gate signal SENSE changes to the gate high voltage VGH.

[0094] The D gate signal SAM may include a pulse of a high voltage H generated within a sensing time SET. The D switching element MD may be turned on in response to the high voltage H of the D gate signal SAM and turned off when the voltage of the D gate signal SAM is a low voltage L. Whenever a pulse of the data voltage Vdata is applied to the A node DTG to transfer the sensing voltage Vsen on the sensing line SL to the ADC, the D gate signal SAM may be the high voltage H. When the voltages of the first gate signal SCAN and the second gate signal SENSE are held at the gate high voltage VGH, that is, when the A switching element MA and the B switching element MB are held in the on state, pulses of the D gate signal SAM may be repeatedly generated. The pulses of the D gate signal SAM and the pulses of the data voltage Vdata may be alternating. Thus, the D switching element MD may be turned on whenever a pulse of the data voltage Vdata is applied to the A node DTG of the pixel circuit.

[0095] For the sensing time SET, the data voltage Vdata applied to the data line DL may include a plurality of pulses with a gradually increasing voltage. The pulse period T of the data voltage Vdata may be 2 horizontal periods, but is not limited thereto. In one embodiment, the threshold voltage (Vth) of the driving element DT may be sensed when the voltage level of the data voltage Vdata changes. Thus, compared with a sensing method using a conventional source follower circuit, the sensing time SET may be significantly reduced. In addition, even when the driving speed increases, the power consumption of the display device may be reduced, the resolution of the display device may be increased, and high-speed sensing may be achieved.

[0096] The driving element DT can drive the light-emitting element EL by supplying current to the light-emitting element EL according to the gate-source voltage (Vgs). The voltage difference between the A node DTG and the B node DTS can be the gate-source voltage (Vgs) of the driving element DT. The driving element DT can include a first electrode connected to the A constant voltage node PLA to which the pixel driving voltage EVDD is applied, a gate electrode connected to the A node DTG, and a second electrode connected to the B node DTS. The capacitor Cst can be connected between the A node DTG and the B node DTS.

[0097] The light-emitting element EL can be implemented as an OLED. The light-emitting element EL can include an anode, a cathode, and an organic compound layer formed between the electrodes. The anode of the light-emitting element EL can be connected to the B node DTS, and the cathode can be connected to the B constant voltage node PLB to which the low-potential power voltage EVSS is applied. The organic compound layer can include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode and cathode of the light-emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to generate excitons. At this time, visible light can be emitted from the light-emitting layer (EML). The light-emitting element EL can be implemented in a series structure in which a plurality of light-emitting layers are stacked. The light-emitting element EL having a series structure can increase the brightness and lifespan of the pixel.

[0098] The A switching element MA can be connected between the data line DL and the A node DTG, and is turned on in response to the gate high voltage VGH of the A gate signal SCAN. When the A switching element MA is turned on, the data voltage Vdata can be applied to the A node DTG. The A switching element MA can include a first electrode connected to the data line DL, a gate electrode connected to the A gate line GLA to which the A gate signal SCAN is applied, and a second electrode connected to the A node DTG.

[0099] The B switching element MB can be connected between the B node DTS and the sensing line SL, and is turned on in response to the gate high voltage VGH of the B gate signal SENSE. When the B switching element MB is turned on, the B node DTS can be electrically connected to the sensing line SL. The B switching element MB can include a first electrode connected to the B node DTS, a gate electrode connected to the B gate line GLB to which the B gate signal SENSE is applied, and a second electrode connected to the sensing line SL.

[0100] The capacitor CS that stores the sensed voltage Vsen can be connected to the sense line SL. The capacitor CS can be a parasitic capacitance connected to the sense line SL.

[0101] The C-th switching element MC can be connected between the sense line SL and the C-th constant voltage node PLC to which a reference voltage Vref is applied, and is turned on in response to a high voltage H of the C-th gate signal SPRE. When the C-th switching element MC is turned on, the reference voltage Vref can be applied to the sense line SL, so that the sense line SL can be initialized to the reference voltage Vref. The C-th switching element MC can include a first electrode connected to the sense line SL, a gate electrode to which the C-th gate signal SPRE is applied, and a second electrode connected to the C-th constant voltage node PLC.

[0102] The D-th switching element MD can be connected between the sense line SL and the ADC, and is turned on in response to a high voltage H of the D-th gate signal SAM. When the D-th switching device MD is turned on, the voltage Vsen sensed at the B-th node DTS of the pixel circuit can be input to the ADC through the sense line SL and the D-th switching element MD.

[0103] When the A-th switching element MA and the B-th switching element MB are kept on, the pulse of the third gate signal SAM can be a high voltage H. Since the D-th switching element MD is turned on at each pulse of the third gate signal SAM, the sensed voltage Vsen that changes according to the pulse voltage of the data voltage Vdata can be input to the ADC at each pulse of the third gate signal SAM.

[0104] The ADC can convert the sensed voltage Vsen into digital data and output the sensed data Dsen. The D-th switching element MD can include a first electrode connected to the sense line SL, a gate electrode to which the D-th gate signal SAM is applied, and a second electrode connected to the input terminal of the ADC. Meanwhile, a sample-and-hold circuit, an amplifier, an integrator, etc. can be added between the D-th switching element MD and the ADC.

[0105] For the sensing time SET, when the gate-source voltage (Vgs) of the driving element DT becomes greater than the threshold voltage of the driving element DT due to the voltage of the data voltage Vdata applied to the A-th node DTG gradually increasing by a plurality of pulses, the driving element DT can be turned on to rapidly increase the drain-source current of the driving element DT. When the driving element DT is turned on, the voltage at the B-th node DTS rapidly increases, and thus the sensed voltage Vsen input to the ADC can also rapidly increase.

[0106] The timing controller can determine that the sensed voltage Vsen indicated by the sensed data Dsen received from the ADC is the threshold voltage (Vth) of the driving element DT when the value of the sensed data Dsen is greater than the preset threshold THR by comparing the sensed data Dsen received from the sensing channel of the data driver with the preset threshold THR, and derive a compensation value for compensating the offset of the threshold voltage of the driving element DT. The threshold voltage (Vth) corresponding to the sensed voltage Vsen and the compensation value for compensating the offset of the threshold voltage (Vth) can be pre-stored in a look-up table memory accessed by the timing controller. The threshold voltage data stored in the look-up table memory can be stored for each sub-pixel. When the sensed data Dsen is input, the look-up table memory can output the compensation value of the threshold voltage (Vth) stored at the address indicated by the sensed data Dsen. The timing controller can update the threshold voltage data stored in the look-up table memory with the sensed data Dsen received from the ADC.

[0107] The timing controller can modulate the pixel data DATA by adding or multiplying the compensation value derived from the sensed data Dsen to or with the pixel data DATA of the input image. The modulated pixel data DATA can have a gray value modulated by the offset of the threshold voltage of the driving element DT. The pixel data DATA' modulated by the timing controller can be transmitted to the data driver within the display time DRT and written on the sub-pixel. The data driver can convert the pixel data DATA' received from the timing controller during the display time DRT into a data voltage Vdata and output the data voltage Vdata.

[0108] Figure 6 is a circuit diagram showing a pixel circuit according to an embodiment of the present specification. Figure 7 is a waveform diagram showing a method of driving a pixel circuit according to an embodiment of the present specification.

[0109] Referring to Figure 6 and Figure 7 , the pixel circuit can include a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements M1 to M5, a first capacitor C1, and a second capacitor C2. The following description will assume that the driving element DT and the switching elements M1 to M5 in the pixel circuit are implemented as n-channel oxide TFTs, but the present specification is not limited thereto.

[0110] The gate signal may include a first scan pulse SC1 (or a first gate pulse), a second scan pulse SC2 (or a second gate pulse), a third scan pulse SC3 (or a third gate pulse), a first EM pulse EM1 (or a fourth gate pulse), and a second EM pulse EM2 (or a fifth gate pulse). To drive the pixel circuit shown, the gate driver may include a first shift register for sequentially outputting the first scan pulse SC1, a second shift register for sequentially outputting the second scan pulse SC2, a third shift register for sequentially outputting the third scan pulse SC3, a fourth shift register for sequentially outputting the first EM pulse EM1, and a fifth shift register for sequentially outputting the second EM pulse EM2.

[0111] Constant voltages such as a pixel driving voltage ELVDD, a low-potential power voltage ELVSS, a reference voltage Vref, and an initialization voltage Vini may be applied to the pixel circuit. The pixel driving voltage ELVDD may be higher than the low-potential power voltage ELVSS. The gate-on voltage VGH / VEH may be set to be higher than the pixel driving voltage ELVDD. The gate-off voltage VGL / VEL may be set to be lower than the low-potential power voltage ELVSS. The initialization voltage Vini may be set to a low-potential voltage higher than the low-potential voltage ELVSS. The reference voltage Vref may be set to a voltage at which the driving element DT can be turned on. The reference voltage Vef may be set to a voltage within the voltage range of the data voltage Vdata output from the data driver 110. The maximum voltage of the data voltage Vdata may be lower than the pixel driving voltage ELVDD, and the minimum voltage of the data voltage Vdata may be higher than the low-potential power voltage ELVSS.

[0112] In the sampling stage SMPL, in order to sample the threshold voltage (Vth) of the driving element DT, the reference voltage Vref is preferably set to a voltage higher than the initialization voltage Vini. The voltage difference between the reference voltage Vref and the initialization voltage Vini may be set to a voltage higher than the threshold voltage (Vth) of the driving element DT. The initialization voltage Vini should be set to a voltage lower than the threshold voltage of the light-emitting element EL to achieve the lowest brightness of the pixel, i.e., the brightness of the black gradation.

[0113] As Figure 7 shown, the display time of the pixel circuit may include an initialization stage INIT, a sampling stage SMPL set after the initialization stage INIT, an addressing stage WR set after the sampling stage SMPL, and an emission stage EMIS set after the addressing stage WR.

[0114] In the addressing stage WR, the first scan pulse SC1 may be a gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data. In the initialization stage INIT, the sampling stage SMPL, and the emission stage EMIS, the first scan pulse SC1 may be a gate-off voltage VGL.

[0115] In the initialization stage INIT and the sampling stage SMPL, the second scan pulse SC2 may be a gate-on voltage VGH. In the addressing stage WR and the emission stage EMIS, the second scan pulse SC2 may be a gate-off voltage VGL.

[0116] In the initialization stage INIT, the third scan pulse SC3 may be a gate-on voltage VGH. In the sampling stage SMPL, the addressing stage WR, and the emission stage EMIS, the third scan pulse SC3 may be a gate-off voltage VGL.

[0117] In the initialization stage INIT and the addressing stage WR, the first EM pulse EM1 may be a gate-off voltage VEL. In the sampling stage SMPL and the emission stage EMIS, the first EM pulse EM1 may be a gate-on voltage VEH.

[0118] In the initialization stage INIT and the emission stage EMIS, the second scan pulse EM2 may be a gate-on voltage VEH. In the sampling stage SMPL and the addressing stage WR, the second EM pulse EM2 may be a gate-off voltage VEL.

[0119] Each of the switching elements M1 to M5 may be turned on when a gate-on voltage VGH / VEH is applied to the gate electrode and turned off when a gate-off voltage VGL and VEL are applied to the gate electrode. The driving element DT may be turned on when the gate-source voltage (Vgs) is higher than the threshold voltage (Vth) to generate a current according to the gate-source voltage (Vgs) and may drive the light-emitting element EL.

[0120] The light-emitting element EL may be implemented as an OLED. The OLED may include an organic compound layer formed between the anode and the cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. The anode of the light-emitting element EL may be connected to the fourth node n4, and its cathode may be connected to the VSS node to which a low-potential driving voltage ELVSS is applied. The VSS node may be connected to the VSS line. The light-emitting element EL may include a third capacitor C3 formed between the anode and the cathode.

[0121] When a voltage is applied to the anode and cathode of the light-emitting element EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) can move to the light-emitting layer EML to generate excitons. At this time, visible light can be emitted from the light-emitting layer (EML).

[0122] The driving element DT may include a gate electrode connected to the first node DTG, a first electrode connected to the second node DTS, and a second electrode connected to the third node DTD. The voltages applied to each electrode of the driving element DT may be substantially the same as the voltages at the first to third nodes DTG, DTS, and DTD.

[0123] The first capacitor C1 may be connected between the first node DTG and the second node DTS. The first capacitor C1 may store the gate-source voltage (Vgs) of the driving element DT. The second capacitor C2 may be connected between the second node DTS and the Vx node. A constant voltage, for example, any one of a pixel driving voltage ELVDD, a low-potential power voltage ELVSS, a reference voltage Vref, and an initialization voltage Vini, may be applied to the Vx node. The Vx node may be connected to a relatively stable constant voltage, such as the VDD line to which the pixel driving voltage ELVDD is applied.

[0124] The first capacitor C1 and the second capacitor C2 may determine the transfer rate of the data voltage Vdata at the gate-source voltage (Vgs) of the driving element DT according to their capacitance ratio. The capacitances of the first capacitor C1 and the second capacitor C2 may be appropriately selected according to the voltage range of the data voltage Vdata and the driving characteristics of the display panel.

[0125] In the pixel circuit shown, in the emission stage EMIS, the gate-source voltage (Vgs) of the driving element DT may be Vgs = (1 - C')×(Vdata - Vref) + Vth. Here, C' = C1 / (C1 + C2). When C2 = 0, C' = 1, and in the above equation, (1 - C') becomes zero, resulting in Vgs = Vth. Therefore, the second capacitor C2 may be required to change the gate-source voltage (Vgs) of the driving element DT according to the data voltage Vdata of the pixel data.

[0126] In the addressing stage WR, the first switching element M1 may be turned on according to the gate conduction voltage VGH of the first scan pulse SC1 to supply the data voltage Vdata to the first node DTG. The first switching element M1 may include a gate electrode connected to the first gate line to which the first scan pulse SC1 is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the first node DTG.

[0127] In the initialization stage INIT and the sampling stage SMPL, the second switching element M2 can be turned on according to the gate conduction voltage VGH of the second scan pulse SC2 to supply the reference voltage Vref to the first node DTG. The second switching element M2 can include a gate electrode connected to the second gate line to which the second scan pulse SC2 is applied, a first electrode connected to the REF line to which the reference voltage Vref is applied, and a second electrode connected to the first node DTG.

[0128] When the data voltage Vdata and the reference voltage Vref are applied to the pixel circuit through the data line DL, the number of transitions applied to the data line DL may increase. When the data voltage Vdata and the reference voltage Vref are applied to the pixel circuit through the data line DL, the frequency of the data line DL can increase, thereby increasing the power consumption of the display device. In the display device according to an embodiment of the present specification, the data line DL to which the data voltage Vdata is applied and the REF line to which the reference voltage Vref is applied can be separated. Therefore, the frequency of the voltage applied to the data line DL can be reduced, thereby reducing the power consumption.

[0129] In the initialization stage INIT, the third switching element M3 can be turned on according to the gate conduction voltage VGH of the third scan pulse SC3 to apply the initialization voltage Vini to the second node DTS. The third switching element M3 can include a gate electrode connected to the third gate line to which the third scan pulse SC3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the INI line to which the initialization voltage Vini is applied.

[0130] In the initialization stage INIT and the addressing stage WR, the fourth switching element M4 can be turned off according to the gate cut-off voltage VEL of the first EM pulse EM1 to block the current path between the VDD line to which the pixel driving voltage ELVDD is applied and the third node DTD. In the sampling stage SMPL and the light emitting stage EMIS, the fourth switching element M4 can be turned on according to the gate conduction voltage VEH of the first EM pulse EM1 to connect the VDD line to the third node DTD. The fourth switching element M4 can include a gate electrode connected to the fourth gate line to which the first EM pulse EM1 is applied, a first electrode connected to the VDD line, and a second electrode connected to the third node DTD.

[0131] During the sampling phase SMPL and the addressing phase WR, the fifth switching element M5 can be turned off according to the gate cut-off voltage VEL of the second EM pulse EM2 to block the current path between the second node DTS and the fourth node n4. During the initialization phase INIT and the emission phase EMIS, the fifth switching element M5 can be turned on according to the gate conduction voltage VEH of the second EM pulse EM2 to form a current path between the driving element DT and the light-emitting element EL. The fifth switching element M5 can include a gate electrode connected to a fifth gate line to which the second EM pulse EM2 is applied, a first electrode connected to the second node DTS, and a second electrode connected to the fourth node n4.

[0132] Figures 8A to 8D is a circuit diagram showing the operating states of pixel circuits corresponding to Figure 7 each operation of.

[0133] Referring to Figure 7 and Figure 8A , during the initialization phase INIT, the second switching element M2, the third switching element M3, and the fifth switching element M5 can be turned on. During the initialization phase INIT, the first switching element M1 and the fourth switching element M4 can be turned off. The voltages at the main nodes during the initialization phase INIT are DTD = Vref + Vth, DTG = Vref, and DTS = Vinit. "Vth" represents the threshold voltage of the driving element DT. Therefore, during the initialization phase INIT, the driving element DT can be turned on because its gate-source voltage (Vgs) is Vref - Vinit, which is higher than the threshold voltage (Vth).

[0134] Referring to Figure 7 and Figure 8B , during the sampling phase SMPL, when the second switching element M2 and the fourth switching element M4 can be turned on, the other switching elements M1, M3, and M5 can be turned off. During the sampling phase SMPL, when the voltage at the second node DTS increases and thus the gate-source voltage (Vgs) of the driving element DT reaches the threshold voltage (Vth), the driving element DT can be turned off. At the end of the sampling phase SMPL, the voltages at the main nodes are DTD = ELVDD, DTG = Vref, and DTS = Vref - Vth. Therefore, at the end of the sampling phase SMPL, the gate-source voltage (Vgs) of the driving element DT is Vgs = Vth. The sampling threshold voltage (Vth) of the driving element DT can be charged into the first capacitor C1.

[0135] Referring to Figure 7 and Figure 8C, in the addressing stage WR, the first switching element M1 can be turned on to apply the data voltage Vdata of the pixel data to the first node DTG. At this time, the other switching elements M2, M3, M4, and M5 can be turned off. At the end of the addressing stage WR, the voltage at the main node can be changed to DTD = ELVDD, DTG = Vdata, and DTS = Vref - Vth + C’×(Vdata - Vref). Here, C’ = C1 / (C1 + C2). In the addressing stage WR, the gate-source voltage (Vgs) of the driving element DT can be changed to Vgs = (1 - C’)×(Vdata - Vref) + Vth.

[0136] In the sampling stage SMPL and the addressing stage WR, the second node DTS can be electrically separated from the fourth node n4, as Figure 8B and Figure 8C shown. Therefore, since the threshold voltage sampling and data addressing of the driving element DT are not affected by the resistance of the light-emitting element EL and the process deviation of the light-emitting element EL, the influence of the light-emitting element EL on the brightness of the pixel can be excluded.

[0137] Referring to Figure 7 and Figure 8D , in the light-emitting stage EMIS, when the fourth switching element M4 and the fifth switching element M5 can be turned on, the other switching elements M1, M2, and M3 can be turned off. In the light-emitting stage EMIS, the voltage at the main node can be changed to DTD = ELVDD, DTG = Vdata, and DTS = Vref - Vth + C’×(Vdata - Vref). In the light-emitting stage EMIS, the voltage at the second node DTS can be equal to the anode voltage (Vel) of the light-emitting element EL. In the light-emitting stage EMIS, the gate-source voltage (Vgs) of the driving element DT is Vgs = (1 - C’)×(Vdata - Vref) + Vth.

[0138] Figure 9 is a waveform diagram showing a method of driving a pixel circuit according to another embodiment of the present specification. Figure 10 is a circuit diagram showing the current flowing in the pixel circuit shown in Figure 6 during the second initialization operation. Components that perform substantially the same functions as those described in the above embodiments are denoted by the same reference numerals, and their repeated descriptions will be omitted.

[0139] Referring to Figure 7 , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9 and Figure 10, the display time of the pixel circuit may include a first initialization stage INIT1, a sampling stage SMPL set after the first initialization stage INIT1, an addressing stage WR set after the sampling stage SMPL, a second initialization stage INIT2 set after the addressing stage WR, and a light-emitting stage EMIS set after the second initialization stage INIT2, as Figure 9 shown.

[0140] In the addressing stage WR, the first scan pulse SC1 may be a gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data. In the first initialization stage INIT1, the sampling stage SMPL, the second initialization stage INIT2, and the light-emitting stage EMIS, the first scan pulse SC1 may be a gate-off voltage VGL. In the first initialization stage INIT1 and the sampling stage SMPL, the second scan pulse SC2 may be a gate-on voltage VGH. In the addressing stage WR, the second initialization stage INIT2, and the light-emitting stage EMIS, the second scan pulse SC2 may be a gate-off voltage VGL. In the first initialization stage INIT1 and the second initialization stage INIT2, the third scan pulse SC3 may be a gate-on voltage VGH. In the sampling stage SMPL, the addressing stage WR, and the light-emitting stage EMIS, the third scan pulse SC3 may be a gate-off voltage VGL.

[0141] In the first initialization stage INIT1, the sampling stage WR, and the second initialization stage INIT2, the first EM pulse EM1 may be a gate-off voltage VEL. In the sampling stage SMPL and the light-emitting stage EMIS, the first EM pulse EM1 may be a gate-on voltage VEH.

[0142] In the first initialization stage INIT1, the second initialization stage INIT2, and the light-emitting stage EMIS, the second EM pulse EM2 may be a gate-on voltage VEH. In the sampling stage SMPL and the addressing stage WR, the second EM pulse EM2 may be a gate-off voltage VEL.

[0143] Referring to Figure 7 , Figure 8A , Figure 8B , Figure 8C and Figure 8D, in the first initialization stage INIT, the second switching element M2, the third switching element M3, and the fifth switching element M5 can be turned on. The first switching element M1 and the fourth switching element M4 can be turned off. In the sampling stage SMPL, when the second switching element M2 and the fourth switching element M4 can be turned on, the other switching elements M1, M3, and M5 can be turned off. In the addressing stage WR, the first switching element M1 can be turned on to apply the data voltage Vdata of the pixel data to the first node DTG. At this time, the other switching elements M2, M3, M4, and M5 can be turned off.

[0144] Refer to Figure 9 and Figure 10 , in the second initialization stage INIT2, when the third switching element M3 and the fifth switching element M5 can be turned on, the other switching elements M1, M2, and M4 can be turned off. In the second initialization stage INIT2, the voltage at the second node DTS can be initialized to DTS = Vinit. At this time, since the voltage at the first node DTG can also increase to the same amount as the initialization voltage Vinit, the gate-source voltage (Vgs) of the driving element DT can be maintained at the voltage set in the addressing stage WR.

[0145] In the light emitting stage EMIS, when the fourth switching element M4 and the fifth switching element M5 can be turned on, the other switching elements M1, M2, and M3 can be turned off. In the light emitting stage EMIS, the light emitting element EL can be driven by the current generated according to the gate-source voltage (Vgs) of the driving element DT to emit light with a brightness corresponding to the gray value of the pixel data.

[0146] Figure 11A is a view showing an embodiment in which the output signals of the pixel and the gate driver in this specification are shared. Figure 11B is a view showing another embodiment in which the output signals of the pixel and the gate driver in this specification are shared.

[0147] Refer to Figure 11A , the pixel array may include a plurality of pixel row groups PXLOE(n) and PXLOE(n + 1) (n is an odd or even number greater than or equal to 1). Each of the plurality of pixel row groups PXLOE(n) and PXLOE(n + 1) may include odd pixel rows PXLO(n) and PXLO(n + 1) and even pixel rows PXLE(n) and PXLE(n + 1).

[0148] For example, n can be 1. The first pixel row group PXLOE(1) may include odd pixel rows PXLO(1) and even pixel rows PXLE(1). The second pixel row group PXLOE(2) may include odd pixel rows PXLO(2) and even pixel rows PXLE(2).

[0149] For example, n can be 2. The second pixel row group PXLOE(2) may include odd pixel rows PXLO(2) and even pixel rows PXLE(2). The third pixel row group PXLOE(3) may include odd pixel rows PXLO(3) and even pixel rows PXLE(3).

[0150] For example, n can be 3. The third pixel row group PXLOE(3) may include odd pixel rows PXLO(3) and even pixel rows PXLE(3). The fourth pixel row group PXLOE(4) may include odd pixel rows PXLO(4) and even pixel rows PXLE(4).

[0151] For example, n can be 4. The fourth pixel row group PXLOE(4) may include odd pixel rows PXLO(4) and even pixel rows PXLE(4). The fifth pixel row group PXLOE(5) may include odd pixel rows PXLO(5) and even pixel rows PXLE(5).

[0152] Each of the odd pixel rows PXLO and the even pixel rows PXLE may include a row of pixels arranged in the row direction (e.g., Figure 1A or Figure 1B the X-axis direction in ) in the pixel array of the display panel. The pixels arranged in one pixel row may share a gate line.

[0153] The gate driver may include a plurality of shift registers. The gate driver may include a first shift register SR1 for sequentially outputting pulses of a first gate signal G1OUT, a second shift register SR2 for sequentially outputting pulses of a second gate signal G2OUT, a third shift register SR3 for sequentially outputting pulses of a third gate signal G3OUT, a fourth shift register SR4 for sequentially outputting pulses of a fourth gate signal G4OUT, and a fifth shift register SR5 for sequentially outputting pulses of a fifth gate signal G5OUT.

[0154] The first gate signal G1OUT may be a first gate pulse. The second gate signal G2OUT may be a second gate pulse. The third gate signal G3OUT may be a third gate pulse. The fourth gate signal G4OUT may be a first EM pulse. The fifth gate signal G5OUT may be a second EM pulse.

[0155] The first shift register SR1 may include a plurality of odd signal transmission units ST1O for receiving a first odd start pulse G1VST(ODD) and a first clock G1CLK, and sequentially outputting pulses of odd gate signals G1OUTO(n) and G1OUTO(n + 1).

[0156] The first shift register SR1 may include a plurality of even signal transmission units ST1E for receiving a first even start pulse G1VST(EVEN) and a first clock G1CLK, and sequentially outputting pulses of even gate signals G1OUTE(n) and G1OUTE(n + 1).

[0157] The pulse width of the first gate signal G1OUT may be one horizontal period.

[0158] The first clock G1CLK may include two or more shift clocks having different phases.

[0159] A carry signal may be transmitted between adjacent odd signal transmission units ST1O and even signal transmission units ST1E.

[0160] To adjust the luminance difference between pixel rows, the phase timing, pulse width, etc. of the pulses of the gate signals G1OUTO(n) and G1OUTO(n + 1) applied to odd pixel rows and the pulses of the gate signals G1OUTE(n) and G1OUTE(n + 1) applied to even pixel rows may be adjusted differently.

[0161] After the pulse of the odd gate signal G1OUTO(n) is applied to the n-th odd pixel row PXLO(n), the pulse of the even gate signal G1OUTE(n) may be applied to the n-th even pixel row PXLE(n). Subsequently, after the pulse of the odd gate signal G1OUTO(n + 1) is applied to the (n + 1)-th odd pixel row PXLO(n + 1), the pulse of the even gate signal G1OUTE(n + 1) may be applied to the (n + 1)-th even pixel row PXLE(n + 1).

[0162] For example, n may be 1. After the pulse of the odd gate signal G1OUTO(1) is applied to the first odd pixel row PXLO(1), the pulse of the even gate signal G1OUTE(1) may be applied to the first even pixel row PXLE(1). Subsequently, after the pulse of the odd gate signal G1OUTO(2) is applied to the second odd pixel row PXLO(2), the pulse of the even gate signal G1OUTE(2) may be applied to the second even pixel row PXLE(2).

[0163] For example, n can be 2. The gate signal G2OUT(2) can be simultaneously applied to a second pixel row group PXLOE(2) including adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2). The gate signal G2OUT(3) can be simultaneously applied to a third pixel row group PXLOE(3) including adjacent third odd pixel row PXLO(3) and third even pixel row PXLE(3).

[0164] The second shift register SR2 can include a plurality of signal transmission units ST2 connected in cascade with each other to receive a second start pulse G2VST and a second clock G2CLK and sequentially output pulses of the second gate signal G2OUT.

[0165] The pulse width of the second gate signal G2OUT can be set to be greater than one horizontal period and simultaneously applied to pixels provided in a plurality of pixel rows.

[0166] The clock G2CLK can include two or more shift clocks having different phases.

[0167] The carry signal can be transmitted between the signal transmission units ST2.

[0168] The n-th gate signal G2OUT(n) can be simultaneously applied to an n-th pixel row group PXLOE(n) including adjacent n-th odd pixel row PXLO(n) and n-th even pixel row PXLE(n). The (n + 1)-th gate signal G2OUT(n + 1) can be simultaneously applied to an (n + 1)-th pixel row group PXLOE(n + 1) including adjacent (n + 1)-th odd pixel row PXLO(n + 1) and (n + 1)-th even pixel row PXLE(n + 1).

[0169] For example, n can be 1. The gate signal G2OUT(1) can be simultaneously applied to a first pixel row group PXLOE(1) including adjacent first odd pixel row PXLO(1) and first even pixel row PXLE(1). The gate signal G2OUT(2) can be simultaneously applied to a second pixel row group PXLOE(2) including adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2).

[0170] For example, n can be 2. The gate signal G2OUT(2) can be simultaneously applied to a second pixel row group PXLOE(2) including adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2). The gate signal G2OUT(3) can be simultaneously applied to a third pixel row group PXLOE(3) including adjacent third odd pixel row PXLO(3) and third even pixel row PXLE(3).

[0171] The third shift register SR3 may include a plurality of signal transmission units ST3 connected in cascade to each other for receiving a third start pulse G3VST and a third clock G3CLK and sequentially outputting pulses of a third gate signal G3OUT.

[0172] The pulse width of the third gate signal G3OUT may be set to be greater than one horizontal period and is simultaneously applied to pixels provided in a plurality of pixel rows.

[0173] The clock G3CLK may include two or more shift clocks having different phases.

[0174] A carry signal may be transmitted between the signal transmission units ST3.

[0175] The gate signal G3OUT(n) may be simultaneously applied to an nth pixel row group PXLOE(n) including adjacent nth odd pixel row PXLO(n) and nth even pixel row PXLE(n). The gate signal G3OUT(n + 1) may be simultaneously applied to an (n + 1)th pixel row group PXLOE(n + 1) including adjacent (n + 1)th odd pixel row PXLO(n + 1) and (n + 1)th even pixel row PXLE(n + 1).

[0176] For example, n may be 1. The gate signal G3OUT(1) may be simultaneously applied to a first pixel row group PXLOE(1) including adjacent first odd pixel row PXLO(1) and first even pixel row PXLE(1). The gate signal G3OUT(2) may be simultaneously applied to a second pixel row group PXLOE(2) including adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2).

[0177] For example, n may be 2. The gate signal G3OUT(2) may be simultaneously applied to a second pixel row group PXLOE(2) including adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2). The gate signal G3OUT(3) may be simultaneously applied to a third pixel row group PXLOE(3) including adjacent third odd pixel row PXLO(3) and third even pixel row PXLE(3).

[0178] The fourth shift register SR4 may include a plurality of signal transmission units ST4 connected in cascade to each other for receiving a fourth start pulse G4VST and a fourth clock G4CLK and sequentially outputting pulses of a fourth gate signal G4OUT.

[0179] The pulse width of the fourth gate signal G4OUT may be set to be greater than one horizontal period and is simultaneously applied to pixels provided in a plurality of pixel rows.

[0180] The clock G4CLK may include two or more shift clocks having different phases.

[0181] The carry signal may be transmitted between the signal transmission units ST4.

[0182] The gate signal G4OUT(n) may be simultaneously applied to the nth pixel row group PXLOE(n) including the adjacent nth odd pixel row PXLO(n) and the nth even pixel row PXLE(n). The gate signal G4OUT(n + 1) may be simultaneously applied to the (n + 1)th pixel row group PXLOE(n + 1) including the adjacent (n + 1)th odd pixel row PXLO(n + 1) and the (n + 1)th even pixel row PXLE(n + 1).

[0183] For example, n may be 1. The gate signal G4OUT(1) may be simultaneously applied to the first pixel row group PXLOE(1) including the adjacent first odd pixel row PXLO(1) and the first even pixel row PXLE(1). The gate signal G4OUT(2) may be simultaneously applied to the second pixel row group PXLOE(2) including the adjacent second odd pixel row PXLO(2) and the second even pixel row PXLE(2).

[0184] For example, n may be 2. The gate signal G4OUT(2) may be simultaneously applied to the second pixel row group PXLOE(2) including the adjacent second odd pixel row PXLO(2) and the second even pixel row PXLE(2). The gate signal G4OUT(3) may be simultaneously applied to the third pixel row group PXLOE(3) including the adjacent third odd pixel row PXLO(3) and the third even pixel row PXLE(3).

[0185] The fifth shift register SR5 may include a plurality of signal transmission units ST5 connected in cascade to each other for receiving a fifth start pulse G5VST and a fifth clock G5CLK and sequentially outputting pulses of a fifth gate signal G5OUT.

[0186] The pulse width of the fifth gate signal G5OUT may be set to be greater than one horizontal period and simultaneously applied to the pixels provided in a plurality of pixel rows.

[0187] The clock G5CLK may include two or more shift clocks having different phases.

[0188] The carry signal may be transmitted between the signal transmission units ST5.

[0189] The gate signal G5OUT(n) can be simultaneously applied to the n-th pixel row group PXLOE(n) including the adjacent n-th odd pixel row PXLO(n) and n-th even pixel row PXLE(n). The gate signal G5OUT(n + 1) can be simultaneously applied to the (n + 1)-th pixel row group PXLOE(n + 1) including the adjacent (n + 1)-th odd pixel row PXLO(n + 1) and (n + 1)-th even pixel row PXLE(n + 1).

[0190] For example, n can be 1. The gate signal G5OUT(1) can be simultaneously applied to the first pixel row group PXLOE(1) including the adjacent first odd pixel row PXLO(1) and first even pixel row PXLE(1). The gate signal G5OUT(2) can be simultaneously applied to the second pixel row group PXLOE(2) including the adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2).

[0191] For example, n can be 2. The gate signal G5OUT(2) can be simultaneously applied to the second pixel row group PXLOE(2) including the adjacent second odd pixel row PXLO(2) and second even pixel row PXLE(2). The gate signal G5OUT(3) can be simultaneously applied to the third pixel row group PXLOE(3) including the adjacent third odd pixel row PXLO(3) and third even pixel row PXLE(3).

[0192] Referring to Figure 11B , the gate driver can be disposed in the left non-display area and the right non-display area of the display panel to apply the gate signals G1OUT, G2OUT, G3OUT, G4OUT, and G5OUT to the pixel rows in a dual-feed method. In the dual-feed method, the gate signals can be simultaneously applied at both ends of the gate line. The gate driver can be disposed in the opposite sides of the display panel in the above manner to minimize signal distortion caused by load differences at each position. In an embodiment, at least some circuits of the gate driver can be disposed in the display area.

[0193] Figure 12 is a view schematically showing the shift register of the gate driver. Other shift registers included in the gate driver can be implemented as substantially the same circuit.

[0194] Referring to Figure 12 , the shift register can be implemented as a known shift register circuit for driving a display panel. The shift register can include a plurality of signal transmission units ST(1) to ST(n) connected in cascade with each other. The signal transmission units ST(1) to ST(n) can be GIP elements formed using the GIP method. The signal transmission unit can be interpreted as a stage of the shift register.

[0195] When compared with the uppermost signal transmission unit ST(1), the configurations and connection relationships of the signal transmission units ST(2) to ST(n) other than the uppermost signal transmission unit ST(1) are substantially the same as those of the uppermost signal transmission unit ST(1), except that the remaining signal transmission units ST(2) to ST(n) receive carry signals C(1) to C(n) instead of the external start signal VST, receive the signal Qb(n - 1) applied from the Qb node in the previous signal transmission unit instead of the Qb start signal QbST, and output gate signals GOUT(1) to GOUT(n) having different phases.

[0196] When comparing the signal transmission units ST(2) to ST(n) other than the uppermost signal transmission unit ST(1), the configurations and connection relationships of the signal transmission units ST(2) to ST(n) are substantially the same as each other, except that the remaining signal transmission units ST(2) to ST(n) receive clock signals CLK having different phases and output gate signals GOUT(2) to GOUT(n) having different phases.

[0197] The clock CLK may include two or more shift clocks having different phases.

[0198] Each of the signal transmission units may include a buffer transistor BUF, which outputs a pulse of the gate signal by charging / discharging the output node nO in response to the voltage at the CLK node where the clock CLK is input thereto, the voltage at the VST node where the start pulse VST or the carry signal C(n) from the previous signal transmission unit or input from the previous signal transmission unit is input thereto, the voltage at the first control node Q, the voltage at the second control node Qb, and the voltage at the output node nO.

[0199] The "previous signal transmission unit" is the signal transmission unit that outputs the previous gate signal before the output signal of the signal transmission unit for outputting the current gate signal. For example, in the case of the Nth signal transmission unit for outputting the Nth gate signal, the previous signal transmission unit may be the (N - i)th signal transmission unit (N is a natural number, and i is a natural number between 1 and 6).

[0200] The "immediate previous signal transmission unit" is the signal transmission unit that outputs the previous gate signal before the output signal of the signal transmission unit for outputting the current gate signal. For example, in the case of the Nth signal transmission unit for outputting the Nth gate signal, the immediate previous signal transmission unit may be the (N - i)th signal transmission unit (i is 1).

[0201] The operation of the topmost signal transmission unit ST(1) can be activated according to an external start signal, and the operations of the second topmost signal transmission unit ST(2) to the lowest signal transmission unit ST(n) can be activated according to the carry signal C(n - 1) of the previous signal transmission unit. The carry signal C(n - 1) is the gate signal of the previous signal transmission unit and can be an internal start signal.

[0202] The first high potential voltage GVDD0, the second high potential voltage GVDD1, the first low potential voltage GVSS0, and the second low potential voltage GVSS1 can be applied to each of the signal transmission units ST(1) to ST(n). The first high potential voltage GVDD0, the second high potential voltage GVDD1, the first low potential voltage GVSS0, and the second low potential voltage GVSS1 can all be DC voltages (or constant voltages). The first high potential voltage GVDD0, the second high potential voltage GVDD1, the first low potential voltage GVSS0, and the second low potential voltage GVSS1 supplied to the signal transmission units can be supplied to the gate driver through one line.

[0203] The phase of the clock CLK can be sequentially shifted. The signal transmission unit ST can receive one or more clocks.

[0204] In the illustrated embodiment, the CLK node of each of the signal transmission units ST can be connected to a clock line provided in the non-display area of the display panel to receive the clock CLK. However, the node is not limited to the illustrated embodiment and can receive the clock CLK through a clock line provided in the display area.

[0205] The first signal transmission unit ST(1) can receive the clock CLK, the start pulse VST (hereinafter referred to as the "VST signal"), and the Qb start pulse QbST (hereinafter referred to as the "QbST signal"), and output the pulse of the gate signal GOUT(1), the pulse of the voltage level signal Qb(1) applied to the Qb node nQb, and the pulse of the carry signal C(1).

[0206] The second signal transmission unit ST(2) can receive the clock CLK, the carry signal C(1), and the voltage level signal Qb(1) applied to the Qb node nQb of the previous signal transmission unit, and output the pulse of the gate signal GOUT(2), the pulse of the voltage level signal Qb(2) applied to the Qb node nQb, and the pulse of the carry signal C(2).

[0207] The n-th signal transmission unit ST(n) can receive a clock CLK, a carry signal C(n - 1), and a voltage level signal Qb(n - 1) applied to the Qb node (nQb) of the previous signal transmission unit ST(n - 1), and output pulses of a gate signal GOUT(n), a voltage level signal Qb(n) applied to the Qb node nQb, and a carry signal C(n) (n is a positive integer of 1 or greater).

[0208] The buffer transistor BUF can include a pull-up transistor Tu controlled by the voltage at a first control node Q and a pull-down transistor Td controlled by the voltage at a second control node Qb.

[0209] The pull-up transistor Tu can be turned on according to the voltage at the first control node Q to charge the voltage at the output node nO to the gate turn-on voltage GVDD. The pull-up transistor Tu can include a gate electrode connected to the first control node Q, a first electrode to which the gate turn-on voltage GVDD is applied, and a second electrode connected to the output node nO.

[0210] The pull-down transistor Td can be turned on according to the voltage at the second control node Qb and supply the gate cut-off voltage GVSS to the output node nO. The pull-down transistor Td can include a gate electrode connected to the second control node Qb, a first electrode connected to the output node nO, and a second electrode to which the gate cut-off voltage GVSS is applied.

[0211] As described below, the output node nO can include a first output node connected to a first output terminal for outputting a pulse of the carry signal C(n), and a second output node connected to a second output terminal for outputting pulses of the gate signals GOUT(1) to GOUT(n).

[0212] Figure 13 is a circuit diagram showing a pixel circuit according to an embodiment of the present specification. Figure 14 is a waveform diagram showing the voltage levels of signals input to the Figure 13 switching element shown during a sensing time for external compensation of a display device. Figure 15 is a circuit diagram showing the operating state of the pixel circuit during a sensing time for external compensation of a display device. Components that perform substantially the same functions as those described in the above embodiment are denoted by the same reference numerals, and their repeated description will be omitted.

[0213] Refer to Figure 13, as shown in the figure, due to space limitations, only two pixel circuits are exemplarily shown in the vertical direction. The display device may include a plurality of pixel row groups PXLOE(n) and PXLOE(n + 1) (n is an odd or even number greater than or equal to 1). Each of the plurality of pixel row groups PXLOE(n) and PXLOE(n + 1) may include an odd pixel row PXLO(n) and PXLO(n + 1) and an even pixel row PXLE(n) and PXLE(n + 1).

[0214] The pixel circuits included in each of the pixel row groups PXLOE(n) and PXLOE(n + 1) may further include Figure 3 the external compensation circuit unit YB shown.

[0215] The nth pixel row group PXLOE(n) may include the nth odd pixel row PXLO(n) and the nth even pixel row PXLE(n) that are vertically adjacent to each other. The (n + 1)th pixel row group PXLOE(n + 1) may include the (n + 1)th odd pixel row PXLO(n + 1) and the (n + 1)th even pixel row PXLE(n + 1) that are vertically adjacent to each other.

[0216] However, the term "vertically" adjacent is an example, and pixel rows define pixels sharing a gate line, and thus the positional relationship between adjacent pixel rows can be appropriately modified by the operator.

[0217] The nth odd pixel row PXLO(n) and the nth even pixel row PXLE(n) may share the INI line to which the initialization voltage Vini is applied. The (n + 1)th odd pixel row PXLO(n + 1) and the (n + 1)th even pixel row PXLE(n + 1) may share the INI line to which the initialization voltage Vini is applied. The nth pixel row group PXLOE(n) and the (n + 1)th pixel row group PXLOE(n + 1) may share the INI line to which the initialization voltage Vini is applied.

[0218] Referring to Figure 14 , for the threshold voltage (Vth) sensing time of the driving element DT for external compensation of the display device, the second scan pulse SC2 may be the gate cut-off voltage VGL, and the first EM pulse EM1 and the second EM pulse EM2 may be the gate conduction voltage VEH.

[0219] After the first odd scan pulse SC1O(n) at the gate conduction voltage VGH is applied to the nth odd pixel row PXLO(n), the first even scan pulse SC1E(n) at the gate conduction voltage VGH may be applied to the nth even pixel row PXLE(n).

[0220] After the first odd scan pulse SC1O(n + 1) at the gate-on voltage VGH is applied to the (n + 1)-th odd pixel row PXLO(n + 1), the first even scan pulse SC1E(n + 1) at the gate-on voltage VGH can be applied to the n-th even pixel row PXLE(n).

[0221] After the n-th first scan pulse SC1O(n) / SC1E(n) at the gate-on voltage VGH is applied to the n-th pixel row group PXLOE(n), the (n + 1)-th first scan pulse SC1O(n + 1) / SC1E(n + 1) at the gate-on voltage VGH can be applied to the (n + 1)-th pixel row group PXLOE(n + 1).

[0222] The n-th third scan pulse SC3(n) at the gate-on voltage VGH can be simultaneously applied to the n-th pixel row group PXLOE(n) including the n-th odd pixel row PXLO(n) and the n-th even pixel row PXLE(n).

[0223] The (n + 1)-th third scan pulse SC3(n + 1) at the gate-on voltage VGH can be simultaneously applied to the (n + 1)-th pixel row group PXLOE(n + 1) including the (n + 1)-th odd pixel row PXLO(n + 1) and the (n + 1)-th even pixel row PXLE(n + 1).

[0224] The n-th first scan pulse SC1O(n) / SC1E(n) at the gate-on voltage VGH can be applied while the n-th third scan pulse SC3(n) at the gate-on voltage VGH is applied.

[0225] The (n + 1)-th first scan pulse SC1O(n + 1) / SC1E(n + 1)(n + 1) at the gate-on voltage VGH can be applied while the (n + 1)-th third scan pulse SC3(n + 1) at the gate-on voltage VGH is applied.

[0226] The n-th first scan pulse SC1O(n) / SC1E(n) at the gate-on voltage VGH can be applied synchronously with the rising edge of the n-th third scan pulse SC3(n) at the gate-on voltage VGH.

[0227] The (n + 1)-th first scan pulse SC1O(n) / SC1E(n) at the gate-on voltage VGH can be applied synchronously with the rising edge of the (n + 1)-th third scan pulse SC3(n + 1) at the gate-on voltage VGH.

[0228] Refer to Figure 14 and Figure 15For the threshold voltage (Vth) sensing time of the driving element DT for external compensation of a display device, the second switching element M2 to which the second scan pulse SC2 is applied may be turned off, and the fourth switching element M4 and the fifth switching element M5 to which the first EM pulse EM1 and the second EM pulse EM2 are applied may be turned on.

[0229] In the SL section, the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) may be held at the gate-on voltage VGH in a section where the third scan pulse SC3(n + 1) applied to the n-th pixel row group PXLOE(n) is held at the gate-on voltage VGH. In the SL section, the section where the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is held at the gate-on voltage VGH and the section where the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) is held at the gate-on voltage VGH may partially overlap each other.

[0230] For threshold voltage (Vth) sensing, the third scan pulse SC3(n + 1) having the gate-on voltage VGH may be simultaneously input to the (n + 1)-th odd pixel row PXLO(n + 1) and the (n + 1)-th even pixel row PXLE(n + 1) included in the (n + 1)-th pixel row group PXLOE(n + 1). In this case, the sensing load of the corresponding sensing line may be increased by the third scan pulse SC3(n) having the gate-on voltage VGH applied to the n-th pixel row group PXLOE(n). For example, the capacitive load may increase due to an increase in the capacitance of the sensing line. Therefore, there may be a problem that the sensing error increases due to an increase in the influence of the sensing time and noise.

[0231] Figure 16 is a view schematically showing a shift register of a gate driver according to an embodiment of the present specification. Other shift registers included in the gate driver may be implemented as substantially the same circuit. Components performing substantially the same functions as those described in the above embodiment are denoted by the same reference numerals, and their repeated description will be omitted.

[0232] Refer to Figure 16, the shift register can sequentially output a gate signal GOUT, which includes any one selected from the group including the following: the above-mentioned second gate signal G2OUT, third gate signal G3OUT, fourth gate signal G4OUT, and fifth gate signal G5OUT. In an exemplary embodiment, the gate signal GOUT can be the third gate signal G3OUT. More preferably, the shift register can be a third shift register for outputting a third scan pulse.

[0233] The gate signal GOUT can be simultaneously applied to pixels provided in a plurality of pixel rows. The gate signal GOUT(n) can be simultaneously applied to the nth pixel row group including the nth odd pixel row and the nth even pixel row adjacent to each other. The gate signal GOUT(n + 1) can be simultaneously applied to the (n + 1)th pixel row group including the (n + 1)th odd pixel row and the (n + 1)th even pixel row adjacent to each other.

[0234] For example, n can be 1. The gate signal GOUT(1) can be simultaneously applied to the first pixel row group including the first odd pixel row and the first even pixel row adjacent to each other. The gate signal GOUT(n2) can be simultaneously applied to the second pixel row group including the second odd pixel row and the second even pixel row adjacent to each other.

[0235] The gate signal simultaneously applied to pixels provided in a plurality of pixel rows can be any one of the second scan pulse, third scan pulse, first EM pulse, and second EM pulse described above. In an exemplary embodiment, the gate signal simultaneously applied to pixels provided in a plurality of pixel rows can be the third scan pulse described above.

[0236] Since the signal output from one signal transmission unit ST is simultaneously transmitted to a pixel row group including two pixel rows, the number of signal transmission units ST(1), ST(2),... can be half or substantially half of the number of pixel rows provided on the display panel. Since one pixel row group shares one signal transmission unit ST, the number of signal transmission units ST(1), ST(2),... can be half or substantially half of the number of pixel rows provided on the display panel.

[0237] Each of the signal transmission units may include a CTRL node to which a control signal CTRL is input and a plurality of CTRLB nodes to which a control bar signal CTRLB is input. The control bar signal CTRLB may be referred to as an inverted control signal CTRLB. The control bar signal CTRLB is generated to have a phase inverted from that of the control signal CTRL and is an inverted signal of the control signal CTRL. The control signal CTRL and the control bar signal CTRLB have phases inverted from each other and have a phase difference of 180 degrees. The control bar signal CTRLB may be an inverted phase signal of the control signal CTRL. For example, when the control signal CTRL is a gate-on voltage, the control bar signal CTRLB may be a gate-off voltage. For example, when the control signal CTRL is a gate-off voltage, the control bar signal CTRLB may be a gate-on voltage.

[0238] The control signal CTRL may include an odd control signal CTRLO input to odd signal transmission units ST(1),... and an even control signal CTRLE input to even signal transmission units ST(2),....

[0239] The control bar signal CTRLB may include an odd control bar signal CTRLBO input to odd signal transmission units ST(1),... and an even control bar signal CTRLBE input to even signal transmission units ST(2),....

[0240] Both the control signal CTRL and the control bar signal CTRLB may be supplied to each of the signal transmission units ST(1), ST(2),....

[0241] Figure 17 is a circuit diagram specifically showing the signal transmission unit included in a gate driver according to an embodiment of the present specification. Figure 18 is a waveform diagram showing input / output waveforms during a display time in a gate driver according to an embodiment of the present specification.

[0242] Referring to Figure 17 and Figure 18 the signal transmission unit may include a plurality of transistors T1 to T12, a plurality of capacitors C3 to C5, and nodes connecting the transistors and the capacitors.

[0243] The first transistor T1 to the twelfth transistor T12 may be implemented as an n-channel oxide TFT. The n-channel TFT may be turned on in response to a gate high voltage VGH and turned off in response to a gate low voltage VGL. In the case of an n-channel transistor, the gate-on voltage may be the gate high voltage VGH, and the gate-off voltage may be the gate low voltage VGL.

[0244] The first low potential voltage GVDD0 can be set to be higher than the second low potential voltage GVDD1.

[0245] The circuit diagram shown is the circuit of the nth signal transmission unit ST(n) (n is a positive integer). When the dummy stage is omitted and n is 1, the carry signal C(n - 1) can be an external start signal VST (see Figure 16 ), and the Qb signal Qb(n - 1) can be the Figure 16 QbST signal in

[0246] Other signal transmission units can also be implemented as circuits substantially the same as the nth signal transmission unit ST(n).

[0247] The signal transmission unit can include a first control node nQ (hereinafter referred to as the "Q node"), a second control node nQb(n) (hereinafter referred to as the "Qb node"), a first circuit unit 71, a second circuit unit 72, and a third circuit unit 73.

[0248] When the clock CLK is a voltage higher than or equal to the gate conduction voltage VGH, the first circuit unit 71 can supply the voltage of the (n - 1)th carry signal C(n - 1) from the (n - 1)th signal transmission unit ST(n - 1) as the previous signal transmission unit to the Q node nQ to charge the Q node nQ. The first circuit unit 71 can include a first transistor to a third transistor T1, T2, and T3.

[0249] When the clock CLK is the gate conduction voltage VGH, the first transistor T1 can conduct to supply the voltage of the carry signal C(n - 1) to the Qh node nQh. The first transistor T1 can include a gate electrode to which the clock CLK is applied, a first electrode to which the (n - 1)th carry signal C(n - 1) is applied, and a second electrode connected to the Qh node nQh.

[0250] When the clock CLK is at the gate-on voltage VGH, the second transistor T2 can conduct to supply the voltage of the Qh node nQh to the Q node nQ to charge the Q node. The second transistor T2 can include a gate electrode to which the clock CLK is applied, a first electrode connected to the Qh node nQh, and a second electrode connected to the Q node nQ.

[0251] The first transistor T1 and the second transistor T2 can be connected in series. The first transistor T1 and the second transistor T2 can be connected in series between the node to which the (n - 1)-th carry signal C(n - 1) is applied and the Qh node nQh.

[0252] When the Q node nQ is charged, the third transistor T3 can conduct to supply the second high-potential voltage GVDD1 to the Qh node nQh through the node to which the second high-potential voltage GVDD1 is applied. The second high-potential voltage GVDD1 can be supplied from the node to which the second high-potential voltage GVDD1 is applied to the Qh node nQh. The third transistor T3 can include a gate electrode connected to the Q node nQ, a first electrode connected to the node to which the second high-potential voltage GVDD1 is applied, and a second electrode connected to the Qh node nQh.

[0253] The second circuit unit 72 can include an inverter circuit that inverts the potential of the Q node nQ to apply an inverted potential to the Qb node nQb(n). The inverter circuit of the second circuit unit 72 can include a Qb node charging unit and a Qb node discharging unit.

[0254] The Qb node charging unit can include a 4A transistor T4A and a 4B transistor T4B. The 4A transistor T4A can include a 4A1 transistor T4A1 and a 4A2 transistor T4A2. The 4A1 transistor T4A1 and the 4A2 transistor T4A2 can be connected in series to reduce leakage current. The 4B transistor T4B can include a 4B1 transistor T4B1 and a 4B2 transistor T4B2. The 4B1 transistor T4B1 and the 4B2 transistor T4B2 can be connected in series to reduce leakage current.

[0255] The Qb node charging unit can switch the current path between the node to which the second high-potential voltage GVDD1 is applied and the Qb node nQb(n) according to the voltage Qb(n - 1) applied from the (n - 1)-th Qb node nQb(n - 1) of the (n - 1)-th signal transmission unit ST(n - 1).

[0256] When the voltage at the I node nI is the gate turn-on voltage VGH, the 4Ath transistor T4A can be turned on to connect the node to which the second high potential voltage GVDD1 is applied to the Qb node nQb(n), thereby charging the Qb node nQb(n) to a high voltage equal to or higher than the gate turn-on voltage VGH. The 4Ath transistor T4A may include a gate electrode connected to the I node nI, a first electrode connected to the node to which the second high potential voltage GVDD1 is applied, and a second electrode connected to the Qb node nQb(n).

[0257] The 4Ath transistor T4A may include a 4A1st transistor T4A1 and a 4A2nd transistor T4A2 connected in series. The 4A1st transistor T4A1 and the 4A2nd transistor T4A2 may be connected in series to reduce the leakage current. The 4A1st transistor T4A1 may include a gate electrode connected to the I node nI, a first electrode connected to the node to which the second high potential voltage GVDD1 is applied, and a second electrode connected to the Qb node nQb(n). The 4A2nd transistor T4A2 may include a gate electrode connected to the I node nI, a first electrode connected to the second electrode of the 4A1st transistor T4A1, and a second electrode connected to the Qb node nQb(n).

[0258] When the voltage Qb(n - 1) applied from the (n - 1)th Qb node nQb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1) is a high voltage equal to or higher than the gate turn-on voltage VGH, the 4Bth transistor T4B can be turned on to supply the second high potential voltage GVDD1 to the I node nI. The I node nI can be charged to the gate turn-on voltage VGH or higher. The 4Bth transistor T4B may include a gate electrode connected to the node to which the voltage Qb(n - 1) applied from the (n - 1)th Qb node nQb(n - 1) of the (n - 1)th signal transmission unit ST(n - 1) is input, a first electrode connected to the node to which the second high potential voltage GVDD1 is applied, and a second electrode connected to the I node nI.

[0259] The 4B transistor T4B may include a 4B1 transistor T4B1 and a 4B2 transistor T4B2. The 4B1 transistor T4B1 may include a gate electrode connected to a node that receives the voltage Qb(n - 1) applied to the (n - 1)th Qb node nQb(n - 1) from the (n - 1)th signal transmission unit ST(n - 1), a first electrode connected to a node to which a second high potential voltage GVDD1 is applied, and a second electrode connected to the I node nI. The 4B2 transistor T4B2 may include a gate electrode connected to a node that receives the voltage Qb(n - 1) applied to the (n - 1)th Qb node nQb(n - 1) from the (n - 1)th signal transmission unit ST(n - 1), a first electrode connected to the second electrode of the 4B1 transistor T4B1, and a second electrode connected to the I node nI.

[0260] The Qb node discharge unit may include a 5A transistor T5A and a 5B transistor T5B. The 5A transistor T5A and the 5B transistor T5B may be connected in series.

[0261] When the voltage at the Q node nQ and the voltage of the previous carry signal C(n - 1) input from the (n - 1)th signal transmission unit ST(n - 1) are high voltages that are higher than or equal to the gate high voltage VGH, the Qb node discharge unit may be turned on to discharge the Qb node nQb(n).

[0262] When the voltage at the Qh node nQh is a high voltage that is higher than or equal to the gate conduction voltage VGH, the 5A transistor T5A may be turned on to connect the I node nI to the Qb node nQb(n). The 5A transistor T5A may include a gate electrode connected to the Qh node nQh, a first electrode connected to the I node nI, and a second electrode connected to the Qb node nQb(n).

[0263] When the voltage at the Qh node nQh is a high voltage that is higher than or equal to the gate conduction voltage VGH, the 5B transistor T5B may be turned on to connect the Qb node nQb(n) to the second low potential voltage GVSS1. The voltage at the Qb node nQb(n) may be discharged to the second low potential voltage GVSS1. The 5B transistor T5B may include a gate electrode connected to the Qh node nQh, a first electrode connected to the Qb node nQb(n), and a second electrode connected to the node to which the second low potential voltage GVSS1 is applied.

[0264] The third circuit unit 73 may include a 3 - 1 circuit unit 731, a 3 - 2 circuit unit 732, and a 3 - 3 circuit unit 733.

[0265] The 3-1 circuit unit 731 and the 3-2 circuit unit 732 can output a gate signal GOUT(n) and a carry signal C(n) in response to the potentials of the Q node nQ and the Qb node nQb(n).

[0266] The 3-1 circuit unit 731 can include first buffer transistors T6 and T7 that output the carry signal C(n).

[0267] The first buffer transistors T6 and T7 can include a first pull-up transistor T6 that conducts based on the potential of the Q node nQ and a first pull-down transistor T7 that conducts based on the potential of the Qb node nQb(n). The first pull-up transistor T6 can be the sixth transistor T6. The first pull-down transistor T7 can be the seventh transistor T7.

[0268] The first pull-up transistor T6 can include a gate electrode connected to the Q node nQ, a first electrode connected to a node to which a second high potential voltage GVDD1 is applied, and a second electrode connected to a first output terminal O1 that outputs the carry signal C(n).

[0269] The first pull-down transistor T7 can include a gate electrode connected to the Qb node nQb(n), a first electrode connected to a node to which a second high potential voltage GVDD1 is applied, and a second electrode connected to a node to which a second low potential voltage GVSS1 is supplied.

[0270] The first buffer transistors T6 and T7 can output the carry signal C(n) based on the second high potential voltage GVDD1 applied through a node to which the second high potential voltage GVDD1 is applied and the second low potential voltage GVSS1 applied through a node to which the second low potential voltage GVSS1 is applied.

[0271] The 3-2 circuit unit 732 can include second buffer transistors T8 and T9 that output the gate signal GOUT(n).

[0272] The second buffer transistors T8 and T9 can include a second pull-up transistor T8 that conducts based on the potential of the Q node nQ and a second pull-down transistor T9 that conducts based on the potential of the Qb node nQb(n). The second pull-up transistor T8 can be the eighth transistor T8. The second pull-down transistor T9 can be the ninth transistor T9.

[0273] By using the tenth transistor T10, the first pull-up transistor T6 can be held at the gate-on voltage VGH, and the second pull-up transistor T8 can be held at the gate-off voltage VGL.

[0274] The second pull-up transistor T8 may include a gate electrode connected to one end of the fourth capacitor C4, a first electrode connected to the node to which the first high potential voltage GVDD0 is applied, and a second electrode connected to the second output terminal O2 of the output gate signal GOUT(n).

[0275] The second pull-down transistor T9 may include a gate electrode connected to the Qb node nQb(n), a first electrode connected to the second output terminal O2 of the output gate signal GOUT(n) and the other end of the fourth capacitor C4, and a second electrode connected to the node to which the first low potential voltage GVSS0 is applied.

[0276] The second buffer transistors T8 and T9 may output the gate signal GOUT(n) based on the first high potential voltage GVDD0 applied to the node to which the first high potential voltage GVDD0 is applied and the first low potential voltage GVSS0 applied to the node to which the first low potential voltage GVSS0 is applied.

[0277] The 3-3 circuit unit 733 may include a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The 3-3 circuit unit 733 may stably control the switching between the input / output waveform for displaying time and the input / output waveform for sensing time for external compensation.

[0278] The tenth transistor T10 may be disposed between the sixth transistor T6 and the eighth transistor T8 to separate the Q node nQ that shares the gate electrodes of the sixth transistor T6 and the eighth transistor T8. The tenth transistor T10 may be disposed between the sixth transistor T6 and the eighth transistor T8 to separate the electrical connection between the sixth transistor T6 and the eighth transistor T8 in response to the control signal CTRL(n). By arranging the tenth transistor T10, the sixth transistor T6 may operate based on the potential of the Q node nQ, and the eighth transistor T8 may operate based on the potential of a separate separated node. When the eleventh transistor T11 is turned on in a state where the tenth transistor T10 does not exist, the potential of the Q node nQ connected to the sixth transistor T6 and the eighth transistor T8 through the second low potential voltage GVSS1 may be the gate low voltage VGL. In this case, the carry signal C(n) output from the first output terminal O1 may be in a floating state. Therefore, the next signal transmission unit (e.g., ST(n + 1)) may operate abnormally.

[0279] The tenth transistor T10 may include a gate electrode connected to a control signal input terminal CI to which a control signal CTRL(n) (CTRLO(n) / CTRLE(n) / CTRLO(n + 1) / CTRLE(n + 1)) is input, a first electrode connected to the Q node nQ, and a second electrode connected to one end of the fourth capacitor C4 and the gate electrode of the second pull-up transistor T8.

[0280] The eleventh transistor T11 may be disposed between the sixth transistor T6 and the eighth transistor T8 to isolate the Q node nQ that shares the gate electrodes of the sixth transistor T6 and the eighth transistor T8. The eleventh transistor T11 may be configured to supply the second low potential voltage GVSS1 to the gate electrode of the eighth transistor T8 in response to a control bar signal CTRLB(n) to turn off the eighth transistor T8. The eleventh transistor T11 may be disposed between the tenth transistor T10 and the eighth transistor T8 to supply the second low potential voltage GVSS1 to the eighth transistor T8. The eleventh transistor T11 may enable the eighth transistor T8 to be turned off, thereby preventing a short circuit caused by simultaneously applying the first high potential voltage GVDD0 and the first low potential voltage GVSS0 to the second output terminal O2 in a state where the twelfth transistor T12 is already turned on.

[0281] The eleventh transistor T11 may include a gate electrode connected to a control signal input terminal CBI1 to which a control bar signal CTRLB(n) (CTRLBO(n) / CTRLBE(n) / CTRLBO(n + 1) / CTRLBE(n + 1)) is input, a first electrode connected to one end of the fourth capacitor C4 and the gate electrode of the second pull-up transistor T8, and a second electrode connected to a node to which the second low potential voltage GVSS0 is applied.

[0282] The problems in the case where neither the tenth transistor T10 nor the eleventh transistor T11 exists and only the twelfth transistor T12 is provided will be described. The eighth transistor T8 can be turned on by applying a gate conduction voltage VGH to the gate of the Q node nQ. The gate signal GOUT(n) output from the second output terminal O2 can be the first high potential voltage GVDD0. Since neither the tenth transistor T10 nor the eleventh transistor T11 exists, the eighth transistor T8 may not be turned off, and in this state, when the twelfth transistor T12 is turned on, the first low potential voltage GVSS0 and the first high potential voltage GVDD0 can be applied to the second output terminal O2 simultaneously, resulting in a short circuit. The tenth transistor T10 and the eleventh transistor T11 can be used to separate the Q node nQ that shares the gate electrodes of the sixth transistor T6 and the eighth transistor T8 to turn off the eighth transistor T8. The tenth transistor T10 and the eleventh transistor T11 can stably hold the gate signal GOUT(n) output from the second output terminal O2 at the gate cut-off voltage VGL.

[0283] When the twelfth transistor T12 does not exist while the Qb node nQb(n) is held at the gate low voltage VGL, even when the eighth transistor T8 is turned off by the tenth transistor T10 and the eleventh transistor T11, the ninth transistor T9 can be turned off by the Qb node nQb(n) having the gate low voltage VGL. In this case, the gate signal GOUT(n) can be held at the gate conduction voltage VGH by floating. The gate signal GOUT(n) may become an unknown state due to coupling and operate abnormally. The twelfth transistor T12 can be used to stably supply the first low potential voltage GVSS0 to the second output terminal O2 in response to the control bar signal CTRLB(n) in the state where the eighth transistor T8 has been turned off. The twelfth transistor T12 can enable the gate signal GOUT(n) at the gate cut-off voltage VGL to be output from the second output terminal O2 in the state where the eighth transistor T8 has been turned off.

[0284] The twelfth transistor T12 can include a gate electrode connected to the second control bar signal input terminal CBI2 to which the control bar signal CTRLB(n) (CTRLBO(n) / CTRLBE(n) / CTRLBO(n + 1) / CTRLBE(n + 1)) is input, a first electrode connected to the second output terminal O2 for outputting the gate signal GOUT(n) and the other end of the fourth capacitor C4, and a second electrode connected to the node to which the first low potential voltage GVSS0 is applied.

[0285] Figure 19 is a view showing Figure 18 the operating state of the signal transmission unit corresponding to the DA section to the DC section of Figures 20A to 20F is a view showingFigure 18 Circuit diagram of the operating states of the signal transmission units corresponding to the DA section to the DC section.

[0286] Although the following description will assume that the nth signal transmission unit ST(n) is an odd signal transmission unit and the (n + 1)th signal transmission unit ST(n + 1) is an even signal transmission unit, the present disclosure is not limited thereto. When n is 1, C(n - 1) can be a VST signal, and Qb(n - 1) can be a QbST signal.

[0287] Figure 20A 、 Figure 20C and Figure 20E shows the operating state of the nth signal transmission unit. The carry signal C(n - 1) applied from the previous signal transmission unit, the Qb signal Qb(n - 1) applied from the Qb node in the previous signal transmission unit, and the CLK signals CLK and CLK1 can be input to the nth signal transmission unit ST(n). Both the odd control signal CTRLO and the odd control bar signal CTRLBO can be input to the nth signal transmission unit ST(n).

[0288] Figure 20B 、 Figure 20D and Figure 20F shows the operating state of the (n + 1)th signal transmission unit. The carry signal C(n) applied from the previous signal transmission unit, the Qb signal Qb(n) applied from the Qb node in the previous signal transmission unit, and the CLK signals CLK and CLK2 can be input to the (n + 1)th signal transmission unit ST(n + 1). Both the odd control signal CTRLE and the odd control bar signal CTRLBE can be input to the (n + 1)th signal transmission unit ST(n + 1).

[0289] For the display time, the control signals CTRLO(n) and CTRLE(n + 1) can be the gate-on voltage VGH. The tenth transistor T10 can be in the on state.

[0290] For the display time, the control bar signals CTRLBO(n) and CTRLBE(n + 1) can be the gate-off voltage VGL. The eleventh transistor T11 and the twelfth transistor T12 can be in the off state.

[0291] Referring to Figure 18 、 Figure 19 and Figure 20A , the carry signal C(n - 1) input to the nth signal transmission unit ST(n) in the DA section can be the gate-off voltage VGL, the Qb signal Qb(n - 1) can be the gate-on voltage VGH, and the CLK signals CLK and CLK1 can be the gate-on voltage VGH.

[0292] The first transistor T1 and the second transistor T2 may be in an on state. The third transistor T3 may be in an off state. The 4B transistors T4B1 and T4B2 may be in an on state.

[0293] The potential of the Qh node nQh may be the gate cut-off voltage VGL. The fifth transistors T5A and T5B may be in an off state.

[0294] The potential of the I node nI may be the second high potential voltage GVDD1. The 4A transistors T4A1 and T4A2 may be in an on state.

[0295] The potential of the Q node nQ may be the gate cut-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 may be in an off state.

[0296] The potential of the Qb node nQb(n) may be the second high potential voltage GVDD1. The seventh transistor T7 and the ninth transistor T9 may be in an on state.

[0297] The carry signal C(n) at the second low potential voltage GVSS1 may be output from the first output terminal. The carry signal C(n) at the gate cut-off voltage VGL may be output from the first output terminal.

[0298] The gate signal GOUT(n) at the first low potential voltage GVSS0 may be output from the second output terminal. The gate signal GOUT(n) at the gate cut-off voltage VGL may be output from the second output terminal.

[0299] Refer to Figure 18 、 Figure 19 and Figure 20B and, the carry signal C(n) input to the (n + 1)-th signal transmission unit ST(n + 1) in the DA section may be the gate cut-off voltage VGL, the Qb signal Qb(n) may be the gate on voltage VGH, and the CLK signals CLK and CLK2 may be the gate on voltage VGH.

[0300] The first transistor T1 and the second transistor T2 may be in an on state. The third transistor T3 may be in an off state. The 4B transistors T4B1 and T4B2 may be in an on state.

[0301] The potential of the Qh node nQh may be the gate cut-off voltage VGL. The fifth transistors T5A and T5B may be in an off state.

[0302] The potential of the I node nI may be the second high potential voltage GVDD1. The 4A transistors T4A1 and T4A2 may be in an on state.

[0303] The potential of the Q node nQ can be the gate cut-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 can be in the cut-off state.

[0304] The potential of the Qb node nQb(n + 1) can be the second highest potential voltage GVDD1. The seventh transistor T7 and the ninth transistor T9 can be in the conducting state.

[0305] The carry signal C(n + 1) with the second lowest potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n + 1) with the gate cut-off voltage VGL can be output from the first output terminal.

[0306] The gate signal GOUT(n + 1) with the first lowest potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n + 1) with the gate cut-off voltage VGL can be output from the second output terminal.

[0307] Refer to Figure 18 、 Figure 19 and Figure 20C , The carry signal C(n - 1) input to the nth signal transmission unit ST(n) in the DB section can be the gate conduction voltage VGH, the Qb signal Qb(n - 1) can be the gate cut-off voltage VGL, and the CLK signals CLK and CLK1 can be the gate conduction voltage VGH.

[0308] The first transistor T1 and the second transistor T2 can be in the conducting state. The third transistor T3 can be in the conducting state. The 4B transistors T4B1 and T4B2 can be in the cut-off state.

[0309] The potential of the Qh node nQh can be the gate conduction voltage VGH. The fifth transistors T5A and T5B can be in the conducting state.

[0310] The potential of the I node nI can be the second lowest potential voltage GVSS1. The 4A transistors T4A1 and T4A2 can be in the cut-off state.

[0311] The potential of the Q node nQ can be the gate conduction voltage VGH. The potential of the Q node nQ can be the gate conduction voltage VGH + αV. The sixth transistor T6 and the eighth transistor T8 can be in the conducting state.

[0312] The potential of the Qb node nQb(n) can be the second lowest potential voltage GVSS1. The potential of the Qb node nQb(n) can be the gate cut-off voltage VGL. The seventh transistor T7 and the ninth transistor T9 can be in the cut-off state.

[0313] The carry signal C(n) with the second high potential voltage GVDD1 can be output from the first output terminal. The carry signal C(n) with the gate conduction voltage VGH can be output from the first output terminal.

[0314] The gate signal GOUT(n) with the first high potential voltage GVDD0 can be output from the second output terminal. The gate signal GOUT(n) with the gate conduction voltage VGH can be output from the second output terminal.

[0315] Refer to Figure 18 、 Figure 19 and Figure 20D and, the carry signal C(n) input to the (n + 1)-th signal transmission unit ST(n + 1) in the DB section can be the gate conduction voltage VGH, the Qb signal Qb(n) can be the gate cut-off voltage VGL, and the CLK signals CLK and CLK2 can be the gate conduction voltage VGH.

[0316] The first transistor T1 and the second transistor T2 can be in the on state. The third transistor T3 can be in the on state. The 4B transistors T4B1 and T4B2 can be in the off state.

[0317] The potential of the Qh node nQh can be the gate conduction voltage VGH. The fifth transistors T5A and T5B can be in the on state.

[0318] The potential of the I node nI can be the second low potential voltage GVSS1. The 4A transistors T4A1 and T4A2 can be in the off state.

[0319] The potential of the Q node nQ can be the gate conduction voltage VGH. The sixth transistor T6 and the eighth transistor T8 can be in the on state.

[0320] The potential of the Qb node nQb(n + 1) can be the second low potential voltage GVSS1. The seventh transistor T7 and the ninth transistor T9 can be in the off state.

[0321] The carry signal C(n + 1) with the second high potential voltage GVDD1 can be output from the first output terminal. The carry signal C(n + 1) with the gate conduction voltage VGH can be output from the first output terminal.

[0322] The gate signal GOUT(n + 1) with the first high potential voltage GVDD0 can be output from the second output terminal. The gate signal GOUT(n + 1) with the gate conduction voltage VGH can be output from the second output terminal.

[0323] Refer to Figure 18 、 Figure 19 and Figure 20E, the carry signal C(n - 1) input to the n-th signal transmission unit ST(n) in the DC section can be the gate cut-off voltage VGL, the Qb signal Qb(n - 1) can be the gate conduction voltage VGH, and the CLK signals CLK and CLK1 can be the gate conduction voltage VGH.

[0324] The first transistor T1 and the second transistor T2 can be in the on state. The third transistor T3 can be in the off state. The 4B transistors T4B1 and T4B2 can be in the on state.

[0325] The potential of the Qh node nQh can be the gate cut-off voltage VGL. The fifth transistors T5A and T5B can be in the off state.

[0326] The potential of the I node nI can be the second high potential voltage GVDD1. The 4A transistors T4A1 and T4A2 can be in the on state.

[0327] The potential of the Q node nQ can be the gate cut-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 can be in the off state.

[0328] The potential of the Qb node nQb(n) can be the second high potential voltage GVDD1. The potential of the Qb node nQb(n) can be the gate conduction voltage VGH. The seventh transistor T7 and the ninth transistor T9 can be in the on state.

[0329] The carry signal C(n) having the second low potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n) having the gate cut-off voltage VGL can be output from the first output terminal.

[0330] The gate signal GOUT(n) having the first low potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n) having the gate cut-off voltage VGL can be output from the second output terminal.

[0331] Refer to Figure 18 、 Figure 19 and Figure 20F , the carry signal C(n) input to the (n + 1)-th signal transmission unit ST(n + 1) in the DC section can be the gate cut-off voltage VGL, the Qb signal Qb(n) can be the gate conduction voltage VGH, and the CLK signals CLK and CLK2 can be the gate cut-off voltage VGL.

[0332] The first transistor T1 and the second transistor T2 can be in the off state. The third transistor T3 can be in the off state. The 4B transistors T4B1 and T4B2 can be in the on state.

[0333] The potential of the Qh node nQh can be the gate cut-off voltage VGL. The fifth transistors T5A and T5B can be in the cut-off state.

[0334] The potential of the I node nI can be the second highest potential voltage GVDD1. The 4A transistors T4A1 and T4A2 can be in the conducting state.

[0335] The potential of the Q node nQ can be the gate conducting voltage VGH. The sixth transistor T6 and the eighth transistor T8 can be in the conducting state.

[0336] The potential of the Qb node nQb(n + 1) can be the second highest potential voltage GVDD1. The seventh transistor T7 and the ninth transistor T9 can be in the conducting state.

[0337] The carry signal C(n + 1) having the second lowest potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n + 1) having the gate cut-off voltage VGL can be output from the first output terminal.

[0338] The gate signal GOUT(n + 1) having the first lowest potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n + 1) having the gate cut-off voltage VGL can be output from the second output terminal.

[0339] Figure 21 is a waveform diagram showing the input / output waveforms during the sensing time period for external compensation in a gate driver according to an embodiment of the present specification. Figure 22 is a view showing Figure 21 the operating state of the signal transmission unit corresponding to the SA section to the SC section of Figures 23A to 23F is a view showing Figure 21 the circuit diagram of the signal transmission unit corresponding to the SA section to the SC section of

[0340] Although the following description will assume that the nth signal transmission unit ST(n) is an odd signal transmission unit and the (n + 1)th signal transmission unit ST(n + 1) is an even signal transmission unit, the present disclosure is not limited thereto. When n is 1, C(n - 1) can be the VST signal, and Qb(n - 1) can be the QbST signal.

[0341] Figure 23A 、 Figure 23C and Figure 23EThe operation state of the nth signal transmission unit is shown. The carry signal C(n-1) applied from the previous signal transmission unit, the Qb signal Qb(n-1) applied from the Qb node in the previous signal transmission unit, and the CLK signals CLK and CLK1 may be input to the nth signal transmission unit ST(n). Both the odd control signal CTRLO and the odd control bar signal CTRLBO may be input to the nth signal transmission unit ST(n).

[0342] Figure 23B , Figure 23D and Figure 23F The operation state of the (n+1)th signal transmission unit is shown. The carry signal C(n) applied from the previous signal transmission unit, the Qb signal Qb(n) applied from the Qb node in the previous signal transmission unit, and the CLK signals CLK and CLK2 may be input to the (n+1)th signal transmission unit ST(n+1). Both the odd control signal CTRLE and the odd control bar signal CTRLBE may be input to the (n+1)th signal transmission unit ST(n+1).

[0343] Reference Figure 21 , Figure 22 and Figure 23A , the carry signal C(n-1) input to the nth signal transmission unit ST(n) in the SA segment may be the gate-off voltage VGL, the Qb signal Qb(n-1) may be the gate-on voltage VGH, and the CLK signals CLK and CLK1 may be the gate-on voltage VGH.

[0344] The first transistor T1 and the second transistor T2 may be in an on state. The third transistor T3 may be in an off state. The 4B transistors T4B1 and T4B2 may be in an on state.

[0345] The potential of the Qh node nQh may be the gate-off voltage VGL. The fifth transistors T5A and T5B may be in a turned-off state.

[0346] The potential of the I node nI may be the second high potential voltage GVDD1. The 4A-th transistors T4A1 and T4A2 may be in a turned-on state.

[0347] The potential of the Q node nQ may be the gate-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 may be in a turned-off state.

[0348] The potential of the Qb node nQb(n) may be the second high potential voltage GVDD1. The seventh transistor T7 and the ninth transistor T9 may be in a turned-on state.

[0349] The carry signal C(n) with the second lowest potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n) with the gate cut-off voltage VGL can be output from the first output terminal.

[0350] The control signal CTRLO(n) input to the nth signal transmission unit ST(n) can be held at the gate conduction voltage VGH. The tenth transistor T10 can be in the on state.

[0351] The control bar signal CTRLBO(n) can be the gate cut-off voltage VGL. The eleventh transistor T11 and the twelfth transistor T12 can be in the off state.

[0352] The gate signal GOUT(n) with the first low potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n) with the gate cut-off voltage VGL can be output from the second output terminal.

[0353] Refer to Figure 21 、 Figure 22 and Figure 23B , the carry signal C(n) input to the (n + 1)th signal transmission unit ST(n + 1) in the SA section can be the gate cut-off voltage VGL, the Qb signal Qb(n) can be the gate conduction voltage VGH, and the CLK signals CLK and CLK2 can be the gate conduction voltage VGH.

[0354] The first transistor T1 and the second transistor T2 can be in the on state. The third transistor T3 can be in the off state. The 4B transistors T4B1 and T4B2 can be in the on state.

[0355] The potential of the Qh node nQh can be the gate cut-off voltage VGL. The fifth transistors T5A and T5B can be in the off state.

[0356] The potential of the I node nI can be the second highest potential voltage GVDD1. The 4A transistors T4A1 and T4A2 can be in the on state.

[0357] The potential of the Q node nQ can be the gate cut-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 can be in the off state.

[0358] The potential of the Qb node nQb(n + 1) can be the second highest potential voltage GVDD1. The seventh transistor T7 and the ninth transistor T9 can be in the on state.

[0359] The carry signal C(n + 1) with the second lowest potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n + 1) with the gate cut-off voltage VGL can be output from the first output terminal.

[0360] The control signal CTRLO(n) input to the n-th signal transmission unit ST(n) can be maintained at the gate-on voltage VGH. The tenth transistor T10 can be in the on state.

[0361] The control bar signal CTRLBO(n) can be the gate-off voltage VGL. The eleventh transistor T11 and the twelfth transistor T12 can be in the off state.

[0362] The gate signal GOUT(n + 1) having the first low potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n + 1) having the gate-off voltage VGL can be output from the second output terminal.

[0363] Refer to Figure 21 、 Figure 22 and Figure 23C and, the carry signal C(n - 1) input to the n-th signal transmission unit ST(n) in the SB section can be the gate-on voltage VGH, the Qb signal Qb(n - 1) can be the gate-off voltage VGL, and the CLK signals CLK and CLK1 can be the gate-on voltage VGH.

[0364] The first transistor T1 and the second transistor T2 can be in the on state. The third transistor T3 can be in the on state. The 4B transistors T4B1 and T4B2 can be in the off state.

[0365] The potential of the Qh node nQh can be the gate-on voltage VGH. The fifth transistors T5A and T5B can be in the on state.

[0366] The potential of the I node nI can be the second low potential voltage GVSS1. The 4A transistors T4A1 and T4A2 can be in the off state.

[0367] The potential of the Q node nQ can be the gate-on voltage VGH + αV. The sixth transistor T6 can be in the on state. The eighth transistor T8 can initially be in the on state.

[0368] The potential of the Qb node nQb(n) can be the second low potential voltage GVSS1. The potential of the Qb node nQb(n) can be the gate-off voltage VGL. The seventh transistor T7 can be in the off state. The ninth transistor T9 can initially be in the off state.

[0369] The carry signal C(n) having the second high potential voltage GVDD1 can be output from the first output terminal. The carry signal C(n) having the gate-on voltage VGH can be output from the first output terminal.

[0370] The control signal CTRLO(n) input to the n-th signal transmission unit ST(n) may initially be the gate-on voltage VGH. The state of the control signal CTRLO(n) may change from the gate-on voltage VGH to the gate-off voltage VGL. The tenth transistor T10 may initially be in the on state. The tenth transistor T10 may change from the on state to the off state.

[0371] The tenth transistor T10 may be disposed between the sixth transistor T6 and the eighth transistor T8 to isolate the Q node nQ that shares the gate electrodes of the sixth transistor T6 and the eighth transistor T8. Since the carry signal C(n) output from the first output terminal becomes a floating state, the tenth transistor T10 may prevent the next signal transmission unit (e.g., ST(n+1)) from operating abnormally.

[0372] The control bar signal CTRLBO(n) may initially be the gate-off voltage VGL. The state of the control bar signal CTRLBO(n) may change from the initial gate-off voltage VGL to the gate-on voltage VGH. When the state of the control signal CTRLBO(n) changes from the gate-off voltage VGL to the gate-on voltage VGH, the state of the control bar signal CTRLBO(n) may change from the gate-off voltage VGL to the gate-on voltage VGH. The eleventh transistor T11 and the twelfth transistor T12 may initially be in the off state. The states of the eleventh transistor T11 and the twelfth transistor T12 may change from the off state to the on state.

[0373] The state of the eighth transistor T8 may change from the on state to the off state. The on-off relationship between the sixth transistor and the eighth transistor T8 may be reversed.

[0374] The state of the ninth transistor T9 may change from the off state to the on state.

[0375] The eleventh transistor T11 may be used to supply the second low potential voltage GVSS1 to the gate electrode of the eighth transistor T8 to turn off the eighth transistor T8. The eleventh transistor T11 may turn off the eighth transistor T8 in response to the control bar signal CTRLB(n), thereby preventing a short circuit caused by simultaneously applying the first high potential voltage GVDD0 and the first low potential voltage GVSS0 to the second output terminal while the twelfth transistor T12 is in the on state.

[0376] The twelfth transistor T12 may be used to stably supply the first low potential voltage GVSS0 to the second output terminal in a state where the eighth transistor T8 is already off. The twelfth transistor T12 may enable the gate signal GOUT(n) having the gate-off voltage VGL to be output from the second output terminal in a state where the eighth transistor T8 is already off.

[0377] A gate signal GOUT(n) having a gate conduction voltage VGH can be output from the second output terminal. The state of the control signal GOUT(n) can be changed from the gate conduction voltage VGH to a gate cut-off voltage VGL.

[0378] Referring to Figure 21 、 Figure 22 and Figure 23D , the carry signal C(n) input to the (n + 1)-th signal transmission unit ST(n + 1) in the DB section can be the gate conduction voltage VGH, the Qb signal Qb(n) can be the gate cut-off voltage VGL, and the CLK signals CLK and CLK2 can be the gate conduction voltage VGH.

[0379] The first transistor T1 and the second transistor T2 can be in an on state. The third transistor T3 can be in an on state. The 4B transistors T4B1 and T4B2 can be in an off state.

[0380] The potential of the Qh node nQh can be the gate conduction voltage VGH. The fifth transistors T5A and T5B can be in an on state.

[0381] The potential of the I node nI can be the second low potential voltage GVSS1. The 4A transistors T4A1 and T4A2 can be in an off state.

[0382] The potential of the Q node nQ can be the gate conduction voltage VGH. The sixth transistor T6 and the eighth transistor T8 can be in an on state.

[0383] The potential of the Qb node nQb(n + 1) can be the second low potential voltage GVSS1. The seventh transistor T7 and the ninth transistor T9 can be in an off state.

[0384] A carry signal C(n + 1) having a second high potential voltage GVDD1 can be output from the first output terminal. A carry signal C(n + 1) having a gate conduction voltage VGH can be output from the first output terminal.

[0385] The control signal CTRLE(n + 1) input to the (n + 1)-th signal transmission unit ST(n + 1) can be the gate conduction voltage VGH. The tenth transistor T10 can be in an on state.

[0386] The control bar signal CTRLBE(n + 1) can be the gate cut-off voltage VGL. The eleventh transistor T11 and the twelfth transistor T12 can be in an off state.

[0387] A gate signal GOUT(n + 1) having a first high potential voltage GVDD0 can be output from the second output terminal. A gate signal GOUT(n + 1) having a gate conduction voltage VGH can be output from the second output terminal. When the state of the gate signal GOUT(n) output from the second output terminal changes from the gate conduction voltage VGH to the gate cut-off voltage VGL, a gate signal GOUT(n + 1) having the gate conduction voltage VGH can be output from the second output terminal.

[0388] Refer to Figure 21 、 Figure 22 and Figure 23E , the carry signal C(n - 1) input to the nth signal transmission unit ST(n) in the SC section can be the gate cut-off voltage VGL, the Qb signal Qb(n - 1) can be the gate conduction voltage VGH, and the CLK signals CLK and CLK1 can be the gate conduction voltage VGH.

[0389] The first transistor T1 and the second transistor T2 can be in the on state. The third transistor T3 can be in the off state. The 4B transistors T4B1 and T4B2 can be in the on state.

[0390] The potential of the Qh node nQh can be the gate cut-off voltage VGL. The fifth transistors T5A and T5B can be in the off state.

[0391] The potential of the I node nI can be the second high potential voltage GVDD1. The 4A transistors T4A1 and T4A2 can be in the on state.

[0392] The potential of the Q node nQ can be the gate cut-off voltage VGL. The sixth transistor T6 and the eighth transistor T8 can be in the off state.

[0393] The potential of the Qb node nQb(n) can be the second high potential voltage GVDD1. The potential of the Qb node nQb(n) can be the gate conduction voltage VGH. The seventh transistor T7 and the ninth transistor T9 can be in the on state.

[0394] A carry signal C(n) having a second low potential voltage GVSS1 can be output from the first output terminal. A carry signal C(n) having a gate cut-off voltage VGL can be output from the first output terminal.

[0395] The control signal CTRLO(n) input to the nth signal transmission unit ST(n) can be held at the gate conduction voltage VGH. The tenth transistor T10 can be in the on state.

[0396] The control bar signal CTRLBO(n) can be the gate cut-off voltage VGL. The eleventh transistor T11 and the twelfth transistor T12 can be in the cut-off state.

[0397] The gate signal GOUT(n) having the first low potential voltage GVSS0 can be output from the second output terminal. The gate signal GOUT(n) having the gate cut-off voltage VGL can be output from the second output terminal.

[0398] Refer to Figure 21 、 Figure 22 and Figure 23F and, the carry signal C(n) input to the (n + 1)-th signal transmission unit ST(n + 1) in the DC section can be the gate conduction voltage VGH, the Qb signal Qb(n) can be the gate cut-off voltage VGL, and the CLK signals CLK and CLK2 can be the gate conduction voltage VGH.

[0399] The first transistor T1 and the second transistor T2 can be in the conducting state. The third transistor T3 can be in the conducting state. The 4B transistors T4B1 and T4B2 can be in the cut-off state.

[0400] The potential of the Qh node nQh can be the gate conduction voltage VGH. The fifth transistors T5A and T5B can be in the conducting state.

[0401] The potential of the I node nI can be the second low potential voltage GVSS1. The 4A transistors T4A1 and T4A2 can be in the cut-off state.

[0402] The potential of the Q node nQ can be the gate conduction voltage VGH. The sixth transistor T6 can be in the conducting state. The eighth transistor T8 can initially be in the conducting state.

[0403] The potential of the Qb node nQb(n + 1) can be the second low potential voltage GVSS1. The seventh transistor T7 can be in the cut-off state. The ninth transistor T9 can initially be in the cut-off state.

[0404] The carry signal C(n + 1) having the second low potential voltage GVSS1 can be output from the first output terminal. The carry signal C(n + 1) having the gate cut-off voltage VGL can be output from the first output terminal.

[0405] The control signal CTRLE(n + 1) input to the (n + 1)-th signal transmission unit ST(n + 1) can initially be the gate conduction voltage VGH. The state of the control signal CTRLO(n) can change from the gate conduction voltage VGH to the gate cut-off voltage VGL. The tenth transistor T10 can initially be in the conducting state. The tenth transistor T10 can change from the conducting state to the cut-off state.

[0406] The tenth transistor T10 may be disposed between the sixth transistor T6 and the eighth transistor T8 to separate the Q node nQ that shares the gate electrodes of the sixth transistor T6 and the eighth transistor T8. Since the carry signal C(n) output from the first output terminal becomes a floating state, the tenth transistor T10 can prevent the next signal transmission unit (e.g., ST(n+1)) from operating abnormally.

[0407] The control bar signal CTRLBO(n) may initially be the gate cutoff voltage VGL. The state of the control bar signal CTRLBO(n) may change from the initial gate cutoff voltage VGL to the gate conduction voltage VGH. When the state of the control signal CTRLBO(n) changes from the gate cutoff voltage VGL to the gate conduction voltage VGH, the state of the control bar signal CTRLBO(n) may change from the gate cutoff voltage VGL to the gate conduction voltage VGH. The eleventh transistor T11 and the twelfth transistor T12 may initially be in the cutoff state. The states of the eleventh transistor T11 and the twelfth transistor T12 may change from the cutoff state to the conduction state.

[0408] The state of the eighth transistor T8 may change from the conduction state to the cutoff state. The on-off relationship between the sixth transistor and the eighth transistor T8 may be inverted.

[0409] The state of the ninth transistor T9 may change from the cutoff state to the conduction state.

[0410] The eleventh transistor T11 may be used to supply the second low potential voltage GVSS1 to the gate electrode of the eighth transistor T8 to cutoff the eighth transistor T8. The eleventh transistor T11 may cutoff the eighth transistor T8, thereby preventing a short circuit caused by simultaneously applying the first high potential voltage GVDD0 and the first low potential voltage GVSS0 to the second output terminal while the twelfth transistor T12 is in the conduction state.

[0411] The twelfth transistor T12 may be used to stably supply the first low potential voltage GVSS0 to the second output terminal in a state where the eighth transistor T8 has been cutoff. The twelfth transistor T12 may enable the gate signal GOUT(n) having the gate cutoff voltage VGL to be output from the second output terminal in a state where the eighth transistor T8 has been cutoff.

[0412] The gate signal GOUT(n+1) having the gate conduction voltage VGH may initially be output from the second output terminal. The state of the control signal GOUT(n+1) may change from the gate conduction voltage VGH to the gate cutoff voltage VGL.

[0413] Figure 24is a waveform diagram showing the voltage levels of signals input to the Figure 13 switching element shown during the sensing time for external compensation of a display device according to an embodiment of the present specification. Figure 25 is a circuit diagram showing the operating state of a pixel circuit during the sensing time for external compensation of a display device according to an embodiment of the present specification.

[0414] Referring to Figure 24 and Figure 25 , for the threshold voltage (Vth) sensing time of the driving element DT for external compensation of a display device according to an embodiment of the present disclosure, the second switching element M2 to which the second scan pulse SC2 is applied may be turned off, and the fourth switching element M4 and the fifth switching element M5 to which the first EM pulse EM1 and the second EM pulse EM2 are applied may be turned on.

[0415] According to this specification, in the DSL section, the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) can be maintained at the gate cut-off voltage VGL, and the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) can be maintained at the gate conduction voltage VGH. The section where the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate conduction voltage VGH and the section where the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) is maintained at the gate conduction voltage VGH may not overlap with each other. When the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate conduction voltage VGH, the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) can be maintained at the gate cut-off voltage VGL, and when the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate cut-off voltage VGL, the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) can be maintained at the gate conduction voltage VGH. When the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate conduction voltage VGH, the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) can be maintained at the gate cut-off voltage VGL, and when the third scan pulse SC3(n + 1) is maintained at the gate conduction voltage VGH, the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) can be maintained at the gate cut-off voltage VGL. When the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate cut-off voltage VGL, the third scan pulse SC3(n + 1) applied to the (n + 1)-th pixel row group PXLOE(n + 1) can be maintained at the gate cut-off voltage VGL, and when the third scan pulse SC3(n + 1) is maintained at the gate cut-off voltage VGL, the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) can be maintained at the gate conduction voltage VGH.

[0416] In the DSL section, at least a part of the section where the third scan pulse SC3(n) applied to the n-th pixel row group PXLOE(n) is maintained at the gate conduction voltage VGH and then maintained at the gate cut-off voltage VGL may overlap with the section where the third scan pulse SC3(n + 1) is maintained at the gate conduction voltage VGH.

[0417] According to this specification, when a third scan pulse SC3(n + 1) having a gate-on voltage VGH is input to an (n + 1)-th odd pixel row PXLO(n + 1) and an (n + 1)-th even pixel row PXLOE(n + 1) included in an (n + 1)-th pixel row group PXLOE(n + 1), a third scan pulse SC3(n) having a gate-off voltage VGL may be applied to an n-th pixel row group PXLOE(n).

[0418] Therefore, the sensing load of the corresponding sensing line can be reduced. For example, the capacitance of the sensing line can be reduced and the load can be reduced. Accordingly, the sensing time and the influence of noise can be reduced, and sensing errors can occur less frequently. In addition, the capacitance can be charged faster than in the related art during sensing, and more accurate sensing than in the related art can be achieved.

[0419] According to this specification, the sensing load of the sensing line can be reduced.

[0420] According to this specification, the capacitance or capacitive load of the sensing line can be reduced and the load can be reduced.

[0421] According to this specification, the sensing time and the influence of noise can be reduced, and sensing errors can occur less frequently. In addition, by reducing the capacitive load during sensing compared with the related art, the capacitance can be charged quickly, and more accurate sensing than in the related art can be achieved.

[0422] Through the above description, embodiments of the present disclosure provide the following technical solutions, but are not limited thereto.

[0423] Solution 1. A gate driver including a plurality of signal transmission units cascaded with each other and configured to receive a clock signal and sequentially output gate signals,

[0424] wherein at least one of the plurality of signal transmission units includes:

[0425] a first pull-up transistor turned on based on the potential of a Q node;

[0426] a second pull-up transistor turned on based on the potential of the Q node;

[0427] a first pull-down transistor turned on based on the potential of a Qb node;

[0428] a second pull-down transistor turned on based on the potential of the Qb node; and

[0429] a first A transistor disposed between the first pull-up transistor and the second pull-up transistor and configured to electrically isolate the Q node in response to a control signal.

[0430] 2. The gate driver according to Solution 1 further includes a B transistor, which is disposed between the first pull-up transistor and the second pull-up transistor and is configured to supply a second low potential voltage to the second pull-up transistor in response to a control bar signal.

[0431] 3. The gate driver according to Solution 2, wherein the B transistor is disposed between the A transistor and the second pull-up transistor.

[0432] 4. The gate driver according to Solution 3 further includes:

[0433] A first output terminal configured to output a carry signal according to the operations of the first pull-up transistor and the first pull-down transistor;

[0434] A second output terminal configured to output the gate signal according to the operations of the second pull-up transistor and the second pull-down transistor; and

[0435] A C transistor connected to the second output terminal to supply a first low potential voltage in response to the control bar signal.

[0436] 5. The gate driver according to Solution 4, wherein when the control signal has a gate-on voltage, the control bar signal has a gate-off voltage, and

[0437] when the control signal has a gate-off voltage, the control bar signal has a gate-on voltage.

[0438] 6. The gate driver according to Solution 5, wherein the gate electrode of the A transistor is connected to a control signal input terminal for inputting the control signal thereto,

[0439] the first electrode of the A transistor is connected to the Q node, and

[0440] the second electrode of the A transistor is connected to the gate electrode of the second pull-up transistor.

[0441] 7. The gate driver according to Solution 6, wherein the gate electrode of the B transistor is connected to a first control bar signal input terminal for inputting the control bar signal thereto,

[0442] the second low potential voltage is applied to the first electrode of the B transistor, and

[0443] the second electrode of the B transistor is connected to the gate electrode of the second pull-up transistor.

[0444] 8. The gate driver according to aspect 7, wherein a gate electrode of the C-th transistor is connected to a second control bar signal input terminal that inputs the control bar signal thereto.

[0445] The first low potential voltage is applied to a first electrode of the C-th transistor, and

[0446] a second electrode of the C-th transistor is connected to the second output terminal.

[0447] 9. The gate driver according to aspect 8, further comprising:

[0448] a first circuit unit configured to control charging / discharging of the Q node and the Qb node;

[0449] a second circuit unit including an inverter circuit configured to invert a potential of the Q node and apply the inverted potential to the Qb node; and

[0450] a third circuit unit including a 3-1 circuit unit having the first pull-up transistor and the first pull-down transistor, a 3-2 circuit unit having the second pull-up transistor and the second pull-down transistor, and a 3-3 circuit unit having the A-th transistor, the B-th transistor, and the C-th transistor.

[0451] 10. The gate driver according to aspect 9, wherein the first circuit unit includes:

[0452] a first transistor including a gate electrode to which the clock signal is input, a first electrode to which the carry signal is input, and a second electrode connected to the Qh node;

[0453] a second transistor connected in series with the first transistor and including a gate electrode to which the clock signal is input, a first electrode connected to the Qh node, and a second electrode connected to the Q node; and

[0454] a third transistor including a gate electrode connected to the Q node, a first electrode to which a second high potential voltage is applied, and a second electrode connected to the Qh node.

[0455] 11. The gate driver according to aspect 9, wherein the second circuit unit includes:

[0456] The 4A transistor, wherein the 4A transistor includes a gate electrode connected to the I node, a first electrode to which a second high potential voltage is applied, and a second electrode connected to the Qb node;

[0457] The 4B transistor, wherein the 4B transistor includes a gate electrode to which the Qb signal is input, a first electrode to which the second high potential voltage is applied, and a second electrode connected to the I node;

[0458] The 5A transistor, wherein the 5A transistor includes a gate electrode connected to the Qh node, a first electrode connected to the I node, and a second electrode connected to the Qb node; and

[0459] The 5B transistor, wherein the 5B transistor includes a gate electrode connected to the Qh node, a first electrode connected to the Qb node, and a second electrode to which the second low potential voltage is applied.

[0460] 12. The gate driver according to aspect 9, wherein the second circuit unit includes:

[0461] The 4A1 transistor, wherein the 4A1 transistor includes a gate electrode connected to the I node, a first electrode connected to a node to which the second high potential voltage is applied, and a second electrode;

[0462] The 4A2 transistor, wherein the 4A2 transistor is connected in series with the 4A1 transistor, and includes a gate electrode connected to the I node, a first electrode connected to the second electrode of the 4A1 transistor, and a second electrode connected to the Qb node;

[0463] The 4B1 transistor, wherein the 4B1 transistor includes a gate electrode to which the Qb signal is input, a first electrode to which the second high potential voltage is applied, and a second electrode; and

[0464] The 4B2 transistor, wherein the 4B2 transistor is connected in series with the 4B1 transistor, and includes a gate electrode to which the Qb signal is input, a first electrode connected to the second electrode of the 4B1 transistor, and a second electrode connected to the I node.

[0465] 13. The gate driver according to aspect 5, wherein when the control signal changes from the gate-on voltage to the gate-off voltage, the control bar signal changes from the gate-off voltage to the gate-on voltage.

[0466] 14. The gate driver according to Solution 5, wherein when the control signal changes from the gate-on voltage to the gate-off voltage, the on-off relationship between the first pull-up transistor and the second pull-up transistor is inverted.

[0467] 15. The gate driver according to Solution 5, wherein when the control signal changes from the gate-on voltage to the gate-off voltage, the gate signal changes from the gate-on voltage to the gate-off voltage.

[0468] 16. The gate driver according to Solution 4, wherein a carry signal output by one of the plurality of signal transmission units is set to a floating state to prevent abnormal operation of the next signal transmission unit of this signal transmission unit.

[0469] 17. A gate driver, which includes an nth signal transmission unit and an (n + 1)th signal transmission unit that are cascaded with each other and are configured to receive a clock signal and sequentially output gate signals, where n is a positive integer greater than or equal to 1,

[0470] wherein each of the nth signal transmission unit and the (n + 1)th signal transmission unit includes:

[0471] A first pull-up transistor that is turned on based on the potential of the Q node;

[0472] A second pull-up transistor that is turned on based on the potential of the Q node;

[0473] A first pull-down transistor that is turned on based on the potential of the Qb node;

[0474] A second pull-down transistor that is turned on based on the potential of the Qb node;

[0475] A first output terminal configured to output a carry signal according to the operation of the first pull-up transistor and the operation of the first pull-down transistor;

[0476] A second output terminal configured to output the gate signal according to the operation of the second pull-up transistor and the operation of the second pull-down transistor;

[0477] A transistor A, which is disposed between the first pull-up transistor and the second pull-up transistor and is configured to electrically isolate the Q node in response to a control signal;

[0478] A transistor B, which is disposed between the transistor A and the second pull-up transistor and is configured to supply a second low-potential voltage to the second pull-up transistor in response to a control bar signal; and

[0479] The C transistor is connected to the second output terminal to supply a first low potential voltage in response to the control bar signal.

[0480] 18. The gate driver according to claim 17, wherein when the gate signal output from the (n + 1)-th signal transmission unit changes from a gate cut-off voltage to a gate on-voltage, the gate signal output from the n-th signal transmission unit changes from the gate on-voltage to the gate cut-off voltage.

[0481] 19. The gate driver according to claim 17, wherein the carry signal output from the n-th signal transmission unit is set to a floating state to prevent the (n + 1)-th signal transmission unit from operating abnormally.

[0482] 20. A display device, comprising:

[0483] A gate driver including an n-th signal transmission unit and an (n + 1)-th signal transmission unit connected in cascade with each other, where n is a positive integer greater than or equal to 1;

[0484] An n-th pixel row group including an n-th odd pixel row receiving an n-th gate signal output from the n-th signal transmission unit and an n-th even pixel row receiving the n-th gate signal output from the n-th signal transmission unit; and

[0485] An (n + 1)-th pixel row group including an (n + 1)-th odd pixel row receiving an (n + 1)-th gate signal output from the (n + 1)-th signal transmission unit and an (n + 1)-th even pixel row receiving the (n + 1)-th gate signal output from the (n + 1)-th signal transmission unit,

[0486] wherein, for a sensing time for external compensation, when the n-th gate signal has a gate on-voltage, the (n + 1)-th gate signal has a gate cut-off voltage, and when the (n + 1)-th gate signal has a gate on-voltage, the n-th gate signal has a gate cut-off voltage.

[0487] 21. The display device according to claim 20, wherein, for a sensing time for external compensation, when the n-th gate signal has a gate cut-off voltage, the (n + 1)-th gate signal has a gate on-voltage, and when the (n + 1)-th gate signal has a gate cut-off voltage, the n-th gate signal has a gate on-voltage.

[0488] 22. The display device according to claim 21, wherein each pixel circuit included in the n-th pixel row group and the (n + 1)-th pixel row group includes a third switching element, the third switching element including a gate electrode to which the n-th gate signal or the (n + 1)-th gate signal is applied, a first electrode connected to a fourth node connected to an anode of a light-emitting element, and a second electrode to which a sensing voltage is applied.

[0489] Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical spirit of the present invention.

[0490] Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments.

[0491] Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

[0492] The scope of the present invention should be construed in accordance with the appended claims, and all technical spirits within the equivalent scope should be construed as being included within the scope of the present invention.

Claims

1. A gate driver comprising a plurality of signal transmission units which are cascade-connected to each other and configured to receive a clock signal and sequentially output gate signals, in, At least one of the plurality of signal transmission units comprises: a first pull-up transistor turned on based on the potential of the Q node; a second pull-up transistor turned on based on the potential of the Q node; a first pull-down transistor turned on based on a potential of the Qb node; a second pull-down transistor turned on based on the potential of the Qb node; and An Ath transistor is disposed between the first pull-up transistor and the second pull-up transistor and is configured to electrically isolate the Q node in response to a control signal. 2 . The gate driver according to claim 1 , further comprising a Bth transistor disposed between the first pull-up transistor and the second pull-up transistor and configured to supply a second low potential voltage to the second pull-up transistor in response to a control bar signal.

3. The gate driver according to claim 2, wherein: The Bth transistor is disposed between the Ath transistor and the second pull-up transistor.

4. The gate driver according to claim 3, further comprising: a first output terminal configured to output a carry signal according to an operation of the first pull-up transistor and an operation of the first pull-down transistor; a second output terminal configured to output the gate signal according to an operation of the second pull-up transistor and an operation of the second pull-down transistor; as well as A Cth transistor is connected to the second output terminal to supply a first low potential voltage in response to the control bar signal.

5. The gate driver according to claim 4, wherein: When the control signal has a gate-on voltage, the control bar signal has a gate-off voltage, and When the control signal has a gate-off voltage, the control bar signal has a gate-on voltage.

6. The gate driver according to claim 5, wherein: The gate electrode of the A-th transistor is connected to a control signal input terminal to which the control signal is input, The first electrode of the Ath transistor is connected to the Q node, and The second electrode of the Ath transistor is connected to the gate electrode of the second pull-up transistor.

7. The gate driver according to claim 6, wherein: The gate electrode of the B-th transistor is connected to a first control bar signal input terminal to which the control bar signal is input, The second low potential voltage is applied to the first electrode of the B-th transistor, and The second electrode of the B-th transistor is connected to the gate electrode of the second pull-up transistor.

8. The gate driver according to claim 7, wherein: The gate electrode of the C-th transistor is connected to a second control bar signal input terminal to which the control bar signal is input, The first low potential voltage is applied to the first electrode of the Cth transistor, and A second electrode of the Cth transistor is connected to the second output terminal.

9. The gate driver according to claim 8, further comprising: a first circuit unit configured to control charging / discharging of the Q node and the Qb node; a second circuit unit including an inverter circuit configured to invert the potential of the Q node and apply the inverted potential to the Qb node; as well as A third circuit unit, the third circuit unit includes a 3-1 circuit unit having the first pull-up transistor and the first pull-down transistor, a 3-2 circuit unit having the second pull-up transistor and the second pull-down transistor, and a 3-3 circuit unit having the Ath transistor, the Bth transistor, and the Cth transistor.

10. The gate driver according to claim 5, wherein: When the control signal changes from the gate-on voltage to the gate-off voltage, the control bar signal changes from the gate-off voltage to the gate-on voltage.

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