Display panel and display device including same

Abstract

The present disclosure relates to a display panel including a plurality of sub-pixels, where each sub-pixel includes: a driving element configured to generate a current; a first light emitting element configured to emit light by a current from the driving element; a second light emitting element configured to emit light by a current from the driving element; a mode selection circuit configured to switch a current path from the driving element in response to the first horizontal mode selection signal, the second horizontal mode selection signal, the first vertical mode selection signal, and the bridge signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0193965, filed on December 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display panel having a variable viewing angle in units of pixels and a display device including the display panel. Background art

[0004] Variable viewing angle technology can be applied to display devices. The variable viewing angle technology can display video content or visual information reproduced on the display device only to users within a narrow viewing angle range or to multiple users existing within a wide viewing angle range.

[0005] As the market for future vehicles such as electric vehicles and autonomous vehicles expands, the demand for vehicle display devices has increased rapidly. Research is being conducted on methods for dividing the screen of a vehicle display device and controlling a part with a narrow viewing angle and another part with a wide viewing angle of the screen. This technology can display personal content or information that can only be viewed by a specific user by driving pixels with a narrow viewing angle arranged in a partial area of the screen, and at the same time, display shared content that can be seen by multiple users together by driving pixels with a wide viewing angle arranged in another area of the screen.

[0006] The display panel of an organic light - emitting display device has received attention in vehicle display devices. The organic light - emitting display device includes an organic light - emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, brightness, and viewing angle. The organic light - emitting display device has a fast response speed, excellent luminous efficiency, brightness, viewing angle, etc., as well as excellent contrast and color reproduction rate because the black gray level can be represented as pure black. Since the display panel of the organic light - emitting display device can be flexibly bent, a curved surface can be easily achieved. Due to these advantages, the market share of the organic light - emitting display device in the vehicle display device market has increased rapidly. Summary of the invention

[0007] In a display device to which variable viewing angle technology is applied, the viewing angle is not partially controlled. The entire screen can be controlled at a specific viewing angle, or the viewing angle can be controlled in units of screen regions having a preset size. Therefore, a technology capable of freely controlling the viewing angle within the screen of a display device is needed.

[0008] An object of the present disclosure is to solve the above needs and / or problems.

[0009] The present disclosure provides a display panel and a display device including the display panel. In the display panel, the viewing angle can be freely changed at all positions of the screen to control pixels at a viewing angle different from the background in the window area of the screen.

[0010] The problems or limitations to be solved or addressed by the present disclosure are not limited to those described above, and those skilled in the art will clearly understand other problems or limitations not mentioned from the following description.

[0011] The display panel according to an embodiment of the present disclosure includes a plurality of sub-pixels. Each of the sub-pixels includes a driving element that generates a current; a first light-emitting element that emits light through the current from the driving element; a second light-emitting element that emits light through the current from the driving element; a mode selection circuit that selects a current path from the driving element in response to a first horizontal mode selection signal Sx, a second horizontal mode selection signal Px, a vertical mode selection signal, and a bridging signal BR; and a first pixel switching element that is connected to the driving element through a first node and is connected to the mode selection circuit through a second node. The vertical mode selection signal includes at least the second vertical mode selection signal among the first vertical mode selection signal and the second vertical mode selection signal.

[0012] The mode selection circuit may include: a first switching element configured to conduct in response to the gate conduction voltage of the first horizontal mode selection signal to electrically connect the second node to a third node; a second switching element configured to conduct in response to the gate conduction voltage of the second horizontal mode selection signal to electrically connect the second node to a fourth node; a third switching element configured to conduct in response to the gate conduction voltage of the bridging signal to electrically connect the third node to the fourth node; and a fourth switching element configured to conduct in response to the gate conduction voltage of the second vertical mode selection signal to electrically connect the fourth node to the anode electrode of the second light-emitting element.

[0013] The anode electrode of the first light-emitting element may be connected to the third node.

[0014] When the first switching element and the third switching element are turned on, and the second switching element and the fourth switching element are in the off state, the sub-pixel can be driven in a first mode. When the first switching element and the fourth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel can be driven in a first mode. When the second switching element and the third switching element are turned on, and the first switching element and the fourth switching element are in the off state, the sub-pixel can be driven in a first mode. When the second switching element and the fourth switching element are turned on, and the first switching element and the third switching element are in the off state, the sub-pixel can be driven in a second mode.

[0015] The mode selection circuit may further include a fifth switching element configured to be turned on in response to the gate conduction voltage of the first vertical mode selection signal to electrically connect the third node to the anode electrode of the first light-emitting element.

[0016] When the first switching element, the third switching element, and the fifth switching element are turned on, and the second switching element and the fourth switching element are in the off state, the sub-pixel can be driven in a first mode. When the first switching element, the fourth switching element, and the fifth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel can be driven in a first mode. When the second switching element, the third switching element, and the fifth switching element are turned on, and the first switching element and the fourth switching element are in the off state, the sub-pixel can be driven in a first mode. When the second switching element, the fourth switching element, and the fifth switching element are turned on, and the first switching element and the third switching element are in the off state, the sub-pixel can be driven in a second mode.

[0017] When the first switching element, the fourth switching element, and the fifth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel can be driven in a first mode. When the first switching element, the third switching element, and the fourth switching element are turned on, and the second switching element and the fifth switching element are in the off state, the sub-pixel can be driven in a second mode. When the second switching element, the fourth switching element, and the fifth switching element are turned on, and the first switching element and the third switching element are in the off state, the sub-pixel can be driven in a second mode. When the second switching element, the third switching element, and the fourth switching element are turned on, and the first switching element and the fifth switching element are in the off state, the sub-pixel can be driven in a second mode.

[0018] The viewing angle of the sub-pixels driven in the first mode can be greater than the viewing angle of the sub-pixels driven in the second mode.

[0019] Each of the sub-pixels may further include a capacitor connected between a sixth node and a seventh node; a second pixel switching element connected between a data line to which a data voltage of pixel data is applied and the sixth node to conduct in response to a gate conduction voltage of a first scan signal; a third pixel switching element connected between the first node and the seventh node to conduct in response to a gate conduction voltage of a second scan signal; a fourth pixel switching element connected between a REF node to which a reference voltage is applied and an anode electrode of the first light-emitting element to conduct in response to a gate conduction voltage of the second scan signal; a fifth pixel switching element connected between the REF node and an anode electrode of the second light-emitting element to conduct in response to a gate conduction voltage of the second scan signal; and a sixth pixel switching element connected between the REF node and the sixth node to conduct in response to a gate conduction voltage of a light-emitting signal. The first pixel switching element may be connected between the first node and the second node to conduct in response to a gate conduction voltage of the light-emitting signal. The driving element may include a first electrode to which a pixel driving voltage is applied, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

[0020] Each of the sub-pixels may further include: a capacitor connected between a VDD node to which the pixel driving voltage is applied and the seventh node; a second pixel switching element connected between a data line to which a data voltage of pixel data is applied and the sixth node and turned on in response to a gate turn-on voltage of the second scan signal; a third pixel switching element connected between the first node and the seventh node and turned on in response to a gate turn-on voltage of the first scan signal; a fourth pixel switching element connected between an AR node to which a second compensation voltage is applied and an anode electrode of the first light-emitting element and turned on in response to a gate turn-on voltage of a third scan signal; a fifth pixel switching element connected between the AR node and an anode electrode of the second light-emitting element and turned on in response to a gate turn-on voltage of the third scan signal; a sixth pixel switching element connected between an INI node to which an initialization voltage is applied and the seventh node and turned on in response to a gate turn-on voltage of a fourth scan signal; a seventh pixel switching element connected between the VDD node and the sixth node and turned on in response to a gate turn-on voltage of the light-emitting signal; and an eighth pixel switching element connected between an OBS node to which a first compensation voltage is applied and the sixth node and turned on in response to a gate turn-on voltage of the third scan signal. The first pixel switching element may be connected between the first node and the second node and turned on in response to a gate turn-on voltage of the light-emitting signal. The driving element may include a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

[0021] Each of the sub-pixels may include: a capacitor connected between a VDD node to which a pixel driving voltage is applied and the seventh node; a second pixel switching element connected between a data line to which a data voltage of pixel data is applied and the sixth node and turned on in response to a gate conduction voltage of an N-th scan signal (where N is a natural number); a third pixel switching element connected between the first node and the seventh node and turned on in response to a gate conduction voltage of the N-th scan signal; a fourth pixel switching element connected to an INI node to which an initialization voltage is applied and an anode electrode of a first light-emitting element and turned on in response to a gate conduction voltage of an (N-1)-th scan signal; a fifth pixel switching element connected between the INI node and an anode electrode of a second light-emitting element and turned on in response to a gate conduction voltage of the (N-1)-th scan signal; a sixth pixel switching element connected between the INI node and the seventh node and turned on in response to a gate conduction voltage of the (N-1)-th scan signal; and a seventh pixel switching element connected between the VDD node and the sixth node and turned on in response to a gate conduction voltage of a light-emitting signal. The first pixel switching element may be connected between the first node and the second node and turned on in response to a gate conduction voltage of the light-emitting signal. The driving element may include a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

[0022] Each of the sub-pixels may include a capacitor connected between the seventh node and the eighth node; a second pixel switching element connected between a data line to which a pixel data voltage is applied and the sixth node and turned on in response to a gate-on voltage of an N-th scan signal (where N is a natural number); a third pixel switching element connected between the first node and the seventh node and turned on in response to the gate-on voltage of the N-th scan signal; a fourth pixel switching element connected to an INI node to which an initialization voltage is applied and an anode electrode of the first light-emitting element and turned on in response to a gate-on voltage of an (N-1)-th scan signal; a fifth pixel switching element connected between the INI node and an anode electrode of the second light-emitting element and turned on in response to the gate-on voltage of the (N-1)-th scan signal; a sixth pixel switching element connected between the INI node and the seventh node and turned on in response to the gate-on voltage of the (N-1)-th scan signal; a seventh pixel switching element connected between the sixth node and the eighth node and turned on in response to the gate-on voltage of the light-emitting signal; an eighth pixel switching element connected between a VDD node to which a pixel driving voltage is applied and the eighth node and turned on in response to the gate-on voltage of the light-emitting signal; a ninth pixel switching element connected between a REF node to which a reference voltage is applied and the eighth node and turned on in response to the gate-on voltage of the (N-1)-th scan signal; and a tenth pixel switching element connected between the REF node and the eighth node and turned on in response to the gate-on voltage of the N-th scan signal. The first pixel switching element may be connected between the first node and the second node and turned on in response to the gate-on voltage of the light-emitting signal. The driving element may include a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

[0023] A display device according to an embodiment of the present disclosure includes: a display panel; a data driver that supplies a data voltage to a data line; a gate driver that receives a gate timing signal and supplies a scan signal and a light-emitting signal to the gate line; and a level shifter that outputs a gate timing signal, a first horizontal mode selection signal, a second horizontal mode selection signal, a vertical mode selection signal, and a bridge signal.

[0024] The display panel may further include a plurality of vertical mode lines parallel to the data lines; and a plurality of horizontal mode lines parallel to the gate lines. A vertical mode selection signal and a bridging signal may be applied to the vertical mode lines. A first horizontal mode selection signal and a second horizontal mode selection signal may be applied to the horizontal mode lines.

[0025] The gate driver may be disposed on the display panel. At least a portion of the horizontal mode lines may overlap with the gate driver on the display panel.

[0026] The present disclosure allows for low power and process optimization, as well as freely changing the viewing angle of pixels by using the mode selection signals of the pixels.

[0027] According to the present disclosure, the viewing angle of a window pixel region surrounded by a background pixel region may be controlled differently from the background pixel region.

[0028] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0031] Figure 2 is a diagram showing a transmission path of a mode selection signal;

[0032] Figure 3 is a diagram showing an example of differently controlling the viewing angle of pixels for each pixel region;

[0033] Figure 4 is a circuit diagram schematically showing a pixel circuit according to an embodiment of the present disclosure;

[0034] Figure 5 is a diagram showing an example of a lens disposed on a light-emitting element;

[0035] Figures 6 to 8 is showing Figure 4 an example of the configuration and operation of the mode selection circuit shown;

[0036] Figure 9 is a circuit diagram schematically showing a pixel circuit according to another embodiment of the present disclosure;

[0037] Figures 10 to 15 is showing Figure 9A diagram showing an example of the configuration and operation of the mode selection circuit shown;

[0038] Figure 16 is a circuit diagram showing an example of a pixel circuit to which the Figure 4 and 6 mode selection circuit shown is applied;

[0039] Figure 17 is a waveform diagram showing examples of a gate signal and a mode selection signal input to the Figure 16 pixel circuit shown;

[0040] Figure 18 is a circuit diagram showing an example of a pixel circuit to which the Figure 9 mode selection circuit shown is applied;

[0041] Figure 19A and 19B is a waveform diagram showing examples of a gate signal and a mode selection signal input to the Figure 18 pixel circuit shown;

[0042] Figures 20A to 20B is a diagram showing Figure 16 other diagrams of the initialization phase, data write and threshold voltage sampling phase, and light emission phase of the pixel circuit shown;

[0043] Figures 21A to 21B is a diagram showing Figure 16 other diagrams of the initialization phase, data write and threshold voltage sampling phase, and light emission phase of the pixel circuit shown;

[0044] Figures 22A to 22B is a diagram showing Figure 16 the initialization phase, data write and threshold voltage sampling phase, and light emission phase of the pixel circuit shown;

[0045] Figure 23 is a circuit diagram showing another example of a pixel circuit to which the Figure 4 and 6 mode selection circuit shown is applied;

[0046] Figures 24A to 24B is a diagram showing Figure 23 the first reset phase, initialization phase, data write and threshold voltage sampling phase, second reset phase, and light emission phase of the pixel circuit shown;

[0047] Figures 25A to 25B is a diagram showing Figure 23 other diagrams of the first reset phase, initialization phase, data write and threshold voltage sampling phase, second reset phase, and light emission phase of the pixel circuit shown;

[0048] Figures 26A to 26B Another figure showing Figure 23 the first reset stage, initialization stage, data writing and threshold voltage sampling stage, second reset stage, and light emission stage of the pixel circuit shown;

[0049] Figures 27A to 27B Another figure showing Figure 23 the first reset stage, initialization stage, data writing and threshold voltage sampling stage, second reset stage, and light emission stage of the pixel circuit shown;

[0050] Figures 28A to 28B Another figure showing Figure 23 the first reset stage, initialization stage, data writing and threshold voltage sampling stage, second reset stage, and light emission stage of the pixel circuit shown;

[0051] Figure 29 Another figure showing the pixel circuit to which Figure 4 and 6 the mode selection circuit shown is applied;

[0052] Figures 30A to 30B Another figure showing Figure 29 the initialization stage, data writing and threshold voltage sampling stage, and light emission stage of the pixel circuit shown;

[0053] Figures 31A to 31B Another figure showing Figure 29 the initialization stage, data writing and threshold voltage sampling stage, and light emission stage of the pixel circuit shown;

[0054] Figures 32A to 32B Another figure showing Figure 29 the initialization stage, data writing and threshold voltage sampling stage, and light emission stage of the pixel circuit shown;

[0055] Figure 33 Another figure showing the pixel circuit to which Figure 4 and 6 the mode selection circuit shown is applied; and

[0056] Figure 34 Another figure showing Figure 33 the initialization stage, data writing and threshold voltage sampling stage, and light emission stage of the pixel circuit shown.

[0057] Figure 35 Another figure showing Figure 33 the initialization stage, data writing and threshold voltage sampling stage, and light emission stage of the pixel circuit shown.

[0058] Figure 36 Another figure showingFigure 33 Another diagram of the initialization phase, data writing and threshold voltage sampling phase, and light emission phase of the pixel circuit shown. Detailed implementation

[0059] Advantages and features of the present disclosure and methods for implementing the same will be more clearly understood according to the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but may be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims.

[0060] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0061] Terms such as "including", "comprising", "having", and "containing" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise clearly stated.

[0062] Even if not explicitly stated, components are interpreted to include a normal error range.

[0063] When describing the positional or interconnection relationship between two components, such as "on top of", "above", "below", "adjacent to", "connected or coupled to", "across", "crossing", etc., one or more other components may be inserted between them unless the terms "immediately" or "directly" are used.

[0064] When describing the time precedence relationship, such as "after", "subsequent to", "immediately following", "before", etc., it may not be continuous in terms of time base unless the terms "immediately" or "directly" are used.

[0065] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the functions or structures of the components are not limited by the ordinal numbers or component names in front of the components.

[0066] The following embodiments may be partially or fully combined or combined with each other, and may be connected and operated in various technical ways. The embodiments may be executed independently of each other or in association with each other.

[0067] The pixel circuit of the display device may also include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including oxide semiconductors, low temperature polycrystalline silicon TFTs (LTPS TFTs) including low temperature polycrystalline silicon, etc.

[0068] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, such that electrons can flow from the source to the drain. The n - channel transistor has a current direction flowing from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, such that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. Note that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0069] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage may be a gate - high voltage VGH, and the gate - off voltage may be a gate - low voltage VGL. In the case of a p - channel transistor, the gate - on voltage may be a gate - low voltage VGL, and the gate - off voltage may be a gate - high voltage VGH.

[0070] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0071] Reference Figure 1 , a display device according to an embodiment of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. The display device also includes a power supply 150.

[0072] The display panel 100 may be, but is not limited to, a rectangular panel having a length in the X - axis direction (or the first direction), a width in the Y - axis direction (or the second direction), and a thickness in the Z - axis direction (or the third direction). For example, the display panel 100 may be at least partially curved or an elliptical deformed panel.

[0073] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 may also include a power supply line commonly connected to the pixels. The power supply line may be commonly connected to the pixel circuit and supply a voltage required to drive the pixel 101 to the pixel 101.

[0074] Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each of the pixels may also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. The light-emitting element may be implemented as an organic light-emitting element (such as an OLED) or an inorganic light-emitting element (such as a micro light-emitting diode (LED)). Each of the pixel circuits may be connected to a data line, a gate line, and a power supply line. Hereinafter, the pixel may be interpreted to have the same meaning as the sub-pixel.

[0075] Each of the pixels 101 may include a first light-emitting element that emits light in a first viewing angle mode (hereinafter referred to as the "first mode") and a second light-emitting element that emits light in a second viewing angle mode (hereinafter referred to as the "second mode"). In the first mode, each of the pixels 101 may emit light from the first light-emitting element at a wide viewing angle, while in the second mode, it may emit light from the second light-emitting element at a narrow viewing angle. For example, the narrow viewing angle may be 30 to 60 degrees with respect to the normal, and the wide viewing angle may be 90 to 180 degrees with respect to the normal.

[0076] The display area AA includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes pixels of a line arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line may share the gate line 103. The sub-pixels arranged in the column direction (Y) may share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0077] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on the screen and an actual object is visible outside the display panel. The display panel 100 may be manufactured as a flexible display panel that can be flexibly bent.

[0078] The power supply 150 receives an input voltage from the host system 200 and outputs voltages required to drive the pixels 101 of the display panel 100 and the display panel driving circuit. To this end, the power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 150 may output constant voltages (or DC voltages), such as a gate high voltage, a gate low voltage, a pixel driving voltage, a cathode voltage, a reference voltage, an initialization voltage, and an IC driving voltage, through the DC-DC converter for the display panel driving circuit. The gate high voltage and the gate low voltage may be provided to the level shifter 140 and the gate driver 120. Constant voltages such as the pixel driving voltage, the cathode voltage, the reference voltage, and the initialization voltage are provided to the pixels 101 via power lines commonly connected to the pixels 101.

[0079] The power supply 150 may further include a gamma voltage generator. The gamma voltage generator may receive a high-potential reference voltage and a low-potential reference voltage and output a plurality of gamma reference voltages divided at predetermined voltage differences on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are provided to the data driver 110. The gamma reference voltages are divided by a voltage dividing circuit and subdivided into gray-scale voltages in the data driver 110. The gamma voltage generator may be implemented as a programmable gamma circuit capable of adjusting the voltage of each gamma reference voltage according to digital data. The timing controller 130 or the host system 200 or a separate external device may update the digital data stored in the register of the programmable gamma circuit through a communication interface.

[0080] The display panel driving circuit writes pixel data of an input image into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110, a gate driver 120, a level shifter 140, and a timing controller 130.

[0081] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into a source driver integrated circuit (IC).

[0082] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 may receive gamma reference voltages and generate gamma compensation voltages for each gray scale through a voltage dividing circuit. The gamma compensation voltages are provided to digital-to-analog converters (“DACs”) provided on each channel of the data driver 110.

[0083] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data into the DAC. Here, the digital data includes the pixel data of the input image. The DAC converts the pixel data into a gamma-compensated voltage and outputs the data voltage of the pixel data.

[0084] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wirings in the display area AA. The gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA of the display panel 100, or at least a part thereof may be disposed within the display area AA.

[0085] The gate driver 120 may be disposed in the non-display areas NA on both sides of the display panel 100, with the display area AA of the display panel therebetween, and may provide gate pulses from both sides of the gate line 103 in a dual-feed method. In another embodiment, the gate driver 120 may be disposed on at least one of the left non-display area NA and the right non-display area NA of the display panel 100 to provide a gate signal to the gate line 103 in a single-feed method. The gate driver 120 sequentially outputs the pulses of the gate signal to the gate line 103 under the control of the timing controller 130. The gate driver 120 may shift the pulses of the gate signal by using a shift register and edge triggers to sequentially provide the gate signal to the gate line 103.

[0086] The gate signal may include a scan signal and an emission signal (hereinafter referred to as "EM signal") input to the pixel circuit via a plurality of gate lines. In this case, the gate driver may include a gate driver that outputs the scan signal and a gate driver that outputs the EM signal. Each of the scan signal and the EM signal may swing between a gate high voltage and a gate low voltage.

[0087] The timing controller 130 receives the digital video data of the input image and the timing signals synchronized with the data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal period (1H).

[0088] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200, thereby controlling the display panel driving circuit. The timing controller 130 synchronizes the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0089] The timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The mode selection signal output from the timing controller 130 can be input to the mode selection circuit through the level shifter 140. The mode selection signal can include a vertical mode selection signal, a horizontal mode selection signal, and a bridging signal.

[0090] The level shifter 140 can convert the voltage level of the signal received from the timing controller 130 into a swing width between the gate high voltage and the gate low voltage and output the swing width. The level shifter 140 can decode the gate timing signal to output a start pulse and a clock to drive the gate driver 120, and can decode the mode selection signal to output a vertical mode selection signal, a horizontal mode selection signal, and a bridging signal. The start pulse, the clock, the vertical mode selection signal, the horizontal mode selection signal, and the bridging signal are all AC signals that swing between the gate high voltage and the gate low voltage.

[0091] The host system 200 can scale the image signal from the video source to match the resolution of the display panel 100 and can transmit it to the timing controller 130 together with the timing signals. The host system 200 can transmit the viewing angle mode signal having different logic values in the first mode and the second mode to the timing controller 130 together with the image signal at least once per frame. The timing controller 130 can output a vertical mode selection signal, a horizontal mode selection signal, and a bridging signal in response to the viewing angle mode signal.

[0092] Figure 2 FIG. is a diagram showing the transmission path of the mode selection signal.

[0093] Reference Figure 2 Referring to

[0094] The vertical mode lines 104 are arranged in parallel with the data lines 102 and are connected to the pixel circuits PIX of each sub-pixel. The horizontal mode lines 105 are arranged in parallel with the gate lines 103 and are connected to the pixel circuits PIX of each sub-pixel. Some of the horizontal mode lines 105 may overlap with the circuit of the gate driver 120 with an insulating layer therebetween.

[0095] The vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, and the bridge signals BR1, BR2, and BR3 can be applied to the pixel circuit PIX of the pixel through the vertical mode line 104. The vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3 can select the viewing angle of each pixel in the Y-axis direction (or the second direction). The horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3 can be applied to the pixel circuit PIX of the pixel through the horizontal mode line 105. The horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3 can select the viewing angle of each pixel in the X-axis direction (or the first direction). The bridge signals BR1, BR2, and BR3 can differently control the viewing angles between the pixels arranged along the X-axis direction, and differently control Figure 3 the viewing angles of the pixels between the window pixel region and the background pixel region shown.

[0096] The vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, the horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3, and the bridge signals BR1, BR2, and BR3 can be input to the pixels at each position in the display area AA, so that the viewing angle can be individually controlled for each pixel region existing in the display area AA. For example, the first mode selection signal group Sy1, Py1, Sx1, Px1, and BR1 can be input to the pixels in the first pixel region, and the second mode selection signal group Sy2, Py2, Sx2, Px2, and BR2 can be input to the pixels in the second pixel region. The third mode selection signal group Sy3, Py3, Sx3, Px3, and BR3 can be input to the pixels in the third pixel region.

[0097] The display device may include a circuit board (PCB) and a chip on film (COF) that are electrically connected to the display panel 100. The source driver IC (DIC) with the circuit on which the data driver 110 is integrated can be mounted on the flexible film of the COF.

[0098] The circuit board PCB may include a timing controller 130, a level shifter 140, a power supply 150, etc. The circuit board PCB can be electrically connected to the COF.

[0099] The COF can be connected between the circuit board PCB and the display panel 100 to electrically connect the circuit board PCB to the display panel 100 and supply the data voltage output from the source driver IC (DIC) to the data lines on the display panel 100.

[0100] The gate timing control signal and the mode selection signal output from the timing controller 130 can be provided to the level shifter 140. The level shifter 140 receives the signals received from the timing controller 130, the gate high voltage VGH, and the gate low voltage VGL. The level shifter 140 decodes the gate timing control signal to output a start pulse and a clock that swing between the gate high voltage VGH and the gate low voltage VGL. The start pulse and the clock are provided to the gate driver 120. When the start pulse and the clock are input, the gate driver 120 can output pulses of the gate signal. The level shifter 140 decodes the mode selection signal to output a vertical mode selection signal Sy1, Py1, Sy2, Py2, Sy3, and Py3, a horizontal mode selection signal Sx1, Px1, Sx2, Px2, Sx3, and Px3, and bridging signals BR1, BR2, and BR3 that swing between the gate high voltage VGH and the gate low voltage VGL. The vertical mode selection signal Sy1, Py1, Sy2, Py2, Sy3, and Py3, the horizontal mode selection signal Sx1, Px1, Sx2, Px2, Sx3, and Px3, and the bridging signals BR1, BR2, and BR3 are provided to the pixel circuit PIX of the pixel through the corresponding vertical mode lines 104 and horizontal mode lines 105. Each pixel can be driven individually in a viewing angle mode indicated by the vertical mode selection signal Sy1, Py1, Sy2, Py2, Sy3, and Py3, the horizontal mode selection signal Sx1, Px1, Sx2, Px2, Sx3, and Px3, and the bridging signals BR1, BR2, and BR3.

[0101] Figure 3 FIG. is an example showing that the viewing angle of each pixel is controlled differently for each pixel region. In Figure 3 FIG., the non-shaded portion is a pixel region including pixels that emit light with a wide viewing angle in the first mode (S mode). The shaded portion is a pixel region including pixels that emit light with a wide viewing angle in the second mode (P mode). The viewing angle of the pixel region can vary according to the vertical mode selection signal Sy1, Py1, Sy2, Py2, Sy3, and Py3, the horizontal mode selection signal Sx1, Px1, Sx2, Px2, Sx3, and Px3, and the bridging signals BR1, BR2, and BR3.

[0102] Referring to Figure 3 FIG., the display area AA can be divided into a plurality of pixel regions according to the viewing angle mode of the pixels. Each pixel region can include two or more pixels.

[0103] The display area AA can be controlled by horizontal blocks HB1, HB2, and HB3 having different viewing angles. For example, the first horizontal block HB1 and the third horizontal block HB3 can be pixel areas driven in a first mode, and the second horizontal block HB2 can be a pixel area driven in a second mode. Each of the horizontal blocks HB1, HB2, and HB3 can be driven in the first mode or the second mode by vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3, and bridging signals BR1, BR2, and BR3.

[0104] The display area AA can be controlled by vertical blocks VB1, VB2, and VB3 having different viewing angles. For example, the first vertical block VB1 and the third vertical block VB3 can be pixel areas driven in a first mode, and the second vertical block VB2 can be a pixel area driven in a second mode. Each of the vertical blocks VB1, VB2, and VB3 can be driven in the first mode or the second mode by vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3, and bridging signals BR1, BR2, and BR3.

[0105] The display area AA can be controlled by a background pixel area B having different viewing angles from each other and a window pixel area W surrounded by the background pixel area B. The window pixel area W can be interpreted as a pop-up window area. Each of the background pixel area B and the window pixel area W includes pixels driven in the first mode or the second mode by vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3, and bridging signals BR1, BR2, and BR3. The size and position of each of the background pixel area B and the window pixel area W can be changed by vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3, horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3, and bridging signals BR1, BR2, and BR3.

[0106] The vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3 can include a first vertical mode selection signal Sy for starting the first mode and a second vertical mode selection signal Py for starting the second mode, but are not limited thereto. For example, as Figure 4As shown, any one of the vertical mode selection signals Sy1, Py1, Sy2, Py2, Sy3, and Py3 can be omitted. The horizontal mode selection signals Sx1, Px1, Sx2, Px2, Sx3, and Px3 can include a first horizontal mode selection signal Sx for starting the first mode and a second horizontal mode selection signal Px for starting the second mode.

[0107] Figure 4 is a circuit diagram schematically showing a pixel circuit according to an embodiment of the present disclosure.

[0108] Referring Figure 4 , the pixel circuit PIX includes a first light-emitting element EL1 that emits light in a first mode (S mode), a second light-emitting element EL2 that emits light in a second mode (P mode), a driving element DT that generates currents required to drive the light-emitting elements EL1 and EL2, and a mode selection circuit SPM that selects a current path between the driving element DT and the light-emitting elements EL1 and EL2 according to a selected viewing angle mode. The pixel circuit PIX may further include a pixel switching element M01 that switches a current path between the driving element DT and the mode selection circuit SPM.

[0109] The driving element DT can generate currents required to drive the first light-emitting element EL1 and the second light-emitting element EL2 according to a gate-source voltage. The pixel switching element M01 can be connected to the driving element DT through a first node n1, and as Figure 6 shown, can be connected to the mode selection circuit SPM through a second node n2. The mode selection circuit SPM can include a plurality of switching elements T1, T2, T3, and T4, as Figure 6 shown. In the pixel circuit PIX, each of the driving element DT, the pixel switching element M01, and the switching elements T1, T2, T3, and T4 of the mode selection circuit SPM can be implemented as a transistor.

[0110] The pixel circuit PIX can be driven through an initialization stage, a data writing and threshold voltage sampling stage, and a light-emitting stage. To this end, the pixel circuit PIX may further include a compensation circuit PIC. The compensation circuit PIC can initialize the pixel circuit PIX using two or more pixel switching elements and capacitors in the initialization stage, sample a threshold voltage of the driving element DT in the data writing and threshold voltage sampling stage, and apply a data voltage Vdata compensated by the threshold voltage to a gate electrode of the driving element DT. The compensation circuit PIC can turn on the pixel switching element M01 in the light-emitting stage to electrically connect the driving element DT and the mode selection circuit SPM.

[0111] The mode selection circuit SPM receives a vertical mode selection signal Py, a first horizontal mode selection signal Sx, a second horizontal mode selection signal Px, and a bridging signal BR, and supplies the current from the driving element DT to the light-emitting elements EL1 and EL2 driven in the light-emitting stage.

[0112] Figure 5 It is a diagram showing an example of a lens provided on the light-emitting element.

[0113] Reference Figure 5 , the first lens 32 can be provided on the first light-emitting element EL1. The first lens 32 can be implemented as a semi-cylindrical lens to limit the vertical viewing angle and widen the horizontal viewing angle. The first lens 32 can be longer in the X-axis direction parallel to the gate line 103 of the display panel 100, and can have a narrow and convex central portion in the Y-axis direction parallel to the data line 102. The first lens 32 diffuses the light of the first light-emitting element EL1 emitted in the first mode S mode in the horizontal viewing angle.

[0114] The second lens 34 can be provided on the second light-emitting element EL2. The second lens 34 can be a hemispherical lens having a convex central portion and thinning toward the edge. The second lens 34 can converge the light of the second light-emitting element EL2 emitted in the second mode (P mode) to narrow the vertical and horizontal viewing angles of the second light-emitting element EL2.

[0115] The first lens 32 and the second lens 34 can be implemented as a transparent medium or a transparent insulating layer pattern provided in the display panel 100, but are not limited thereto.

[0116] Figure 6 It is a diagram showing Figure 4 An example of the configuration and operation of the mode selection circuit shown. In Figure 6 , the "S mode" is a state in which the pixel is driven in the first mode. The "P mode" is a state in which the pixel is driven in the second mode. Figure 7 It is a diagram showing Figure 6 An example of the mode selection signals input to the mode selection circuit shown.

[0117] Reference Figure 6 and 7 , the mode selection circuit SPM includes a first switching element T1, a second switching element T2, a third switching element T3, and a fourth switching element T4. As an example, the switching elements T1, T2, T3, and T4 can be implemented as p-channel transistors. In this case, each of the switching elements T1, T2, T3, and T4 can be turned on in response to a low gate voltage VGL, and each of the switching elements T1, T2, T3, and T4 can be turned off in response to a high gate voltage VGH. In Figures 6 to 11In the example, the gate low voltage VGL is described as the gate-on voltage, and the gate high voltage VGH is described as the gate-off voltage. However, in an alternative example, the gate high voltage VGH can be used as the gate-on voltage, and the gate low voltage VGL can be used as the gate-off voltage.

[0118] The first switching element T1 can be connected between the second node n2 and the third node n3 and conduct in response to the gate-on voltage VGL of the first horizontal mode selection signal Sx. The second node n2 is connected to the pixel switching element M01. The third node n3 is connected to the anode electrode of the first light-emitting element EL1. When the first switching element T1 conducts, the second node n2 can be electrically connected to the anode electrode of the first light-emitting element EL1.

[0119] The second switching element T2 can be connected between the second node n2 and the fourth node n4 and conduct in response to the gate-on voltage VGL of the second horizontal mode selection signal Px. When the second switching element T2 conducts, the second node n2 can be electrically connected to the fourth node n4.

[0120] The third switching element T3 can be connected between the third node n3 and the fourth node n4 and conduct in response to the gate-on voltage VGL of the bridging signal BR. When the third switching element T3 conducts, the third node n3 can be electrically connected to the fourth node n4.

[0121] The fourth switching element T4 can be connected between the fourth node n4 and the anode electrode of the second light-emitting element EL2 and conduct in response to the gate-on voltage VGL of the vertical mode selection signal Py. When the fourth switching element T4 conducts, the fourth node n4 can be electrically connected to the anode electrode of the second light-emitting element EL2.

[0122] Reference Figure 6 and 7 and, the first switching element T1 and the third switching element T3 can conduct in response to the bridging signal BR and the first horizontal mode selection signal Sx, and the second switching element T2 and the fourth switching element T4 can be in the off state (BR is on and Sx is on). In this case, the current from the driving element DT can be supplied to the first light-emitting element EL1 through the first switching element T1. In this case, the pixel can be driven in the first mode (S mode) so that the first light-emitting element EL1 can emit light.

[0123] The first switching element T1 and the fourth switching element T4 can be turned on in response to the vertical mode selection signal Py and the first horizontal mode selection signal Sx, and the second switching element T2 and the third switching element T3 can be in the off state (Py is on and Sx is on). In this case, the current from the driving element DT can be supplied to the first light-emitting element EL1 through the first switching element T1. In this case, the pixel can be driven in the first mode, the S mode, so that the first light-emitting element EL1 can emit light.

[0124] The second switching element T2 and the third switching element T3 can be turned on in response to the bridging signal BR and the second horizontal mode selection signal Px, and the first switching element T1 and the fourth switching element T4 can be in the off state (BR is on and Px is on). In this case, the current from the driving element DT can be supplied to the first light-emitting element EL1 through the second switching element T2 and the third switching element T3. In this case, the pixel can be driven in the first mode (S mode) so that the first light-emitting element EL1 can emit light.

[0125] The second switching element T2 and the fourth switching element T4 can be turned on in response to the vertical mode selection signal Py and the second horizontal mode selection signal Px, and the first switching element T1 and the third switching element T3 can be in the off state (Py is on and Px is on). In this case, the current from the driving element DT can be supplied to the second light-emitting element EL2 through the second switching element T2 and the fourth switching element T4. In this case, the pixel can be driven in the second mode, the P mode, so that the second light-emitting element EL2 emits light.

[0126] Figure 8 is a diagram showing an example of driving a window pixel region and a background pixel region in different viewing angle modes by a control method of a mode selection circuit shown by Figure 6 and 7 In the example of Figure 8 , the pixels in the background pixel region B can be driven in the first mode (S mode) to emit light with a narrow viewing angle, and the pixels in the window pixel region W can be driven in the second mode (P mode) to emit light with a wide viewing angle.

[0127] Figure 9 is a circuit diagram schematically showing a pixel circuit according to another embodiment of the present disclosure. In Figures 9 to 15 , components substantially the same as those in the above embodiment are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0128] Refer to Figures 9 to 11, the mode selection circuit SPM includes a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, and a fifth switching element T5. The switching elements T1, T2, T3, T4, and T5 can be implemented as p-channel transistors.

[0129] The first switching element T1 can be connected between the second node n2 and the third node n3 and turn on in response to the gate conduction voltage VGL of the first horizontal mode selection signal Sx. The second switching element T2 can be connected between the second node n2 and the fourth node n4 and turn on in response to the gate conduction voltage VGL of the second horizontal mode selection signal Px. The third switching element T3 can be connected between the third node n3 and the fourth node n4 and turn on in response to the gate conduction voltage VGL of the bridge signal BR. The fourth switching element T4 can be connected between the fourth node n4 and the anode electrode of the second light-emitting element EL2 and turn on in response to the gate conduction voltage VGL of the second vertical mode selection signal Py.

[0130] The fifth switching element T5 can be connected between the third node n3 and the anode electrode of the first light-emitting element EL1 and turn on in response to the gate conduction voltage VGL of the first vertical mode selection signal Sy. When the fifth switching element T5 is turned on, the third node n3 can be electrically connected to the anode electrode of the first light-emitting element EL1.

[0131] When the first mode (S mode) is the basic setting, as Figure 10 and 11 shown, the fifth switching element T5 can always be in the on state.

[0132] Referring to Figure 10 and 11 , the first switching element T1 and the third switching element T3 can turn on in response to the bridge signal BR and the first horizontal mode selection signal Sx, and the second switching element T2 and the fourth switching element T4 can be in the off state (BR is on and Sx is on). In this case, the fifth switching element T5 can be in the on state. In this case, the pixel can be driven in the first mode (S mode).

[0133] The first switching element T1 and the fourth switching element T4 can turn on in response to the second vertical mode selection signal Py and the first horizontal mode selection signal Sx, and the second switching element T2 and the third switching element T3 can be in the off state (Py is on and Sx is on). In this case, the fifth switching element T5 can be in the on state. In this case, the pixel can be driven in the first mode (S mode).

[0134] The second switching element T2 and the third switching element T3 can be turned on in response to the bridging signal BR and the second horizontal mode selection signal Px, and the first switching element T1 and the fourth switching element T4 can be in the off state (BR is on and Px is on). In this case, the fifth switching element T5 can be in the on state. In this case, the pixel can be driven in the first mode (S mode).

[0135] The second switching element T2 and the fourth switching element T4 can be turned on in response to the second vertical mode selection signal Py and the second horizontal mode selection signal Px, and the first switching element T1 and the third switching element T3 can be in the off state (Py is on and Px is on). In this case, the fifth switching element T5 can be in the on state. In this case, the pixel can be driven in the second mode (P mode), and as Figure 12 shown, the pixels in the window pixel region W can be driven in the second mode (P mode).

[0136] When the second mode (P mode) is the basic setting, as Figure 13 and 14 shown, the fourth switching element T4 can always be in the on state.

[0137] Refer to Figure 13 and 14 , the first switching element T1 and the fifth switching element T5 can be turned on in response to the first vertical mode selection signal Sy and the first horizontal mode selection signal Sx, and the second switching element T2 and the third switching element T3 can be in the off state (Sy is on and Sx is on). In this case, the fourth switching element T4 can be in the on state. In this case, the pixel can be driven in the first mode (S mode) like the window pixel region W as Figure 15 shown.

[0138] The first switching element T1 and the third switching element T3 can be turned on in response to the bridging signal BR and the first horizontal mode selection signal Sx, and the second switching element T2 and the fifth switching element T5 can be in the off state (BR is on and Sx is on). In this case, the fourth switching element T4 can be in the on state. In this case, the pixel can be driven in the second mode (P mode) like the background pixel region B as Figure 15 shown.

[0139] The second switching element T2 and the fifth switching element T5 can be turned on in response to the first vertical mode selection signal Sy and the second horizontal mode selection signal Px, and the first switching element T1 and the third switching element T3 can be off (Sy is on and Px is on). In this case, the fourth switching element T4 can be in the on state. In this case, the pixel can be driven like Figure 15Drive the pixel in a second mode (P mode) as in the background pixel region B shown.

[0140] The second switching element T2 and the third switching element T3 can be turned on in response to the bridging signal BR and the second horizontal mode selection signal Px, and the first switching element T1 and the fifth switching element T5 can be in an off state (BR is on and Px is on). In this case, the fourth switching element T4 can be in an on state. In this case, the pixel can be driven in a second mode (P mode) as in Figure 15 the background pixel region B shown.

[0141] Figure 16 is a circuit diagram showing an example of a pixel circuit to which Figure 4 and 6 the mode selection circuit shown is applied. Figure 17 is a waveform diagram showing an example of a gate signal and a mode selection signal input to the Figure 16 pixel circuit shown. In Figure 16 and 17 the detailed description of components that are substantially the same as those of the above-described embodiments will be omitted.

[0142] Refer to Figure 16 and 17 , the pixel circuit includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT, a capacitor Cst, a plurality of pixel switching elements M1 to M6, and a mode selection circuit SPM. The switching elements T1, T2, T3, and T4 of the driving element DT, the pixel switching elements M1 to M6, and the mode selection circuit SPM can be implemented as p-channel transistors, but are not limited thereto.

[0143] The pixel circuit is connected to a VDD node to which a pixel driving voltage VDD is applied, a VSS node to which a cathode voltage VSS is applied, and a REF node to which a reference voltage Vref is applied. The VDD node, the VSS node, and the REF node can be connected to corresponding power supply lines to be commonly connected to all pixels. The pixel circuit can be connected to a data line to which a data voltage Vdata is applied and gate lines to which gate signals SCAN1, SCAN2, and EM are applied. The mode selection circuit SPM can be connected to vertical mode lines and horizontal mode lines to which mode selection signals Sy, Py, Sx, and Px and a bridging signal BR are applied.

[0144] The pixel driving voltage VDD can be set to a voltage higher than the maximum voltage of the data voltage Vdata and allows the driving element DT to operate in the saturation region. The pixel driving voltage VDD is a voltage higher than the cathode voltage VSS. The reference voltage Vref can be set to a voltage lower than the minimum voltage of the data voltage Vdata and higher than or equal to the cathode voltage VSS. For example, the reference voltage Vref can be set to a voltage 1 to 2 V higher than the cathode voltage VSS, but is not limited thereto. The gate cut-off voltage VGH can be set to a voltage higher than the pixel driving voltage VDD, and the gate conduction voltage VGL can be set to a voltage lower than the cathode voltage VSS. For example, it can be VDD = 15 [V], VSS = 3 [V], Vref = 3 [V], VGH = 16 [V], and VGL = -9 [V], but is not limited thereto. The data voltage Vdata of the pixel data can have a dynamic range between 2 V and 7 V. The higher the gray level value of the pixel data, the lower the voltage level of the data voltage Vdata that can be selected. The higher the gray level value of the pixel data, the higher the brightness of the light-emitting elements EL1 and EL2.

[0145] The first light-emitting element EL1 includes an anode electrode connected to the third node n3 and a cathode electrode to which the cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode electrode connected to the fifth node n5 and a cathode electrode to which the cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by the current from the driving element DT and emit light in the first mode (S mode). The second light-emitting element EL2 can be driven by the current from the driving element DT and emit light in the second mode (P mode).

[0146] The driving element DT includes a first electrode to which the pixel driving voltage VDD is applied, a second electrode connected to the first node n1, and a gate electrode connected to the seventh node n7. The driving element DT generates the current required to drive the first light-emitting element EL1 and the second light-emitting element EL2 according to the gate-source voltage, which varies according to the data voltage Vdata. The capacitor Cst is connected between the sixth node n6 and the seventh node n7.

[0147] The first pixel switching element M1 is connected between the first node n1 and the second node n2 and conducts in response to the gate conduction voltage VGL of the EM signal EM. When the first pixel switching element M1 conducts, the first node n1 can be electrically connected to the second node n2. The first pixel switching element M1 includes a first electrode connected to the first node n1, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the second node n2. Note that M1 should not be confused with M01 in Figure 4 and Figure 9 M01 in

[0148] The second pixel switching element M2 is connected between the data line to which the pixel data is applied, i.e., the data voltage Vdata, and the sixth node n6, and is turned on in response to the gate conduction voltage VGL of the first scan signal SCAN1. When the second pixel switching element M2 is turned on, the data voltage Vdata can be applied to the sixth node n6. The second pixel switching element M2 includes a first electrode to which the data voltage Vdata is applied, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the sixth node n6.

[0149] The third pixel switching element M3 is connected between the first node n1 and the seventh node n7, and is turned on in response to the gate conduction voltage VGL of the second scan signal SCAN2. When the third pixel switching element M3 is turned on, the first node n1 can be electrically connected to the seventh node n7. The third pixel switching element M3 includes a first electrode connected to the first node n1, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the seventh node n7.

[0150] The fourth pixel switching element M4 is connected between the REF node to which the reference voltage Vref is applied and the third node n3, and is turned on in response to the gate conduction voltage VGL of the second scan signal SCAN2. When the fourth pixel switching element M4 is turned on, the reference voltage Vref can be applied to the third node n3. The fourth pixel switching element M4 includes a first electrode connected to the REF node, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0151] The fifth pixel switching element M5 is connected between the REF node to which the reference voltage Vref is applied and the fifth node n5, and is turned on in response to the gate conduction voltage VGL of the second scan signal SCAN2. When the fifth pixel switching element M5 is turned on, the reference voltage Vref can be applied to the fifth node n5. The fifth pixel switching element M5 includes a first electrode connected to the REF node, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0152] The sixth pixel switching element M6 is connected between the REF node to which the reference voltage Vref is applied and the sixth node n6, and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the sixth pixel switching element M6 is turned on, the reference voltage Vref can be applied to the sixth node n6. The sixth pixel switching element M6 includes a first electrode connected to the REF node, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the sixth node n6.

[0153] The mode selection circuit SPM is the same as Figure 6 the circuit shown.

[0154] When the first switching element T1 is turned on, the second node n2 can be electrically connected to the anode electrode of the first light-emitting element EL1. The first switching element T1 includes a first electrode connected to the second node n2, a gate electrode to which a first horizontal mode selection signal Sx is applied, and a second electrode connected to the third node n3. When the second switching element T2 is turned on, the second node n2 can be electrically connected to the fourth node n4. The second switching element T2 includes a first electrode connected to the second node n2, a gate electrode to which a second horizontal mode selection signal Px is applied, and a second electrode connected to the fourth node n4.

[0155] When the third switching element T3 is turned on, the third node n3 can be electrically connected to the fourth node n4. The third switching element T3 includes a first electrode connected to the third node n3, a gate electrode to which a bridging signal BR is applied, and a second electrode connected to the fourth node n4. When the fourth switching element T4 is turned on, the fourth node n4 can be electrically connected to the anode electrode of the second light-emitting element EL2. The fourth switching element T4 includes a first electrode connected to the fourth node n4, a gate electrode to which a vertical mode selection signal Py is applied, and a second electrode connected to the fifth node n5.

[0156] Figure 18 is a circuit diagram showing an example of a pixel circuit to which the Figure 9 shown mode selection circuit is applied. Figure 19A and 19B is a waveform diagram showing an example of the gate signal and the mode selection signal input to the Figure 18 shown pixel circuit. Referring to Figures 18 to 19B , a detailed description of components that are substantially the same as those of the above-described embodiment will be omitted.

[0157] Referring to Figure 18 , the mode selection circuit SPM of the pixel circuit PIX is substantially the same as the Figure 10 shown circuit.

[0158] The mode selection circuit SPM of the pixel circuit further includes a fifth switching element T5. When the fifth switching element T5 is turned on, the third node n3 can be electrically connected to the anode electrode of the first light-emitting element EL1. The fifth switching element T5 includes a first electrode connected to the third node n3, a gate electrode to which a first vertical mode selection signal Sy is applied, and a second electrode connected to the anode electrode of the first light-emitting element EL1.

[0159] When the first mode (S mode) is the basic setting, the first vertical mode selection signal Sy can be set to the gate-on voltage VGL, as Figure 19A shown. In this case, the fifth switching element T5 can be in a normally-on state.

[0160] When the second mode (P mode) is the basic setting, the second vertical mode selection signal Py can be set to the gate-on voltage VGL, as Figure 19B shown. In this case, the fourth switching element T4 can be in a constantly-on state.

[0161] The pixel circuit PIX can be driven by an initialization phase, a data writing and threshold voltage sampling phase, and a light emitting phase. Hereinafter, the operation of the pixel circuit PIX will be described in detail.

[0162] Figures 20A to 22B is a diagram showing Figure 16 the initialization phase, the data writing and threshold voltage sampling phase, and the light emitting phase of the pixel circuit shown. The initialization phase, the data writing and threshold voltage sampling phase, and the light emitting phase of the pixel circuit are substantially the same as those of the pixel circuit shown in Figure 18 For example, the gate signals SCAN1, SCAN2, and EM can be applied in the same way to the pixel circuits shown in Figure 16 and 18 . The time for performing the initialization phase, the data writing and threshold voltage sampling phase, and the light emitting phase can be controlled by the waveforms of the gate signals SCAN1, SCAN2, and EM. In this pixel circuit, the switching elements T1 to T4 of the mode selection circuit SPM are controlled by the mode selection signals Py, Sx, and Px and the bridging signal BR shown in Figure 7 and 17 . The operation of the mode selection circuit SPM is basically the same as that of the embodiment shown in Figures 6 to 18 above, and thus the description thereof will be omitted.

[0163] Figure 20A and 20B are a waveform diagram and a circuit diagram showing the initialization phase of the pixel circuit shown in Figure 16 respectively. The initialization phase can be performed during the first period INI.

[0164] Referring to Figure 20A and Figure 20B , during the first period INI, the voltage of the first scan signal SCAN1 is the gate-off voltage VGH, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate-on voltage VGL. The third pixel switching element M3, the fourth pixel switching element M4, the fifth pixel switching element M5, and the sixth pixel switching element M6 are turned on during the first period INI. The second pixel switching element M2 is turned off during the first period INI. The driving element DT is turned on during the first period INI.

[0165] During the first period INI, as shown in Figure 17As shown, it can be the gate turn-on voltage VGL of the first horizontal mode selection signal Sx. Therefore, the reference voltage Vref can be applied to the second node n2 through the first switching element T1 during the first period INI.

[0166] During the first period INI, the capacitor Cst and the light-emitting elements EL1 and EL2 are initialized to the reference voltage Vref. During the first period INI, the light-emitting elements EL1 and EL2 are turned off.

[0167] Figure 21A and 21B respectively show Figure 16 The waveform diagram and circuit diagram of the data writing and threshold voltage sampling phases of the pixel circuit shown. The data writing and threshold voltage sampling phases are executed during the second period DWR.

[0168] Refer to Figure 21A and 21B , during the second period DWR, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate turn-on voltage VGL, and the voltage of the EM signal EM is the gate cut-off voltage VGH. During the second period DWR, the second pixel switching element M2, the third pixel switching element M3, the fourth pixel switching element M4, and the fifth pixel switching element M5 are turned on, and the sixth pixel switching element M6 is turned off. During the second period DWR, the data voltage Vdata of the pixel data is applied to the sixth node n6. At the end of the second period DWR, the voltage of the sixth node n6 is the data voltage Vdata, and the voltage of the seventh node n7 is VDD + Vth. Here, Vth is the threshold voltage of the driving element DT. During the second period DWR, the light-emitting elements EL1 and EL2 are in the off state.

[0169] Figure 22A and 22B respectively show Figure 16 The waveform diagram and circuit diagram of the light-emitting phase of the pixel circuit shown. The light-emitting phase is executed during the third period EMI.

[0170] Refer to Figure 22A and 22B , during the third period EMI, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 are the gate cut-off voltage VGH, and the voltage of the EM signal EM is the gate turn-on voltage VGL. The sixth pixel switching element M6 is turned on during the third period EMI, while the second pixel switching element M2, the third pixel switching element M3, the fourth pixel switching element M4, and the fifth pixel switching element M5 are turned off. When the third period EMI in the first mode (S mode) ends, the voltage of the sixth node n6 is the reference voltage Vref, and the voltage of the seventh node n7 is Vref – Vdata + VDD + Vth.

[0171] During the third period EMI, the current generated according to the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 or the second light-emitting element EL2 through the mode selection circuit SPM. Therefore, according to Figure 6 , 7 and the on / off states of the switching elements T1, T2, T3, and T4 shown in FIG. 17, during the third period EMI, one of the first light-emitting element EL1 and the second light-emitting element EL2 can emit light and conduct, while the other can be in an off state.

[0172] Figure 23 is a circuit diagram showing another example of a pixel circuit to which the Figure 4 and 6 shown mode selection circuit is applied. The pixel circuit according to the present embodiment can be driven at a variable refresh rate (VRR) under the control of the timing controller 130. The timing controller 130 can reduce the power consumption of the display device by analyzing the input image and reducing the refresh rate when the input image does not change within a predetermined time. When the display device operates in the standby mode or in response to a user command, the timing controller 130 can reduce the refresh rate of the pixels. In the always-on display (AOD) screen, the refresh rate can be reduced. The AOD screen is a partial pixel area of the display area AA, where preset information, such as brief information such as the remaining battery capacity, time, etc., is displayed in the standby mode. In Figure 23 , a detailed description of components that are substantially the same as those of the above-described embodiment will be omitted.

[0173] Referring to Figure 23 , the pixel circuit includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT, a capacitor Cst, a plurality of pixel switching elements M31 to M38, and a plurality of switching elements T1, T2, T3, and T4. The driving element DT, the pixel switching elements M31, M32, M34, M35, M37, and M38, and the switching elements T1, T2, T3, and T4 can be implemented as p-channel transistors. The third pixel switching element M33 and the sixth pixel switching element M36 can be implemented as n-channel transistors. The p-channel transistor can conduct in response to a low gate voltage VGL and can be cut off in response to a high gate voltage VGH. The n-channel transistor can conduct in response to a high gate voltage VGH and can be cut off in response to a low gate voltage VGL.

[0174] The pixel circuit can be connected to a VDD node to which a pixel driving voltage VDD is applied, a VSS node to which a cathode voltage VSS is applied, a REF node to which a reference voltage Vref is applied, an INI node to which an initialization voltage Vini is applied, an OBS node to which a first compensation voltage VOBS is applied, and an AR node to which a second compensation voltage VAR is applied. The VDD node, VSS node, REF node, INI node, OBS node, and AR node can be connected to corresponding power supply lines to be commonly connected to all pixels. The pixel circuit can be connected to a data line to which a data voltage Vdata is applied and gate lines to which gate signals SCAN1, SCAN2, SCAN3, SCAN4, and EM are applied. The mode selection circuit SPM can be connected to vertical mode lines and horizontal mode lines to which mode selection signals Sy, Py, Sx, and Px and a bridging signal BR are applied. The mode selection circuit SPM is substantially the same as Figure 6 the circuit shown.

[0175] The first light-emitting element EL1 includes an anode electrode connected to the third node n3 and a cathode electrode to which the cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode electrode connected to the fifth node n35 and a cathode electrode to which the cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by a current from the driving element DT to emit light in a first mode (S mode). The second light-emitting element EL2 can be driven by a current from the driving element DT to emit light in a second mode (P mode).

[0176] The driving element DT includes a first electrode connected to the sixth node n36, a second electrode connected to the first node n31, and a gate electrode connected to the seventh node n37. The driving element DT generates a current required to drive the first light-emitting element EL1 and the second light-emitting element EL2 according to a gate-source voltage that varies according to the data voltage Vdata. A capacitor Cst is connected between the VDD node and the seventh node n37.

[0177] The first pixel switching element M31 is connected between the first node n31 and the second node n2 and turns on in response to a low gate voltage VGL of the EM signal EM. When the first pixel switching element M31 is turned on, the first node n31 can be electrically connected to the second node n2. The first pixel switching element M31 includes a first electrode connected to the first node n31, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the second node n2.

[0178] The second pixel switching element M32 is connected between the data line to which the pixel data's data voltage Vdata is applied and the sixth node n36, and is turned on in response to the gate low voltage VGL of the second scan signal SCAN2. When the second pixel switching element M32 is turned on, the data voltage Vdata can be applied to the sixth node n36. The second pixel switching element M32 includes a first electrode to which the data voltage Vdata is applied, a gate electrode to which the second scan signal SCAN2 is applied, and a second electrode connected to the sixth node n36.

[0179] The third pixel switching element M33 is connected between the first node n31 and the seventh node n37, and is turned on in response to the gate high voltage VGH of the first scan signal SCAN1. When the third pixel switching element M33 is turned on, the first node n31 can be electrically connected to the seventh node n37. The third pixel switching element M33 includes a first electrode connected to the first node n31, a gate electrode to which the first scan signal SCAN1 is applied, and a second electrode connected to the seventh node n37.

[0180] The fourth pixel switching element M34 is connected between the AR node to which the second compensation voltage VAR is applied and the third node n3, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the fourth pixel switching element M34 is turned on, the second compensation voltage VAR can be applied to the third node n3. The fourth pixel switching element M34 includes a first electrode connected to the AR node to which the second compensation voltage VAR is applied, a gate electrode to which the third scan signal SCAN3 is applied, and a second electrode connected to the third node n3.

[0181] The fifth pixel switching element M35 is connected between the AR node to which the second compensation voltage VAR is applied and the fifth node n35, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the fifth pixel switching element M35 is turned on, the second compensation voltage VAR can be applied to the fifth node n35. The fifth pixel switching element M35 includes a first electrode to which the second compensation voltage VAR is applied, a gate electrode to which the third scan signal SCAN3 is applied, and a second electrode connected to the fifth node n35.

[0182] The sixth pixel switching element M36 is connected between the INI node to which the initialization voltage Vini is applied and the seventh node n37, and is turned on in response to the gate high voltage VGH of the fourth scan signal SCAN4. When the sixth pixel switching element M36 is turned on, the initialization voltage Vini can be applied to the seventh node n37. The sixth pixel switching element M36 includes a first electrode to which the initialization voltage Vini is applied, a gate electrode to which the fourth scan signal SCAN4 is applied, and a second electrode connected to the seventh node n37.

[0183] The seventh pixel switching element M37 is connected between the VDD node to which the pixel driving voltage VDD is applied and the sixth node n36, and is turned on in response to the gate low voltage VGL of the EM signal EM. When the seventh pixel switching element M37 is turned on, the pixel driving voltage VDD can be applied to the sixth node n36. The seventh pixel switching element M37 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the sixth node n36.

[0184] The eighth pixel switching element M38 is connected between the OBS node to which the first compensation voltage VOBS is applied and the sixth node n36, and is turned on in response to the gate low voltage VGL of the third scan signal SCAN3. When the eighth pixel switching element M38 is turned on, the first compensation voltage VOBS can be applied to the sixth node n36. The eighth pixel switching element M38 includes a first electrode to which the first compensation voltage VOBS is applied, a gate electrode to which the third scan signal SCAN3 is applied, and a second electrode connected to the sixth node n36.

[0185] Figures 24A to 28B is a diagram showing Figure 23 the first reset phase, initialization phase, data writing and threshold voltage sampling phase, second reset phase, and light emission phase of the pixel circuit shown.

[0186] Figure 24A and Figure 24B are respectively a waveform diagram and a circuit diagram showing Figure 23 the first reset phase of the pixel circuit shown. The first reset phase is executed during the first time period RS1.

[0187] Referring to Figure 24A and 24B , during the first time period RS1, the voltages of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate high voltage VGH.

[0188] During the first time period RS1, the fourth pixel switching element M34, the fifth pixel switching element M35, and the eighth pixel switching element M38 are turned on, while the other pixel switching elements M31, M32, M33, M36, and M37 are turned off. During the first time period RS1, the first compensation voltage VOBS is applied to the sixth node n36 to turn on the driving element DT. During the first time period RS1, the second compensation voltage VAR is applied to the third node n33 and the fifth node n35 through the turned-on fourth pixel switching element M34 and fifth pixel switching element M35. The light emitting elements EL1 and EL2 are in the off state.

[0189] Figure 25A and 25B are waveform diagrams and circuit diagrams showing the initialization phase of the pixel circuit shown in Figure 23 The initialization phase is executed during the second period INI.

[0190] Refer to Figure 25A and 25B , during the second period INI, the voltages of the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the EM signal EM are the gate high voltage VGH.

[0191] During the second period INI, the third pixel switch element M33 and the sixth pixel switch element M36 are turned on, while the other pixel switch elements M31, M32, M34, M35, M37, and M38 are turned off. During the second period INI, an initialization voltage Vini is applied to the seventh node n37 to initialize the capacitor Cst. During the second period INI, the light-emitting elements EL1 and EL2 are in the off state.

[0192] Figure 26A and 26B are waveform diagrams and circuit diagrams showing the data writing and threshold voltage sampling phases of the pixel circuit shown in Figure 23 The data writing and threshold voltage sampling phases are executed during the third period DWR.

[0193] Refer to Figure 26A and 26B , during the third period DWR, the voltages of the first scan signal SCAN1 and the third scan signal SCAN3 are the gate high voltage VGH, and the voltages of the second scan signal SCAN2 and the fourth scan signal SCAN4 are the gate low voltage VGL. During the third period DWR, the voltage of the EM signal EM is the gate high voltage VGH.

[0194] During the third period DWR, the second pixel switch element M32 and the third pixel switch element M33 are turned on, while the other pixel switch elements M31, M34, M35, M36, M37, and M38 are turned off. At the end of the third period DWR, the voltages of the first node n31 and the sixth node n36 are the data voltage Vdata, and the voltage of the seventh node n37 is the voltage of Vdata + Vth. Here, Vth is the threshold voltage of the driving element DT. During the third period DWR, the light-emitting elements EL1 and EL2 are in the off state.

[0195] Figure 27A and 27B are waveform diagrams and circuit diagrams showing the Figure 23Waveform diagram and circuit diagram of the second reset phase of the pixel circuit shown. The second reset phase is executed during the fourth period RS2.

[0196] Reference Figure 27A and Figure 27B , during the fourth period RS2, the voltages of the first scan signal SCAN1, the third scan signal SCAN3, and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the EM signal EM are the gate high voltage VGH.

[0197] During the fourth period RS2, the fourth pixel switch element M34, the fifth pixel switch element M35, and the eighth pixel switch element M38 are turned on, while the other pixel switch elements M31, M32, M33, M36, and M37 are turned off. During the fourth period RS2, the first compensation voltage VOBS is applied to the sixth node n36 to turn on the driving element DT. During the fourth period RS2, the second compensation voltage VAR is applied to the third node n3 and the fifth node n35. During the fourth period RS2, the light-emitting elements EL1 and EL2 are in the off state.

[0198] Figure 28A and 28B respectively show Figure 23 Waveform diagram and circuit diagram of the light-emitting phase of the pixel circuit shown. The light-emitting phase is executed during the fifth period EMI.

[0199] Reference Figure 28A and 28B , during the fifth period EMI, the voltages of the first scan signal SCAN1 and the fourth scan signal SCAN4 are the gate low voltage VGL, and the voltages of the second scan signal SCAN2 and the third scan signal SCAN3 are the gate high voltage VGH. During the fifth period EMI, the voltage of the EM signal EM is the gate low voltage VGL. During the fifth period EMI, the first pixel switch element M31 and the seventh pixel switch element M37 are turned on, while the other pixel switch elements M32, M33, M34, M35, M36, and M38 are turned off.

[0200] In the fifth period EMI, the current generated by the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 or the second light-emitting element EL2 through the mode selection circuit SPM. Therefore, according to the on / off states of the switching elements T1, T2, T3, and T4, during the fifth period EMI, the first light-emitting element EL1 or the second light-emitting element EL2 can be lit by emitting light, and the other can be in the off state.

[0201] Figure 29 shows the application of Figure 4 and 6Another example circuit of the pixel circuit of the mode selection circuit shown. The mode selection circuit SPM of this pixel circuit is substantially the same as the embodiment described above in Figure 6 and 7 .

[0202] Referring to Figure 29 , the pixel circuit includes a first light-emitting element EL1, a second light-emitting element EL2, a driving element DT for driving the light-emitting elements EL1 and EL2, a plurality of pixel switching elements M41 to M46, and a plurality of switching elements T1, T2, T3, and T4. The driving element DT, the pixel switching elements M41 to M46, and the switching elements T1, T2, T3, and T4 can be implemented as, but not limited to, p-channel transistors.

[0203] The first light-emitting element EL1 includes an anode electrode connected to the third electrode n3 and a cathode electrode to which a cathode voltage VSS is applied. The second light-emitting element EL2 includes an anode electrode connected to the fifth node n45 and a cathode electrode to which a cathode voltage VSS is applied. The first light-emitting element EL1 can be driven by a current from the driving element DT to emit light in a first mode (S mode). The second light-emitting element EL2 can be driven by a current from the driving element DT to emit light in a second mode (P mode).

[0204] The driving element DT includes a first electrode connected to the sixth node n46, a second electrode connected to the first node n41, and a gate electrode connected to the seventh node n47. The driving element DT generates a current required to drive the first light-emitting element EL1 and the second light-emitting element EL2 according to the gate-source voltage that varies with the data voltage Vdata. A capacitor Cst is connected between the VDD node and the seventh node n47.

[0205] The first pixel switching element M41 is connected between the first node n41 and the second node n2 and conducts in response to the gate conduction voltage VGL of the EM signal EM. When the first pixel switching element M41 conducts, the first node n41 can be electrically connected to the second node n2. The first pixel switching element M41 includes a first electrode connected to the first node n41, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the second node n2.

[0206] The second pixel switching element M42 is connected between the data line to which the pixel data's data voltage Vdata is applied and the sixth node n46, and is turned on in response to the gate conduction voltage VGL of the N-th scan signal SCAN(N), where N is a natural number. When the second switching element M42 is turned on, the data voltage Vdata can be applied to the sixth node n46. The second pixel switching element M42 includes a first electrode to which the data voltage Vdata is applied, a gate electrode to which the N-th scan signal SCAN(N) is applied, and a second electrode connected to the sixth node n46.

[0207] The third pixel switching element M43 is connected between the first node n41 and the seventh node n47, and is turned on in response to the gate conduction voltage VGL of the N-th scan signal SCAN(N). When the third pixel switching element M43 is turned on, the first node n41 can be electrically connected to the seventh node n47. The third pixel switching element M43 includes a first electrode connected to the first node n41, a gate electrode to which the N-th scan signal SCAN(N) is applied, and a second electrode connected to the seventh node n47.

[0208] The fourth pixel switching element M44 is connected between the INI node to which the initialization voltage Vini is applied and the third node n3, and is turned on in response to the gate conduction voltage VGL of the (N - 1)-th scan signal SCAN(N - 1). When the fourth pixel switching element M44 is turned on, the third node n3 can be initialized to the initialization voltage Vini. The fourth pixel switching element M44 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate electrode to which the (N - 1)-th scan signal SCAN(N - 1) is applied, and a second electrode connected to the third node n3.

[0209] The fifth pixel switching element M45 is connected between the INI node to which the initialization voltage Vini is applied and the fifth node n45, and is turned on in response to the gate conduction voltage VGL of the (N - 1)-th scan signal SCAN(N - 1). When the fifth pixel switching element M45 is turned on, the fifth node n45 can be initialized to the initialization voltage Vini. The fifth pixel switching element M45 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate electrode to which the (N - 1)-th scan signal SCAN(N - 1) is applied, and a second electrode connected to the fifth node n45.

[0210] The sixth pixel switching element M46 is connected between the INI node to which the initialization voltage Vini is applied and the seventh node n47, and is turned on in response to the gate-on voltage VGL of the (N-1)th scan signal SCAN(N-1). When the sixth pixel switching element M46 is turned on, the capacitor Cst can be initialized. The sixth pixel switching element M46 includes a first electrode connected to the INI node to which the initialization voltage Vini is applied, a gate electrode to which the (N-1)th scan signal SCAN(N-1) is applied, and a second electrode connected to the seventh node n47.

[0211] The seventh pixel switching element M47 is connected between the VDD node to which the pixel driving voltage is applied and the sixth node n46, and is turned on in response to the gate-on voltage VGL of the EM signal EM. When the seventh pixel switching element M47 is turned on, a current path is formed between the VDD node and the driving element DT. The seventh pixel switching element M47 includes a first electrode connected to the VDD node to which the pixel driving voltage VDD is applied, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the sixth node n46.

[0212] Figure 29 The pixel circuit shown can be driven by an initialization stage, a data writing and threshold voltage sampling stage, and a light emitting stage. Figures 30A to 32B is a diagram showing Figure 29 the initialization stage, the data writing and threshold voltage sampling stage, and the light emitting stage of the pixel circuit shown.

[0213] Figure 30A and 30B are respectively a waveform diagram and a circuit diagram showing Figure 29 the initialization stage of the pixel circuit shown. The initialization stage is executed during the first period INI.

[0214] Refer to Figure 30A and 30B , during the first period INI, the voltage of the (N-1)th scan signal SCAN(N-1) is the gate-on voltage VGL, and the voltages of the Nth scan signal SCAN(N) and the EM signal EM are the gate-off voltage VGH.

[0215] During the first interval INI, the fourth pixel switching element M44, the fifth pixel switching element M45, and the sixth pixel switching element M46 are turned on, while the other pixel switching elements M41, M42, M43, and M47 are turned off. During the first period INI, the driving element DT is turned on. During the first period INI, the capacitor Cst and the light emitting elements EL1 and EL2 are initialized. During the first period INI, the light emitting elements EL1 and EL2 are in the off state and do not emit light.

[0216] Figure 31A and 31B are a waveform diagram and a circuit diagram showing the data writing and threshold voltage sampling phases of the pixel circuit in Figure 29 respectively. The data writing and threshold voltage sampling phases are performed during the second period DWR.

[0217] Refer to Figure 31A and 31B . During the second period DWR, the voltage of the Nth scan signal SCAN(N) is the gate-on voltage VGL, and the voltages of the (N - 1)th scan signal SCAN(N - 1) and the EM signal EM are the gate-off voltage VGH. During the second period DWR, the second pixel switching element M42 and the third pixel switching element M43 are turned on, while the other pixel switching elements M41, M44, M45, M46, and M47 are turned off. During the second period DWR, the data voltage Vdata of the pixel data is applied to the sixth node n46.

[0218] Figure 32A and 32B are a waveform diagram and a circuit diagram showing the light emission phase of the pixel circuit shown in Figure 29 respectively.

[0219] Refer to Figure 32A and 32B . During the second period EMI, the voltages of the scan signals SCAN(N - 1) and SCAN(N) are the gate-off voltage VGH, and the voltage of the EM signal EM is the gate-on voltage VGL. During the third period EMI, the first pixel switching element M41 and the seventh pixel switching element M47 are turned on, while the other pixel switching elements M42, M43, M44, M45, and M46 are turned off.

[0220] During the third period EMI, the current generated by the gate-source voltage of the driving element DT is supplied to the first light-emitting element EL1 or the second light-emitting element EL2 through the mode selection circuit SPM. Therefore, according to the on / off states of the switching elements T1, T2, T3, and T4, during the third period EMI, one of the first light-emitting element EL1 and the second light-emitting element EL2 can be lit by light emission, and the other can be in an off state.

[0221] Figure 33 is a circuit diagram showing another example of a pixel circuit to which the Figure 4 and 6 shown mode selection circuit is applied. The gate signals SCAN(N - 1), SCAN(N), and EM input to this pixel circuit and the mode selection circuit are basically the same as those in Figure 30A , 31B and 32B. The mode selection circuit SPM of this pixel circuit is the same as that above inFigure 6 and 7 is substantially the same as the embodiment described in. In this embodiment, components substantially the same as those of the above Figures 29 to 32B pixel circuit are denoted by the same reference numerals and will not be described in detail.

[0222] Referring to Figure 33 , the driving element DT includes a first electrode connected to the sixth node n46, a second electrode connected to the first node n41, and a gate electrode connected to the seventh node n47. The capacitor Cst is connected between the eighth node n48, to which the pixel driving voltage VDD is applied through the eighth pixel switching element M48, and the seventh node n47. The capacitor Cst is connected between the seventh node n47 and the eighth node n48.

[0223] The seventh pixel switching element M47 is connected between the sixth node n46 and the eighth node n48 and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the seventh pixel switching element M47 is turned on, the eighth node n48 can be electrically connected to the sixth node n46 to form a current path between the VDD node and the driving element DT. The seventh pixel switching element M47 includes a first electrode connected to the eighth node n48, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the sixth node n46.

[0224] The eighth pixel switching element M48 is connected between the VDD node, to which the pixel driving voltage is applied, and the eighth node n48 and is turned on in response to the gate conduction voltage VGL of the EM signal EM. When the eighth pixel switching element M48 is turned on, the VDD node can be electrically connected to the eighth node n48. The eighth pixel switching element M48 includes a first electrode connected to the VDD node, to which the pixel driving voltage VDD is applied, a gate electrode to which the EM signal EM is applied, and a second electrode connected to the eighth node n48.

[0225] The ninth pixel switching element M49 is connected between the REF node, to which the reference voltage Vref is applied, and the eighth node n48 and is turned on in response to the gate conduction voltage VGL of the (N - 1)th scan signal SCAN(N - 1). When the ninth pixel switching element M49 is turned on, the reference voltage Vref is applied to the eighth node n48. The ninth pixel switching element M49 includes a first electrode connected to the REF node, to which the reference voltage Vref is applied, a gate electrode to which the (N - 1)th scan signal SCAN(N - 1) is applied, and a second electrode connected to the eighth node n48.

[0226] The tenth pixel switching element M50 is connected between the REF node to which the reference voltage Vref is applied and the eighth node n48, and is turned on in response to the gate-on voltage VGL of the Nth scan signal SCAN(N). When the tenth pixel switching element M50 is turned on, the reference voltage Vref is applied to the eighth node n48. The tenth pixel switching element M50 includes a first electrode connected to the REF node to which the reference voltage Vref is applied, a gate electrode to which the Nth scan signal SCAN(N) is applied, and a second electrode connected to the eighth node n48.

[0227] Figure 33 The pixel circuit shown can be driven by an initialization phase, a data writing and threshold voltage sampling phase, and a light emitting phase. Figures 34 to 36 It is shown Figure 33 a diagram showing the initialization phase, the data writing and threshold voltage sampling phase, and the light emitting phase of the pixel circuit shown.

[0228] Refer to Figure 30A and 34 During the first period INI, the initialization phase of the pixel circuit is executed. During the first period INI, the voltage of the (N - 1)th scan signal SCAN(N - 1) is the gate-on voltage VGL, and the voltages of the Nth scan signal SCAN(N) and the EM signal EM are the gate-off voltage VGH. In this case, the fourth pixel switching element M44, the fifth pixel switching element M45, the sixth pixel switching element M46, and the ninth pixel switching element M49 are turned on, while the other pixel switching elements M41, M42, M43, M47, M48, and M50 are turned off. During the first period INI, the driving element DT is turned on. During the first period INI, the capacitor Cst and the light emitting elements EL1 and EL2 are initialized. During the first period INI, the light emitting elements EL1 and EL2 are in the off state.

[0229] Refer to Figure 31A and 35 During the second period DWR, the data writing and threshold voltage sampling phase of the pixel circuit is executed. During the second period DWR, the voltage of the Nth scan signal SCAN(N) is the gate-on voltage VGL, and the voltages of the (N - 1)th scan signal SCAN(N - 1) and the EM signal EM are the gate-off voltage VGH. During the second period DWR, the second pixel switching element M42, the third pixel switching element M43, and the tenth pixel switching element M50 are turned on, while the other pixel switching elements M41, M44, M45, M46, M47, M48, and M49 are turned off. The data voltage Vdata of the pixel data is applied to the sixth node n46.

[0230] Refer to Figure 32A and Figure 36, the light emitting phase of the pixel circuit is performed during the third period EMI. During the third period EMI, the voltages of the scan signals SCAN(N-1) and SCAN(N) are the gate-off voltage VGH, and the voltage of the EM signal EM is the gate-on voltage VGL. During the third period EMI, the first pixel switch element M41, the seventh pixel switch element M47, and the eighth pixel switch element M48 are turned on, while the other pixel switch elements M42, M43, M44, M45, M46, M49, and M50 are turned off. During the third period EMI, the current generated by the gate-source voltage of the driving element DT is supplied to the first light emitting element EL1 or the second light emitting element EL2 through the mode selection circuit SPM.

[0231] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation, vehicle navigation, vehicle display devices, vehicle equipment, theater equipment, theater display devices, televisions, wallpaper devices, sign devices, game devices, laptop computers, monitors, cameras, video cameras, and household appliances, etc. The display device according to one or more embodiments of the present disclosure can be applied to an organic light emitting lighting device or an inorganic light emitting lighting device.

[0232] The objects to be achieved by the present disclosure, the means for achieving the above objects of the present disclosure, and the effects do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0233] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display panel, comprising: Multiple sub-pixels, Wherein, each of the sub-pixels comprises: a driving element configured to generate an electric current; a first light emitting element configured to emit light by a current from the driving element; a second light emitting element configured to emit light by the current from the driving element; and The mode selection circuit is configured to switch a current path from the driving element in response to a first horizontal mode selection signal, a second horizontal mode selection signal, a first vertical mode selection signal, and a bridge signal. 2 . The display panel of claim 1 , wherein the first horizontal mode selection signal, the second horizontal mode selection signal, the first vertical mode selection signal, and the bridge signal are operable to select a viewing angle of each sub-pixel.

3. The display panel according to claim 1 or 2, further comprising: a first pixel switching element connected to the driving element via a first node and to the mode selection circuit via a second node; as well as Wherein, the mode selection circuit comprises: a first switching element configured to be turned on in response to a gate-on voltage of the first horizontal mode selection signal to electrically connect the second node to a third node; a second switching element configured to be turned on in response to a gate-on voltage of the second horizontal mode selection signal to electrically connect the second node to a fourth node; a third switching element configured to be turned on in response to a gate-on voltage of the bridge signal to electrically connect the third node to the fourth node; and A fourth switching element is configured to be turned on in response to a gate-on voltage of the first vertical mode selection signal to electrically connect the fourth node to the anode electrode of the second light emitting element.

4. The display panel according to claim 3, wherein: An anode electrode of the first light emitting element is connected to the third node.

5. The display panel according to claim 3 or 4, wherein: When the first switch element and the third switch element are turned on, and the second switch element and the fourth switch element are in the off state, the sub-pixel is driven in a first mode, When the first switching element and the fourth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel is driven in the first mode, When the second switching element and the third switching element are turned on, and the first switching element and the fourth switching element are in the off state, the sub-pixel is driven in the first mode, and When the second switching element and the fourth switching element are turned on, and the first switching element and the third switching element are in an off state, the sub-pixel is driven in a second mode.

6. The display panel according to claim 5, wherein: A viewing angle of a sub-pixel driven in the first mode is greater than a viewing angle of the sub-pixel driven in the second mode.

7. The display panel according to any one of claims 3 to 6, wherein: The mode selection circuit further comprises: A fifth switching element is configured to be turned on in response to a gate-on voltage of a second vertical mode selection signal to electrically connect the third node to the anode electrode of the first light emitting element.

8. The display panel according to claim 7, wherein: When the first switching element, the third switching element, and the fifth switching element are turned on, and the second switching element and the fourth switching element are in the off state, the sub-pixel is driven in the first mode, When the first switching element, the fourth switching element and the fifth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel is driven in the first mode, When the second switching element, the third switching element and the fifth switching element are turned on, and the first switching element and the fourth switching element are in the off state, the sub-pixel is driven in the first mode, and When the second switching element, the fourth switching element, and the fifth switching element are turned on, and the first switching element and the third switching element are in an off state, the sub-pixel is driven in the second mode.

9. The display panel according to claim 7, wherein: When the first switching element, the fourth switching element and the fifth switching element are turned on, and the second switching element and the third switching element are in the off state, the sub-pixel is driven in the first mode, When the first switching element, the third switching element and the fourth switching element are turned on, and the second switching element and the fifth switching element are in the off state, the sub-pixel is driven in the second mode, When the second switching element, the fourth switching element and the fifth switching element are turned on, and the first switching element and the third switching element are in the off state, the sub-pixel is driven in the second mode, and When the second switching element, the third switching element, and the fourth switching element are turned on, and the first switching element and the fifth switching element are in an off state, the sub-pixel is driven in the second mode.

10. The display panel according to claim 8 or 9, wherein: A viewing angle of a sub-pixel driven in the first mode is greater than a viewing angle of the sub-pixel driven in the second mode.

11. The display panel according to claim 3 or 7, wherein: Each of the sub-pixels further comprises: a capacitor connected between the sixth node and the seventh node; a second pixel switching element connected between a data line arranged to be applied with a data voltage having pixel data and the sixth node, the second pixel switching element being arranged to be turned on in response to a gate-on voltage of the first scanning signal; a third pixel switching element connected between the first node and the seventh node to be turned on in response to a gate-on voltage of a second scanning signal; a fourth pixel switching element connected between a REF node arranged to be applied with a reference voltage and an anode electrode of the first light emitting element, the fourth pixel switching element being arranged to be turned on in response to a gate-on voltage of the second scanning signal; a fifth pixel switching element connected between the REF node and the anode electrode of the second light emitting element to be turned on in response to the gate-on voltage of the second scanning signal; and a sixth pixel switching element connected between the REF node and the sixth node to be turned on in response to a gate-on voltage of a light emitting signal, and wherein the first pixel switch element is connected between the first node and the second node to be turned on in response to a gate-on voltage of the light emitting signal, and The driving element includes a first electrode arranged to be applied with a pixel driving voltage, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

12. The display panel according to claim 3 or 7, wherein: Each of the sub-pixels further comprises: a capacitor connected between a VDD node arranged to be applied with the pixel driving voltage and the seventh node; a second pixel switching element connected between a data line arranged to be applied with a data voltage of pixel data and the sixth node, the second pixel switching element being turned on in response to a gate-on voltage of the second scanning signal; a third pixel switching element connected between the first node and the seventh node to be turned on in response to a gate-on voltage of the first scanning signal; a fourth pixel switching element connected between the AR node arranged to be applied with the second compensation voltage and the anode electrode of the first light emitting element, the fourth pixel switching element being arranged to be turned on in response to the gate-on voltage of the third scanning signal; a fifth pixel switch element connected between the AR node and the anode electrode of the second light emitting element, and turned on in response to a gate-on voltage of the third scanning signal; a sixth pixel switching element connected between the INI node arranged to be applied with the initialization voltage and the seventh node, the sixth pixel switching element being arranged to be turned on in response to the gate-on voltage of the fourth scan signal; a seventh pixel switching element connected between the VDD node and the sixth node to be turned on in response to a gate-on voltage of the light emitting signal; and an eighth pixel switching element connected between the OBS node arranged to be applied with the first compensation voltage and the sixth node, the eighth pixel switching element being arranged to be turned on in response to the gate-on voltage of the third scanning signal, and wherein the first pixel switch element is connected between the first node and the second node to be turned on in response to a gate-on voltage of the light emitting signal, and The driving element includes a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

13. The display panel according to claim 3 or 7, wherein: Each of the sub-pixels comprises: a capacitor connected between a VDD node arranged to be applied with a pixel driving voltage and the seventh node; a second pixel switching element connected between a data line arranged to be applied with a data voltage having pixel data and the sixth node, the second pixel switching element being arranged to be turned on in response to a gate-on voltage of an Nth scanning signal, wherein N is a natural number; a third pixel switch element connected between the first node and the seventh node to be turned on in response to a gate-on voltage of the Nth scanning signal; a fourth pixel switching element connected to the INI node arranged to be applied with the initialization voltage and the anode electrode of the first light emitting element, the fourth pixel switching element being arranged to be turned on in response to the gate-on voltage of the (N-1)th scanning signal; a fifth pixel switch element connected between the INI node and the anode electrode of the second light emitting element, and turned on in response to a gate-on voltage of an (N-1)th scanning signal; a sixth pixel switching element connected between the INI node and the seventh node to be turned on in response to a gate-on voltage of an (N-1)th scanning signal; and a seventh pixel switching element connected between the VDD node and the sixth node to be turned on in response to a gate-on voltage of a light emitting signal, and wherein the first pixel switch element is connected between the first node and the second node to be turned on in response to a gate-on voltage of a light emitting signal, and The driving element includes a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

14. The display panel according to claim 3 or 7, wherein: Each of the sub-pixels comprises: a capacitor connected between the seventh node and the eighth node; a second pixel switching element connected between a data line arranged to be applied with a data voltage having pixel data and the sixth node, the second pixel switching element being arranged to be turned on in response to a gate-on voltage of an Nth scanning signal, wherein N is a natural number; a third pixel switch element connected between the first node and the seventh node to be turned on in response to a gate-on voltage of the Nth scanning signal; a fourth pixel switching element connected to an INI node arranged to be applied with an initialization voltage and an anode electrode of the first light emitting element, the fourth pixel switching element being arranged to be turned on in response to a gate-on voltage of an (N-1)th scanning signal; a fifth pixel switch element connected between the INI node and the anode electrode of the second light emitting element, and turned on in response to a gate-on voltage of an (N-1)th scanning signal; a sixth pixel switch element connected between the INI node and the seventh node to be turned on in response to a gate-on voltage of an (N-1)th scanning signal; a seventh pixel switch element connected between the sixth node and the eighth node to be turned on in response to a gate-on voltage of the light emitting signal; an eighth pixel switching element connected between a VDD node arranged to be applied with a pixel driving voltage and the eighth node, the eighth pixel switching element being arranged to be turned on in response to a gate-on voltage of the light emitting signal; a ninth pixel switching element connected between a REF node arranged to be applied with a reference voltage and the eighth node, the ninth pixel switching element being arranged to be turned on in response to a gate-on voltage of an (N-1)th scanning signal; and a tenth pixel switching element connected between the REF node and the eighth node to be turned on in response to a gate-on voltage of the Nth scanning signal, and wherein the first pixel switch element is connected between the first node and the second node to be turned on in response to a gate-on voltage of the light emitting signal, and The driving element includes a first electrode connected to the sixth node, a second electrode connected to the first node, and a gate electrode connected to the seventh node.

15. A display panel according to any preceding claim, wherein the fifth switching element is in a conducting state.

16. A display device, comprising: A display panel according to any preceding claim; a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of sub-pixels arranged in a display panel; a data driver configured to provide a data voltage to the data line; a gate driver configured to receive a gate timing signal and provide a scan signal and a light emitting signal to the gate line; as well as A level shifter is configured to output a gate timing signal, a first horizontal mode selection signal, a second horizontal mode selection signal, a first vertical mode selection signal, and a bridge signal.

17. The display device according to claim 16, wherein: The display panel further comprises: a plurality of vertical mode lines parallel to the data lines; and a plurality of horizontal mode lines parallel to the gate lines, and wherein the vertical mode selection signal and the bridge signal are applied to the vertical mode line, and The first horizontal mode selection signal and the second horizontal mode selection signal are applied to the horizontal mode lines.

18. The display device according to claim 17, wherein: The gate driver is disposed on the display panel, and At least a portion of the horizontal mode lines overlaps the gate driver on the display panel.

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