Pixel circuit, display panel and display device

Abstract

The present embodiment relates to a pixel circuit, a display panel, and a display device, and more particularly, to a pixel circuit, a display panel, and a display device capable of reducing the number of power lines and / or sufficiently ensuring a time for sampling a threshold voltage of a driving element in the pixel circuit.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit, a display panel, and a display device. Background Art

[0002] An organic electroluminescent display device includes an organic light emitting diode (OLED), and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a large viewing angle.

[0003] Such an organic electroluminescent display device includes a pixel circuit for operating the OLED. Here, the pixel circuit may include a driving element for driving the OLED.

[0004] In addition, there may be an electrical characteristic deviation between pixel circuits. Here, the electrical characteristics of the pixel circuit may include the threshold voltage of the driving element, the mobility of the driving element, etc.

[0005] As the driving time of the pixel circuit increases, the electrical characteristic deviation between pixel circuits may become larger.

[0006] In order to compensate for the electrical characteristic deviation of the driving elements between pixel circuits, an internal compensation circuit may be added to the pixel circuit.

[0007] Here, the internal compensation circuit may be divided into a source follower type and a diode connection type.

[0008] The description provided in this background art section should not be assumed to be prior art merely because it is mentioned in or associated with the background art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0009] The inventors of the present application newly recognized that the diode connection type has a driving element with a low threshold voltage loss, and thus has good compensation performance. However, since the threshold voltage of the driving element is sampled while addressing the data voltage in one horizontal period, the sampling time may become insufficient in the high-speed driving of the display device with a shortened one horizontal period. In addition, since a power supply line for setting the voltage of the corresponding node is added to the internal compensation circuit, it may be difficult to design the display device with high resolution.

[0010] Therefore, the inventors of the present disclosure recognized the above-mentioned limitations and other limitations associated with the related art, and conducted various experiments to implement a pixel circuit, a display panel, and a display device that can reduce the number of power supply lines and / or sufficiently ensure the time for sampling the threshold voltage of the driving elements in the pixel circuit.

[0011] Additional features and aspects of the present disclosure are set forth in part in the following description, and in part will become apparent from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by the structures pointed out or derived therefrom in the present disclosure, as well as the appended claims and the drawings.

[0012] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a pixel circuit includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; a light-emitting element including an anode electrode and a cathode electrode and configured to emit light by current from the driving element; and a first switching element connected between the anode electrode and the cathode electrode and configured to electrically connect the anode electrode and the cathode electrode to each other in response to a first strobe signal.

[0013] The first switching element may be configured to conduct until the light-emitting element emits light by current and to maintain the anode electrode and the cathode electrode electrically connected to each other until the light-emitting element emits light.

[0014] The pixel circuit may be configured to be driven in an order of an initialization period, a sampling period, a data writing period, and a light-emitting period; the first strobe signal may be a gate-on voltage during the initialization period, the sampling period, and the data writing period, and may be a gate-off voltage during the light-emitting period; and the first switching element may be configured to conduct in response to the gate-on voltage of the first strobe signal to electrically connect the anode electrode and the cathode electrode to each other, and to turn off in response to the gate-off voltage of the first strobe signal.

[0015] The pixel circuit may further include: a first capacitor connected between a fourth node connected to the anode electrode and the second node; a second switching element connected between the first node and the second node and configured to conduct in response to the gate-on voltage of the first strobe signal to electrically connect the first node and the second node to each other; a third switching element configured to conduct in response to the gate-on voltage of a second strobe signal to electrically connect a driving power line providing the pixel driving voltage and the first node to each other; a fourth switching element configured to conduct in response to the gate-on voltage of a third strobe signal to electrically connect a third node connected to the second electrode of the driving element and an initialization power line providing an initialization voltage to each other; a second capacitor connected between a data line to which the data voltage is applied and the second node; a fifth switching element configured to conduct in response to the gate-on voltage of a fourth strobe signal to electrically connect the data line and the second capacitor to each other; and a sixth switching element configured to conduct in response to the gate-on voltage of a fifth strobe signal to electrically connect the third node and the fourth node to each other.

[0016] The cathode voltage applied from the cathode electrode to the anode electrode may be a voltage lower than the initialization voltage, and the pixel driving voltage may be a voltage higher than the initialization voltage.

[0017] The pixel circuit may be configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; in the initialization period, the first gate signal and the second gate signal may be gate-on voltages, and the third gate signal, the fourth gate signal, and the fifth gate signal may be gate-off voltages; in the sampling period, the first gate signal and the third gate signal may be gate-on voltages, and the second gate signal, the fourth gate signal, and the fifth gate signal may be gate-off voltages; in the data writing period, the first gate signal, the third gate signal, and the fourth gate signal may be gate-on voltages, and the second gate signal and the fifth gate signal may be gate-off voltages; and in the light emitting period, the second gate signal and the fifth gate signal may be gate-on voltages, and the first gate signal, the third gate signal, and the fourth gate signal may be gate-off voltages.

[0018] The first switching element and the second switching element may be turned on in the initialization period, the sampling period, and the data writing period.

[0019] The third switching element may be turned on in the initialization period and the light emitting period, and the fourth switching element may be turned on in the sampling period and the data writing period.

[0020] The fifth switching element may be turned on in the data writing period, and the sixth switching element may be turned on in the light emitting period.

[0021] In another aspect, the present embodiment provides a display device including: a display panel on which a plurality of data lines, a plurality of gate lines, a plurality of pixel circuits, a cathode power line configured to supply a cathode voltage to the pixel circuits, a driving power line configured to supply a pixel driving voltage to the pixel circuits, and an initialization power line configured to supply an initialization voltage to the pixel circuits are provided; a data driving circuit configured to output a data voltage of pixel data to the plurality of data lines; and a gate driving circuit configured to sequentially output gate signals to the plurality of gate lines, wherein the pixel circuit includes: a driving element including a first electrode connected to a first node to which the pixel driving voltage is applied, a gate electrode connected to a second node to which the data voltage is applied, and a second electrode; a light emitting element including an anode electrode and a cathode electrode connected to the cathode power line, and configured to emit light by a current from the driving element; and a first switching element connected between the anode electrode and the cathode electrode, and configured to electrically connect the anode electrode and the cathode electrode to each other in response to the first gate signal.

[0022] The pixel circuit may further include a second switching element connected between the first node and the second node and configured to electrically connect the first node and the second node to each other in response to a first strobe signal.

[0023] The pixel circuit may be configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; the first strobe signal may be a gate-on voltage during the initialization period, the sampling period, and the data writing period, and may be a gate-off voltage during the light emitting period; and the first switching element may be configured to turn on in response to the gate-on voltage of the first strobe signal to electrically connect the anode electrode and the cathode electrode to each other, and turn off in response to the gate-off voltage of the first strobe signal; and the second switching element may be configured to turn on in response to the gate-on voltage of the first strobe signal to electrically connect the first node and the second node to each other, and turn off in response to the gate-off voltage of the first strobe signal.

[0024] The pixel circuit may further include: a first capacitor connected between a fourth node connected to the anode electrode and the second node; a third switching element configured to turn on in response to the gate-on voltage of a second strobe signal to electrically connect the driving power supply line and the first node to each other; a fourth switching element configured to turn on in response to the gate-on voltage of a third strobe signal to electrically connect a third node connected to a second electrode of the driving element and the initialization power supply line to each other; a second capacitor connected between the data line to which a data voltage is applied and the second node; a fifth switching element configured to turn on in response to the gate-on voltage of a fourth strobe signal to electrically connect the data line and the second capacitor to each other; and a sixth switching element configured to turn on in response to the gate-on voltage of a fifth strobe signal to electrically connect the third node and the fourth node to each other.

[0025] The pixel circuit may be configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; in the initialization period, the first strobe signal and the second strobe signal may be gate-on voltages, and the third strobe signal, the fourth strobe signal, and the fifth strobe signal may be gate-off voltages; in the sampling period, the first strobe signal and the third strobe signal may be gate-on voltages, and the second strobe signal, the fourth strobe signal, and the fifth strobe signal may be gate-off voltages; in the data writing period, the first strobe signal, the third strobe signal, and the fourth strobe signal may be gate-on voltages, and the second strobe signal and the fifth strobe signal may be gate-off voltages; and in the light emitting period, the second strobe signal and the fifth strobe signal may be gate-on voltages, and the first strobe signal, the third strobe signal, and the fourth strobe signal may be gate-off voltages.

[0026] In another aspect, the present embodiment provides a display panel, which includes: a display area on which an input image is displayed; a non-display area outside the display area; a plurality of cathode power lines provided in the display area; and a plurality of pixel circuits provided in the display area, wherein each pixel circuit includes: a light-emitting element, which includes an anode electrode and a cathode electrode and is configured to emit light by a current from a driving element; and a first switching element, which includes a first electrode connected to the anode electrode, a second electrode connected to the cathode electrode, and a gate electrode to which a scan signal is applied, wherein the cathode electrode of the light-emitting element and the second electrode of the first switching element are connected to corresponding cathode power lines.

[0027] The display panel may further include: a first shorting bar, which is provided on one side of the non-display area and is connected to one end of each cathode power line; and a second shorting bar, which is provided on the other side of the non-display area and is connected to the other end of each cathode power line.

[0028] The display panel may further include: an insulating layer, which covers the first electrode and the second electrode of the first switching element and the cathode power lines; a first planarization layer, which covers the insulating layer; a first connection electrode, which contacts the cathode power line in the non-display area through a first contact hole penetrating the first planarization layer; a second connection electrode, which contacts the first electrode of the first switching element in the display area through a second contact hole penetrating the first planarization layer; a second planarization layer, which covers the first connection electrode and the second connection electrode; and a bank layer, which covers the second planarization layer, wherein the anode electrode may contact the second connection electrode in the display area through a third contact hole penetrating the second planarization layer, and the cathode electrode may contact the first connection electrode through a fourth contact hole penetrating the bank layer and the second planarization layer.

[0029] In another aspect, the present embodiment provides a pixel circuit, which includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; a light-emitting element including an anode electrode connected to a fourth node and a cathode electrode connected to a cathode power line; a first switching element including a first electrode connected to the fourth node, a gate electrode connected to a first gate line, and a second electrode connected to the cathode electrode; a first capacitor connected to the fourth node and the second node; a second switching element including a first electrode connected to the first node, a gate electrode connected to the first gate line, and a second electrode connected to the second node; a third switching element including a first electrode connected to a driving power line that provides the pixel driving voltage, a gate electrode connected to a second gate line, and a second electrode connected to the first node; a fourth switching element including a first electrode connected to an initialization power line that provides an initialization voltage, a gate electrode connected to a third gate line, and a second electrode connected to a third node; a second capacitor connected to the second node and a data line to which the data voltage is applied; a fifth switching element including a first electrode connected to the data line, a gate electrode connected to a fourth gate line, and a second electrode connected to the second capacitor; and a sixth switching element including a first electrode connected to the third node, a gate electrode connected to a fifth gate line, and a second electrode connected to the fourth node.

[0030] According to the present embodiment as described above, since the number of power lines can be reduced and / or the time for sufficiently ensuring the threshold voltage of the driving element in the pixel circuit can be secured, high-speed driving and high-resolution design of the display device can be promoted.

[0031] The various beneficial advantages and effects of the embodiment are not limited to the above, and will be more easily understood according to the description of the specific embodiment.

[0032] It should be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the inventive concept claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings may be included to provide a further understanding of the present disclosure, and may be incorporated into and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the various principles of the present disclosure.

[0034] By referring to the exemplary embodiments of the present disclosure described in detail with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer to those of ordinary skill in the art. In the drawings:

[0035] Figure 1is a block diagram showing a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 2 is a cross-sectional view showing a cross-sectional structure of a display panel shown according to an exemplary embodiment of the present disclosure; Figure 1

[0037] Figure 3 is a view showing a layout structure of a gate driving circuit shown according to an exemplary embodiment of the present disclosure; Figure 1

[0038] Figure 4 is a circuit diagram exemplarily illustrating a pixel circuit according to an exemplary embodiment of the present disclosure;

[0039] Figure 5 is a waveform diagram showing a waveform of a gate signal applied to a pixel circuit shown according to an exemplary embodiment of the present disclosure; Figure 4

[0040] Figure 6 and Figure 7 is a view showing an initialization period operation of a pixel circuit shown according to an exemplary embodiment of the present disclosure; Figure 4

[0041] Figure 8 and Figure 9 is a view showing a sampling period operation of a pixel circuit shown according to an exemplary embodiment of the present disclosure; Figure 4

[0042] Figure 10 and Figure 11 is a view showing a data writing period operation of a pixel circuit shown according to an exemplary embodiment of the present disclosure; Figure 4

[0043] Figure 12 and Figure 13 is a view showing a light emitting period operation of a pixel circuit shown according to an exemplary embodiment of the present disclosure; Figure 4

[0044] Figure 14 is a view schematically exemplifying a metal layer of a power line on which a pixel circuit including a separate low voltage power line is formed according to an exemplary embodiment of the present disclosure;

[0045] Figure 15 is a view schematically exemplifying a metal layer of a power line on which a pixel circuit according to an exemplary embodiment of the present disclosure is formed;

[0046] Figure 16 ​​​​​​​is a diagram schematically illustrating a configuration in which a cathode power line is disposed on a display panel according to an exemplary embodiment of the present disclosure;

[0047] Figure 17 and Figure 18 is a diagram illustrating a configuration in which a first switching element of a pixel circuit according to an exemplary embodiment of the present disclosure is connected to a cathode power line; and

[0048] Figures 19 to 24 is a diagram illustrating various combinations of switching elements in a pixel circuit according to an exemplary embodiment of the present disclosure.

[0049] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their illustrations, may be exaggerated.

[0050] [List of Reference Numerals]

[0051] 100: Display panel 101: Pixel circuit

[0052] 102: Data line 103: Gate line

[0053] 110: Data driving circuit 120: Gate driving circuit

[0054] 130: Timing controller 140: Power supply circuit

[0055] 150: Level shifter 1510: Substrate

[0056] 1520: Shorting bar 1530: Cathode power line

[0057] 1610: Cathode metal layer 1810: Contact hole

[0058] 1820: First connection electrode 1830: Second connection electrode

[0059] 1840: Anode electrode Detailed Description

[0060] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of well-known functions or configurations related to this document is determined to unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. Like reference numerals designate like elements throughout. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0061] Advantages and features of the present disclosure and a method for realizing the same will be more clearly understood through the example embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following example embodiments and may be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the appended claims. Any implementation described herein need not be construed as being preferred or advantageous over other implementations.

[0062] The shapes, sizes, ratios, angles, quantities, etc. disclosed in the accompanying drawings for describing the example embodiments of the present disclosure are exemplary, and the present disclosure is not limited to the items shown. Like reference numerals always refer to like elements. Additionally, when describing the present disclosure, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present disclosure, its detailed description will be omitted or briefly provided.

[0063] Terms such as "comprising", "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0064] Even if not explicitly mentioned, components are construed to include a normal error range.

[0065] For the description of positional relationships, for example, when the positional relationship and the connection relationship between two components are described as "on", "above", "under", "next to", "connected or coupled", "crossed or intersected", etc., unless more restrictive terms such as "immediately" or "directly" are used in the expression, one or more other components may be interposed therebetween.

[0066] The terms "first", "second", "A", "B", "(a)", "(b)", etc. may be used to distinguish components from each other, but the functions, structures, essences, orders, sequences or quantities of the components are not limited by the ordinal numbers or component names in front of the components. Since the claims are written around the necessary components, the ordinal numbers in front of the component names in the claims may not match the ordinal numbers in front of the component names in the embodiments. In addition, when an element or layer is described as "connected", "coupled" or "adhered" to another element or layer, the element or layer may not only be directly connected or adhered to the other element or layer, but also be indirectly connected or adhered to the other element or layer, and one or more intermediate elements or layers are "disposed" between the element or layer, unless otherwise specified.

[0067] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element and the third element" covers the combinations of all three listed elements, the combinations of any two of the three elements, and each individual element, the first element, the second element or the third element.

[0068] The features of the various embodiments of the present disclosure may be partially or wholly coupled or combined with each other, and may interoperate with each other in various ways and be technically driven, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together according to relevant dependencies.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. For example, the term "component" or "unit" may be applied, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as should be understood by those of ordinary skill in the art.

[0070] In the display device of the present disclosure, a display panel driving circuit, a pixel circuit, a level shifter, etc. may include transistors. The transistors may be implemented by oxide transistors including oxide semiconductors, LTPS transistors including low-temperature polycrystalline silicon (LTPS), etc. Here, the transistors may be thin-film transistors (TFTs).

[0071] A transistor is a three-terminal device including a gate, a source, and a drain. The source is the terminal that supplies carriers to the transistor. In a transistor, carriers flow starting from the source. The drain is the terminal where carriers flow out of the transistor. The direction of carrier flow in a transistor is from the source to the drain. In the case of an N-channel transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage, enabling electrons to flow from the source to the drain. In an N-channel transistor, the direction of current is from the drain to the source. In the case of a P-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, enabling holes to flow from the source to the drain. In a P-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the drain and source of the transistor are referred to as the first electrode and the second electrode.

[0072] The scan signal swings between the gate-on voltage and the gate-off voltage. The gate-off voltage can be interpreted as the first voltage, and the gate-on voltage can be interpreted as the second voltage. The transistor conducts in response to the gate-on voltage, while the transistor cuts off in response to the gate-off voltage. In the case of an N-channel transistor, the gate-on voltage can be the gate high voltage (VGH), and the gate-off voltage can be the gate low voltage (VGL). In the case of a P-channel transistor, the gate-on voltage can be the gate low voltage (VGL), and the gate-off voltage can be the gate high voltage (VGH).

[0073] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, all components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0074] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure. Figure 2 is shown Figure 1 a cross-sectional view showing the cross-sectional structure of the display panel shown.

[0075] Referring to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure may be an organic light-emitting display device, but the present disclosure is not limited thereto. For example, the display device of the present disclosure may also be other types of display devices, such as a micro light-emitting diode (micro-LED) display device, etc. Such a display device may include a display panel 100, a display panel driving circuit for writing pixel data on the pixel circuit of the display panel 100, and a power supply circuit 140 for generating the power required to drive the pixel circuit and the display panel driving circuit.

[0076] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but the present disclosure is not limited thereto. As an example, the display panel 100 may be a panel having a rectangular structure with a length in the Y-axis direction and a width in the X-axis direction. As another example, the display panel 100 may be a panel having a structure with any shape such as a square shape, a circular shape, an oval shape, etc.

[0077] The display area AA of the display panel 100 includes a pixel array on which an image is displayed. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the plurality of data lines 102, and pixel circuits 101 disposed at intersections of the plurality of data lines 102 and the plurality of gate lines 103 in a matrix form. The display panel 100 may further include: a power supply line commonly connected to the pixel circuits 101. The power supply line is connected to the pixel circuits and supplies a constant voltage required to drive the pixel circuits 101 to the pixel circuits 101.

[0078] The pixel circuit 101 may be divided into two or more sub-pixel circuits for realizing color. For example, three sub-pixel circuits sequentially arranged in the X-axis direction may be divided into a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit, but the present disclosure is not limited thereto.

[0079] In addition, four sub-pixel circuits sequentially arranged in the X-axis direction may be divided into a red sub-pixel circuit, a green sub-pixel circuit, a blue sub-pixel circuit, and a white sub-pixel circuit.

[0080] Each pixel circuit 101 is connected to a data line, a gate line, and a power supply line.

[0081] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes one row of pixel circuits arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixel circuits arranged on one pixel row share the gate line 103. The pixel circuits arranged in the column direction (Y-axis direction) along the data line direction share the same data line 102. As an example, one horizontal period is a time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0082] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on a screen and real things in the background are visible. The display panel 100 may be implemented as a flexible display panel or a non-flexible display panel.

[0083] At least a part of the display panel 100 may include a transmissive pixel structure that overlaps with an optical device disposed on the lower portion of the display panel 100. The optical device may include an image sensor (or camera), a proximity sensor, and optical elements such as lighting elements, or an infrared sensor for face recognition.

[0084] The cross-sectional structure of such a display panel 100 is as follows.

[0085] Figure 2 It is shown Figure 1 A cross-sectional view showing the cross-sectional structure of the display panel shown.

[0086] Figure 2 The cross-sectional view of includes two thin film transistors TFT1 and TFT2 and a capacitor CST. The two thin film transistors TFT1 and TFT2 include a polycrystalline thin film transistor TFT1 containing a polycrystalline semiconductor material such as low temperature polycrystalline silicon (LTPS) and an oxide thin film transistor TFT2 containing an oxide semiconductor material, but the present disclosure is not limited thereto.

[0087] Figure 2 The polycrystalline thin film transistor TFT1 shown is a light-emitting switch thin film transistor or a driving transistor connected to the light-emitting element EL, and the oxide thin film transistor TFT2 is any one of the switch thin film transistors connected to the capacitor CST.

[0088] In Figure 2 One pixel includes a light-emitting element EL and a pixel driving circuit that applies a driving current to the light-emitting element EL. The pixel driving circuit is disposed on the substrate 211, and the light-emitting element EL is disposed on the pixel driving circuit. In addition, a packaging layer 220 is disposed on the light-emitting element EL. The packaging layer 220 protects the light-emitting element EL.

[0089] The pixel driving circuit may refer to a pixel array portion including a driving thin film transistor, a switch thin film transistor, and a capacitor. In addition, the light-emitting element EL may refer to an array portion for light emission including an anode electrode, a cathode electrode, and a light-emitting layer disposed therebetween.

[0090] In an embodiment, the driving thin film transistor and at least one switch thin film transistor use an oxide semiconductor as an active layer. Compared with a thin film transistor using a polycrystalline semiconductor material as an active layer, a thin film transistor using an oxide semiconductor material as an active layer has an excellent leakage current blocking effect and a relatively low manufacturing cost. Therefore, in order to reduce power consumption and manufacturing cost, the pixel driving circuit according to the embodiment includes a driving thin film transistor and at least one switch thin film transistor using an oxide semiconductor material.

[0091] All thin film transistors constituting the pixel driving circuit can be implemented by using an oxide semiconductor material, or only some switching thin film transistors can be implemented by using an oxide semiconductor material.

[0092] The substrate 211 can be implemented as a multi-layer in which organic layers and inorganic layers are alternately stacked. For example, the substrate 211 can be formed by alternately stacking an organic layer such as polyimide and an inorganic layer such as silicon oxide (SiO2).

[0093] In addition, the substrate 211 can include glass, plastic, or a flexible polymer film. For example, the flexible polymer film can be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cycloolefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS). These materials are only examples and are not necessarily limited thereto.

[0094] The lower buffer layer 212a is formed on the substrate 211. The lower buffer layer 212a is used to block moisture and the like that may penetrate from the outside, and can be used by stacking layers such as a silicon oxide (SiO2) layer into a multi-layer. An auxiliary buffer layer 212b can be further provided on the lower buffer layer 212a to protect the elements from moisture penetration.

[0095] The polycrystalline thin film transistor TFT1 is formed above the substrate 211. The polycrystalline thin film transistor TFT1 can use polycrystalline semiconductor as the active layer. The polycrystalline thin film transistor TFT1 includes a first active layer ACT1 having a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0096] The first active layer ACT1 includes a first channel region, a first source region provided on one side of the first channel region, and a first drain region provided on the other side of the first channel region.

[0097] The first source region and the first drain region are regions formed by doping group 5 or group 3 impurity ions (for example, phosphorus (P) or boron (B)) into an intrinsic polycrystalline semiconductor material at a predetermined concentration to form a conductor. The first channel region provides a path for electrons or holes to move by maintaining the intrinsic state of the polycrystalline semiconductor material.

[0098] In addition, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping with a first channel region of the first active layer ACT1. A first gate insulating layer 213 is disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 213 can be a single layer or multiple layers of an inorganic layer such as a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, etc.

[0099] In one embodiment, the polycrystalline thin film transistor TFT1 has a top gate structure in which the first gate electrode GE1 is located above the first active layer ACT1, but the present disclosure is not limited thereto. For example, the polycrystalline thin film transistor TFT1 can have a bottom gate structure or a double gate structure. Therefore, the first electrode CST1 included in the capacitor CST and the light blocking layer LS included in the oxide thin film transistor TFT2 can be formed of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first electrode CST1, and the light blocking layer LS via one mask process, the mask process can be simplified. However, the present disclosure is not limited thereto, and the light blocking layer LS can be formed on the lower buffer layer 212a and the auxiliary buffer layer 212b through a separate mask process. In this case, the light blocking layer LS can be formed under any transistor, not limited to the oxide thin film transistor TFT2. Additionally, the light blocking layer LS can be disposed under the capacitor CST and overlap therewith to form a double capacitor.

[0100] The first gate electrode GE1 is made of a metal material. For example, the first gate electrode GE1 can be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

[0101] A first interlayer insulating layer 214 is disposed on the first gate electrode GE1. The first interlayer insulating layer 214 can be formed of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0102] The display panel 100 may further include an upper buffer layer 215, a second gate insulating layer 216, and a second interlayer insulating layer 217 sequentially disposed on the first interlayer insulating layer 214. The polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2 formed on the second interlayer insulating layer 217 and respectively connected to the first source region and the first drain region.

[0103] The first source electrode SD1 and the first drain electrode SD2 can be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

[0104] The upper buffer layer 215 separates the second active layer ACT2 of the oxide thin film transistor TFT2 made of an oxide semiconductor material from the first active layer ACT1 made of a polycrystalline semiconductor material, and provides a base for forming the second active layer ACT2.

[0105] The second gate insulating layer 216 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 216 is formed on the second active layer ACT2 made of an oxide semiconductor material, and is thus implemented as an inorganic layer. For example, the second gate insulating layer 216 can be formed of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0106] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 can be a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto.

[0107] In addition, the oxide thin film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 215 and made of an oxide semiconductor material, a second gate electrode GE2 provided on the second gate insulating layer 216, and a second source electrode SD3 and a second drain electrode SD4 provided on the second interlayer insulating layer 217.

[0108] The second active layer ACT2 is made of an oxide semiconductor material, and includes an intrinsic second channel region not doped with impurities, and a second source region and a second drain region doped with impurities to become conductors.

[0109] The oxide thin film transistor TFT2 further includes a light-blocking layer LS located below the upper buffer layer 215 and overlapping with the second active layer ACT2. The light-blocking layer LS can block the light incident on the second active layer ACT2 to ensure the reliability of the oxide thin film transistor TFT2. The light-blocking layer LS can be made of the same material as the first gate electrode GE1, and can be formed on the top surface of the first gate insulating layer 213. The light-blocking layer LS can be electrically connected to the second gate electrode GE2 to form a double-gate structure.

[0110] The second source electrode SD3 and the second drain electrode SD4 can be formed simultaneously on the second interlayer insulating layer 217 using the same material as the first source electrode SD1 and the first drain electrode SD2, thereby reducing the number of mask processes.

[0111] In addition, the capacitor CST can be implemented by disposing a second electrode CST2 on the first interlayer insulating layer 214 to overlap with the first electrode CST1. The second electrode CST2 can be a single layer or a multi-layer made of any one of, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0112] The capacitor CST stores the data voltage applied through the data line DL for a certain period of time and supplies it to the light-emitting element EL. The capacitor CST includes two electrodes corresponding to each other and a dielectric disposed therebetween. The first interlayer insulating layer 214 is located between the first electrode CST1 and the second electrode CST2.

[0113] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, the present disclosure is not limited thereto, and the connection relationship of the capacitor CST can vary according to the pixel driving circuit.

[0114] In addition, the first planarization layer 218 and the second planarization layer 219 are sequentially disposed on the pixel driving circuit to planarize the steps caused by the pixel driving circuit. The first planarization layer 218 and the second planarization layer 219 can be organic layers such as polyimide or acrylic resin.

[0115] Then, the light-emitting element EL is formed on the second planarization layer 219.

[0116] The light-emitting element EL includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer LEL disposed between the anode electrode ANO and the cathode electrode CAT. When implemented in a pixel driving circuit that commonly uses a low-potential voltage connected to the cathode electrode CAT, the anode electrode ANO is set as a separate electrode for each sub-pixel. When implemented in a pixel driving circuit that commonly uses a high-potential voltage, the cathode electrode CAT can be set as a separate electrode for each sub-pixel.

[0117] The light-emitting element EL is electrically connected to the driving element through an intermediate electrode CNE disposed on the first planarization layer 218. Specifically, the anode electrode ANO of the light-emitting element EL and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit are connected to each other through the intermediate electrode CNE.

[0118] The anode electrode ANO is connected to the intermediate electrode CNE exposed through a contact hole penetrating the second planarization layer 219. In addition, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole penetrating the first planarization layer 218, but is not limited thereto. For example, depending on the structure of the pixel driving circuit, the intermediate electrode CNE may be connected to the first drain electrode SD2, the second source electrode SD3, or the second drain electrode SD4.

[0119] The intermediate electrode CNE serves as a medium for connecting the first source electrode SD1 to the anode electrode ANO. The intermediate electrode CNE may be made of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0120] The anode electrode ANO may be formed as a multilayer structure including a transparent conductive layer and an opaque conductive layer having a high reflection efficiency. The transparent conductive layer may be made of a material having a relatively large work function value such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer may be formed as a single-layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the anode electrode ANO may be formed as a structure in which the transparent conductive layer, the opaque conductive layer, and the transparent conductive layer are sequentially stacked, or a structure in which the transparent conductive layer and the opaque conductive layer are sequentially stacked.

[0121] The light-emitting layer LEL is formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the anode electrode ANO.

[0122] The bank layer BNK may be a pixel defining layer that exposes the anode electrode ANO of each pixel. The bank layer BNK may be made of an opaque material (e.g., black) to prevent or reduce light interference between adjacent pixels. In this case, the bank layer BNK includes a light-blocking material made of at least one of a color pigment, organic black, and carbon. A spacer may be further provided on the bank layer BNK.

[0123] The cathode electrode CAT is formed opposite to the anode electrode ANO, and the light-emitting layer LEL is interposed therebetween, and the cathode electrode CAT is formed on the top surface and the side surface of the light-emitting layer LEL. The cathode electrode CAT may be integrally formed above the entire display area AA. When applied to a top-emission type organic light-emitting display device, the cathode electrode CAT may be formed of a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0124] An encapsulation layer 220 for suppressing moisture penetration may be further provided on the cathode electrode CAT.

[0125] The encapsulation layer 220 can prevent external moisture or oxygen from penetrating into the light-emitting element EL that is vulnerable to external moisture or oxygen. To achieve this, the encapsulation layer 220 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the present disclosure, the structure of the encapsulation layer 220 in which the first encapsulation layer 221, the second encapsulation layer 222, and the third encapsulation layer 223 are sequentially stacked will be described as an example.

[0126] The first encapsulation layer 221 is formed above the substrate 211 on which the cathode electrode CAT is formed. The third encapsulation layer 223 is formed above the substrate 211 on which the second encapsulation layer 222 is formed, and may be formed to surround the top surface, bottom surface, and side surface of the second encapsulation layer 222 together with the first encapsulation layer 221. The first encapsulation layer 221 and the third encapsulation layer 223 can minimize, reduce, or prevent external moisture or oxygen from penetrating into the light-emitting element EL. The first encapsulation layer 221 and the third encapsulation layer 223 may be made of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3) that can be deposited at low temperature. Since the first encapsulation layer 221 and the third encapsulation layer 223 are deposited in a low-temperature atmosphere, the light-emitting element EL that is vulnerable to a high-temperature atmosphere can be prevented or reduced from being damaged during the deposition process of the first encapsulation layer 221 and the third encapsulation layer 223.

[0127] The second encapsulation layer 222 can be used as a buffer layer to relieve the interlayer stress caused by the bending of the display device 20 and can planarize the step difference between layers. The second encapsulation layer 222 may be formed above the substrate 211 on which the first encapsulation layer 221 is formed, and is formed of a non-photosensitive organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbide (SiOC)) or a photosensitive organic insulating material (such as photosensitive acrylic), but is not limited thereto. When the second encapsulation layer 222 is formed by an inkjet method, a dam portion DAM may be provided to prevent or reduce the diffusion of the second encapsulation layer 222 in liquid form to the edge of the substrate 211. The dam portion DAM may be provided closer to the edge of the substrate 211 than the second encapsulation layer 222. Due to the dam portion DAM, the diffusion of the second encapsulation layer 222 to the pad region having the conductive pad provided at the outermost part of the substrate can be prevented or reduced.

[0128] The dam portion DAM is designed to prevent or reduce the diffusion of the second encapsulation layer 222, but if the second encapsulation layer 222 is formed to exceed the height of the dam portion DAM during the process, the second encapsulation layer 222 as an organic layer may be exposed to the outside, which can cause moisture, etc. to penetrate into the light-emitting element. Therefore, to prevent or reduce this situation, at least ten or more dam portions DAM may be formed in an overlapping manner.

[0129] The DAM can be disposed on the second interlayer insulating layer 217 in the non-display area NA.

[0130] In addition, the DAM can be formed simultaneously with the first planarization layer 218 and the second planarization layer 219. When forming the first planarization layer 218, the lower layer of the DAM can be formed together, and when forming the second planarization layer 219, the upper layer of the DAM can be formed together, and they can be stacked into a double-layer structure.

[0131] Therefore, the DAM can be made of the same material as the first planarization layer 218 and the second planarization layer 219, but is not limited thereto.

[0132] The DAM can be formed to overlap with the cathode power line PL1. For example, in the non-display area NA, the cathode power line PL1 can be formed in the lower layer of the area where the DAM is located. Here, the non-display area NA can include a border area.

[0133] The cathode power line PL1 and the gate driving circuit 120 configured in the form of gate-in-panel (GIP) can be formed to surround the outer periphery of the display panel, and the cathode power line PL1 can be positioned more outward than the gate driving circuit 120. In addition, the cathode power line PL1 can be connected to the cathode electrode CAT to apply a common voltage. The gate driving circuit 120 is simply drawn in the plan view and cross-sectional view of the drawing, but the gate driving circuit 120 can be configured using thin film transistors having the same structure as the thin film transistors in the display area AA.

[0134] The cathode power line PL1 is set to be more outward than the gate driving circuit 120. The cathode power line PL1 is set to be more outward than the gate driving circuit 120 and surround the display area AA. For example, the cathode power line PL1 can be made of the same material as the first gate electrode GE1, but is not limited thereto, and can be made of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2, but is not limited thereto.

[0135] In addition, the cathode power line PL1 can be electrically connected to the cathode electrode CAT. The cathode power line PL1 can supply a low-voltage power supply EVSS to the pixels in the display area AA.

[0136] The touch layer can be disposed on the encapsulation layer 220. In the touch layer, the touch buffer layer 251 can be located between the touch sensor metal including the touch electrode connection lines 252 and 254 and the touch electrodes 255 and 256 and the cathode electrode CAT of the light-emitting element EL.

[0137] The touch buffer layer 251 can prevent or reduce the infiltration of chemical solutions (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 251, moisture from the outside, etc. into the light-emitting layer LEL containing organic materials. Therefore, the touch buffer layer 251 can prevent or reduce damage to the light-emitting element EL vulnerable to chemical solutions or moisture.

[0138] The touch buffer layer 251 can be formed of an organic insulating material capable of being formed at a low temperature equal to or lower than a specific temperature (e.g., 100 °C) and having a low dielectric constant of 1 to 3 to prevent or reduce damage to the light-emitting layer LEL containing organic materials vulnerable to high temperatures. For example, the touch buffer layer 251 can be formed of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer layer 251 made of an organic insulating material and having a planarization property can prevent or reduce damage to the encapsulation layer 220 and cracking of the touch sensor metal formed on the touch buffer layer 251 due to bending of the organic light-emitting display device.

[0139] According to the mutual capacitance-based touch sensor structure, the touch electrodes 255 and 256 can be disposed on the touch buffer layer 251, and the touch electrodes 255 and 256 can be disposed to cross each other.

[0140] The touch electrode connection lines 252 and 254 can electrically connect the touch electrodes 255 and 256 to each other. The touch electrode connection lines 252 and 254 and the touch electrodes 255 and 256 can be located on different layers, and the touch insulating layer 253 is interposed therebetween.

[0141] The touch electrode connection lines 252 and 254 can be disposed to overlap the bank layer BNK to prevent or reduce a decrease in the aperture ratio.

[0142] In addition, a part of the touch electrode connection line 252 can be electrically connected to a touch driving circuit (not shown) through a touch pad PAD that exceeds the top portion and side surface of the encapsulation layer 420 and the top portion and side surface of the dam portion DAM.

[0143] A part of the touch electrode connection line 252 can receive a touch driving signal from the touch driving circuit, send it to the touch electrodes 255 and 256, and can also send a touch sensing signal from the touch electrodes 255 and 256 to the touch driving circuit.

[0144] The touch passivation layer 257 can be disposed on the touch electrodes 255 and 256. Although the touch passivation layer 257 is shown as being disposed only on the touch electrodes 255 and 256, the present disclosure is not limited thereto, and the touch passivation layer 257 can extend before or after the dam portion DAM to be disposed on the touch electrode connection line 252.

[0145] In addition, a color filter (not shown) may be further provided on the encapsulation layer 220, and the color filter may be located on the touch layer or may be located between the encapsulation layer 220 and the touch layer. It should be noted that although Figure 2 the detailed layer structure of the display panel is shown, it is provided only by way of example, and the present disclosure is not limited thereto. For example, the layer structure of the display panel may be changed in various ways, and one or more of the buffer layer or the planarization layer may be omitted when necessary.

[0146] The power circuit 140 generates a DC voltage (or constant voltage) required to drive the pixel array and the display panel driving circuit of the display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power circuit may generate a constant voltage, such as a gamma reference voltage VGMA, a gate-on voltage VGH, a gate-off voltage VGL, a pixel driving voltage EVDD, a cathode voltage EVSS, an initialization voltage Vinit, etc., by adjusting the level of the DC input voltage applied from a host system (not shown). The gamma reference voltage VGMA is supplied to the data driving circuit 110. The gate-on voltage VGH and the gate-off voltage VGL are supplied to the level shifter 150 and the gate driving circuit 120. Constant voltages, such as the pixel driving voltage EVDD, the cathode voltage EVSS, and the initialization voltage Vinit, are supplied to the pixel circuit 101 through a power line commonly connected to the pixel circuit 101.

[0147] In addition, the pixel driving voltage EVDD may be output from the main power supply of the host system 200 and may be supplied to the display panel 100. In this case, the power circuit 140 does not need to output the pixel driving voltage EVDD.

[0148] Under the control of the timing controller 130, the display panel driving circuit writes the pixel data of the input image into the pixel circuit of the display panel 100.

[0149] The display panel driving circuit includes a data driving circuit 110 and a gate driving circuit 120.

[0150] In addition, the display panel driving circuit may further include a touch sensor driving circuit (not shown) for driving the touch sensor. The data driving circuit 110 and the touch sensor driving circuit (not shown) may be integrated into one driving integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power circuit 140, the level shifter 150, the data driving circuit 110, and the touch sensor driving circuit (not shown) may be integrated into one driving IC.

[0151] The data driving circuit 110 receives pixel data of an input image received from the timing controller 130 as a digital signal and outputs a data voltage. The data driving circuit 110 converts the pixel data of the input image into a gamma-compensated voltage for each frame period by using a digital-to-analog converter (DAC) and outputs a data voltage Vdata. The gamma reference voltage VGMA is divided into gamma-compensated voltages for each gray scale by a voltage divider circuit. The gamma-compensated voltages for each gray scale are provided to the DAC of the data driving circuit 110. The data voltage Vdata is output on each channel of the data driving circuit 110 through an output buffer.

[0152] The data driving circuit 110 may be integrated into a source driver integrated circuit (SDIC). The source driver IC may be connected to the bonding pads of the display panel 100 according to a tape automated bonding (TAB) method or a chip-on-glass (COG) method. In addition, the source driver IC may be implemented according to a chip-on-film (COF) method.

[0153] The gate driving circuit 120 may be formed on a circuit layer CIR on the display panel 100 together with the wirings of the TFT array and the pixel array. The gate driving circuit 120 may be disposed on a bezel that is a non-display area NA of the display panel 100, or may be distributed in the pixel array that reproduces the input image.

[0154] The gate driving circuit 120 may be disposed in two bezels (BZ) of the display panel, and the display area of the display panel is interposed therebetween, and may provide gate pulses to both sides of the gate line 103 by a dual-feed method. In another embodiment, the gate driving circuit 120 may be disposed on either the left bezel or the right bezel of the display panel 100, and may provide a gate signal to the gate line 103 by a single-feed method. The gate driving circuit 120 sequentially outputs pulses of the gate signal under the control of the timing controller 130. The gate driving circuit 120 may sequentially provide the gate signal to the gate line 103 by shifting the pulses of the gate signal by using a shift register.

[0155] The gate driving circuit 120 may include a plurality of gate driving units that output pulses of the gate signal. In the case of the pixel circuit 101 as shown in Figure 4 shown, as Figure 3As shown, the gate driving circuit 120 may include a first gate driving unit 310 that sequentially outputs a first gate signal SCAN1, a second gate driving unit 320 that sequentially outputs a second gate signal EM1, a third gate driving unit 330 that sequentially outputs a third gate signal SCAN2, a fourth gate driving unit 340 that sequentially outputs a fourth gate signal SCAN3, and a fifth gate driving unit 350 that sequentially outputs a fifth gate signal EM2. Here, the plurality of gate driving units may be implemented as shift registers or edge flip-flops. Some of the plurality of gate driving units may be implemented as shift registers, and the rest may be implemented as edge flip-flops. Although Figure 3 the gate driving circuit 120 is shown to include a first gate driving unit to a fifth gate driving unit, the present disclosure is not limited thereto, and more or fewer gate driving units may be included in the gate driving circuit 120 when needed.

[0156] Here, the second gate signal EM1 and the fifth gate signal EM2 may be light emission signals, and the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 may be scan signals.

[0157] Between the fifth gate driving unit 350 that outputs the fifth gate signal EM2 as a light emission signal and the second gate driving unit 320, the first gate driving unit 310 that outputs the first gate signal SCAN1 as a scan signal and the third gate driving unit 330 that outputs the third gate signal SCAN2 may be provided.

[0158] In addition, between the first gate driving unit 310 that outputs the first gate signal SCAN1 as a scan signal and the fourth gate driving unit 340 that outputs the fourth gate signal SCAN3, the second gate driving unit 320 that outputs the second gate signal EM1 as a light emission signal may be provided. However, the present disclosure is not necessarily limited thereto.

[0159] In an embodiment of the present disclosure, the fifth gate driving unit 350 may be provided on the outermost side of the gate driving circuit 120.

[0160] In addition, although Figure 3 the gate driving units 320 and 350 that output light emission signals and the gate driving units 310, 330, and 340 that output scan signals are illustrated as being symmetrically arranged about the display area AA, the present disclosure is not limited thereto, and the gate driving units 320 and 350 that output light emission signals and the gate driving units 310, 330, and 340 that output scan signals may be arranged asymmetrically about the display area AA.

[0161] In addition, in Figure 3Among them, the fourth gate driving unit 340 may be connected to each of the odd-numbered pixel rows and the even-numbered pixel rows, and the first gate driving unit 310, the second gate driving unit 320, the third gate driving unit 330, and the fifth gate driving unit 350 may be commonly connected to two pixel rows.

[0162] The timing controller 130 receives image data and a timing signal synchronized with the image data from a host system (not shown). The image data received by the timing controller 130 is a digital signal. The timing controller 130 may convert the image data into a data format suitable for use in the data driving circuit 110, and may send the converted image data to the data driving circuit 110. Here, the timing signal may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and a data enable signal. Since the vertical period and the horizontal period can be known by a method of counting the data enable signal, the vertical synchronization signal and the horizontal synchronization signal may be omitted. The data enable signal has a period of one horizontal period (1H).

[0163] The timing controller 130 may generate a data timing control signal for controlling the operation timing of the data driving circuit 110, a gate timing control signal for controlling the operation timing of the gate driving circuit 120, etc., based on the timing signal received from a host system (not shown).

[0164] The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driving circuit 120 through the level shifter 150. The level shifter 150 may receive the input gate timing control signal, and may generate a start pulse and a shift clock and provide the start pulse and the shift clock to the gate driving circuit 120.

[0165] As described above, the display device including the display panel 100, the display panel driving circuit, and the power supply circuit 140 may be a display device that ensures a sufficient threshold voltage sampling time of the driving element in the case of internal compensation in the pixel circuit 101. This allows the display device to be driven at high speed.

[0166] In addition, the display device may be a display device with a reduced number of power supply lines of the pixel circuit 101. This allows the display device to be designed to have a high resolution.

[0167] As described above, in order to ensure a sufficient threshold voltage sampling time in the case of internal compensation in the pixel circuit 101, and to reduce the number of power supply lines required in the case of internal compensation, the pixel circuit 101 may include the following configuration.

[0168] Figure 4 It is a circuit diagram schematically illustrating a pixel circuit according to an embodiment of the present disclosure.

[0169] Reference Figure 4 Figure 4

[0170] The pixel circuit 101 is connected to a data line DL to which a data voltage Vdata is applied and gate lines GL1 to GL4 to which a gate signal SCAN1, SCAN2, SCAN3, EM1, and EM2 are applied.

[0171] The pixel circuit 101 is connected to a cathode power line PL1 that provides a cathode voltage EVSS, a driving power line PL2 that provides a pixel driving voltage EVDD, and an initialization power line PL3 that provides an initialization voltage Vinit. On the display panel 100, the power lines PL1, PL2, and PL3 may be commonly connected to all pixels.

[0172] The pixel driving voltage EVDD is set to a voltage that is higher than the maximum voltage of the data voltage Vdata (Vdata white max) and at which the driving element DT can operate in the saturation region. The initialization voltage Vinit may be set to a voltage that is lower than the minimum voltage of the data voltage Vdata (Vdata black) and higher than the cathode voltage EVSS.

[0173] The gate-on voltage VGH may be set to a voltage higher than the pixel driving voltage EVDD, and the gate-off voltage VGL may be set to a voltage lower than the cathode voltage EVSS.

[0174] For example, if the maximum voltage of the data voltage Vdata (Vdata white max) is 6 [V] and its minimum voltage (Vdata black) is 1 [V], the pixel driving voltage EVDD may be set in a voltage range of 10 [V] to 16 [V]. The initialization voltage Vinit may be set in a voltage range of 0.5 [V] to 1 [V], and the cathode voltage EVSS may be set in a voltage range of -8 [V] to -0.5 [V].

[0175] The gate-on voltage VGH may be set in a voltage range of 8 [V] to 24 [V], and the gate-off voltage VGL may be set in a voltage range of -5 [V] to -16 [V].

[0176] In other words, the voltage levels applied to the pixel circuit 101 can be in the following order: gate-on voltage (VGH) > pixel driving voltage (EVDD) > maximum voltage (Vdata white max) > minimum voltage (Vdata black) > initialization voltage (Vinit) > cathode voltage (EVSS) > gate-off voltage (VGL).

[0177] The strobe signals SCAN1, SCAN2, SCAN3, EM1, and EM2 include a pulse that swings between the gate-on voltage VGH and the gate-off voltage VGL. The strobe signals SCAN1, SCAN2, SCAN3, EM1, and EM2 include a first strobe signal SCAN1, a second strobe signal EM1, a third strobe signal SCAN2, a fourth strobe signal SCAN3, and a fifth strobe signal EM2.

[0178] The driving periods of the pixel circuit 101 can be in the following order: initialization period INI, sampling period SAM, data writing period WR, and emission period EMI. As Figure 5 shown, the initialization period INI, the sampling period SAM, the data writing period WR, and the emission period can be determined by the waveforms of the strobe signals SCAN1, SCAN2, SCAN3, EM1, and EM2.

[0179] Specifically, in the initialization period INI, the voltages of the first strobe signal SCAN1 and the second strobe signal EM1 are the gate-on voltage VGH. In addition, the voltages of the third strobe signal SCAN2, the fourth strobe signal SCAN3, and the fifth strobe signal EM2 are the gate-off voltage VGL.

[0180] In the sampling period SAM, the voltages of the first strobe signal SCAN1 and the third strobe signal SCAN2 are the gate-on voltage VGH. In addition, the voltages of the second strobe signal EM1, the fourth strobe signal SCAN3, and the fifth strobe signal EM2 are the gate-off voltage VGL.

[0181] In the data writing period WR, the voltages of the first strobe signal SCAN1, the third strobe signal SCAN2, and the fourth strobe signal SCAN3 are the gate-on voltage VGH. In addition, the voltages of the second strobe signal EM1 and the fifth strobe signal EM2 are the gate-off voltage VGL.

[0182] In the emission period EMI, the voltages of the second strobe signal EM1 and the fifth strobe signal EM2 are the gate-on voltage VGH. In addition, the voltages of the first strobe signal SCAN1, the third strobe signal SCAN2, and the fourth strobe signal SCAN3 are the gate-off voltage VGL.

[0183] In addition, the driving element DT of the pixel circuit 101 drives the light-emitting element EL by generating a current according to the gate-source voltage Vgs. The driving element DT includes a first electrode connected to the first node N1, a gate electrode connected to the second node N2, and a second electrode connected to the third node N3. Here, the pixel driving voltage EVDD can be applied to the first node N1, and the data voltage Vdata can be applied to the second node N2. Specifically, during the initialization period INI and the light-emitting period, the pixel driving voltage EVDD can be applied to the first node N1, and during the data writing period WR, the data voltage Vdata can be applied to the second node N2.

[0184] The light-emitting element EL can be implemented as an OLED. The light-emitting element EL includes an anode electrode and a cathode electrode, and emits light by the current from the driving element DT. Here, the light-emitting element EL may further include an organic compound layer formed between the anode electrode and the cathode electrode.

[0185] The anode electrode of the light-emitting element EL is connected to the fourth node N4, and the cathode electrode is connected to the cathode power line PL1 that provides the cathode voltage EVSS. Here, the fourth node N4 can be selectively connected to the third node N3 through the on and off of the sixth switching element T6.

[0186] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL, but is not limited thereto. If a voltage is applied to the anode electrode and the cathode electrode of the light-emitting element EL, the holes that have passed through the hole transport layer HTL and the electrons that have passed through the electron transport layer ETL move to the light-emitting layer EML and form excitons. In this case, visible light is emitted from the light-emitting layer EML. The light-emitting element EL can be implemented as a cascade structure in which a plurality of light-emitting layers are stacked. The light-emitting element EL having a cascade structure can improve the brightness and lifespan of the pixel.

[0187] The first capacitor C1 is connected between the second node N2 and the fourth node N4, stores the threshold voltage Vth of the driving element DT sampled during the sampling period SAM, and maintains the gate-source voltage Vgs of the driving element DT during the light-emitting period EMI.

[0188] The second capacitor C2 is connected between the data line DL to which the data voltage Vdata is applied and the second node N2. The second capacitor C2 stores the data voltage Vdata applied through the fifth switching element T5 during the data writing period WR and sends the stored data voltage to the second node N2.

[0189] As a result, the potential of the second node N2 in the data write period WR becomes a voltage obtained by adding together the voltage applied to the second node N2 in the sampling period SAM and the data voltage Vdata.

[0190] In the case where the second capacitor C2 does not exist between the second node N2 and the fourth node N4, the data voltage Vdata can be immediately transferred to the second node N2 in the data write period WR, and the potential of the second node N2 can be reset to the data voltage Vdata.

[0191] In other words, the second capacitor C2 can be a buffer capacitor that prevents or reduces the sudden transfer of the data voltage Vdata to the second node N2 when transferring the data voltage Vdata. Here, the capacitance of the second capacitor C2 can be smaller than the capacitance of the first capacitor C1. For example, the capacitance of the first capacitor C1 can be 141 [femtofarads (fF)], and the capacitance of the second capacitor C2 can be 135 [fF].

[0192] In addition, the switching elements T1 to T6 of the pixel circuit 101 include a first switching element T1 and a second switching element T2 that conduct in response to the gate conduction voltage VGH of the first gate signal SCAN1, a third switching element T3 that conducts in response to the gate conduction voltage VGH of the second gate signal EM1, a fourth switching element T4 that conducts in response to the gate conduction voltage VGH of the third gate signal SCAN2, a fifth switching element T5 that conducts in response to the gate conduction voltage VGH of the fourth gate signal SCAN3, and a sixth switching element T6 that conducts in response to the gate conduction voltage VGH of the fifth gate signal EM2.

[0193] The first switching element T1 is connected between the anode electrode and the cathode electrode of the light-emitting element EL. In other words, the first switching element T1 is connected between the fourth node N4 on the anode electrode side and the cathode power line PL1 on the cathode electrode side.

[0194] Specifically, the first electrode of the first switching element T1 is connected to the anode electrode of the light-emitting element EL, for example, the fourth node N4, and the second electrode is connected to the cathode electrode of the light-emitting element EL, for example, the cathode power line PL1. In addition, the gate electrode is connected to the first gate line GL1, and the first gate signal SCAN1 is applied to the gate electrode.

[0195] The first switching element T1 electrically connects the anode electrode and the cathode electrode to each other in response to the first gate signal SCAN1.

[0196] In other words, the first switching element T1 conducts in response to the gate conduction voltage VGH of the first gate signal SCAN1, and applies the cathode voltage EVSS to the fourth node N4.

[0197] Here, the first switching element T1 conducts until the light emission period EMI, and maintains the potential of the fourth node N4 at the cathode voltage EVSS until the light emission period EMI.

[0198] In other words, since the voltage of the first gate signal SCAN1 is the gate-on voltage VGH during the initialization period INI, the sampling period SAM, and the data write period WR, the first switching element T1 conducts during the initialization period INI, the sampling period SAM, and the data write period WR, and maintains the potential of the fourth node N4 at the cathode voltage EVSS during the initialization period INI, the sampling period SAM, and the data write period WR.

[0199] Since the voltage of the first gate signal SCAN1 is the gate-off voltage during the light emission period, the first switching element T1 turns off according to the gate-off voltage during the light emission period.

[0200] The second switching element T2 is connected between the first node N1 and the second node N2.

[0201] Specifically, the first electrode of the second switching element T2 is connected to the first node N1, and its second electrode is connected to the second node N2. In addition, the gate electrode is connected to the first gate line GL1, and the first gate signal SCAN1 is applied to the gate electrode.

[0202] In other words, the second switching element T2 shares the first gate signal SCAN1 with the first switching element T1.

[0203] The second switching element T2 conducts in response to the gate-on voltage VGH of the first gate signal SCAN1.

[0204] Here, the second switching element T2 conducts until the light emission period EMI, and maintains the driving element DT in a diode-connected state until the light emission period EMI.

[0205] In other words, since the voltage of the first gate signal SCAN1 is the gate-on voltage VGH during the initialization period INI, the sampling period SAM, and the data write period WR, the second switching element T2 conducts during the initialization period INI, the sampling period SAM, and the data write period WR, and maintains the driving element DT in a diode-connected state during the initialization period INI, the sampling period SAM, and the data write period WR. Here, diode connection means that the gate electrode and the first electrode of the driving element DT are connected to each other.

[0206] Since the voltage of the first gate signal SCAN1 is the gate-off voltage during the light emission period, the second switching element T2 turns off according to the gate-off voltage during the light emission period.

[0207] The third switching element T3 is connected between the driving power supply line PL2 that provides the pixel driving voltage EVDD and the first node N1.

[0208] Specifically, the first electrode of the third switching element T3 is connected to the driving power supply line PL2, and its second electrode is connected to the first node N1. In addition, its gate electrode is connected to the second gate line GL2, and the second gate signal EM1 is applied to the gate electrode.

[0209] The third switching element T3 is turned on in response to the gate conduction voltage VGH of the second gate signal EM1.

[0210] Here, since the voltage of the second gate signal EM1 is the gate conduction voltage VGH during the initialization period INI and the light emission period EMI, the third switching element T3 is only turned on during the initialization period INI and then turned off again during the light emission period EMI.

[0211] The fourth switching element T4 is connected between the initialization power supply line PL3 that provides the initialization voltage and the third node N3.

[0212] Specifically, the first electrode of the fourth switching element T4 is connected to the initialization power supply line PL3, and its second electrode is connected to the third node N3. In addition, its gate electrode is connected to the third gate line GL3, and the third gate signal SCAN2 is applied to the gate electrode.

[0213] The fourth switching element T4 is turned on in response to the gate conduction voltage VGH of the third gate signal SCAN2.

[0214] Here, since the voltage of the third gate signal SCAN2 is the gate conduction voltage VGH during the sampling period SAM and the data writing period WR, the fourth switching element T4 is turned on during the sampling period SAM and the data writing period WR.

[0215] The fifth switching element T5 is connected between the data line DL and the second capacitor C2.

[0216] Specifically, the first electrode of the fifth switching element T5 is connected to the data line DL, and its second electrode is connected to the second capacitor C2. In addition, its gate electrode is connected to the fourth gate line GL4, and the fourth gate signal SCAN3 is applied to the gate electrode.

[0217] The fifth switching element T5 is turned on in response to the gate conduction voltage VGH of the fourth gate signal SCAN3.

[0218] Here, since the voltage of the fourth gate signal SCAN3 is the gate conduction voltage VGH during the data writing period WR, the fifth switching element T5 is only turned on during the data writing period WR.

[0219] The sixth switching element T6 is connected between the third node N3 and the fourth node N4.

[0220] Specifically, the first electrode of the sixth switching element T6 is connected to the third node N3, and its second electrode is connected to the fourth node N4. In addition, its gate electrode is connected to the fifth gate line GL5, and the fifth gate signal EM2 is applied to the gate electrode.

[0221] The sixth switching element T6 is turned on in response to the gate conduction voltage VGH of the fifth gate signal EM2.

[0222] Here, since the voltage of the fifth gate signal EM2 is the gate conduction voltage VGH during the light emission period EMI, the sixth switching element T6 is turned on only during the light emission period EMI and connects the third node N3 to the fourth node N4.

[0223] If the third node N3 and the fourth node N4 are connected to each other during the light emission period EMI, a current path is formed between the cathode power line PL1 and the driving power line PL2, and current can flow to the light emitting element EL.

[0224] Hereinafter, the operation of the pixel circuit 101 will be described step by step according to the driving period of the pixel circuit 101.

[0225] Figure 6 and Figure 7 are diagrams showing Figure 4 the operation of the pixel circuit shown during the initialization period. Figure 8 and Figure 9 are diagrams showing Figure 4 the operation of the pixel circuit shown during the sampling period. Figure 10 and Figure 11 are diagrams showing Figure 4 the operation of the pixel circuit shown during the data writing period. Figure 12 and Figure 13 are diagrams showing Figure 4 the operation of the pixel circuit shown during the light emission period.

[0226] Referring to Figure 6 and Figure 7 , the main nodes of the pixel circuit 101 are initialized during the initialization period INI. During the initialization period INI, the voltages of the first gate signal SCAN1 and the second gate signal EM1 are the gate conduction voltage VGH as in Figure 6 . During the initialization period INI, the voltages of the third gate signal SCAN2, the fourth gate signal SCAN3, and the fifth gate signal EM2 are the gate cut-off voltage VGL.

[0227] Therefore, during the initialization period INI, as Figure 7 shown, the first switching element T1 and the second switching element T2 are turned on in response to the gate conduction voltage VGH of the first strobe signal SCAN1, and the third switching element T3 is turned on in response to the gate conduction voltage VGH of the second strobe signal EM1. Here, by turning on the second switching element T2, the driving element DT becomes in a diode-connected state during the initialization period INI.

[0228] In addition, the fourth switching element T4, the fifth switching element T5, and the sixth switching element T6 are turned off according to the gate cut-off voltage VGL of the third strobe signal SCAN2, the fourth strobe signal SCAN3, and the fifth strobe signal EM2. As a result, during the initialization period INI, the potentials of the first node N1 and the second node N2 are initialized to the pixel driving voltage EVDD, and the potential of the third node N3 becomes a voltage (EVDD - Vth) obtained by subtracting the threshold voltage Vth of the driving element DT from the pixel driving voltage EVDD.

[0229] In addition, the potential of the fourth node N4 is initialized to the cathode voltage EVSS. When the voltage difference between the pixel driving voltage EVDD and the threshold voltage Vth of the driving element DT is higher than the threshold voltage Vth of the driving element DT, the driving element DT can be turned on during the initialization period INI. In an embodiment of the present disclosure, during the initialization period INI, by applying the cathode voltage EVSS, which is a low voltage, to the anode electrode (e.g., the fourth node N4) of the light-emitting element EL, light emission of the light-emitting element EL can be prevented or reduced when the second node N2 is initialized with the pixel driving voltage EVDD, which is a high voltage. Here, the light emission of the light-emitting element EL is caused by the coupling phenomenon of the first capacitor C1 that occurs when the second node N2 is initialized with the pixel driving voltage EVDD.

[0230] Referring to Figure 8 and Figure 9 , during the sampling period SAM, the threshold voltage Vth of the driving element DT is sampled by the first capacitor C1.

[0231] During the sampling period SAM, as Figure 8 shown, the voltages of the first strobe signal SCAN1 and the third strobe signal SCAN2 are the gate conduction voltage VGH. During the sampling period SAM, the voltages of the second strobe signal EM1, the fourth strobe signal SCAN3, and the fifth strobe signal EM2 are the gate cut-off voltage VGL.

[0232] Therefore, during the sampling period SAM, as Figure 9Among them, the first switching element T1 and the second switching element T2 remain in the on state in response to the gate conduction voltage VGH of the first strobe signal SCAN1, and the fourth switching element T4 conducts in response to the gate conduction voltage VGH of the third strobe signal SCAN2. Here, due to the conduction of the second switching element T2, the driving element DT remains in the diode-connected state during the sampling period SAM.

[0233] In addition, the third switching element T3, the fifth switching element T5, and the sixth switching element T6 are turned off according to the gate cut-off voltage VGL of the second strobe signal EM1, the fourth strobe signal SCAN3, and the fifth strobe signal EM2.

[0234] As a result, during the sampling period SAM, the potentials of the first node N1 and the second node N2 become the voltage (Vinit + Vth) obtained by adding the initialization voltage Vinit and the threshold voltage Vth of the driving element DT together, and the potential of the third node N3 becomes the initialization voltage Vinit. In addition, the potential of the fourth node becomes the cathode voltage EVSS.

[0235] In an embodiment of the present disclosure, by maintaining the potential of the fourth node N4 as the cathode voltage EVSS during the sampling period SAM, an increase in the voltage of the fourth node N4 can be prevented or reduced. Therefore, it is possible to prevent or reduce the light emission of the light-emitting element EL due to the increase in the voltage of the fourth node N4 during the sampling period SAM.

[0236] Refer to Figure 10 and 11 , during the data writing period WR, the data voltage Vdata of the pixel data is applied to the second node N2. Therefore, the data voltage Vdata in which the threshold voltage Vth of the driving element DT is compensated can be stored in the first capacitor C1.

[0237] During the data writing period WR, as Figure 10 shown in, the voltages of the first strobe signal SCAN1, the third strobe signal SCAN2, and the fourth strobe signal SCAN3 are the gate conduction voltage VGH. During the data writing period WR, the voltages of the second strobe signal EM1 and the fifth strobe signal EM2 are the gate cut-off voltage VGL.

[0238] Therefore, during the data writing period WR, as Figure 11In this case, the first switching element T1 and the second switching element T2 are kept in an on state in response to the gate conduction voltage VGH of the first strobe signal SCAN1, and the fourth switching element T4 is kept in an on state in response to the gate conduction voltage VGH of the third strobe signal SCAN2. In addition, the fifth switching element T5 is turned on in response to the gate conduction voltage VGH of the fourth strobe signal SCAN3. Here, due to the conduction of the second switching element T2, the driving element DT is kept in a diode-connected state during the data writing period WR.

[0239] In addition, the third switching element T3 and the sixth switching element T6 are turned off according to the gate cut-off voltage VGL of the second strobe signal EM1 and the fifth strobe signal EM2.

[0240] As a result, during the data writing period WR, the potential of the first node N1 becomes a voltage (Vinit + Vth) obtained by adding together the initialization voltage Vinit and the threshold voltage Vth of the driving element DT, and the potential of the second node N2 becomes a voltage (Vinit + Vth + Vdata) obtained by adding together the initialization voltage Vinit, the threshold voltage Vth of the driving element DT, and the data voltage Vdata. In addition, the potential of the third node N3 becomes the initialization voltage Vinit, and the potential of the fourth node N4 becomes the cathode voltage EVSS.

[0241] In an embodiment of the present disclosure, by keeping the potential of the fourth node N4 as the cathode voltage EVSS during the data writing period WR, an increase in the voltage of the fourth node N4 can be prevented or reduced. Therefore, light emission of the light emitting element EL during the data writing period WR due to an increase in the voltage of the fourth node N4 can be prevented or reduced.

[0242] Referring to Figure 12 and Figure 13 , during the light emission period EMI, as in Figure 12 , the voltages of the second strobe signal EM1 and the fifth strobe signal EM2 are the gate conduction voltage VGH. During the light emission period EMI, the voltages of the first strobe signal SCAN1, the third strobe signal SCAN2, and the fourth strobe signal SCAN3 are the gate cut-off voltage VGL.

[0243] Therefore, during the light emission period EMI, as in Figure 13 , the third switching element T3 is turned on in response to the gate conduction voltage VGH of the second strobe signal EM1, and the sixth switching element T6 is turned on in response to the gate conduction voltage VGH of the fifth strobe signal EM2.

[0244] In addition, the first switching element T1, the second switching element T2, the fourth switching element T4, and the fifth switching element T5 are turned off according to the gate cut-off voltage VGL of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3.

[0245] According to the conduction and cut-off of the switching elements as described above, during the light-emitting period EMI, a current path is formed between the cathode power line PL1 and the driving power line PL2, and the light-emitting element EL can emit light by the current flowing through the driving element DT. Here, the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data.

[0246] In addition, during the light-emitting period EMI, the potential of the first node N1 becomes the pixel driving voltage EVDD, and the potential of the second node N2 becomes the voltage (Vinit + Vth + Vdata) obtained by adding together the initialization voltage Vinit, the threshold voltage Vth of the driving element DT, and the data voltage Vdata. In addition, the potentials of the third node N3 and the fourth node N4 become the initialization voltage Vinit.

[0247] In addition, the current Ioled flowing to the light-emitting element EL during the light-emitting period EMI is determined by the following formula.

[0248] [Equation 1]

[0249] I oled = K(Vgs - Vth) 2

[0250] = K(Vinit + Vth + Vdata - Vinit - Vth) 2

[0251] = K(Vdata) 2

[0252] Here, Vgs is the gate-source voltage of the driving element DT, and K represents a constant value determined by the mobility and parasitic capacitance of the driving element DT. In addition, Vinit represents the initialization voltage, Vdata represents the data voltage, and Vth represents the threshold voltage of the driving element DT.

[0253] Since during the light-emitting period EMI, the potential of the second node N2, which is the gate-side node of the driving element DT, is Vinit + Vth + Vdata, and the potential of the third node N3 or the fourth node N4, which is the source-side node, is Vinit, the gate-source voltage becomes Vinit + Vth + Vdata – Vinit.

[0254] As in Equation 1 above, in the current Ioled flowing to the light-emitting element EL, the threshold voltage Vth of the driving element DT is not reflected, and only the data voltage Vdata is reflected. In other words, the current Ioled flowing to the light-emitting element EL is a current in which the threshold voltage Vth of the driving element DT is compensated.

[0255] In addition, during the light-emitting period EMI, one or more of the second gate signal EM1 and the fifth gate signal EM2 may be generated as pulse-width modulation (PWM) pulses. The PWM pulses may have a duty cycle that changes according to the digital brightness value (DBV).

[0256] As described above, in the pixel circuit 101 according to an embodiment of the present disclosure, the sampling period SAM and the data writing period WR are separated from each other. Therefore, regardless of one horizontal period (1H) corresponding to the data writing period WR, the sampling period SAM can be sufficiently ensured.

[0257] In addition, in the pixel circuit 101 according to an embodiment of the present disclosure, since the potential of the anode electrode (e.g., the fourth node N4) of the light-emitting element EL is maintained at the cathode voltage EVSS by the first switching element T1 until the light-emitting period EMI, a separate low-voltage power supply line such as a reference voltage line VREF does not need to be provided in the pixel circuit 101. Therefore, the number of power supply lines required for the pixel circuit 101 can be reduced.

[0258] In other words, if a separate low-voltage power supply line such as a reference voltage line VREF is provided in the pixel circuit, then as Figure 14 shown, the area occupied by the power supply lines in the pixel circuit increases. As a result, the size of the pixel circuit increases, making it difficult to design a high-resolution display device. In Figure 14 , the power supply lines may be the first data line DL1, the cathode power supply line PL1 provided between the second data line DL2 and the third data line DL3, the driving power supply line PL2, the initialization power supply line PL3, and the reference voltage line PL4.

[0259] On the contrary, if a separate low-voltage power supply line such as the reference voltage line PL4 is not provided in the pixel circuit, then as Figure 15 shown, the area occupied by the power supply lines in the pixel circuit decreases. As a result, the size of the pixel circuit decreases, thus facilitating the high-resolution design of the display device. In Figure 15 , the power supply lines may be the first data line DL1, the cathode power supply line PL1 provided between the second data line DL2 and the third data line DL3, the driving power supply line PL2, and the initialization power supply line PL3.

[0260] It should be noted that Figure 4The structure of the pixel circuit 101 shown and Figure 5 The driving timing of the pixel circuit 101 shown is provided by way of example only, and the present disclosure is not limited thereto. For example, more or fewer transistors and capacitors may be included in the pixel circuit of the present disclosure, and its driving method may be changed in various ways.

[0261] From now on, a configuration for connecting the first switching element T1 and the cathode power line PL1 to each other in the pixel circuit 101 according to an embodiment of the present disclosure will be described.

[0262] Figure 16 is a diagram schematically illustrating a configuration in which the cathode power line is provided on the display panel, and Figure 17 and Figure 18 is a diagram illustrating a configuration in which the first switching element of the pixel circuit according to an embodiment of the present disclosure is connected to the cathode power line.

[0263] Referring to Figure 16 , on one side of the substrate 1610 for forming the display panel 100, a first shorting bar 1622 may be provided; and on the other side of the substrate 1610, a second shorting bar 1624 may be provided. Here, one side and the other side of the substrate 1610 may correspond to the non-display area NA of the display panel 100. In other words, on one side of the non-display area NA, the first shorting bar 1622 may be provided, and on the other side of the substrate 1610, the second shorting bar 1624 may be provided.

[0264] In addition, a plurality of cathode power lines 1630 may be provided between the first shorting bar 1622 and the second shorting bar 1624.

[0265] In other words, one end of each cathode power line 1630 may be connected to the first shorting bar 1622, and the other end of each cathode power line 1630 may be connected to the second shorting bar 1624. Here, the cathode power line 1630 may be provided in the display area AA of the display panel 100.

[0266] In addition, as shown by the dotted line display portion in Figure 17 , the first electrode of the first switching element T1 of the pixel circuit 101 is connected to the cathode power line 1630, and its second electrode is connected to the fourth node N4, for example, the anode electrode of the light-emitting element EL.

[0267] In the cross-sectional structure of the display panel 100 as in Figure 18 , the first switching element T1 may be provided in a plurality of insulating layers.

[0268] Specifically, the plurality of insulating layers may include a first insulating layer 1812 covering a multi-buffer layer 1802 stacked on a substrate 1610 of the display panel 100, a second insulating layer 1814 covering the first insulating layer 1812, and a third insulating layer 1816 covering the second insulating layer 1814. Here, the multi-buffer layer 1802 may block moisture and the like that may invade from the outside. The multi-buffer layer 1802 may be formed by laminating silicon oxide SiOx and silicon nitride SiNx in multiple layers, but is not limited thereto.

[0269] The multi-buffer layer 1802 may include a first buffer layer B1 and a second buffer layer B2. A first-first metal layer 1804 and a first-second metal layer 1805 may be formed on the first buffer layer B1. In addition, a second-first metal layer 1806 and a second-second metal layer 1807 may be formed on the second buffer layer B2. A first capacitor C1 may be formed by the first-first metal layer 1804, the second-first metal layer 1806, and the first buffer layer B1 as a dielectric material disposed therebetween. In addition, a second capacitor C2 may be formed by the second-first metal layer 1806, the second-second metal layer 1807, and the first buffer layer B1 as a dielectric material disposed therebetween.

[0270] Any one of the first-first metal layer 1804 and the second-first metal layer 1806 may be electrically connected to the second node n2, and the other thereof may be electrically connected to the fourth node n4.

[0271] Any one of the second-first metal layer 1806 and the second-second metal layer 1807 may be electrically connected to a second electrode of a fifth switching element T5, and the other thereof may be electrically connected to the second node n2.

[0272] A first electrode 1822 and a second electrode 1824 of a first switching element T1 may be disposed on the third insulating layer 1816. In addition, a gate electrode 1826 of the first switching element T1 may be disposed on the second insulating layer 1814, and a semiconductor layer 1828 may be disposed on the first insulating layer 1812. Here, the semiconductor layer 1828 may be made of an oxide semiconductor. The oxide semiconductor material may include at least one of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, an SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn-Oxynitride)-based oxide semiconductor material.

[0273] In addition, the first electrode 1822 and the second electrode 1824 provided on the third insulating layer 1816 may be covered by a protective layer 1818 composed of an insulating layer.

[0274] The first planarization layer 1832 may cover the protective layer 1818. In addition, the second planarization layer 1834 may cover the first planarization layer 1832.

[0275] The first planarization layer 1832 may planarize the upper part of the first switching element T1 and may protect the first switching element T1.

[0276] The second planarization layer 1834 may cover the first planarization layer 1832. In addition, a light-emitting element EL may be provided on the second planarization layer 1834. Here, the light-emitting element EL may include, but is not limited to, an anode electrode 1872, an organic compound layer 1874, a cathode electrode 1876, and a bank layer 1878.

[0277] Here, the bank layer 1878 may expose the anode electrode 1872. Through the bank layer 1878, the size and shape of the light-emitting region in each pixel circuit may be different. The bank layer 1878 may be formed of a photosensitive organic insulating material or a material including black, but is not limited thereto. The bank layer 1878 may be made of at least one of an inorganic insulating material (such as silicon nitride (SiNx) or silicon oxide (SiOx)) or an organic insulating material (such as BCB (benzocyclobutene), acrylic resin, epoxy resin, or polyimide resin). The bank layer 1878 may be provided to cover an edge portion of the anode electrode 1872 on the second planarization layer 1834.

[0278] The organic compound layer 1874 including the light-emitting layer of the light-emitting element EL may cover the anode electrode 1872 and the bank layer 1878. The cathode electrode 1876 of the light-emitting element EL may be provided on the organic compound layer 352. The cathode electrode 1876 may be formed of a metal layer having an area the same as or similar to the area of the substrate 1610, and a plurality of pixel circuits may share the cathode electrode 1876.

[0279] An encapsulation layer may be provided on the cathode electrode 1876, and a touch sensor layer may be provided on the encapsulation layer. Here, the encapsulation layer may be composed of at least two stacked insulating layers 1882, 1784, and 1786 including an inorganic diaphragm and an organic diaphragm.

[0280] In the cross-sectional structure of the display panel 100 as described above, the cathode power line 1630 may be connected to the second electrode 1824 of the first switching element T1 on the third insulating layer 1816.

[0281] In other words, the cathode power line 1630, and the first electrode 1822 and the second electrode 1824 of the first switching element T1 can be disposed on the third insulating layer 1816. In addition, the cathode power line 1630, the first electrode 1822, and the second electrode 1824 can be covered by a protective layer 1818 made of an insulating layer.

[0282] Here, the first electrode 1822 and the second electrode 1824 of the first switching element T1 can be located in the display area AA of the display panel 100.

[0283] In addition, the cathode power line 1630 connected to the second electrode 1824 can extend until the non-display area NA of the display panel 100.

[0284] In the non-display area NA, the cathode power line 1630 can be in contact with the first connection electrode 1852 through a first contact hole 1842 penetrating the first planarization layer 1832. Here, the first connection electrode 1852 can be disposed on the first planarization layer 1832 and can be covered by the second planarization layer 1834.

[0285] The cathode electrode 1876 located in the non-display area NA can be in contact with the first connection electrode 1852 through a fourth contact hole 1848 penetrating the bank layer 1860 and the second planarization layer 1834.

[0286] With the above configuration, the cathode power line 1630 connected to the second electrode 1824 can be connected to the cathode electrode 1876. In other words, the second electrode 1824 and the cathode electrode 1876 can be connected to each other through the above configuration. Here, the first shorting bar 1622 or the second shorting bar 1624 can be composed of the first contact hole 1842, the first connection electrode 1852, and the fourth contact hole 1848 located in the non-display area NA.

[0287] In addition, the second connection electrode 1854 can be in contact with the first electrode 1822 of the first switching element T1 through a second contact hole 1844 penetrating the first planarization layer 1832. Here, the second connection electrode 1854 can also be disposed on the first planarization layer 1832 and can be covered by the second planarization layer 1834.

[0288] In the display area AA, the anode electrode 1872 disposed on the second planarization layer 1834 can be in contact with the second connection electrode 1854 through a second contact hole 1846 penetrating the second planarization layer 1834.

[0289] With the above configuration, the second electrode 1824 and the anode electrode 1872 can be connected to each other. Here, the anode electrode 1872 can correspond to the fourth node N4.

[0290] In addition, in the embodiments of the present disclosure, although it is described that the switching elements T1 to T6 of the pixel circuit 101 are composed of N-channel transistors, the present disclosure is not limited thereto.

[0291] In other words, one or more of the switching elements T1 to T6 may be composed of P-channel transistors.

[0292] For example, as Figure 19 shown, the first switching element T1, the second switching element T2, the third switching element T3, the fourth switching element T4, and the sixth switching element T6 may be composed of P-channel transistors, and the fifth switching element T5 may be composed of an N-channel transistor.

[0293] In this case, as Figure 20 shown, the gate-on voltages of the first strobe signal SCAN1, the second strobe signal EM1, the third strobe signal SCAN2, and the fifth strobe signal EM2 may be the gate low voltage VGL, and their gate-off voltages may be the gate high voltage VGH.

[0294] In another example, as Figure 21 shown, the first switching element T1, the second switching element T2, the third switching element T3, and the sixth switching element T6 may be composed of P-channel transistors, and the fourth switching element T4 and the fifth switching element T5 may be composed of N-channel transistors.

[0295] In this case, as Figure 22 shown, the gate-on voltages of the first strobe signal SCAN1, the second strobe signal EM1, and the fifth strobe signal EM2 may be the gate low voltage VGL, and their gate-off voltages may be the gate high voltage VGH.

[0296] In yet another example, as Figure 23 shown, the third switching element T3 and the sixth switching element T6 may be composed of P-channel transistors, and the first switching element T1, the second switching element T2, the fourth switching element T4, and the fifth switching element T5 may be composed of N-channel transistors.

[0297] In this case, as Figure 24 shown, the gate-on voltages of the second strobe signal EM1 and the fifth strobe signal EM2 may be the gate low voltage VGL, and their gate-off voltages may be the gate high voltage VGH.

[0298] The objectives to be achieved by the present disclosure described above, the means for achieving the objectives, and the effects of the present disclosure are not essential technical features of the claimed rights. Therefore, the scope of the claims is not limited to the disclosed content of the present disclosure.

[0299] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical idea of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided only for illustrative purposes and are not intended to limit the technical idea of the present disclosure. The scope of the technical idea of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical ideas within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0300] Cross-reference to related applications

[0301] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0197850, filed in Korea on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

Claims

1. A pixel circuit, comprising: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; a light emitting element, the light emitting element including an anode electrode and a cathode electrode, the light emitting element being configured to emit light by a current from the driving element; as well as A first switching element is connected to the anode electrode and the cathode electrode, and is configured to electrically connect the anode electrode and the cathode electrode to each other in response to a first gate signal.

2. The pixel circuit according to claim 1, wherein: The first switching element is configured to be turned on until the light emitting element emits light by the current, and to maintain the electrical connection between the anode electrode and the cathode electrode until the light emitting element emits light.

3. The pixel circuit according to claim 1, wherein: The pixel circuit is configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; wherein the first selection signal is a gate-on voltage during the initialization period, the sampling period, and the data writing period, and is a gate-off voltage during the light emitting period; and The first switching element is configured to be turned on in response to the gate-on voltage of the first selection signal and electrically connect the anode electrode and the cathode electrode to each other, and to be turned off in response to the gate-off voltage of the first selection signal.

4. The pixel circuit according to claim 1, further comprising: a first capacitor connected to the second node and a fourth node connected to the anode electrode; a second switching element connected to the first node and the second node, the second switching element being configured to be turned on in response to a gate-on voltage of the first gating signal and to electrically connect the first node and the second node to each other; a third switching element configured to be turned on in response to a gate-on voltage of a second selection signal and to electrically connect a driving power line providing the pixel driving voltage and the first node to each other; a fourth switching element configured to be turned on in response to a gate-on voltage of a third gating signal and to electrically connect a third node connected to the second electrode of the driving element and an initialization power line supplying an initialization voltage to each other; a second capacitor connected to the second node and the data line to which the data voltage is applied; a fifth switching element configured to be turned on in response to a gate-on voltage of a fourth selection signal and to electrically connect the data line and the second capacitor to each other; as well as a sixth switching element configured to be turned on in response to a gate-on voltage of a fifth gate signal and to electrically connect the third node and the fourth node to each other.

5. The pixel circuit according to claim 4, wherein: A cathode voltage applied from the cathode electrode is a voltage lower than the initialization voltage, and the pixel driving voltage is a voltage higher than the initialization voltage.

6. The pixel circuit according to claim 4, wherein: The pixel circuit is configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; wherein, in the initialization period, the first selection signal and the second selection signal are the gate-on voltages, and the third selection signal, the fourth selection signal and the fifth selection signal are gate-off voltages; wherein, in the sampling period, the first selection signal and the third selection signal are the gate-on voltages, and the second selection signal, the fourth selection signal and the fifth selection signal are the gate-off voltages; wherein, in the data writing period, the first selection signal, the third selection signal and the fourth selection signal are the gate-on voltages, and the second selection signal and the fifth selection signal are the gate-off voltages; and In the light emitting period, the second selection signal and the fifth selection signal are the gate-on voltages, and the first selection signal, the third selection signal and the fourth selection signal are the gate-off voltages.

7. The pixel circuit according to claim 6, wherein: The first switching element and the second switching element are turned on in the initialization period, the sampling period, and the data writing period.

8. The pixel circuit according to claim 6, wherein: The third switching element is turned on in the initialization period and the light emission period, and the fourth switching element is turned on in the sampling period and the data writing period.

9. The pixel circuit according to claim 6, wherein: The fifth switching element is turned on in the data writing period, and the sixth switching element is turned on in the light emitting period.

10. A display device, comprising: A display panel, the display panel comprising a plurality of data lines, a plurality of gate lines, a plurality of pixel circuits, a cathode power line configured to provide a cathode voltage to a pixel circuit among the plurality of pixel circuits, a driving power line configured to provide a pixel driving voltage to the pixel circuit, and an initialization power line configured to provide an initialization voltage to the pixel circuit; a data driving circuit configured to output data voltages of pixel data to the plurality of data lines; as well as a gate driving circuit, the gate driving circuit being configured to sequentially output a gate signal to the plurality of gate lines, Wherein, the pixel circuit comprises: a driving element including a first electrode connected to a first node to which the pixel driving voltage is applied, a gate electrode connected to a second node to which the data voltage is applied, and a second electrode; a light emitting element including an anode electrode and a cathode electrode connected to the cathode power supply line, the light emitting element being configured to emit light by a current from the driving element; and A first switching element is connected to the anode electrode and the cathode electrode, and is configured to electrically connect the anode electrode and the cathode electrode to each other in response to a first gate signal.

11. The display device according to claim 10, further comprising: A second switching element is connected to the first node and the second node, and is configured to electrically connect the first node and the second node to each other in response to the first gating signal.

12. The display device according to claim 11, wherein: The pixel circuit is configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; wherein the first selection signal is a gate-on voltage during the initialization period, the sampling period and the data writing period, and is a gate-off voltage during the light emitting period; wherein the first switching element is configured to be turned on in response to the gate-on voltage of the first gating signal and electrically connect the anode electrode and the cathode electrode to each other, and to be turned off in response to the gate-off voltage of the first gating signal; and The second switching element is configured to be turned on in response to the gate-on voltage of the first selection signal and electrically connect the first node and the second node to each other, and to be turned off in response to the gate-off voltage of the first selection signal.

13. The display device according to claim 11, further comprising: a first capacitor connected to the second node and a fourth node connected to the anode electrode; a third switching element configured to be turned on in response to a gate-on voltage of a second gating signal and to electrically connect the driving power line and the first node to each other; a fourth switching element configured to be turned on in response to a gate-on voltage of a third gating signal and to electrically connect a third node connected to the second electrode of the driving element and the initialization power line to each other; a second capacitor connected to the second node and the data line to which the data voltage is applied; a fifth switching element configured to be turned on in response to a gate-on voltage of a fourth selection signal and to electrically connect the data line and the second capacitor to each other; as well as a sixth switching element configured to be turned on in response to a gate-on voltage of a fifth gate signal and to electrically connect the third node and the fourth node to each other.

14. The display device according to claim 13, wherein: The pixel circuit is configured to be driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period; wherein, in the initialization period, the first selection signal and the second selection signal are the gate-on voltages, and the third selection signal, the fourth selection signal and the fifth selection signal are gate-off voltages; wherein, in the sampling period, the first selection signal and the third selection signal are the gate-on voltages, and the second selection signal, the fourth selection signal and the fifth selection signal are the gate-off voltages; wherein, in the data writing period, the first selection signal, the third selection signal and the fourth selection signal are the gate-on voltages, and the second selection signal and the fifth selection signal are the gate-off voltages; and In the light emitting period, the second selection signal and the fifth selection signal are the gate-on voltages, and the first selection signal, the third selection signal and the fourth selection signal are the gate-off voltages.

15. A display panel, comprising: a display area on which an input image is displayed; a non-display area, the non-display area being outside the display area; a plurality of cathode power lines, wherein the plurality of cathode power lines are within the display area; as well as A plurality of pixel circuits, wherein the plurality of pixel circuits are in the display area, Wherein, each of the plurality of pixel circuits comprises: a light emitting element including an anode electrode and a cathode electrode, the light emitting element being configured to emit light by a current from a driving element; and a first switching element including a first electrode connected to the anode electrode, a second electrode connected to the cathode electrode, and a gate electrode to which a scan signal is applied, The cathode electrode of the light emitting element and the second electrode of the first switching element are connected to corresponding cathode power lines among the plurality of cathode power lines.

16. The display panel according to claim 15, further comprising: a first shorting bar on one side of the non-display area and connected to one end of each of the plurality of cathode power supply lines; as well as A second shorting bar is on the other side of the non-display area and connected to the other end of each of the plurality of cathode power lines.

17. The display panel according to claim 15, further comprising: an insulating layer, the insulating layer covering the first electrode and the second electrode of the first switching element and a cathode power line among the plurality of cathode power lines; a first planarization layer, wherein the first planarization layer covers the insulating layer; a first connection electrode, the first connection electrode being in contact with the cathode power line in the non-display area through a first contact hole penetrating the first planarization layer; a second connecting electrode, the second connecting electrode being in contact with the first electrode of the first switching element in the display area through a second contact hole penetrating the first planarization layer; a second planarization layer, wherein the second planarization layer covers the first connection electrode and the second connection electrode; as well as a bank layer, the bank layer covering the second planarization layer, The anode electrode contacts the second connection electrode in the display area through a third contact hole penetrating the second planarization layer, and the cathode electrode contacts the first connection electrode through a fourth contact hole penetrating the bank layer and the second planarization layer.

18. A pixel circuit, comprising: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; a light emitting element including an anode electrode connected to the fourth node and a cathode electrode connected to a cathode power supply line; a first switching element including a first electrode connected to the fourth node, a gate electrode connected to a first gate line, and a second electrode connected to the cathode electrode; a first capacitor connected to the fourth node and the second node; a second switching element including a first electrode connected to the first node, a gate electrode connected to the first gate line, and a second electrode connected to the second node; a third switching element, the third switching element comprising a first electrode connected to a driving power line providing the pixel driving voltage, a gate electrode connected to a second gate line, and a second electrode connected to the first node; a fourth switching element including a first electrode connected to an initialization power line providing an initialization voltage, a gate electrode connected to a third gate line, and a second electrode connected to a third node; a second capacitor connected to the second node and the data line to which the data voltage is applied; a fifth switching element including a first electrode connected to the data line, a gate electrode connected to a fourth gate line, and a second electrode connected to the second capacitor; as well as A sixth switching element includes a first electrode connected to the third node, a gate electrode connected to a fifth gate line, and a second electrode connected to the fourth node.

Images