Chip, network interface card and electronic equipment

Abstract

The invention discloses a chip, a network interface card and electronic equipment, the chip comprises a correction module, a write-back module and a memory, the correction module is used for determining a to-be-corrected address of a single-bit error of the memory and correction data corresponding to the to-be-corrected address under the condition that the memory is determined to have the single-bit error, and the write-back module is used for writing back the to-be-corrected address and the correction data corresponding to the to-be-corrected address; the to-be-corrected address and the correction data are sent to the write-back module; the write-back module is used for storing the to-be-corrected address and correction data corresponding to the to-be-corrected address in a busy state; and the write-back module is also used for writing the stored or received correction data into the to-be-corrected address of the memory in the idle state so as to correct the error data in the to-be-corrected address. Therefore, error data in the memory are corrected in time through the write-back module, so that a chip is prevented from being evolved into a multi-bit error from a single-bit error, a processor can be ensured to acquire correct data, and the conditions of system abnormity or hanging up and the like are avoided.

Description

Technical Field

[0001] This application relates to the technical field of chips, and more particularly, to a chip, a network interface card, and an electronic device. Background Art

[0002] Error Checking and Correcting (ECC) technology detects and corrects errors by adding redundant bits to the memory. When the system reads the data in the memory, ECC can check the integrity of the data and, in the case of detecting a single-bit error, correct it through hardware logic to ensure that the processor can obtain the correct data, thus avoiding the situation where the processor obtains incorrect data, which may cause the system to malfunction or freeze.

[0003] However, due to the failure to correct single-bit errors in a timely manner, errors accumulate, resulting in multi-bit errors. ECC cannot correct multi-bit errors, thus leading to the situation where the processor obtains incorrect data, causing the system to malfunction or freeze. Summary of the Invention

[0004] In view of the above problems, this application provides a chip, a network interface card, and an electronic device, which can timely correct incorrect data in the memory to avoid the occurrence of multi-bit errors.

[0005] In a first aspect, an embodiment of this application provides a chip, which includes: a correction module, a write-back module, and a memory, where: the correction module is configured to determine the address to be corrected where a single-bit error occurs in the memory and the correction data corresponding to the address to be corrected when it is determined that a single-bit error occurs in the memory, and send the address to be corrected and the correction data to the write-back module; the write-back module is configured to store the address to be corrected and the correction data corresponding to the address to be corrected in a busy state; the write-back module is further configured to write the stored or received correction data into the address to be corrected in the memory in an idle state to correct the incorrect data in the address to be corrected.

[0006] In a second aspect, an embodiment of this application provides a network interface card, which includes: the above chip and an interface, and the chip communicates externally through the interface.

[0007] In a second aspect, an embodiment of this application provides an electronic device, which includes a central processing unit and the above chip. The chip is configured to schedule packets to the central processing unit or itself for processing, and the central processing unit is configured to process the packets scheduled by the chip.

[0008] The technical solution provided by this application, the chip includes: a correction module, a write-back module, and a memory, where: the correction module is used to determine the address to be corrected where a single-bit error occurs in the memory and the correction data corresponding to the address to be corrected when it is determined that a single-bit error occurs in the memory, and send the address to be corrected and the correction data to the write-back module; the write-back module is used to store the address to be corrected and the correction data corresponding to the address to be corrected in the busy state; the write-back module is further used to write the stored or received correction data into the address to be corrected in the memory in the idle state to correct the error data in the address to be corrected. Thus, the error data in the memory is corrected in time by the write-back module to prevent the chip from evolving from a single-bit error to a multi-bit error, so as to ensure that the processor can obtain correct data, thereby avoiding situations such as system exceptions or hangs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application, rather than all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0010] Figure 1 FIG. shows a schematic structural diagram of a chip provided by an embodiment of this application.

[0011] Figure 2 FIG. shows a schematic structural diagram of another chip provided by an embodiment of this application.

[0012] Figure 3 FIG. shows a schematic structural diagram of yet another chip provided by an embodiment of this application.

[0013] Figure 4 FIG. shows a schematic structural diagram of yet another chip provided by an embodiment of this application.

[0014] Figure 5 FIG. shows a schematic structural diagram of a write-back module provided by an embodiment of this application.

[0015] Figure 6 FIG. shows a schematic structural diagram of another write-back module provided by an embodiment of this application.

[0016] Figure 7 FIG. shows a schematic structural diagram of a network interface card provided by an embodiment of this application.

[0017] Figure 8 FIG. shows a schematic structural diagram of an electronic device provided by an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the objectives, technical solutions, and advantages of this application clearer, the following will further describe this application in detail with reference to the accompanying drawings. The described embodiments should not be regarded as limitations to this application. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0019] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and they can be combined with each other without conflict. In the following description, the term "a plurality of" refers to at least two.

[0020] In the following description, the terms "first / second" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second" can be interchanged in a specific order or sequence when permitted, so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0022] Error Checking and Correcting (ECC) technology detects and corrects errors by adding redundant bits to the memory. When the system reads the data in the memory, ECC can check the integrity of the data and, in the case of detecting a single-bit error, correct the error through hardware logic to ensure that the processor can obtain the correct data, thereby avoiding the situation where the processor obtains incorrect data and causes the system to malfunction or hang.

[0023] In a specific embodiment, please refer to Figure 1 , Figure 1 which shows a schematic structural diagram of a chip provided by an embodiment of this application. As Figure 1As shown, the chip 100 includes a correction module and a memory 110. Among them, the correction module includes a check value generation unit 121 and an ECC unit. The memory 110 can be a Random Access Memory (RAM). The memory 110 is used to store the data required by the chip. The check value generation unit 121 is used to generate a check value to be written into the memory 110. The ECC unit is used to determine the correction data corresponding to the address where a single-bit error occurs when a single-bit error occurs in the memory 110, so as to send the correction data to the processor to avoid the situation that the processor obtains incorrect data and causes system exceptions or hangs.

[0024] However, since the single-bit error in the memory 110 is not corrected in time, the errors accumulate and a multi-bit error occurs. The ECC unit cannot correct the multi-bit error, resulting in the situation that the processor obtains incorrect data, causing system exceptions or hangs.

[0025] To improve the above problems, the present application provides a chip, a network interface card, and an electronic device. The chip includes a correction module, a write-back module, and a memory, where: The correction module is used to determine the address to be corrected where a single-bit error occurs in the memory and the correction data corresponding to the address to be corrected when it is determined that a single-bit error occurs in the memory, and send the address to be corrected and the correction data to the write-back module; The write-back module is used to store the address to be corrected and the correction data corresponding to the address to be corrected in the busy state; The write-back module is further used to write the stored or received correction data into the address to be corrected in the memory in the idle state to correct the incorrect data in the address to be corrected.

[0026] Thus, the write-back module corrects the incorrect data in the memory in time to prevent a single-bit error from evolving into a multi-bit error, ensuring that the processor can obtain correct data, thereby avoiding situations such as system exceptions or hangs.

[0027] To enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

[0028] Please refer to Figure 2 , Figure 2 which shows a schematic structural diagram of another chip provided by an embodiment of the present application. As Figure 2 shown, the chip 200 includes a correction module 210, a write-back module 220, and a memory 230, where:

[0029] A correction module 210 is configured to determine a to-be-corrected address where a single-bit error occurs in the memory 230 and correction data corresponding to the to-be-corrected address when it is determined that a single-bit error occurs in the memory 230, and send the to-be-corrected address and the correction data to a write-back module 220; The write-back module 220 is configured to store the to-be-corrected address and the correction data corresponding to the to-be-corrected address in a busy state; The write-back module 220 is further configured to write the stored or received correction data into the to-be-corrected address of the memory 230 in an idle state to correct the error data in the to-be-corrected address.

[0030] In an embodiment of the present application, the correction module 210 may include a check value generation unit 211 and an ECC unit. The check value generation unit 211 is configured to generate a check value to be written into the memory 130. The ECC unit is configured to send the to-be-corrected address and the correction data corresponding to the to-be-corrected address to the write-back module 220.

[0031] In an embodiment of the present application, the write-back module 220 may include a Cache cache memory. The Cache cache memory may be configured to store the to-be-corrected address and the correction data corresponding to the to-be-corrected address. Wherein, the depth of the Cache cache memory may be 4 deep. It can be understood that the present application does not limit the specific depth of the Cache cache memory, and the user can use the Cache cache memory with the corresponding depth according to the actual situation.

[0032] In some embodiments, the write-back module 220 may further include a read-write logic function module. The read-write logic function module is configured to perform operations corresponding to a logic function read access request or a logic function write access request when the write-back module 220 receives a logic function read access request or a logic function write access request.

[0033] In an embodiment of the present application, the memory 230 may be a Random Access Memory (RAM).

[0034] That is to say, when the correction module 210 determines that a single-bit error occurs in the memory 230, it records the to-be-corrected address where the single-bit error occurs in the memory 230, and corrects the stored data corresponding to the to-be-corrected address of the memory to obtain the correction data corresponding to the to-be-corrected address. The correction module 210 sends the to-be-corrected address and the correction data corresponding to the to-be-corrected address to the write-back module 220 and / or the processor (so that in an idle state, the write-back module 220 can timely write the correction data back into the memory 230 in a timely manner, and the processor can obtain the correct data for subsequent programs or operations).

[0035] When the write-back module 220 is in a busy state and receives the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210, the address to be corrected and the correction data corresponding to the address to be corrected are stored. When the write-back module 220 switches from the busy state to the idle state, the stored or received correction data is written into the address to be corrected in the memory 230 to correct the error data in the address to be corrected. Thus, through the cooperation of the correction module 210, the write-back module 220, and the memory 230, the data stored in the address where a single-bit error occurs in the memory 230 can be corrected in a timely manner, so as to avoid the situation where the single-bit error in the memory 230 evolves into a multi-bit error, and thus the situation where the processor obtains error data due to the correction module 210 being unable to correct the error data, resulting in system exceptions or hangs, etc.

[0036] It can be understood that when the write-back module 220 is busy and receives the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210, the write-back module 220 can directly write the received correction data into the address to be corrected in the memory 230 to correct the error data in the address to be corrected. That is, the write-back module 220 does not need to store the received correction data and the correction data corresponding to the address to be corrected, and then write the stored correction data into the address to be corrected in the memory 230, so as to ensure that the write-back module 220 can write back in a timely manner while reducing the memory pressure on the write-back module 220.

[0037] Furthermore, in some embodiments, the write-back module 220 is further configured to determine that the state of the write-back module 220 is a busy state when executing a logical function read access request; or, the write-back module 220 is further configured to determine that the state of the write-back module 220 is a busy state when executing a logical function write access request.

[0038] The chip 200 further includes a processor; the processor is configured to send a logical function read access request or a logical function write access request to the write-back module. The processor may be a central processing unit (CPU). It can be understood that the present application does not limit what specific device the processor is, and the user can flexibly replace the device corresponding to the processor according to the actual situation.

[0039] It can be understood that the present application is not limited to the processor sending a logical function read access request or a logical function write access request to the write-back module 220. In other embodiments, other control modules (such as an external host, etc.) may also send a logical function read access request or a logical function write access request to the write-back module 220.

[0040] It can be understood that the present application is not limited to defining the state of the write-back module 220 as the busy state only when the write-back module 220 executes a logical function read access request or a logical function write access request. When the write-back module 220 executes other requests, the state of the write-back module 220 can also be defined as the busy state. The present application defines the state opposite to the busy state as the idle state. For example, the state when the write-back module 220 does not execute a logical function read access request or a logical function write access request can be defined as the idle state.

[0041] As can be seen from the above description, when the write-back module 220 receives the address to be corrected and the correction data corresponding to the address to be corrected from the correction module 210, and the write-back module 220 is executing a logical function read access request or a logical function write access request, the write-back module 220 stores the address to be corrected and the correction data corresponding to the address to be corrected, so that after the write-back module 220 finishes executing the logical function read access request or the logical function write access request, the stored or received correction data is written into the address to be corrected in the memory 130 to correct the error data in the address to be corrected. Among them, for how the write-back module 220 executes the operations corresponding to the logical function read access request or the logical function write access request, please refer to the following description.

[0042] In a specific embodiment, please refer to Figure 3 , Figure 3 which shows a schematic structural diagram of another chip provided by the embodiment of the present application. As Figure 3 shown, the write-back module 220 is further configured to determine whether there is a target address in the stored address to be corrected that is the same as the read address according to the read address corresponding to the logical function read access request; the write-back module 220 is further configured to, when it is determined that there is a target address in the stored address to be corrected that is the same as the read address, provide the correction data corresponding to the stored target address to the processor; the write-back module 220 is further configured to, when it is determined that there is no target address in the stored address to be corrected that is the same as the read address, provide the data stored at the target address in the memory to the processor.

[0043] That is to say, after the processor sends a logical function read access request to the write-back module 220, the write-back module 220 parses the logical function read access request to determine the read address corresponding to the logical function read access request. The write-back module 220 determines whether there is a target address in the stored addresses to be corrected that is the same as the read address according to the read address. When the write-back module 220 determines that there is a target address in the stored addresses to be corrected that is the same as the read address, it provides the correction data corresponding to the stored target address to the processor. When the write-back module 220 determines that there is no target address in the stored addresses to be corrected that is the same as the read address, it provides the data stored at the target address in the memory to the processor. This is to avoid the situation where, because the write-back module 220 has not yet written the correction data back to the memory 230 in a timely manner, the processor directly accesses the incorrect data corresponding to the target address in the memory 230, resulting in system exceptions or hangs due to the processor obtaining incorrect data.

[0044] In another specific embodiment, please refer to Figure 4 , Figure 4 which shows a schematic structural diagram of another chip provided by an embodiment of the present application. As Figure 4 shown, the write-back module 220 is further configured to determine the address to be written and the data to be written corresponding to the logical function write access request; the write-back module 220 is further configured to determine whether there is a target address in the stored addresses to be corrected that is the same as the address to be written; the write-back module 220 is further configured to invalidate the address to be corrected corresponding to the stored target address and the correction data corresponding to the address to be corrected when it is determined that there is a target address in the stored addresses to be corrected that is the same as the address to be written; the write-back module 220 is further configured to write the data to be written into the address to be corrected corresponding to the target address in the memory 230; the write-back module 220 is further configured to directly write the data to be written into the address to be corrected corresponding to the target address in the memory 230 when it is determined that there is no target address in the stored addresses to be corrected that is the same as the address to be written.

[0045] That is to say, after the processor sends a logical function write access request to the write-back module 220, the write-back module 220 parses the logical function write access request to determine the write address and write data corresponding to the logical function write access request. The write-back module 220 determines whether there is a target address in the stored addresses to be corrected that is the same as the write address according to the write address. When the write-back module 220 determines that there is a target address in the stored addresses to be corrected that is the same as the write address, it invalidates the address to be corrected corresponding to the stored target address and the correction data corresponding to the address to be corrected, and then writes the write data into the address to be corrected corresponding to the target address in the memory 230. Timely invalidating the address to be corrected corresponding to the target address and the correction data corresponding to the address to be corrected according to the logical function write access request can avoid writing the correction data corresponding to the target address into the address to be corrected corresponding to the target address in the memory 230 when the write-back module 220 is in an idle state, thus preventing the situation where the memory 230 stores incorrect data.

[0046] When the write-back module 220 determines that there is no target address in the stored addresses to be corrected that is the same as the write address, it directly writes the write data into the address to be corrected corresponding to the target address in the memory 230. After the write-back module 220 finishes the operation corresponding to the logical function write access request, it writes the correction data into the address to be corrected in the memory 130.

[0047] As can be seen from the above description, when the write-back module 120 receives a logical function read access request or a logical function write access request and receives the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module, the write-back module 120 first finishes the operation corresponding to the logical function read access request or the logical function write access request, and then writes the stored or received correction data into the address to be corrected in the memory 130 to avoid conflicts between the write-back module 120 when executing the logical function read access request, the logical function write access request, or writing the stored or received correction data into the address to be corrected in the memory 130.

[0048] When the write-back module 120 receives a logical function read access request or a logical function write access request and receives the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module, the write-back module 220 stores the address to be corrected and the correction data corresponding to the address to be corrected. Specifically, in some embodiments, the write-back module 220 includes a plurality of cache units 221. The write-back module 221 is specifically configured to store the address to be corrected and the correction data corresponding to the address to be corrected in a target cache unit among the plurality of cache units 221 when in a busy state.

[0049] Among them, the target cache unit can be a cache unit 221 among multiple cache units 221 that does not store the address to be corrected and the correction data corresponding to the address to be corrected. For example, when the write-back module 220 is in a busy state and the correction module 210 sends the address to be corrected and the correction data corresponding to the address to be corrected to the write-back module 220, the write-back module 220 can arbitrarily select a cache unit from multiple cache units 221 that do not store the address to be corrected and the correction data corresponding to the address to be corrected as the target cache unit, and store the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210 into the target cache unit.

[0050] Each of the multiple cache units 221 is used to store a set of the address to be corrected and the correction data corresponding to the address to be corrected.

[0051] Exemplarily, when the write-back module 220 is in a busy state and the correction module 210 sends a set of the address to be corrected and the correction data corresponding to the address to be corrected to the write-back module 220 (for example, the address to be corrected A and the correction data a corresponding to the address to be corrected A), the write-back module 220 stores the address to be corrected A and the correction data a corresponding to the address to be corrected A in the target cache unit.

[0052] Exemplarily, when the write-back module 220 is in a busy state and the correction module 210 sends two sets of the address to be corrected and the correction data corresponding to the address to be corrected to the write-back module 220 (for example, the address to be corrected A and the correction data a corresponding to the address to be corrected A, and the address to be corrected B and the correction data b corresponding to the address to be corrected B), the write-back module 220 stores the address to be corrected A and the correction data a corresponding to the address to be corrected A in the target cache unit 1, and the write-back module 220 stores the address to be corrected B and the correction data b corresponding to the address to be corrected B in the target cache unit 2.

[0053] When the write-back module 220 is in a busy state, by storing the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210 in the target cache unit, when the write-back module 220 switches from the busy state to the idle state, the write-back module 220 can write the correction data corresponding to the address to be corrected into the address to be corrected in the memory 230 according to the address to be corrected and the correction data corresponding to the address to be corrected stored in the target cache unit.

[0054] Further, in some embodiments, each of the multiple cache units 221 includes a status bit for indicating the status of the current cache unit 221; a write-back module 220, specifically configured to switch the status bit of the cache unit corresponding to the target address to an invalid status when it is determined that there is a target address in the stored address to be corrected that is the same as the address to be written, so as to invalidate the stored address to be corrected corresponding to the target address and the correction data corresponding to the address to be corrected.

[0055] When the status bit of the target cache unit is 0, it indicates that the current status of the target cache unit is the invalid status. When the status bit of the target cache unit is 1, it indicates that the current status of the target cache unit is the valid status. Specifically, when the write-back module 220 receives a logical function read access request, the write-back module 220 does not determine whether the address stored in the cache unit with the status bit of 0 is the same as the read address corresponding to the logical function read access request. And when the write-back module 220 receives a logical function write access request, the write-back module 220 does not determine whether the address stored in the cache unit with the status bit of 0 is the same as the address to be written corresponding to the logical function read access request.

[0056] In the initial state, the status bit of each of the multiple cache units 221 included in the write-back module 220 is in the invalid status, that is, the status bit of each of the multiple cache units 221 included in the write-back module 220 is 0.

[0057] Exemplarily, please refer to Figure 5 , Figure 5 shows a schematic structural diagram of a write-back module provided by an embodiment of the present application. As Figure 5 shown, the write-back module 220 includes four cache units 221. In the initial state, the status bit 2211 of each of the multiple cache units 221 included in the write-back module 220 is 0.

[0058] When the write-back module 220 is in the busy state and the correction module 210 sends the address to be corrected and the correction data corresponding to the address to be corrected to the write-back module 220, the write-back module 220 arbitrarily selects one cache unit 221 from the multiple cache units 221 as the target cache unit, switches the status bit of the target cache unit from 0 to 1, and stores the address to be corrected sent by the write-back module 220 and the correction data corresponding to the address to be corrected in the target cache unit.

[0059] When the write-back module 220 receives a logical function write access request, the write-back module 220 determines the address to be written and the data to be written corresponding to the logical function write access request; when the write-back module 220 determines that there is a target address in the stored addresses to be corrected that is the same as the address to be written, the write-back module 220 switches the status bit of the target cache unit corresponding to the target address from 1 to 0, so as to invalidate the address to be corrected stored in the target cache unit and the correction data corresponding to the address to be corrected, so as to prevent the write-back module 220 from writing the correction data stored in the target cache unit into the memory 230 again when in the idle state, so as to prevent the memory 230 from storing incorrect data.

[0060] Furthermore, in some embodiments, the write-back module 220 is specifically configured to determine an idle cache unit among multiple cache units 221 when in the busy state; the write-back module 220 is also specifically configured to determine any one of the cache units 221 in the idle cache unit as the target cache unit, and store the address to be corrected and the correction data corresponding to the address to be corrected in the target cache unit.

[0061] When the write-back module 220 is in the busy state and the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210 to the write-back module 220, the write-back module 220 determines an idle cache unit among multiple cache units 221, and arbitrarily selects one of the cache units 221 in the idle cache unit as the target cache unit.

[0062] Wherein, the idle cache unit can be a cache unit 221 among multiple cache units that does not store the address to be corrected and the correction data corresponding to the address to be corrected.

[0063] In some embodiments, each of the multiple cache units 221 includes an address bit and a data bit, the address bit is used to store the address to be corrected; the data bit is used to store the correction data corresponding to the address to be corrected.

[0064] In some embodiments, the write-back module 220 is specifically configured to store the address to be corrected in the address bit of the target cache unit and store the correction data corresponding to the address to be corrected in the data bit of the target cache unit when in the busy state.

[0065] Exemplarily, please refer to Figure 6 , Figure 6 shows a schematic structural diagram of another write-back module provided by an embodiment of the present application, as Figure 6As shown, the write-back module 220 includes four cache units 221. When the write-back module 220 is in a busy state, and the address to be corrected and the correction data corresponding to the address to be corrected sent by the correction module 210 to the write-back module 220, the write-back module 220 determines the fourth cache unit 221 as the target cache unit, switches the status bit 2211 of the target cache unit from 0 to 1, writes the address to be corrected sent by the write-back module 220 into the address bit 2212, and writes the correction data sent by the write-back module 220 into the data bit 2213.

[0066] Further, in some embodiments, the write-back module 220 is specifically configured to, when in an idle state, according to the address to be corrected stored in the target cache unit, write the correction data stored in the target cache unit into the memory address corresponding to the address to be corrected in the memory, and then delete the address to be corrected stored in the address bit of the target cache unit and the correction data stored in the data bit of the target cache unit.

[0067] The write-back module 220 timely deletes the address to be corrected that has been written back and the correction data corresponding to the address to be corrected, so that the write-back module 220 can have more idle cache units 221 to store the address to be corrected newly sent by the correction module 110 and the correction data corresponding to the address to be corrected.

[0068] Please refer to Figure 7 , Figure 7 shows a schematic structural diagram of a network interface card provided by an embodiment of the present application. As Figure 7 shown, the network interface card 300 includes the above-mentioned chip 200 and multiple interfaces 310. The chip 200 communicates externally through the interfaces 310. The interfaces 310 may include PCI / PCI-E interfaces, network interfaces, etc.

[0069] It can be understood that the detailed description of the chip 200 can refer to the above-mentioned embodiment, and will not be repeated here.

[0070] Please refer to Figure 8 , Figure 8 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application. As Figure 8 shown, the electronic device 400 includes a central processing unit 410 and the above-mentioned chip 200. The chip 200 is used to schedule the message to the central processing unit 410 or the chip 200 itself for processing, and the central processing unit 410 is used to process the message scheduled by the chip 200.

[0071] It can be understood that the detailed description of the chip 200 can refer to the above-mentioned embodiment, and will not be repeated here.

[0072] The present application provides a chip, a network interface card and an electronic device. The chip includes: a correction module, a write-back module and a memory, wherein: the correction module is configured to, when determining that a single-bit error occurs in the memory, determine a to-be-corrected address where the single-bit error occurs in the memory and correction data corresponding to the to-be-corrected address, and send the to-be-corrected address and the correction data to the write-back module; the write-back module is configured to store the to-be-corrected address and the correction data corresponding to the to-be-corrected address in a busy state; the write-back module is further configured to, in an idle state, write the stored or received correction data into the to-be-corrected address of the memory to correct the error data in the to-be-corrected address. Thus, the error data in the memory is corrected in time by the write-back module to prevent the single-bit error in the chip from evolving into a multi-bit error, so as to ensure that the processor can obtain correct data, thereby avoiding system exceptions or hangs and the like.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A chip, characterized in that: It includes a correction module, a write-back module and a memory, wherein: The correction module is used to determine the address to be corrected where the single-bit error occurs in the memory and the correction data corresponding to the address to be corrected, and send the address to be corrected and the correction data to the write-back module when it is determined that the memory has a single-bit error. The write-back module is used to store the address to be corrected and the correction data corresponding to the address to be corrected in a busy state; The write-back module is further used to write the stored or received correction data into the address to be corrected of the memory in an idle state to correct the erroneous data in the address to be corrected.

2. The chip according to claim 1, characterized in that: The chip also includes a processor; The processor is used to send a logical function read access request or a logical function write access request to the write-back module; The write-back module is further configured to determine that the state of the write-back module is the busy state when executing the logical function read access request; Alternatively, the write-back module is further configured to determine that the state of the write-back module is the busy state when executing the logical function write access request.

3. The chip according to claim 2, characterized in that: The write-back module is further used to determine whether there is a target address that is the same as the read address in the stored addresses to be corrected according to the read address corresponding to the logical function read access request; The write-back module is further configured to provide the processor with the correction data corresponding to the stored target address when it is determined that there is a target address identical to the read address in the stored addresses to be corrected; The write-back module is further configured to provide the processor with data stored at the target address in the memory when it is determined that there is no target address identical to the read address in the stored addresses to be corrected.

4. The chip according to claim 2, characterized in that: The write-back module is further used to determine the address to be written and the data to be written corresponding to the logical function write access request; The write-back module is further used to determine whether there is a target address that is the same as the address to be written in the stored addresses to be corrected; The write-back module is further configured to invalidate the address to be corrected corresponding to the stored target address and the correction data corresponding to the address to be corrected when it is determined that there is a target address identical to the address to be written in the stored address to be corrected; The write-back module is further used to write the data to be written into the address to be corrected in the memory corresponding to the target address; The write-back module is further configured to directly write the data to be written into the address to be corrected in the memory corresponding to the target address when it is determined that there is no target address identical to the address to be written in the stored addresses to be corrected.

5. The chip according to claim 4, characterized in that: The write-back module includes a plurality of cache units, each of which is used to store a set of addresses to be corrected and the correction data corresponding to the addresses to be corrected; each of the plurality of cache units includes a status bit, and the status bit is used to indicate the current status of the cache unit; The write-back module is specifically used to switch the status bit of the cache unit corresponding to the target address to an invalid state when it is determined that there is a target address that is the same as the address to be written in the stored address to be corrected, so as to invalidate the address to be corrected corresponding to the stored target address and the correction data corresponding to the address to be corrected.

6. The chip according to claim 1, characterized in that: The write-back module includes a plurality of cache units, and the write-back module is specifically configured to store the address to be corrected and the correction data corresponding to the address to be corrected in a target cache unit among the plurality of cache units when in the busy state.

7. The chip according to claim 6, characterized in that: The write-back module is specifically configured to determine a free cache unit among the plurality of cache units when in the busy state; The write-back module is further specifically configured to determine any cache unit in the free cache units as the target cache unit, and store the address to be corrected and the correction data corresponding to the address to be corrected in the target cache unit.

8. The chip according to claim 7, characterized in that: Each of the plurality of cache units includes an address bit and a data bit, wherein the address bit is used to store the address to be corrected; and the data bit is used to store the correction data corresponding to the address to be corrected.

9. The chip according to claim 8, characterized in that: The write-back module is specifically used to store the address to be corrected in the address bit of the target cache unit and store the correction data corresponding to the address to be corrected in the data bit of the target cache unit when in the busy state.

10. The chip according to claim 9, characterized in that: The write-back module is specifically used to, when in the idle state, write the corrected data stored in the target cache unit into the memory address corresponding to the address to be corrected in the memory according to the address to be corrected stored in the target cache unit, and then delete the address to be corrected stored in the address bit of the target cache unit and the corrected data stored in the data bit of the target cache unit.

11. A network interface card, comprising the chip and the interface as claimed in any one of claims 1 to 10, wherein the chip communicates externally through the interface.

12. An electronic device comprising a central processing unit and a chip as claimed in any one of claims 1 to 10, characterized in that: The chip is used to dispatch messages to the central processor or the chip itself for processing, and the central processor is used to process the messages dispatched by the chip.

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