Method for manufacturing gate groove of high electron mobility transistor

Abstract

The invention discloses a method for manufacturing a gate groove of a high-electron-mobility transistor, relates to the technical field of semiconductors, and is used for obtaining the gate groove with a smoother groove bottom surface, preventing an etching product from being accumulated on the surface of the gate groove and improving the performance of the manufactured high-electron-mobility transistor. The manufacturing method of the gate groove of the high electron mobility transistor comprises the following steps: providing a substrate; then, at least a buffer layer, a channel layer, and a barrier layer are formed on the substrate in the thickness direction of the substrate, the buffer layer, the channel layer, and the barrier layer being stacked in this order. Next, a first etching gas is utilized, and a dry etching process is adopted, so that a grid electrode groove which is concave inwards is formed in the side, away from the channel layer, of the barrier layer; the first etching gas comprises boron trichloride, chlorine and a volatile hydrocarbon compound.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a gate groove of a high electron mobility transistor. Background Art

[0002] A high electron mobility transistor, also known as a modulation-doped field effect transistor, is a type of field effect transistor. A high electron mobility transistor uses two materials with different energy gaps to form a heterojunction to provide a channel for carriers, rather than forming a conductive channel by doping as in a metal oxide semiconductor field effect transistor. Among them, the gallium nitride-based high electron mobility transistor developed in recent years has attracted a great deal of attention due to its good high-frequency characteristics. A high electron mobility transistor can operate at extremely high frequencies and is therefore widely used in mobile phones, satellite TVs, and radars.

[0003] However, since the gate groove in the existing high electron mobility transistor is usually formed by a dry etching process, the plasma bombardment in the dry etching is likely to cause material damage, which is not conducive to improving the working performance of the high electron mobility transistor. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a gate groove of a high electron mobility transistor, which is used to obtain a gate groove with a smoother groove bottom surface, prevent the accumulation of etching products on the surface of the gate groove, and is conducive to improving the working performance of the high electron mobility transistor.

[0005] To achieve the above purpose, the present invention provides a method for manufacturing a gate groove of a high electron mobility transistor. The method for manufacturing a gate groove of a high electron mobility transistor includes: First, providing a substrate. Next, along the thickness direction of the substrate, at least a buffer layer, a channel layer, and a barrier layer are sequentially stacked on the substrate. Next, using a first etching gas and adopting a dry etching process, an inwardly recessed gate groove is opened on the side of the barrier layer facing away from the channel layer; the first etching gas includes boron trichloride, chlorine, and a volatile hydrocarbon compound.

[0006] In the case of adopting the above technical solution, in the method for manufacturing a gate groove of a high electron mobility transistor provided by the present invention, an inwardly recessed gate groove is opened on the side of the barrier layer facing away from the channel layer, so that the subsequently formed gate is located in the gate groove, enhancing the control of the gate over the channel layer and enabling the high electron mobility transistor to have higher performance.

[0007] In addition, taking the gate recess of a gallium nitride-based high electron mobility transistor manufactured by using the manufacturing method provided by the present invention as an example for illustration: When using the first etching gas and adopting a dry etching process to form an inwardly recessed gate recess on the side of the barrier layer facing away from the channel layer, the volatile hydrocarbon compound can form a polymer in a plasma state. The dynamic protection layer formed based on this polymer can block the heavy ions bombarding the etching surface, thereby preventing lattice damage to some of the materials near the gate recess after etching, ensuring that the manufactured high electron mobility transistor has a high two-dimensional electron gas concentration and electron mobility, and being conducive to improving the working performance of the high electron mobility transistor. Secondly, the chlorine gas introduced into the reaction chamber can react with the barrier layer to generate etching products AlCl3 and GaCl3; and the volatile hydrocarbon compound introduced into the reaction chamber forms a that can react with the above-mentioned Ga-containing + etching product to generate easily volatile (CH3)3Ga. Since the evaporation temperature corresponding to (CH3)3Ga is only 55.7 °C, which is much lower than the evaporation temperatures corresponding to AlCl3 and GaCl3, it is possible to avoid the accumulation of Ga etching products on the material surface, obtain a smoother etching surface, and be conducive to improving the working performance of the high electron mobility transistor.

[0008] As a possible implementation solution, in the bottom surface of the gate recess, the root mean square surface roughness within each 2 μm × 2 μm area range is less than 0.6 nm. In this case, the bottom surface of the gate recess is relatively smooth. In other words, during the process of forming the gate recess on the side of the barrier layer facing away from the channel layer, at least most of the etching products have been removed, preventing a large amount of the above-mentioned etching products from accumulating on the surface of the gate recess, reducing the roughness of the material surface after etching, and being conducive to improving the working performance of the high electron mobility transistor.

[0009] As a possible implementation solution, the above-mentioned volatile hydrocarbon compound includes: volatile olefin compounds and / or volatile alkyne compounds.

[0010] As a possible implementation solution, the above-mentioned volatile hydrocarbon compound includes at least one of methane, ethane, and ethylene.

[0011] As a possible implementation solution, in the above-mentioned first etching gas, the gas flow rate of the volatile hydrocarbon compound is greater than or equal to 0.2 sccm and less than or equal to 10 sccm.

[0012] In the case of adopting the above technical solution, in the first etching gas, the gas flow rate of the volatile hydrocarbon compound within the above range can prevent the degree of bombardment damage to the etching surface and the degree of reduction in the surface roughness of the gate groove caused by the polymer formed by the volatile hydrocarbon compound in the plasma state from being small, ensuring that the manufactured high electron mobility transistor has high performance.

[0013] As a possible implementation, the pressure corresponding to the above dry etching process is greater than or equal to 1 mtorr and less than or equal to 50 mtorr.

[0014] As a possible implementation, the source power corresponding to the above dry etching process is greater than or equal to 80 W and less than or equal to 300 W.

[0015] As a possible implementation, the radio frequency power corresponding to the above dry etching process is greater than or equal to 5 W and less than or equal to 50 W.

[0016] As a possible implementation, the etching time corresponding to the above dry etching process is greater than or equal to 5 s and less than or equal to 100 s.

[0017] As a possible implementation, after providing a substrate and adopting a dry etching process, before using the first etching gas to form an inwardly recessed gate groove on the side of the barrier layer facing away from the channel layer, the manufacturing method of the gate groove of the high electron mobility transistor includes: along the thickness direction of the substrate, a buffer layer, a channel layer, a barrier layer, and a capping layer are sequentially stacked on the substrate. Next, a mask layer is formed on a part of the capping layer. The mask pattern of the mask layer is the same as the notch pattern of the gate groove. Then, under the masking action of the mask layer, the capping layer is selectively etched.

[0018] As a possible implementation, a dry etching process is adopted to selectively etch the capping layer. Among them, the pressure corresponding to the selective etching is greater than or equal to 1 mtorr and less than or equal to 50 mtorr; and / or, the source power corresponding to the selective etching is greater than or equal to 80 W and less than or equal to 500 W; and / or, the radio frequency power corresponding to the selective etching is greater than or equal to 2 W and less than or equal to 200 W; and / or, the etching time corresponding to the selective etching is greater than or equal to 5 s and less than or equal to 120 s.

[0019] As a possible implementation, the second etching gas is used, and a dry etching process is adopted to selectively etch the capping layer. The second etching gas is boron trichloride.

[0020] As a possible implementation, the above high electron mobility transistor is a gallium nitride-based high electron mobility transistor.

[0021] In the case of adopting the above technical solution, compared with Si and SiC, GaN material has higher electron mobility, saturated electron velocity and breakdown electric field. Based on this, when the manufactured high electron mobility transistor is a gallium nitride-based high electron mobility transistor, it is beneficial to reduce the on-resistance of the high electron mobility transistor and improve the conversion efficiency of the high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0023] Figure 1 It is an enlarged view of the topography of the bottom surface of the gate groove after forming the gate groove by using the relevant manufacturing method;

[0024] Figure 2 It is a simulation diagram of the bombardment energy of the etching surface by heavy ions by using the relevant manufacturing method;

[0025] Figure 3 It is a schematic longitudinal sectional view of the structure of the high electron mobility transistor manufactured in the embodiment of the present invention;

[0026] Figure 4 It is an enlarged view of the topography of the bottom surface of the gate groove in the embodiment of the present invention;

[0027] Figure 5 It is a simulation diagram of the bombardment energy of the etching surface by heavy ions by using the manufacturing method provided in the embodiment of the present invention;

[0028] Figure 6 It is a schematic longitudinal sectional view of the structure of the high electron mobility transistor formed by using the manufacturing method provided in the embodiment of the present invention during the manufacturing process Figure 1 ;

[0029] Figure 7 It is a schematic longitudinal sectional view of the structure of the high electron mobility transistor formed by using the manufacturing method provided in the embodiment of the present invention during the manufacturing process Figure 2 ;

[0030] Figure 8 It is a schematic longitudinal sectional view of the structure of the high electron mobility transistor formed by using the manufacturing method provided in the embodiment of the present invention during the manufacturing process Figure 3 ;

[0031] Figure 9 It is a schematic longitudinal sectional view of the structure of the high electron mobility transistor formed by using the manufacturing method provided in the embodiment of the present invention during the manufacturing process Figure 4 ;

[0032] Figure 10 It is a schematic process diagram when etching the barrier layer in the embodiment of the present invention;

[0033] Figure 11 It is a schematic longitudinal cross-section of the structure of a high electron mobility transistor formed by using the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 5 .

[0034] Reference numerals: 11 is a substrate, 12 is a buffer layer, 13 is a channel layer, 14 is a barrier layer, 15 is a gate recess, 16 is a gate, 17 is a source / drain, 18 is a capping layer, 19 is a mask layer, 20 is an oxide or other contaminants. Detailed implementation manners

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0036] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0037] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present invention and are not used to limit the present invention.

[0038] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] A high electron mobility transistor, also known as a modulation-doped field effect transistor, is a type of field effect transistor. The high electron mobility transistor uses two materials with different energy gaps to form a heterojunction to provide a channel for carriers, unlike a metal oxide semiconductor field effect transistor that requires doping to form a conductive channel. Among them, the gallium nitride-based high electron mobility transistor developed in recent years has attracted a great deal of attention due to its good high-frequency characteristics. The high electron mobility transistor can operate at extremely high frequencies and is thus widely used in mobile phones, satellite TVs, and radars.

[0041] To improve the frequency characteristics of a high electron mobility transistor, the method of shortening the gate length is usually adopted. However, shortening the gate length will also bring about the "short channel" effect, which is not conducive to improving the operating performance of the high electron mobility transistor. Specifically, generally, a gate groove needs to be opened in the barrier layer included in the high electron mobility transistor to achieve the shortening of the gate length. At this time, the subsequently formed gate can be formed in the gate groove to reduce the distance between the gate and the channel layer, which is conducive to improving the control ability of the gate of the high electron mobility transistor over the channel.

[0042] In the actual manufacturing process, as Figure 1 and Figure 2 shown, a dry etching process is usually adopted to open an inwardly recessed gate groove on the side of the barrier layer facing away from the channel layer by using boron trichloride and chlorine gas. Among them, the chlorine gas introduced into the reaction chamber can react with the barrier layer to generate etching products AlCl3 and GaCl3, and the introduced boron trichloride will be excited to BClx + and Cl-(x = 1, 2), where BClx +It has a strong bombardment effect and can act on the etching surface to help remove etching products. Since the volatilization temperatures of the above-mentioned etching products AlCl3 and GaCl3 are 183°C and 201.3°C respectively, and their volatilization temperatures are relatively high. If the etching products are removed by high-energy ion bombardment, lattice damage will occur in some materials near the gate groove, resulting in a decrease in the two-dimensional electron gas concentration and electron mobility in the high electron mobility transistor. If low-power etching is used to reduce etching damage, some etching products will accumulate on the surface of the formed gate groove, resulting in a relatively high surface roughness of the gate groove, which is not conducive to the subsequent formation of the gate. At the same time, low-power etching is also prone to cause plasma instability, affecting the consistency of gate groove etching and resulting in low working performance of the high electron mobility transistor.

[0043] To solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a gate groove of a high electron mobility transistor. In terms of materials, the high electron mobility transistor manufactured by using the manufacturing method provided by the embodiment of the present invention can be any high electron mobility transistor such as a gallium nitride-based high electron mobility transistor or a gallium arsenide-based high electron mobility transistor. In this case, compared with Si and SiC, the GaN material has higher electron mobility, saturated electron velocity, and breakdown electric field. Based on this, when the high electron mobility transistor is a gallium nitride-based high electron mobility transistor, it is beneficial to reduce the on-resistance of the high electron mobility transistor and improve the conversion efficiency of the high electron mobility transistor.

[0044] In terms of structure, the manufacturing method provided by the embodiment of the present invention does not specifically limit the structure of the formed high electron mobility transistor, as long as the gate included in the high electron mobility transistor is formed in the gate groove and can be applied to the manufacturing method provided by the embodiment of the present invention.

[0045] Exemplarily, as Figure 3 shown, the high electron mobility transistor formed by using the manufacturing method provided by the embodiment of the present invention may include: a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a gate 16, and source / drain electrodes 17. Along the thickness direction of the substrate 11, the buffer layer 12, the channel layer 13, and the barrier layer 14 are sequentially stacked on the substrate 11. An inwardly recessed gate groove 15 is formed on the side of the barrier layer 14 facing away from the channel layer 13.

[0046] Among them, the above-mentioned substrate can be a sapphire substrate, a silicon substrate, a silicon carbide substrate, etc.

[0047] For the buffer layer, channel layer, and barrier layer stacked in sequence as described above, the materials of the buffer layer, channel layer, and barrier layer can be determined according to the type of high electron mobility transistor to be fabricated. Exemplarily, when the high electron mobility transistor to be fabricated is a gallium nitride-based high electron mobility transistor, the materials of the buffer layer and channel layer can be gallium nitride, and the material of the barrier layer can be aluminum gallium nitride.

[0048] Secondly, the embodiments of the present invention do not specifically limit the thicknesses of the buffer layer, channel layer, and barrier layer, nor the size of the gate groove formed in the barrier layer, as long as they can be applied to the manufacturing method of the gate groove of the high electron mobility transistor provided by the embodiments of the present invention.

[0049] As for the roughness of the bottom surface of the gate groove, it can be determined according to the specific manufacturing process. Exemplarily, in the bottom surface of the gate groove, the root mean square surface roughness within each 2μm×2μm area range can be less than 0.6nm. Specifically, its specific value can be any value less than 0.6nm. For example: the root mean square surface roughness within each 2μm×2μm area range in the bottom surface of the gate groove can be 0.1nm, 0.2nm, 0.3nm, 0.4nm, 0.5nm, 0.55nm, or 0.59nm, etc.

[0050] For the above-mentioned gate and source / drain, the materials of the gate and source / drain can be conductive materials such as gold, nickel, titanium, or silver. Secondly, the embodiments of the present invention do not specifically limit the distance between the gate and the source / drain, which can be determined according to the size requirements of the high electron mobility transistor to be fabricated in the actual application scenario, and no specific limitation is made here.

[0051] In the case of adopting the above technical solution, as Figure 3 shown, in the high electron mobility transistor formed by using the manufacturing method provided by the embodiments of the present invention, a gate groove recessed inward is formed on the side of the barrier layer 14 facing away from the channel layer 13. And the gate 16 is located in the gate groove to reduce the distance between the gate 16 and the channel layer 13, enhance the control of the gate 16 over the channel layer 13, and enable the high electron mobility transistor to have higher performance. Based on this, as Figure 4 shown, in the bottom surface of the above-mentioned gate groove, the root mean square surface roughness within each 2μm×2μm area range is less than 0.6nm, and at this time, the bottom surface of the gate groove is relatively smooth. In other words, during the process of forming the gate groove on the side of the barrier layer 14 facing away from the channel layer 13, at least most of the etching products have been removed, preventing a large amount of the above-mentioned etching products from accumulating on the surface of the gate groove and affecting the formation of the gate 16, which is beneficial to improving the working performance of the fabricated high electron mobility transistor.

[0052] The following will be based on Figures 6 to 11A cross-sectional view of the operations shown describes the process of manufacturing the gate recess of a high electron mobility transistor according to an embodiment of the present invention. Specifically, the method for manufacturing the gate recess of the high electron mobility transistor includes the following steps:

[0053] First, a substrate is provided. The material of the substrate can be referred to the previous text and will not be elaborated here.

[0054] Next, as Figure 6 shown, along the thickness direction of the substrate 11, at least a buffer layer 12, a channel layer 13, and a barrier layer 14 are sequentially formed and stacked on the substrate 11.

[0055] Among them, the materials of the above buffer layer, channel layer, and barrier layer can be referred to the previous text. Secondly, in the actual manufacturing process, processes such as chemical vapor deposition can be used to form a buffer layer, a channel layer, and a barrier layer that are sequentially stacked on the substrate.

[0056] In some cases, if the manufactured high electron mobility transistor further includes a capping layer, after providing a substrate, the method for manufacturing the gate recess of the high electron mobility transistor may include: as Figure 6 shown, along the thickness direction of the substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a capping layer 18 are sequentially formed and stacked on the substrate 11. Next, as Figure 7 shown, a mask layer 19 is formed on a part of the capping layer 18; the mask pattern of the mask layer 19 is the same as the notch pattern of the gate recess 15. Then, as Figure 8 shown, under the masking action of the mask layer 19, the capping layer 18 is selectively etched.

[0057] In the actual manufacturing process, processes such as chemical vapor deposition can be used to form a buffer layer, a channel layer, a barrier layer, and a capping layer that are sequentially stacked on the substrate. Then, the specific formation process of the mask layer can be determined according to the material of the mask layer. For example: when the mask layer is a photoresist mask layer, a spin coating process can be used to form a whole layer of photoresist material covering the capping layer. Then, the photoresist material is sequentially exposed and developed to obtain the mask layer. Next, processes such as dry etching can be used, and under the masking action of the mask layer, the capping layer is selectively etched. It should be noted that as Figure 7 shown, there may be oxides or other contaminants 20 on the surface of the capping layer, and while selectively etching the capping layer, the oxides or other contaminants 20 exposed by the mask layer 19 also need to be removed.

[0058] Among them, the etching conditions for selectively etching the capping layer can be determined according to the adopted etching process and the actual application scenario. Exemplarily, in the case of selectively etching the capping layer by using a dry etching process, the pressure corresponding to the selective etching can be greater than or equal to 1 mtorr and less than or equal to 50 mtorr; the source power corresponding to the selective etching can be greater than or equal to 80 W and less than or equal to 500 W; secondly, the radio frequency power corresponding to the selective etching can be greater than or equal to 2 W and less than or equal to 200 W; in addition, the etching time corresponding to the selective etching can be greater than or equal to 5 s and less than or equal to 120 s. For example: in the case of selectively etching the capping layer by using a dry etching process, the pressure corresponding to the above-mentioned selective etching can be 1 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr or 50 mtorr, etc.; secondly, the source power corresponding to the selective etching can be 80 W, 100 W, 200 W, 200 W, 300 W, 400 W or 500 W, etc.; thirdly, the radio frequency power corresponding to the selective etching can be 2 W, 10 W, 30 W, 50 W, 80 W, 100 W, 150 W or 200 W, etc.; in addition, the etching time corresponding to the selective etching can be 5 s, 10 s, 30 s, 50 s, 60 s, 80 s, 100 s or 120 s, etc. It can be seen that the source power, radio frequency power and etching time corresponding to the selective etching all have a large optional range, and appropriate values can be selected according to the requirements of different actual application scenarios, which is beneficial to improving the applicability of the gate groove manufacturing method of the high electron mobility transistor provided by the embodiments of the present invention in different application scenarios.

[0059] Exemplarily, a second etching gas can be used, and a dry etching process can be adopted to selectively etch the capping layer. The second etching gas can be boron trichloride. In this case, boron trichloride is excited to BClx + , and the surface oxide and the capping layer are etched away through the bombardment effect. The gas flow rate of the second etching gas can be determined according to the actual application scenario. For example: the gas flow rate of the second etching gas can be 5 sccm.

[0060] Next, as Figure 9 and Figure 10 shown, a first etching gas is used, and a dry etching process is adopted to open an inwardly recessed gate groove 15 on the side of the barrier layer 14 facing away from the channel layer 13; the first etching gas includes boron trichloride, chlorine and volatile hydrocarbon compounds.

[0061] Specifically, the ratio of boron trichloride, chlorine, and volatile hydrocarbon compounds in the first etch gas can be determined according to the actual application scenario and is not specifically limited here. Exemplarily, in the first etch gas, the gas flow rate of boron trichloride can be 2 sccm, and the gas flow rate of chlorine can be 10 sccm. As for the volatile hydrocarbon compound, its gas flow rate can be greater than or equal to 0.2 sccm and less than or equal to 10 sccm. In this case, when the gas flow rate of the volatile hydrocarbon compound in the first etch gas is within the above range, the volatile hydrocarbon gas can form a polymer under plasma conditions, reducing the bombardment damage of the high-energy plasma to the surface of the gate groove, preventing the degree of reducing the bombardment damage of the etch surface and the degree of reducing the roughness of the gate groove surface from being small due to the small gas flow rate of the volatile hydrocarbon compound, and ensuring that the fabricated high electron mobility transistor has high performance. At the same time, it can also prevent the etching effect of boron trichloride and chlorine on the barrier layer from decreasing due to the large gas flow rate of the volatile hydrocarbon compound, avoiding too low etching efficiency.

[0062] As for the type of the volatile hydrocarbon compound, it can be any hydrocarbon compound with volatile characteristics as long as it can be applied to the method for manufacturing the gate groove of the high electron mobility transistor provided in the embodiment of the present invention.

[0063] Exemplarily, the above-mentioned volatile hydrocarbon compound can include: volatile olefin compounds and / or volatile alkyne compounds. Among them, the above-mentioned volatile olefin compounds can be ethylene, propylene, etc. The above-mentioned volatile alkyne compounds can be acetylene, propyne, etc.

[0064] Exemplarily, the above-mentioned volatile hydrocarbon compound can include at least one of methane, ethane, and ethylene.

[0065] In addition, the etching conditions for selectively etching the barrier layer can be determined according to the actual application scenario. Secondly, a dry etching method such as inductively coupled plasma can be used to etch the barrier layer.

[0066] Exemplarily, the pressure corresponding to the above dry etching process can be greater than or equal to 1 mtorr and less than or equal to 50 mtorr. For example: the pressure corresponding to the dry etching process can be 1 mtorr, 5 mtorr, 10 mtorr, 20 mtorr, 30 mtorr, or 50 mtorr, etc.

[0067] Exemplarily, the source power corresponding to the above dry etching process can be greater than or equal to 80 W and less than or equal to 300 W. For example, the source power corresponding to the dry etching process can be 80 W, 100 W, 120 W, 150 W, 200 W, 220 W, 260 W, or 300 W, etc.

[0068] Exemplarily, the radio frequency power corresponding to the above dry etching process can be greater than or equal to 5 W and less than or equal to 50 W. For example, the radio frequency power corresponding to the dry etching process can be 5 W, 10 W, 20 W, 30 W, 40 W, or 50 W, etc.

[0069] Exemplarily, the etching time corresponding to the above dry etching process can be greater than or equal to 5 s and less than or equal to 100 s. For example, the etching time corresponding to the dry etching process can be 5 s, 10 s, 30 s, 60 s, 90 s, or 100 s, etc.

[0070] It should be noted that when the manufactured high electron mobility transistor further includes a capping layer, selective etching of the capping layer and etching of the side of the barrier layer facing away from the channel layer to form a gate groove can be achieved through the same mask layer. When the manufactured high electron mobility transistor does not include a capping layer, the above method can be adopted, and a corresponding mask layer is formed on the barrier layer before etching the barrier layer. And after forming the gate groove, processes such as dry etching or wet etching can be used to remove the mask layer.

[0071] Next, as Figure 11 shown, a gate 16 is formed in the gate groove. Specifically, processes such as physical vapor deposition can be used to form the gate 16 in the gate groove.

[0072] Then, as Figure 11 shown, source / drain electrodes 17 are formed at intervals on both sides of the gate groove. Specifically, processes such as physical vapor deposition can be used to form the above source / drain electrodes 17. The materials of the source / drain electrodes 17 and the gate 16 can refer to the previous text. In addition, the present invention embodiment does not specifically limit the formation order of the gate 16 and the source / drain electrodes 17.

[0073] It can be seen from the above manufacturing process that in the method for manufacturing a gate groove of a high electron mobility transistor provided by the embodiment of the present invention, a gate groove recessed inward is opened on the side of the barrier layer facing away from the channel layer, so that the subsequently formed gate is located in the gate groove, enhancing the control of the gate over the channel layer, and enabling the high electron mobility transistor to have higher performance.

[0074] In addition, as Figures 5 to 10As shown in the figure, taking the gate groove of a gallium nitride-based high electron mobility transistor manufactured by using the manufacturing method provided in the embodiment of the present invention as an example for illustration: When using the first etching gas and adopting a dry etching process to form an inwardly recessed gate groove 15 on the side of the barrier layer 14 away from the channel layer 13, volatile hydrocarbon compounds can form polymers in a plasma state. Based on the dynamic protective layer formed by this polymer (see Figure 10 for the C-H polymer / AlCl3 / GaCl3 in it), it can block the heavy ions bombarding the etching surface, thereby preventing lattice damage to some materials near the gate groove 15 after etching, ensuring that the manufactured high electron mobility transistor has a high two-dimensional electron gas concentration and electron mobility, and is conducive to improving the working performance of the high electron mobility transistor. Secondly, the chlorine gas introduced into the reaction chamber can react with the barrier layer 14 to generate etching products AlCl3 and GaCl3; and the formed by the volatile hydrocarbon compounds introduced into the reaction chamber in a plasma state can react with the above-mentioned etching products containing Ga + to generate easily volatile (CH3)3Ga. Since the evaporation temperature corresponding to (CH3)3Ga is only 55.7 °C, which is much lower than the evaporation temperature corresponding to GaCl3, it is possible to avoid the accumulation of Ga etching products on the material surface, obtain a smoother etching surface, and is conducive to improving the working performance of the high electron mobility transistor.

[0075] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0076] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a gate recess of a high electron mobility transistor, characterized in that, include: providing a substrate; At least a buffer layer, a channel layer and a barrier layer which are stacked in sequence are formed on the substrate along the thickness direction of the substrate; A first etching gas is used and a dry etching process is adopted to open an inwardly recessed gate groove on a side of the barrier layer away from the channel layer; the first etching gas includes boron trichloride, chlorine and volatile hydrocarbon compounds.

2. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, wherein In the bottom surface of the gate groove, the surface root mean square roughness within an area of ​​2 μm×2 μm is less than 0.6 nm.

3. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, characterized in that, The volatile hydrocarbon compounds include: volatile olefin compounds and / or volatile acetylene compounds.

4. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, characterized in that The volatile hydrocarbon compound includes at least one of methane, ethane and ethylene.

5. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, characterized in that, In the first etching gas, a gas flow rate of the volatile hydrocarbon compound is greater than or equal to 0.2 sccm and less than or equal to 10 sccm.

6. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, characterized in that, The pressure corresponding to the dry etching process is greater than or equal to 1 mtorr and less than or equal to 50 mtorr; and / or, The source power corresponding to the dry etching process is greater than or equal to 80 W and less than or equal to 300 W; and / or, The RF power corresponding to the dry etching process is greater than or equal to 5W and less than or equal to 50W; and / or, The etching time corresponding to the dry etching process is greater than or equal to 5 s and less than or equal to 100 s.

7. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 1, wherein After providing a substrate, the dry etching process is adopted, and before a gate groove is formed inwardly on a side of the barrier layer away from the channel layer using a first etching gas, the gate groove manufacturing method of the high electron mobility transistor includes: Forming a buffer layer, a channel layer, a barrier layer and a cap layer stacked in sequence on the substrate along the thickness direction of the substrate; forming a mask layer on a portion of the cap layer; the mask layer has a mask pattern that is the same as the notch pattern of the gate groove; Under the masking effect of the mask layer, the cap layer is selectively etched.

8. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 7, wherein The cap layer is selectively etched by using a dry etching process; wherein, The pressure corresponding to the selective etching is greater than or equal to 1mtorr and less than or equal to 50mtorr; and / or, the source power corresponding to the selective etching is greater than or equal to 80W and less than or equal to 500W; and / or, the RF power corresponding to the selective etching is greater than or equal to 2W and less than or equal to 200W; and / or, the etching time corresponding to the selective etching is greater than or equal to 5s and less than or equal to 120s.

9. The method for manufacturing a gate recess of a high electron mobility transistor according to claim 7, characterized in that, The selective etching of the cap layer is performed using a second etching gas and a dry etching process; the second etching gas is boron trichloride.

10. The method for manufacturing a gate recess of a high electron mobility transistor according to any one of claims 1 to 9, characterized in that, The high electron mobility transistor is a gallium nitride-based high electron mobility transistor.

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