Packaging substrate structure and preparation method thereof

Abstract

The invention provides a package substrate structure and a preparation method thereof, and the method comprises the steps: arranging a graphical interconnection layer on a carrier substrate, and arranging an inorganic material layer on the interconnection layer, and enabling the inorganic material layer to be flush with the surface of a connection structure; the interconnection layer and the inorganic material layer form a core plate layer comprising a first surface and a second surface which are opposite to each other; removing the carrier substrate; the first surface and the second surface are provided with a graphical medium adding layer comprising a through hole penetrating through the medium adding layer, and a part of the interconnection layer is exposed; and the patterned conductive layer is arranged to form effective electric connection with the interconnection layer through the through hole. According to the invention, the inorganic material layer is used as the core plate of the packaging substrate, so that the expansion and contraction deformation of the packaging substrate is reduced, the warping problem of the packaging substrate is relieved, the flatness of the surface of the packaging substrate is improved, and a circuit with higher precision is realized; the interconnection performance of the packaging substrate is improved by utilizing the low dielectric constant and the low dielectric loss factor of the inorganic material layer; in addition, the core plate of the packaging substrate is arranged by using a 3D printing technology, so that the flatness of the core plate is further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a package substrate structure and a preparation method thereof. Background Art

[0002] With the rapid development of electronic technology, the number of I / O (input / output pins) on chips has increased. As a connection bridge between integrated chips and printed circuit boards, the line fineness requirements for package substrates are also getting higher and higher, which puts higher requirements on the package substrates themselves. Traditional package substrates can no longer meet the needs. In addition, multi-chip packaging and heterogeneous integration applications are becoming more and more widespread. Multiple chips are embedded on the package substrate at the same time to form 2.5D or 3D multi-chip packaging. This technology also requires smaller wiring density and higher integration of the package substrate.

[0003] However, such packaging has higher requirements for the warpage and deformation of the package substrate. Due to the core board of traditional organic IC (integrated circuit) package substrates being composed of polymers and glass fibers, there is large shrinkage and expansion deformation, serious warpage, and poor flatness of the board surface, making it difficult to form fine conductive lines, resulting in limited achievable line integration. Moreover, due to the large energy loss and poor interconnect performance of the core board material. The prior art currently solves this problem by increasing the board thickness, but if the board thickness is too large, it will cause an increase in the overall board thickness of the IC package substrate and a significant increase in weight, bringing inconvenience to production operations.

[0004] Therefore, there is an urgent need for a package substrate that can reduce warpage and deformation and improve interconnect performance.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a package substrate structure and a preparation method thereof, which are used to solve the problems of serious warpage and limited integration of the package substrate in the prior art.

[0007] To achieve the above purpose, the present invention provides a preparation method for a package substrate structure, and the preparation method includes:

[0008] Providing a carrier substrate, and disposing a patterned interconnect layer on the carrier substrate, the interconnect layer including a conductive structure and a connection structure, the connection structure being located on a preset conductive structure for effectively electrically connecting to a structure above the connection structure;

[0009] An inorganic material layer is provided on the interconnect layer. The inorganic material layer fills the gaps between the patterned interconnect layers and covers the interconnect layer to be flush with the surface of the connection structure, exposing the surface of the connection structure; the interconnect layer and the inorganic material layer constitute a core board layer, and the core board layer includes opposite first and second surfaces, and both the first surface and the second surface are parallel to the carrier substrate;

[0010] Remove the carrier substrate;

[0011] Patterned dielectric build-up layers are provided on both the first surface and the second surface of the core board layer. The patterned dielectric build-up layers include through holes penetrating the dielectric build-up layers to expose a part of the interconnect layer;

[0012] A patterned conductive layer is provided on the dielectric build-up layer, and the conductive layer forms an effective electrical connection with the interconnect layer through the through hole.

[0013] Optionally, the material of the inorganic material layer is a material including one or more arbitrary combinations of silicon element, nitrogen element or aluminum element.

[0014] Optionally, the material of the inorganic material layer is one or more arbitrary combinations of pure silicon, silicide, alumina or silicon nitride.

[0015] Optionally, multiple layers of the interconnect layer and the inorganic material layer are provided to constitute the core board layer. Each interconnect layer is coated with a layer of the inorganic material layer, and effective electrical connection is achieved between each interconnect layer through the connection structure.

[0016] Optionally, multiple layers of the dielectric build-up layer and the conductive layer are repeatedly provided, and effective electrical connection is formed between adjacent conductive layers through the through holes of the dielectric build-up layer.

[0017] Optionally, a solder mask layer is filled in the gaps between the exposed patterned conductive layers, and / or a surface treatment layer is provided on the exposed patterned conductive layer.

[0018] Optionally, the interconnect layer and / or the inorganic material layer are provided by 3D printing technology.

[0019] Optionally, the interconnect layer is provided by direct metal laser sintering.

[0020] Optionally, the inorganic material layer is provided by stereolithography 3D printing technology.

[0021] The present invention also provides a package substrate structure. The package substrate structure is obtained by using any one of the above preparation methods, and the package substrate structure includes a core board layer, a dielectric build-up layer and a conductive layer;

[0022] The core board layer includes a patterned interconnect layer and an inorganic material layer covering the interconnect layer and the voids therebetween. The interconnect layer includes a conductive structure and a connection structure. The connection structure is located on the conductive structure for effective electrical connection with the structure above the connection structure.

[0023] The core board layer includes opposite first and second surfaces, both of which are parallel to the carrier substrate. The dielectric enhancement layer is located on the first and second surfaces, and the dielectric enhancement layer is provided with through holes penetrating the dielectric enhancement layer. The conductive layer is located on the dielectric enhancement layer, and the conductive layer is effectively electrically connected to the interconnect layer of the core board layer through the through holes.

[0024] As described above, the package substrate structure and its manufacturing method of the present invention have the following beneficial effects:

[0025] In the present invention, by using an inorganic material layer as the core board of the package substrate, the expansion, shrinkage and deformation of the package substrate are reduced, the warping problem of the package substrate is alleviated, the flatness of the package substrate surface is improved, and a circuit with higher precision is realized.

[0026] In the present invention, the low dielectric constant and low dielectric loss factor of the inorganic material layer are utilized to improve the interconnect performance of the package substrate.

[0027] In the present invention, the core board of the package substrate is set by using 3D printing technology, further improving the flatness of the core board. Description of the Drawings

[0028] Figure 1 It shows a schematic structural diagram of providing a carrier substrate and an interconnect layer in step 1 of the manufacturing method of the package substrate structure of the present invention.

[0029] Figure 2 It shows a schematic structural diagram of setting an inorganic material layer in step 2 of the manufacturing method of the package substrate structure of the present invention.

[0030] Figure 3 It shows a schematic structural diagram of setting a multi-layer interconnect layer and an inorganic material layer in an optional example of step 2 of the manufacturing method of the package substrate structure of the present invention.

[0031] Figure 4 It shows a schematic structural diagram of removing the carrier substrate in step 3 of the manufacturing method of the package substrate structure of the present invention.

[0032] Figure 5 It shows a schematic structural diagram of setting a dielectric enhancement layer in step 4 of the manufacturing method of the package substrate structure of the present invention.

[0033] Figure 6It shows a schematic structural diagram of setting a seed layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0034] Figure 7 It shows a schematic structural diagram of setting a mask layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0035] Figure 8 It shows a schematic structural diagram of an electroplated layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0036] Figure 9 It shows a schematic structural diagram of removing the mask layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0037] Figure 10 It shows a schematic structural diagram of setting a multi-layer dielectric build-up layer and a conductive layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0038] Figure 11 It shows a schematic structural diagram of setting a solder mask layer and a surface treatment layer in an optional example of step 5 in the preparation method of the encapsulation substrate structure of the present invention.

[0039] Figure 12 It shows a schematic structural diagram of the encapsulation substrate structure in the present invention.

[0040] Element number description

[0041] 1. Core board layer; 11. Carrier substrate; 12. Interconnection layer; 121. Conductive structure; 122. Connection structure; 13. Inorganic material layer;

[0042] 21. Dielectric build-up layer; 211. Through hole; 22. Conductive layer; 221. Seed layer; 222. Electroplated layer; 23. Mask layer;

[0043] 31. Solder mask layer; 32. Surface treatment layer. Detailed implementation manners

[0044] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] When describing the embodiments of the present invention in detail, for the convenience of description, the schematic diagrams showing the device structure may be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0046] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings.

[0047] In the context of the present application, the structure in which the first feature is "above" the second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0049] The present invention provides a method for preparing a packaging substrate structure, and the preparation method includes:

[0050] Step 1: Provide a carrier substrate, and dispose a patterned interconnect layer on the carrier substrate. The interconnect layer includes a conductive structure and a connection structure, and the connection structure is located on the preset conductive structure for effectively electrically connecting to a structure above the connection structure;

[0051] Step 2: Dispose an inorganic material layer on the interconnect layer. The inorganic material layer fills the gaps between the patterned interconnect layers and covers the interconnect layer to be flush with the surface of the connection structure, so that the surface of the connection structure is exposed; the interconnect layer and the inorganic material layer constitute a core board layer, and the core board layer includes opposite first and second surfaces, and both the first surface and the second surface are parallel to the carrier substrate;

[0052] Step 3: Remove the carrier substrate;

[0053] Step 4: Dispose patterned dielectric layers on both the first surface and the second surface of the core board layer. The patterned dielectric layers include through holes penetrating the dielectric layers to expose part of the interconnect layer;

[0054] Step 5: Form a patterned conductive layer on the dielectric layer by adding layers, and the conductive layer forms an effective electrical connection with the interconnect layer through the through holes.

[0055] The preparation method of the packaging substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the packaging substrate structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0056] First, as Figure 1 shown, perform Step 1, provide a carrier substrate 11, and form a patterned interconnect layer 12 on the carrier substrate 11. The interconnect layer 12 includes a conductive structure 121 and a connection structure 122. The connection structure 122 is located on the preset conductive structure 121 for effective electrical connection with the structure above the connection structure 122.

[0057] In one embodiment, the interconnect layer 12 is formed by 3D printing technology.

[0058] By using 3D printing technology to form the interconnect layer 12, the present invention improves the flatness and transmission performance of the packaging substrate, reduces costs compared with traditional preparation methods, improves the preparation efficiency and preparation accuracy, and is conducive to the application and popularization of this solution.

[0059] In one embodiment, the interconnect layer 12 is formed by direct metal laser sintering.

[0060] The present invention uses direct metal laser sintering (DMLS) to form the interconnect layer 12, which has low cost, fast forming speed and good performance, so as to ensure the preparation yield while improving the preparation efficiency.

[0061] In one embodiment, electron beam melting (EBM) is used to form the interconnect layer 12.

[0062] In one embodiment, the material of the interconnect layer 12 includes any one or more of titanium, titanium alloy, aluminum alloy, copper, copper alloy, silver, silver alloy, tin, and tin alloy. Other suitable materials can also be reasonably selected according to the requirements of the packaging substrate and the performance of the conductive material.

[0063] Then, as Figure 2As shown, step 2 is carried out. An inorganic material layer 13 is provided on the interconnect layer 12. The inorganic material layer 13 fills the gaps between the patterned interconnect layer 12 and covers the interconnect layer 12 to be flush with the surface of the connection structure 122, exposing the surface of the connection structure 122. The interconnect layer 12 and the inorganic material layer 13 constitute a core board layer 1. The core board layer 1 includes opposite first and second surfaces, and both the first surface and the second surface are parallel to the carrier substrate 11.

[0064] In one embodiment, the material of the inorganic material layer 13 is a material including one or more arbitrary combinations of silicon element, nitrogen element or aluminum element.

[0065] In one embodiment, the material of the inorganic material layer 13 is one or more arbitrary combinations of pure silicon, silicide, aluminum oxide or silicon nitride.

[0066] In one embodiment, the material of the inorganic material layer 13 is silicon dioxide.

[0067] The present invention further optimizes the solution to the warping problem of the packaging substrate and the improvement of the transmission performance by using an inorganic material layer 13 based on silicon, nitrogen or / and aluminum.

[0068] In one embodiment, the inorganic material layer 13 is provided by 3D printing technology.

[0069] The present invention provides the inorganic material layer 13 by 3D printing technology, which reduces the cost, improves the preparation efficiency and preparation accuracy compared with the traditional preparation method while improving the flatness and transmission performance of the packaging substrate, and is conducive to the application and popularization of this solution.

[0070] In one embodiment, the inorganic material layer 13 is provided by photocuring 3D printing technology.

[0071] The present invention forms the core board layer 1 by using photocuring 3D printing technology, which has a fast forming speed, high automation degree, can form any complex shape, high dimensional accuracy, excellent surface quality of the formed structure, can achieve high-precision fineness, and can realize rapid forming. Therefore, the preparation of the core board layer 1 is optimized, and the preparation efficiency and finished product fineness are further improved.

[0072] In one embodiment, the inorganic material layer 13 is provided by using direct ink writing (DIW) technology or selective laser sintering (SLS) technology.

[0073] In one embodiment, as Figure 3As shown, a plurality of the interconnect layers 12 and the inorganic material layers 13 are provided to form the core board layer 1. Each of the interconnect layers 12 is coated with one of the inorganic material layers 13, and effective electrical connection between each of the interconnect layers 12 is achieved through the connection structure 122.

[0074] Next, as Figure 4 shown, perform step 3 to remove the carrier substrate 11.

[0075] Then, as Figure 5 shown, perform step 4 to provide patterned dielectric build-up layers 21 on both the first surface and the second surface of the core board layer 1. The patterned dielectric build-up layers 21 include vias 211 penetrating through the dielectric build-up layers 21 to expose a part of the interconnect layers 12.

[0076] In one embodiment, the vias 211 of the dielectric build-up layers 21 are provided by laser drilling.

[0077] In one embodiment, the material of the dielectric build-up layers 21 is Ajinomoto Build-up Film (ABF).

[0078] Finally, perform step 5 to provide a patterned conductive layer 22 on the dielectric build-up layers 21. The conductive layer 22 forms effective electrical connection with the interconnect layers 12 through the vias 211.

[0079] In one embodiment, the preparation method of the conductive layer 22 includes:

[0080] As Figure 6 shown, cover a seed layer 221 on the dielectric build-up layers 21. The seed layer 221 covers the dielectric build-up layers 21 and the exposed surfaces of the interconnect layers 12.

[0081] As Figure 7 shown, provide a patterned mask layer 23 on the seed layer 221.

[0082] As Figure 8 shown, fill an electroplated layer 222 in the gaps between the patterned mask layers 23.

[0083] As Figure 9 shown, remove the mask layer 23 and the seed layer 221 under the mask layer 23. The obtained patterned seed layer 221 and electroplated layer 222 form the conductive layer 22.

[0084] In one embodiment, the seed layer 221 is a copper layer, and the seed layer 221 is obtained by electroless copper plating.

[0085] In one embodiment, the mask layer 23 is a photosensitive material. By exposing and developing the electroplated layer 222 exposed under the mask layer 23, a patterned electroplated layer 222 is obtained.

[0086] In one embodiment, after removing the mask layer 23, the seed layer 221 under the mask layer 23 is removed by flash etching.

[0087] In one embodiment, multiple layers of the dielectric build-up layer 21 and the conductive layer 22 are repeatedly provided. Effective electrical connection is formed between adjacent conductive layers 22 through the through holes 211 of the dielectric build-up layer 21. Specifically, as Figure 10 shown, 4 layers of dielectric build-up layer 21 and conductive layer 22 are provided.

[0088] In one embodiment, a solder mask layer 31 is filled in the gaps between the exposed patterned conductive layers 22, and / or a surface treatment layer 32 is provided on the exposed patterned conductive layers 22. Specifically, as Figure 11 shown, the solder mask layer 31 and the surface treatment layer 32 are provided simultaneously.

[0089] In the present invention, by using the inorganic material layer 13 as the core board layer 1 of the packaging substrate to replace the core board material composed of polymer and glass fiber used in the traditional packaging substrate, and utilizing the low ductility and high flatness of the inorganic material layer 13, the shrinkage and warping deformation of the packaging substrate are effectively controlled. Thus, the warping problem can be reduced without increasing the thickness of the packaging substrate, which is beneficial to the miniaturization of the size of the packaging substrate. At the same time, the interconnection performance of the packaging substrate is improved, and the achievable circuit integration degree is increased; in addition, by utilizing the low dielectric constant and low dielectric loss of the inorganic material layer 13, the transmission performance of electrical signals in the packaging substrate is improved.

[0090] In one embodiment, the surface treatment layer 32 is obtained by dry film type ink.

[0091] In one embodiment, the method for providing the solder mask layer 31 and the surface treatment layer 32 includes: laminating the solder mask layer 31 on the exposed patterned conductive layer 22; patterning the solder mask layer 31 to expose part of the conductive layer 22 that needs to be electrically connected, and providing a surface treatment layer 32 on the exposed conductive layer 22 to protect the exposed conductive layer 22.

[0092] As Figure 12 shown, the present invention also provides a packaging substrate structure. The packaging substrate structure is obtained by using any one of the above preparation methods. The packaging substrate structure includes a core board layer 1, a dielectric build-up layer 21, and a conductive layer 22;

[0093] The core board layer 1 includes a patterned interconnect layer 12 and an inorganic material layer 13 that coats the interconnect layer 12 and the voids therebetween. The interconnect layer 12 includes a conductive structure 121 and a connection structure 122. The connection structure 122 is located on the conductive structure 121 for making an effective electrical connection with the structure above the connection structure 122;

[0094] The core board layer 1 includes opposite first and second surfaces, and both the first surface and the second surface are parallel to the carrier substrate 11. The dielectric enhancement layer 21 is located on the first surface and the second surface, and the dielectric enhancement layer 21 is provided with through holes 211 that penetrate the dielectric enhancement layer 21. The conductive layer 22 is located on the dielectric enhancement layer 21, and the conductive layer 22 makes an effective electrical connection with the interconnect layer 12 of the core board layer 1 through the through holes 211.

[0095] In summary, for the packaging substrate structure and its preparation method of the present invention, by using an inorganic material layer as the core board of the packaging substrate, the expansion, contraction and deformation of the packaging substrate can be reduced, the warping problem of the packaging substrate can be alleviated, the flatness of the surface of the packaging substrate can be improved, and a circuit with higher precision can be achieved; moreover, by utilizing the low dielectric constant and low dielectric loss factor of the inorganic material layer, the interconnect performance of the packaging substrate can be improved; in addition, by using 3D printing technology to set the core board of the packaging substrate, the flatness of the core board can be further improved.

[0096] Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0097] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate structure, characterized in that, The preparation method includes: providing a carrier substrate, and disposing a patterned interconnect layer on the carrier substrate, the interconnect layer including a conductive structure and a connection structure, the connection structure being located on a preset one of the conductive structures for effectively electrically connecting to a structure above the connection structure; disposing an inorganic material layer on the interconnect layer, the inorganic material layer filling voids between the patterned interconnect layers and covering the interconnect layer to be flush with the surface of the connection structure, exposing the surface of the connection structure; the interconnect layer and the inorganic material layer constitute a core board layer, the core board layer including opposite first and second surfaces, both the first surface and the second surface being parallel to the carrier substrate; removing the carrier substrate; disposing patterned dielectric enhancement layers on both the first surface and the second surface of the core board layer, the patterned dielectric enhancement layers including through holes penetrating the dielectric enhancement layers to expose a part of the interconnect layer; disposing a patterned conductive layer on the dielectric enhancement layer, the conductive layer forming an effective electrical connection with the interconnect layer through the through holes.

2. The manufacturing method of the encapsulation substrate structure according to claim 1, wherein The material of the inorganic material layer is a material including one or more arbitrary combinations of silicon element, nitrogen element, or aluminum element.

3. The manufacturing method of the encapsulation substrate structure according to claim 1, characterized in that, The material of the inorganic material layer is one or more arbitrary combinations of pure silicon, silicide, alumina, or silicon nitride.

4. The manufacturing method of the encapsulation substrate structure according to claim 1, characterized in that Multiple layers of the interconnect layer and the inorganic material layer are disposed to constitute the core board layer, each layer of the interconnect layer being coated with a layer of the inorganic material layer, and effective electrical connection between each layer of the interconnect layer being achieved through the connection structure.

5. The manufacturing method of the encapsulation substrate structure according to claim 1, characterized in that Multiple layers of the dielectric enhancement layer and the conductive layer are repeatedly disposed, and effective electrical connection between adjacent conductive layers is formed through the through holes of the dielectric enhancement layer.

6. The manufacturing method of the encapsulation substrate structure according to claim 1, wherein, Filling a solder mask layer in voids between the exposed patterned conductive layers, and / or disposing a surface treatment layer on the exposed patterned conductive layers.

7. The manufacturing method of the encapsulation substrate structure according to any one of claims 1-6, characterized in that, The interconnect layer and / or the inorganic material layer are disposed by 3D printing technology.

8. The manufacturing method of the encapsulation substrate structure according to any one of claims 1-6, characterized in that, The interconnect layer is disposed by direct metal laser sintering.

9. The manufacturing method of the encapsulation substrate structure according to any one of claims 1-6, characterized in that, The inorganic material layer is disposed by stereolithography 3D printing technology.

10. An encapsulation substrate structure, characterized in that, The package substrate structure is obtained by using the preparation method according to any one of claims 1-9, and the package substrate structure includes a core board layer, dielectric enhancement layers, and a conductive layer; The core board layer includes a patterned interconnect layer and an inorganic material layer covering the interconnect layer and voids therebetween, the interconnect layer including a conductive structure and a connection structure, the connection structure being located on the conductive structure for effectively electrically connecting to a structure above the connection structure; The core board layer includes opposite first and second surfaces, both the first surface and the second surface being parallel to the carrier substrate; the dielectric enhancement layers are located on the first surface and the second surface, the dielectric enhancement layers being provided with through holes penetrating the dielectric enhancement layers; the conductive layer is located on the dielectric enhancement layer, and the conductive layer forms an effective electrical connection with the interconnect layer of the core board layer through the through holes.

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