Chip packaging structure, electronic equipment and chip packaging method

Abstract

The invention discloses a chip packaging structure, electronic equipment and a chip packaging method, a heat dissipation cover is arranged in the chip packaging structure, and the heat dissipation efficiency of a chip can be improved. Different from a conventional chip packaging structure in which the heat dissipation cover is bonded and fixed on the first surface of the packaging substrate, according to the chip packaging structure, the side wall of the cover body of the heat dissipation cover surrounds the side wall of the packaging substrate, the side wall of the cover body is provided with the limiting structure, and the limiting structure can limit the periphery of the packaging substrate; according to the chip packaging structure, the packaging substrate is limited in the accommodating space, so that the packaging substrate is prevented from being greatly warped towards one side deviating from the top of the cover body due to deformation, the problem that the chip is separated from the top of the cover body due to the warpage problem is further prevented, and the reliability of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip packaging, and more specifically, to a chip packaging structure, an electronic device, and a chip packaging method. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable important tool for people today.

[0003] The core component for an electronic device to achieve various functions is a chip. In order to protect the chip and facilitate the connection between the chip and the circuit, it is necessary to package and protect the chip. In the existing chip packaging structure, the reliability is poor. Summary of the Invention

[0004] In view of this, the present application provides a chip packaging structure, an electronic device, and a chip packaging method, and the solutions are as follows:

[0005] A chip packaging structure includes:

[0006] A packaging substrate having opposite first and second surfaces; the packaging substrate has interconnection lines therein; the second surface has electrical contact terminals connected to the interconnection lines;

[0007] A chip fixed on the first surface, and the chip is electrically connected to the interconnection lines;

[0008] A heat dissipation cover, the heat dissipation cover includes a cover top and a cover side wall, and the cover top and the cover side wall form an accommodation space; the chip is located in the accommodation space, and the top of the chip is fixed to the inner side of the cover top;

[0009] Wherein, the cover side wall surrounds the side wall of the packaging substrate, and the cover side wall has a limiting structure, and the limiting structure is used to limit the periphery of the packaging substrate to limit the packaging substrate in the accommodation space.

[0010] Preferably, in the above chip packaging structure, the limiting structure also provides a movement space for the periphery of the packaging substrate.

[0011] Preferably, in the above chip packaging structure, one end of the cover side wall away from the cover top has a bent portion that bends towards the second surface for supporting the second surface; wherein, the limiting structure includes the bent portion.

[0012] Preferably, in the above chip packaging structure, the included angle between the bent portion and the cover side wall is less than or equal to 90°;

[0013] And / or, the second surface has a slot for accommodating the end of the bent portion away from the cover side wall.

[0014] Preferably, in the above chip packaging structure, the inner side of the side wall of the cover body has a groove, the groove is disposed opposite to the edge of the side wall of the packaging substrate, and the edge of the side wall of the packaging substrate extends into the groove and is limited by the groove; wherein, the limiting structure includes the groove.

[0015] Preferably, in the above chip packaging structure, the limiting structure has a supporting portion, and the supporting portion is located on the side of the second surface away from the first surface;

[0016] Wherein, the height of the supporting portion is less than the height of the electrical contact end.

[0017] Preferably, in the above chip packaging structure, the limiting structure has a supporting portion, and the supporting portion is located on the side of the second surface away from the first surface;

[0018] Wherein, there is a first spacing between adjacent electrical contact ends; there is a second distance between the supporting portion and the adjacent electrical contact end; the second distance is greater than or equal to the first distance.

[0019] Preferably, in the above chip packaging structure, the top of the chip is in thermal contact with the top of the cover body through a thermal conductive adhesive.

[0020] The present application also provides an electronic device, including the chip packaging structure of any one of the above.

[0021] The present application also provides a chip packaging method, including:

[0022] Providing a packaging substrate, the packaging substrate having opposite first and second surfaces; the packaging substrate having interconnecting lines therein; the second surface having electrical contact ends connected to the interconnecting lines; a chip is fixed on the first surface of the packaging substrate, and the chip is electrically connected to the interconnecting lines;

[0023] Providing a heat dissipation cover, the heat dissipation cover having a cover body top and a cover body side wall, the cover body top and the cover body side wall forming an accommodation space; and the cover body side wall having a limiting structure;

[0024] Mounting the heat dissipation cover on the packaging substrate, fixing the top of the chip to the inner side of the cover body top, such that the chip is located in the accommodation space; the cover body side wall surrounds the side wall of the packaging substrate to limit the periphery of the packaging substrate, so as to limit the packaging substrate in the accommodation space.

[0025] As can be seen from the above description, the technical solution of the present application provides a chip packaging structure, an electronic device, and a chip packaging method. A heat dissipation cover is provided in the chip packaging structure, which can improve the heat dissipation efficiency of the chip. Different from the conventional chip packaging structure in which the heat dissipation cover is adhesively fixed on the first surface of the packaging substrate, in the technical solution of the present application, the side wall of the cover body of the heat dissipation cover surrounds the side wall of the packaging substrate, and the side wall of the cover body has a limiting structure. The limiting structure can limit the periphery of the packaging substrate, limit the packaging substrate in the accommodation space, prevent the packaging substrate from warping significantly towards the side away from the top of the cover body due to deformation, and further prevent the problem of separation between the chip and the top of the cover body caused by this warping problem, thereby improving the reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0027] The structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limiting conditions that the present application can be implemented. Therefore, they do not have technical substance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present application.

[0028] Figure 1 FIG. is a schematic structural diagram of a chip packaging structure when the edge area of the packaging substrate warps towards the side away from the heat dissipation cover;

[0029] Figure 2 FIG. is a schematic structural diagram of a chip packaging structure when the edge area of the packaging substrate warps towards the side of the heat dissipation cover;

[0030] Figure 3 FIG. is a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp;

[0031] Figure 4 For Figure 3 FIG. is a schematic structural diagram of the chip packaging structure shown when the edge area of the packaging substrate warps towards the side away from the top of the cover body;

[0032] Figure 5 For Figure 3 FIG. is a schematic structural diagram of the chip packaging structure shown when the edge area of the packaging substrate warps towards the side of the top of the cover body;

[0033] Figure 6 A cross-sectional view of a heat dissipation cover provided by an embodiment of the present application;

[0034] Figure 7 A schematic structural diagram of another chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp;

[0035] Figure 8 A schematic structural diagram of yet another chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp;

[0036] Figure 9 A schematic structural diagram of yet another chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp;

[0037] Figure 10 A schematic flow diagram of a chip packaging method provided by an embodiment of the present application;

[0038] Figures 11 - 14 Product structure diagrams of different process steps during the production of the heat dissipation cover;

[0039] Figure 15 and Figure 16 A schematic diagram of the principle of installing the heat dissipation cover on the packaging substrate. Detailed implementation manners

[0040] Next, the embodiments in the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0041] Referring to Figure 1 and Figure 2 shown, Figure 1 is a schematic structural diagram of a chip packaging structure when the edge region of the packaging substrate warps away from the heat dissipation cover, Figure 2 is a schematic structural diagram of a chip packaging structure when the edge region of the packaging substrate warps towards the heat dissipation cover. The shown chip packaging structure is an FCBGA packaging structure, including:

[0042] A packaging substrate 11;

[0043] A chip 12 fixed on the packaging substrate 11;

[0044] A heat dissipation cover 13, the heat dissipation cover 13 has a receiving space 130, the heat dissipation cover 13 and the chip 12 are fixed on the same side surface of the packaging substrate 11, and the chip 12 is located in the receiving space 130.

[0045] In Figure 1 and Figure 2 As shown, the heat dissipation cover 13 is fixed on the packaging substrate 11 through the first adhesive layer 14. The top of the chip 12 and the top of the accommodation space 130 are adhesively fixed through the thermal conductive adhesive 15.

[0046] The heat dissipation cover 13 is generally made of a high-hardness material with a small coefficient of thermal expansion, such as a metal material or a ceramic material, and is not easily deformed during temperature changes. The packaging substrate 11 has a large coefficient of thermal expansion and is easily deformed during temperature changes. Since the first adhesive layer 14 needs to be cured at a high temperature, during the process of high and low temperature cycling, a large stress will be generated in the area where the packaging substrate 11 and the heat dissipation cover 13 are adhesively fixed, resulting in warping of the packaging substrate 11. This warping problem will further cause delamination between the top of the chip 12 and the top of the accommodation space 130, affecting the heat dissipation performance of the chip and further affecting the reliability of the chip packaging structure.

[0047] In Figure 1 and Figure 2 As shown, the heat dissipation cover 13 can be considered as not deforming. When the packaging substrate 11 warps, the heat dissipation cover 13 is fixed on the surface of the packaging substrate 11. Since the periphery of the packaging substrate 11 and the heat dissipation cover 13 are fixed, if as Figure 2 shown, the stress causes the middle part of the packaging substrate 11 to bulge and deform in the direction away from the heat dissipation cover 13, and the edge area of the packaging substrate 11 warps towards the heat dissipation cover 13, increasing the distance between the top of the packaging substrate 11 and the top of the accommodation space 130, resulting in delamination between the top of the chip 12 and the heat dissipation cover 13. If as Figure 1 shown, when the stress causes the edge area of the packaging substrate 11 to warp away from the heat dissipation cover 13, it will cause separation between the heat dissipation cover 13 and the packaging substrate 11 at the position corresponding to the first adhesive layer 14.

[0048] Generally at a lower temperature (such as 25 °C), as Figure 1 shown, the edge area of the packaging substrate 11 will warp away from the heat dissipation cover 13. At a higher temperature (such as 260 °C), as Figure 2 shown, the edge area of the packaging substrate 11 will warp towards the heat dissipation cover 13. Taking the chip 12 as a reference, it is equivalent to raising the heat dissipation cover 13, causing the heat dissipation cover 13 to separate from the top of the chip 12. During the switching process of the warping state of the packaging substrate 11 in different directions, it will cause delamination between the top of the chip 12 and the top of the accommodation space 130.

[0049] In view of the above problems, in the conventional method, by reducing the lateral width of the first adhesive layer 14, the stress at the position corresponding to the first adhesive layer 14 during the high-low cycle change of temperature is reduced, and by increasing the thickness of the thermal conductive adhesive 15, the adhesion between the top of the chip 12 and the top of the accommodation space 130 is increased. Although this method can prevent the packaging substrate 11 from warping to a certain extent, the reduction of the lateral width of the first adhesive layer 14 will result in insufficient adhesion, which is likely to cause the heat dissipation cover 13 to fall off from the packaging substrate 11. In addition, the relatively large thickness of the thermal conductive adhesive 15 will affect the heat dissipation speed of the chip 12.

[0050] In view of this, the technical solution of the embodiment of the present application provides a chip packaging structure, an electronic device, and a chip packaging method. Different from the conventional chip packaging structure in which the heat dissipation cover is adhesively fixed on the first surface of the packaging substrate, in the technical solution of the present application, the side wall of the cover body of the heat dissipation cover surrounds the side wall of the packaging substrate, and the side wall of the cover body has a limiting structure. The limiting structure can limit the periphery of the packaging substrate and limit the packaging substrate in the accommodation space, preventing the packaging substrate from warping significantly towards the side away from the top of the cover body due to deformation, and further preventing the separation problem between the chip and the top of the cover body caused by this warping problem, thereby improving the reliability of the chip packaging structure. If the packaging substrate warps towards the top of the cover body, the stress caused by this warping is to squeeze the chip towards the top of the cover body, and it will not cause delamination and peeling between the chip and the top of the cover body.

[0051] Furthermore, based on the limiting structure that limits the packaging substrate in the accommodation space, there is no need for an adhesive layer to fix the heat dissipation cover at the edge area of the first surface, avoiding the warping problem of the packaging substrate caused by the high-temperature curing of this adhesive layer. When the packaging substrate warps due to temperature changes during other process stages or during the use of the chip packaging structure, the limiting structure can limit the movement range of the packaging substrate, thereby preventing the delamination and peeling problem between the chip and the top of the cover body caused by this.

[0052] It should be noted that the chip packaging structure provided by the embodiment of the present application is not limited to the FCBGA packaging structure, and can also be applicable to other types of chip packaging structures that require a heat dissipation cover.

[0053] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Refer to Figures 3 - 5 as shown in Figure 3 a schematic structural diagram of a chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp, Figure 4 and Figure 3 a schematic structural diagram of the chip packaging structure shown when the edge area of the packaging substrate warps towards the side away from the top of the cover body.Figure 5 for Figure 3 The chip packaging structure shown is a schematic diagram of the structure when the edge area of ​​the packaging substrate is warped toward the top side of the cover body, wherein the deformation state of the packaging substrate 11 is shown for the convenience of illustrating the figure clearly. Figure 4 and Figure 5 The interconnection lines 16 inside the package substrate 11 and the connection structure between the package substrate 11 and the chip 12 are not shown.

[0055] like Figures 3 - 5 As shown, the chip packaging structure shown includes:

[0056] The packaging substrate 11 has a first surface 111 and a second surface 112 opposite to each other; the packaging substrate 11 has an interconnection line 16; the second surface 112 has an electrical contact terminal 17 connected to the interconnection line 16;

[0057] A chip 12 fixed to the first surface 111 , the chip 12 being electrically connected to the interconnection line 16 ;

[0058] The heat dissipation cover 13 includes a cover top 131 and a cover side wall 132, and the cover top 131 and the cover side wall 132 form a receiving space 130; the chip 12 is located in the receiving space 130, and the top of the chip 12 is fixed to the inner side of the cover top 131;

[0059] The cover side wall 132 surrounds the side wall of the packaging substrate 11 , and the cover side wall 132 has a limiting structure 133 , and the limiting structure 133 is used to limit the periphery of the packaging substrate 11 so as to limit the packaging substrate 11 in the accommodating space 130 .

[0060] In the chip packaging structure provided in the embodiment of the present application, the side wall 132 of the cover body has a limiting structure 133. The limiting structure 133 can limit the periphery of the packaging substrate 11, and limit the packaging substrate 11 in the accommodating space 130, so as to prevent the packaging substrate 11 from warping toward the side away from the top 131 of the cover body due to deformation, thereby preventing the chip 12 from separating from the top 131 of the cover body due to the warping problem, thereby improving the reliability of the chip packaging structure. If the packaging substrate 11 warps toward the side of the top 131 of the cover body, the stress caused by the warping will squeeze the chip 12 toward the top 131 of the cover body, and will not cause the chip 12 and the top 131 of the cover body to delaminate. When the packaging substrate 11 is not warped, such as Figure 3 As shown, the limiting structure 133 can also provide a supporting force for the second surface 112 , thereby playing a certain supporting role for the packaging substrate 11 .

[0061] Further, the encapsulation substrate 11 is restricted in the accommodation space 130 based on the position-limiting structure 133, eliminating the need for an adhesive layer (the above-mentioned first adhesive layer 14) to fix the heat dissipation cover 13 at the edge area of the first surface 111, thus avoiding the warping problem of the encapsulation substrate 11 caused by the high-temperature curing of this adhesive layer. When the encapsulation substrate 11 warps due to temperature changes during other process stages or during the use of the chip packaging structure, the position-limiting structure 133 can limit the movement range of the encapsulation substrate 11, thereby preventing the delamination problem between the chip 12 and the cover top 131 caused thereby.

[0062] To improve the heat dissipation effect of the chip 12, it is arranged that there is thermal contact between the top of the chip 12 and the cover top 131 through a thermal conductive adhesive 15.

[0063] The bottom of the chip 12 has chip pins 121, and the chip pins 121 are welded and fixed on the first surface 111. An insulating adhesive layer 19 is also filled between the bottom of the chip 12 and the first surface 111.

[0064] It should be noted that for the convenience of illustration, in the schematic diagrams of other chip packaging structures except Figure 3 the interconnection lines 16, chip pins 121 and insulating adhesive layer 19 in the encapsulation substrate 11 are not shown, and these structures can be referred to Figure 3 as shown.

[0065] In the embodiment of the present application, the position-limiting structure 133 also provides a movement space for the periphery of the encapsulation substrate 11. When the encapsulation substrate 11 does not warp and deform, the supporting structure is in non-fixed contact with a part of the second surface 112 below the encapsulation substrate 11 and can support the encapsulation substrate on the second surface 112. When stress causes the edge area of the encapsulation substrate 11 to warp and deform, this movement space can enable the edge area of the encapsulation substrate 11 to generate a bending deformation with a controlled amplitude, preventing the edge area of the encapsulation substrate 11 from generating a large downward warp and causing the separation of the chip 12 and the cover top 131. As Figure 4 or Figure 5 shown, when the edge area of the encapsulation substrate 11 warps, the edge area of the encapsulation substrate 11 can move within the defined movement space of the position-limiting structure 133. Therefore, whether the edge area of the encapsulation substrate 11 warps towards the side of the cover top 131 or towards the side away from the cover top 131, it will not cause an increase in the distance between the central area of the encapsulation substrate 11 and the cover top 131, thereby being able to prevent the separation problem between the top of the chip 12 and the cover top 131.

[0066] Relative to Figure 1 and Figure 2In the manner shown, in the embodiment of the present application, since there is no adhesive layer fixing in the edge regions of the encapsulation substrate 11 and the heat dissipation cover 13, the edge region of the encapsulation substrate 11 warps within the movement space provided by the limiting structure 133.

[0067] As Figure 4 shown, if the edge region of the encapsulation substrate 11 warps downward, restricted by the limiting effect of the limiting structure 133, on the basis of the unwarped state shown in Figure 3 shown, the deformation manner shown in Figure 4 will provide an upward acting force to the chip 12 and the encapsulation substrate 11 in the middle region below it (as shown by the arrow in Figure 4 ), which will make the chip 12 and the top of the cover 131 have a closer positional relationship.

[0068] As Figure 5 shown, if the edge region of the encapsulation substrate 11 warps upward, since there is no adhesive layer fixing between the edge region of the encapsulation substrate 11 and the heat dissipation cover 13, there is no force application point between the edge region of the encapsulation substrate 11 and the heat dissipation cover 13, and the deformation stress will not produce a downward pulling force on the chip 12 either, nor will it cause the chip 12 and the top of the cover 131 to separate.

[0069] Based on Figure 4 and Figure 5 shown, it can be seen that whether the edge region of the encapsulation substrate 11 warps upward or downward, it will not produce a downward pulling force on the chip 12, and will not affect the relative positional relationship at the fixed position of the top of the chip and the heat dissipation cover. Thus, when the edge region of the encapsulation substrate 11 has a warping problem, it can effectively prevent the separation problem between the chip 12 and the top of the cover 131.

[0070] In an implementation manner of the embodiment of the present application, as Figure 3 shown, one end of the cover sidewall 132 far from the top of the cover 131 has a bending portion (the region shown by the dashed ellipse in Figure 3 ), the bending portion bends towards the second surface 112, and the bending portion is used to support the second surface 112; wherein, the limiting structure 133 includes the bending portion. In this manner, a part of the cover sidewall 132 is located below the encapsulation substrate 11 and bends towards the second surface 112 to form a bending portion. When the encapsulation substrate 11 does not warp, the second surface 112 can be supported by the bending portion. Figure 3 The bending portion in

[0071] has an angle less than 90° with the cover sidewall 132 above it. At this time, the bending portion is inclined. In other manners, the bending portion can also be set to have an angle of 90° with the cover sidewall 132 above it. At this time, the bending portion is horizontally arranged.

[0071] Refer to Figure 6 shown, Figure 6A sectional view of a heat dissipation cover provided by an embodiment of the present application, in combination with Figure 3 and Figure 5 As shown, the side wall 132 of the cover body between the supporting structure and the top 131 of the cover body and the top 131 of the cover body meet the perpendicular condition (perpendicular or approximately perpendicular); in the space between the supporting structure and the top 131 of the cover body, the opposite side walls 132 of the cover body and the top 131 of the cover body meet the perpendicular condition, and the distance between the opposite side walls 132 of the cover body and the lateral dimension of the non-warped packaging substrate 11 meet the equal condition (equal or approximately equal). In this way, the bent portion below the packaging substrate 11 can support the second surface 112.

[0072] Optionally, as Figure 6 shown, the included angle β between the bent portion and the side wall 132 of the cover body is set to be not greater than 90° to better support the second surface 112 through the bent portion. Among them, the thickness of the bent portion is less than 0.15 mm to facilitate bending relative to the side wall 132 of the cover body. Considering that the mounting process of the heat dissipation cover 13 will cause a lateral error in the horizontal position of the heat dissipation cover 13, the sum of the lateral width of the bent portion and the maximum lateral error is set to be less than the distance between the edge electrical contact terminal 17 and the adjacent packaging substrate edge to prevent the bent portion from contacting and short-circuiting with the peripheral electrical contact terminal 17. Generally, the mounting process has a maximum lateral error of 0.2 mm. The lateral length of the bent portion can be set to 0.2 mm to 0.5 mm, and based on the distance between the edge electrical contact terminal 17 adapted to the process and the adjacent packaging substrate edge, to ensure that after offset, there is still enough insulation gap between the bent portion and the electrical contact terminal 17, and this insulation gap is greater than 0.5 mm to prevent the bent portion from contacting and short-circuiting with the electrical contact terminal 17. The lateral length of the bent portion can be 0.25 mm.

[0073] Referring to Figure 7 shown, Figure 7 A schematic structural diagram of another chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp. When the limiting structure 133 includes a bent portion, the second surface 112 can be further provided with a slot 18 for accommodating the end of the bent portion away from the side wall 132 of the cover body. Based on the engagement structure between the end of the bent portion away from the side wall 132 of the cover body and the slot 18, the position of the packaging substrate 11 in the horizontal direction can be restricted, the stress of the packaging substrate 11 in the horizontal direction can be overcome, the misalignment movement of the chip 12 in the horizontal direction caused by the stress can be avoided, and the fixing effect between the top of the chip 12 and the inner side of the top 131 of the cover body can be ensured.

[0074] Referring to Figure 8 shown, Figure 8 A schematic structural diagram of yet another chip packaging structure provided by an embodiment of the present application when the packaging substrate does not warp. The difference from the above embodiment is that the implementation manner of the limiting structure 133 is different. Figure 8In the shown manner, the inner side of the cover body side wall 132 has a groove 134, and the groove 134 is disposed opposite to the edge side wall of the encapsulation substrate 11. The edge of the encapsulation substrate 11 extends into the groove 134 and is limited by the groove 134. Among them, the limiting structure 133 includes the groove 134.

[0075] Relative to the above implementation manner in which the bending portion is used as the limiting structure 133, in Figure 8 the shown manner, the groove 134 on the inner side of the cover body side wall 132 is used as the limiting structure 133, which can not only limit the downward warping amplitude of the encapsulation substrate 11, but also limit the upward warping amplitude of the encapsulation substrate 11.

[0076] In the embodiment of the present application, the limiting structure 133 has a supporting portion, and the supporting portion is located on the side of the second surface 112 away from the first surface. When the limiting structure 133 includes a bending portion, the bending portion serves as the supporting portion. When the limiting structure 133 includes a groove 134, the part of the cover body side wall 132 below the encapsulation substrate 11 where the groove 134 is located serves as the supporting portion.

[0077] As described above, the second surface 112 is provided with electrical contact terminals 17. The electrical contact terminals 17 can be solder balls. The electrical contact terminals 17 enable the chip packaging structure to be connected to an external circuit. As Figure 3 、 Figures 7 - 9 shown, the height H1 of the supporting portion is set to be less than the height H0 of the electrical contact terminals 17 to prevent the excessive height H1 of the supporting portion from affecting the soldering effect between the electrical contact terminals 17 and the external circuit.

[0078] As described above, the supporting portion of the limiting structure is located on the side of the second surface 112 away from the first surface; there are a plurality of electrical contact terminals 17 on the second surface 112. As Figures 7 - 9 shown, there is a first pitch L1 between adjacent electrical contact terminals 17; there is a second distance L2 between the supporting portion and the adjacent electrical contact terminal 17; the second distance L2 is greater than or equal to the first distance L1. Horizontally, a first pitch L1 is required between adjacent electrical contact terminals 17 to meet the electrical pitch, facilitate the realization of circuit interconnection, and prevent short circuits. Based on this, the second distance L2 between the supporting portion and the adjacent electrical contact terminal 17 on the periphery needs to be equal to or greater than the first pitch L1 so that the horizontal distance between the supporting portion and the adjacent electrical contact terminal 17 meets the electrical pitch.

[0079] Figure 1 and Figure 2 shown, the chip packaging method of the chip packaging structure includes:

[0080] After fixing the chip 11 on the first surface 111 of the encapsulation substrate 11, an insulating glue layer 19 is filled between the bottom of the chip 11 and the encapsulation substrate 11;

[0081] Further, after filling the insulating glue layer 19, a first glue layer 14 is provided in the peripheral edge area of the first surface 11;

[0082] Further, after forming the first glue layer 14 on the first surface 111, after applying a heat-conducting glue 15 on the top of the chip 11, the heat dissipation cover 13 is fixed on the top of the chip 12 based on the heat-conducting glue 15.

[0083] Finally, after preparing the product identification on the outer side of the top of the heat dissipation cover 13, the ball implantation of the substrate 11 is encapsulated as the electrical contact end 17.

[0084] For the chip packaging structure provided by the embodiment of the present application, since the peripheral edge of the packaging substrate 11 can be limited by the limiting structure 133, the corresponding chip packaging method can save the process step of setting the first glue layer 14 in the peripheral edge area of the first surface 111. In a conventional chip packaging structure, a first glue layer 14 with a preset width needs to be provided on the first surface 111. The larger the transverse dimension A of the chip packaging structure is, in order to ensure the fixing effect of the heat dissipation cover 13, the larger the transverse width B of the first glue layer 14 is. For example, when A≤21mm, B = 2.5mm; when 21mm<A≤33mm, B = 3mm; when 33mm<A≤39mm, B = 3.5mm; when 39mm<A≤42.5mm, B = 4mm; when 42.5mm<A≤45mm, B = 4.5mm; when 45mm<A≤50mm, B = 5mm; when 50mm<A≤52.5mm, B = 5.5mm; when 52.5mm<A≤55mm, B = 6mm. It can be seen that the transverse width B of the first glue layer 14 will greatly affect the layout space of the first surface 111.

[0085] In the embodiment of the present application, based on the limiting structure 133 to limit the peripheral edge of the packaging substrate 11, there is no need to reserve a glue layer bonding area for fixing the heat dissipation cover 13 at the edge position of the first surface 111. When using chips of the same size, when the electrical contact end 17 meets the requirements, the transverse dimension of the packaging substrate 11 can be reduced, thereby reducing the transverse dimension of the chip packaging structure.

[0086] Reference Figure 9 shown Figure 9 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the present application when the packaging substrate does not warp. In this way, an auxiliary electronic component 20 is also fixed on the first surface 111 between the chip 12 and the cover body side wall 132. The auxiliary electronic component 20 includes at least one of a capacitor, an inductor, and a resistor. In this way, when the transverse dimension of the packaging substrate 11 is not reduced, since the space of the first glue layer 14 is saved, the first surface 111 can have sufficient space for laying out the auxiliary electronic component 20.

[0087] In the embodiment of the present application, the periphery of the packaging substrate 11 is limited by the limiting structure 133, and there is no need to reserve an adhesive layer bonding area for fixing the heat dissipation cover 13 at the edge position of the first surface 111, which can make there be a larger space between the side wall of the chip 12 and the side wall of the cover body 132 for arranging the above-mentioned auxiliary electronic components.

[0088] Based on the above embodiment, another embodiment of the present application further provides an electronic device, which adopts the chip packaging structure in any one of the above embodiments. Among them, the electronic device can be any one of a laptop computer, an all-in-one computer, a laptop computer, a mobile phone, and a wearable device.

[0089] The electronic device provided by the embodiment of the present application adopts the chip packaging structure in the above embodiment. The chip packaging structure has good heat dissipation performance, and can prevent the separation problem between the chip 12 and the top of the cover body 131 caused by the warping problem when the packaging substrate 11 has a warping problem. The chip packaging structure has good reliability, thereby ensuring the performance of the electronic device.

[0090] Based on the chip packaging structure provided by the above embodiment, another embodiment of the present application further provides a chip packaging method, and the chip packaging method is as Figure 10 shown.

[0091] Referring to Figure 10 shown, Figure 10 which is a schematic flowchart of a chip packaging method provided by an embodiment of the present application. Combining with the chip packaging structure drawings provided by the above embodiment, the chip packaging method includes:

[0092] Step S11: Provide a packaging substrate 11, the packaging substrate 11 has opposite first surface 111 and second surface 112; there are interconnection lines 16 in the packaging substrate 11; the second surface 112 has electrical contact terminals 17 connected to the interconnection lines 16; a chip 12 is fixed on the first surface 111 of the packaging substrate 11, and the chip 12 is electrically connected to the interconnection lines 16;

[0093] Step S12: Provide a heat dissipation cover 13, the heat dissipation cover 13 has a cover body top 131 and a cover body side wall 132, and the cover body top 131 and the cover body side wall 132 form an accommodation space 130; and the cover body side wall 132 has a limiting structure 133;

[0094] Step S13: Install the heat dissipation cover 13 on the packaging substrate 11, fix the top of the chip 12 to the inside of the cover body top 131, so that the chip 12 is located in the accommodation space 130; the cover body side wall 132 surrounds the side wall of the packaging substrate 11 to limit the periphery of the packaging substrate 11, so as to limit the packaging substrate 11 in the accommodation space 130.

[0095] Based on this chip packaging method, the chip packaging structure provided in the above embodiments can be prepared. The chip packaging structure has good heat dissipation performance and can prevent the separation problem between the chip 12 and the top 131 of the cover body due to the warping problem of the packaging substrate 11. The chip packaging structure has good reliability.

[0096] In step S12, the preparation method of the heat dissipation cover 13 can be as Figures 11 - 14 shown Figures 11 - 14 which is the product structure diagram of different process steps in the production process of the heat dissipation cover. This method includes:

[0097] First, as Figure 11 and Figure 12 shown Figure 11 is the top view of the metal sheet, Figure 12 and is the side view of the metal sheet;

[0098] Then, as Figure 13 shown, bend the edge area of the metal sheet to form a bent part; in other embodiments, the graphic structures of the side wall 131 and the top of the cover body can also be bent first, and then the bent part is formed. The embodiments of the present application do not make any limitations in this regard;

[0099] Then, as Figure 14 shown, bend the metal sheet of a preset length to form the top 131 of the heat dissipation cover body and the side wall 132 of the cover body. Figure 14 The state shown is the state when the heat dissipation cover 13 is not fixedly attached to the chip 12. At this time, the included angle between the two opposite side walls 132 of the cover body is greater than 90°.

[0100] In step S13, the method of installing the heat dissipation cover 13 on the packaging substrate 11 can be as Figure 15 and Figure 16 shown, Figure 15 and Figure 16 are the schematic diagrams of the principle of installing the heat dissipation cover on the packaging substrate. This method includes:

[0101] First, as Figure 15 shown, the heat dissipation cover 13 in the Figure 14 shown posture is grabbed by the robotic arm 41, and the top 131 of the cover body is fixedly attached to the top of the chip 12 through the thermal conductive adhesive 15.

[0102] Then, as Figure 16 shown, the distance between the opposite side walls 132 of the cover body is adjusted by the robotic arm 41 to make this distance smaller. The robotic arm 41 has a mechanical claw 411 for pressurization, which can make the opposite side walls 132 of the cover body change from the Figure 15 shown posture to the Figure 16The posture shown. Among them, after the posture adjustment of the side walls 132 of the opposite covers is completed, the robotic arm rotates 90° to adjust the distance between the other two opposite cover side walls 132. Among them, when the posture adjustment of the four cover side walls is completed in pairs, the cover top 131 and the cover side wall 132 form an accommodation space 130; the chip 12 is located in the accommodation space 130, and the top of the chip 12 is fixed to the inner side of the cover top 131; the limiting structure 133 is used to limit the periphery of the packaging substrate 11 to limit the packaging substrate 11 in the accommodation space 130.

[0103] In this specification, the various embodiments are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the various embodiments can be referred to each other.

[0104] It should be noted that in the description of this application, it should be understood that the descriptions of the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structures. Additionally, for the sake of understanding and easy description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. At the same time, it can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there may be intermediate elements. Additionally, "on..." means positioning the element on or below another element, but essentially does not mean positioning on the upper side of another element according to the direction of gravity.

[0105] The orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intermediate components present.

[0106] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0107] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip packaging structure, comprising: A packaging substrate having opposite first and second surfaces; Interconnecting lines are provided within the packaging substrate; The second surface has electrical contact terminals connected to the interconnecting lines; A chip fixed to the first surface, the chip being electrically connected to the interconnecting lines; A heat dissipation cover, the heat dissipation cover including a cover top and a cover sidewall, the cover top and the cover sidewall forming a receiving space; The chip is located within the receiving space, and the top of the chip is fixed to the inner side of the cover top; Wherein, the cover sidewall surrounds the sidewall of the packaging substrate, and the cover sidewall has a limiting structure, and the limiting structure is used to limit the periphery of the packaging substrate to limit the packaging substrate within the receiving space.

2. The chip packaging structure according to claim 1, wherein the limiting structure further provides a movement space for the periphery of the packaging substrate.

3. The chip packaging structure according to claim 1, wherein one end of the side wall of the cover body away from the top of the cover body has a bent portion, and the bent portion is bent toward the second surface for supporting the second surface; wherein, The limiting structure includes the bent portion.

4. The chip packaging structure according to claim 3, wherein the angle between the bent portion and the cover sidewall is less than or equal to 90°; And / or, the second surface has a card slot for receiving the end of the bent portion away from the cover sidewall.

5. The chip packaging structure according to claim 1, wherein the inner side of the sidewall of the cover body has a groove, the groove is disposed opposite to the sidewall edge of the packaging substrate, and the sidewall edge of the packaging substrate extends into the groove and is limited by the groove; wherein, The limiting structure includes the groove.

6. The chip packaging structure according to claim 1, wherein the limiting structure has a supporting portion, and the supporting portion is located on the side of the second surface facing away from the first surface; Among them, The height of the supporting portion is less than the height of the electrical contact terminal.

7. The chip packaging structure according to claim 1, wherein the limiting structure has a supporting portion, and the supporting portion is located on the side of the second surface facing away from the first surface; Among them, There is a first distance between adjacent electrical contact terminals; there is a second distance between the supporting portion and the adjacent electrical contact terminals; the second distance is greater than or equal to the first distance.

8. The chip packaging structure according to claim 1, wherein the top of the chip is in thermal contact with the inner side of the cover top through a thermal conductive adhesive.

9. An electronic device, comprising the chip packaging structure according to any one of claims 1-8.

10. A chip packaging method, comprising: Providing a packaging substrate having opposite first and second surfaces; Interconnecting lines are provided within the packaging substrate; The second surface has electrical contact terminals connected to the interconnecting lines; A chip is fixed on the first surface of the packaging substrate, and the chip is electrically connected to the interconnecting lines; Providing a heat dissipation cover having a cover top and a cover sidewall, the cover top and the cover sidewall forming a receiving space; And the cover sidewall has a limiting structure; Mounting the heat dissipation cover on the packaging substrate, fixing the top of the chip to the inner side of the cover top, so that the chip is located within the receiving space; the cover sidewall surrounds the sidewall of the packaging substrate to limit the periphery of the packaging substrate to limit the packaging substrate within the receiving space.

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