Method of manufacturing device isolation layer and method of manufacturing semiconductor device using the same

Abstract

A method of manufacturing a device isolation layer and a method of manufacturing a semiconductor device using the same are provided. The method for manufacturing the device isolation layer comprises the following steps: forming a groove in a substrate; conformally forming a first insulating layer on the top surface of the substrate and the inner wall of the trench by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process such that a portion of the second insulating layer is within the trench; performing a dry etching process on the second insulating layer and the first insulating layer to expose a top surface of the substrate; and forming a device isolation layer inside the trench, the device isolation layer including a first insulation pattern formed by etching the first insulation layer and a second insulation pattern formed by etching the second insulation layer, in which the device isolation layer has a curved top surface.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method of manufacturing a device isolation layer and a method of manufacturing a semiconductor device by using the device isolation layer. More specifically, the present disclosure relates to a method of manufacturing a device isolation layer having a curved top surface and a method of manufacturing a semiconductor device by using the device isolation layer. Background Art

[0002] According to the rapid development of the electronics industry and the needs of users, electronic devices have become more compact and lightweight. Therefore, there is a need to use semiconductor devices with high integration in electronic devices, and the design rules for the configuration of semiconductor devices are decreasing. Therefore, the difficulty of manufacturing processes for forming conductive patterns and insulating patterns constituting semiconductor devices is gradually increasing. Summary of the Invention

[0003] Embodiments of the present disclosure provide a method of manufacturing a device isolation layer having a curved top surface and a method of manufacturing a semiconductor device by using the device isolation layer.

[0004] According to an embodiment of the present disclosure, there is provided a method including: forming a trench in a substrate; conformally forming a first insulating layer on a top surface of the substrate and inner walls of the trench by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process such that a part of the second insulating layer is within the trench; performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate; and forming a device isolation layer inside the trench, the device isolation layer including a first insulating pattern formed by etching the first insulating layer and a second insulating pattern formed by etching the second insulating layer, wherein the device isolation layer has a curved top surface.

[0005] According to an embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method including: forming a plurality of trenches in each of a cell array region and a peripheral circuit region of a substrate; conformally forming a first insulating layer on inner walls of the plurality of trenches and on a top surface of the substrate by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process such that a part of the second insulating layer is within the plurality of trenches; forming a plurality of device isolation layers by performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate; sequentially forming a high-k dielectric material layer and a conductive material layer on top surfaces of the plurality of device isolation layers and on the top surface of the substrate; and patterning the high-k dielectric material layer and the conductive material layer, wherein each of the plurality of device isolation layers formed in the peripheral circuit region has a curved top surface.

[0006] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, the method including: forming a first device isolation layer and a second device isolation layer in a substrate, the substrate including a cell array region and a peripheral circuit region, the cell array region including a first active region defined by the first device isolation layer, and the peripheral circuit region including a second active region defined by the second device isolation layer; forming a word line intersecting the first active region and a direct contact connected to the first active region in the cell array region; forming a bit line structure connected to the direct contact and perpendicular to the word line in the cell array region; and forming a peripheral circuit gate structure on the second active region in the peripheral circuit region, wherein forming the first device isolation layer and the second device isolation layer includes: forming trenches in each of the cell array region and the peripheral circuit region; conformally forming a first insulating layer on inner walls of the trenches and a top surface of the substrate by a thermal oxidation process; forming a second insulating layer on the first insulating layer to fill the trenches by an atomic layer deposition process; and performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate, wherein the first device isolation layer has a flat top surface in the cell array region, and wherein the second device isolation layer has a curved top surface in the peripheral circuit region.

[0007] Aspects of embodiments of the present disclosure are not limited to those described above, and other aspects not mentioned herein will be clearly understood by those of ordinary skill in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a flowchart of a method of manufacturing a device isolation layer according to an embodiment;

[0010] Figures 2 to 7 is a cross-sectional view showing a process sequence of a method of manufacturing a device isolation layer according to an embodiment;

[0011] Figure 8 is a graph showing a change in an etching amount according to a flow rate ratio of process gases in a dry etching process used in a method of manufacturing a device isolation layer according to an embodiment;

[0012] Figure 9 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment;

[0013] Figure 10 is a plan layout view showing main elements of a memory cell array region of a semiconductor device according to an embodiment;

[0014] Figures 11 to 22 is a cross-sectional view showing a process sequence of a method of manufacturing a semiconductor device according to an embodiment; and

[0015] Figure 23 is a configuration diagram showing a system including a semiconductor device according to an embodiment. Detailed Embodiment

[0016] Hereinafter, non-limiting exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] It should be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present.

[0018] Figure 1 is a flowchart of a method for manufacturing a device isolation layer according to an embodiment.

[0019] Reference Figure 1 , the method S10 for manufacturing a device isolation layer may include a process sequence of a first operation S110, a second operation S120, a third operation S130, a fourth operation S140, and a fifth operation S150.

[0020] When a certain embodiment is implemented in a different manner, the specific process sequence may be performed differently from the sequence described herein. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0021] According to an embodiment of the present disclosure, the method S10 for manufacturing a device isolation layer may include a first operation S110 of preparing a substrate, a second operation S120 of forming a trench in the substrate, a third operation S130 of conformally forming a first insulating layer on the top surface of the substrate and the inner wall of the trench by a thermal oxidation process, a fourth operation S140 of forming a second insulating layer on the first insulating layer by an atomic layer deposition (ALD) process to fill the trench, and a fifth operation S150 of performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate.

[0022] Hereinafter, aspects of the first operation S110, the second operation S120, the third operation S130, the fourth operation S140, and the fifth operation S150 will be described in detail with reference to Figures 2 to 7 .

[0023] Figures 2 to 7 is a cross-sectional view showing a process sequence of a method for manufacturing a device isolation layer according to an embodiment.

[0024] Reference Figure 2, an etching process for forming a trench 101T in the substrate 101 can be performed.

[0025] The trench 101T can be formed by forming a mask pattern on the substrate 101 and etching the substrate 101 by using the mask pattern as an etching mask. The etching can be dry etching (e.g., plasma etching).

[0026] Due to the characteristics of the dry etching process, the width of the trench 101T can become narrower toward the bottom of the trench 101T. Therefore, the sidewalls of the trench 101T may not be vertical, but may have a slightly inclined tapered shape. Although one trench 101T is shown, embodiments of the present disclosure are not limited thereto. That is, a plurality of trenches 101T can be formed in the substrate 101.

[0027] Subsequently, the mask pattern can be completely removed from the substrate 101 through an ashing and stripping process.

[0028] Reference Figure 3 , a first insulating layer 111L can be conformally formed on the top surface of the substrate 101 and the inner walls of the trench 101T.

[0029] The first insulating layer 111L can be a silicon oxide layer formed through a thermal oxidation process. The first insulating layer 111L formed through the thermal oxidation process can have excellent interface characteristics with respect to the substrate 101, and the quality of the silicon oxide layer can be excellent.

[0030] Reference Figure 4 , a second insulating layer 113L can be formed on the first insulating layer 111L through an ALD process to fill the trench 101T.

[0031] The second insulating layer 113L can be a silicon oxide layer formed through an ALD process. The second insulating layer 113L formed through the ALD process can be formed thick and can have relatively excellent step coverage, and the quality of the silicon oxide layer can be excellent.

[0032] The first insulating layer 111L and the second insulating layer 113L can be manufactured through different processes, but can be formed of the same material. That is, both the first insulating layer 111L and the second insulating layer 113L can be silicon oxide layers.

[0033] Reference Figure 5 , the second insulating layer 113L (see Figure 4 ) and the first insulating layer 111L (see Figure 4 ) can be dry-etched to expose the top surface of the substrate 101.

[0034] The dry etching can be performed on the second insulating layer 113L (see Figure 4) has a second etching rate greater than the first etching rate of the first insulating layer 111L (see Figure 4 ) and is performed under process conditions. That is, the first insulating layer 111L (see Figure 4 ) and the second insulating layer 113L (see Figure 4 ) can perform dry etching under a single process condition with a selectivity ratio of the first etching rate of the first insulating layer 111L to the second etching rate of the second insulating layer 113L.

[0035] In the dry etching process, the first etching rate of the first insulating layer 111L (see Figure 4 ) and the second etching rate of the second insulating layer 113L (see Figure 4 ) can be controlled by the flow rate of the process gas used in the process conditions. The process gas may include hydrogen fluoride (HF) gas and ammonia (NH3) gas. As described below, dry etching can be performed under the condition that the flow rate of the HF gas is greater than the flow rate of the NH3 gas.

[0036] Through dry etching, the first insulating layer 111L (see Figure 4 ) can be formed into a first insulating pattern 111, and the second insulating layer 113L (see Figure 4 ) can be formed into a second insulating pattern 113.

[0037] Therefore, the device isolation layer 110 can be formed in the substrate 101. The device isolation layer 110 may include the first insulating pattern 111 on the outside and the second insulating pattern 113 on the inside. The device isolation layer 110 may be a shallow trench isolation, but the embodiments of the present disclosure are not limited thereto.

[0038] In addition, although one device isolation layer 110 is shown, the embodiments of the present disclosure are not limited thereto. That is, multiple device isolation layers 110 can be formed in the substrate 101.

[0039] In some embodiments, due to dry etching, in the device isolation layer 110, the vertical level of the top surface of the first insulating pattern 111 may be higher than the vertical level of the top surface of the second insulating pattern 113.

[0040] In some embodiments, due to dry etching, the device isolation layer 110 may have a curved (e.g., round) top surface 110R. The round top surface 110R of the device isolation layer 110 can be continuously formed with an approximately constant curvature by the outermost edge of the first insulating pattern 111, the interface between the first insulating pattern 111 and the second insulating pattern 113, and the second insulating pattern 113.

[0041] Reference Figure 6, a high-k dielectric material layer 120 and a conductive material layer 130 can be sequentially formed on the top surface of the device isolation layer 110 and the top surface of the substrate 101.

[0042] First, a high-k dielectric material layer 120 can be formed to conformally cover the top surface of the device isolation layer 110 and the top surface of the substrate 101. The high-k dielectric material layer 120 can be formed flat on the top surface of the substrate 101 and can be formed circular on the top surface of the device isolation layer 110.

[0043] The high-k dielectric material layer 120 can have a dielectric constant higher than that of a silicon oxide layer. For example, the high-k dielectric material layer 120 can have a dielectric constant of about 10 to about 25.

[0044] In some embodiments, the high-k dielectric material layer 120 can include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0045] Subsequently, a conductive material layer 130 can be formed to cover the top surface of the high-k dielectric material layer 120. The conductive material layer 130 can be formed flat on the top surface of the substrate 101 and can be formed with a convex portion on the top surface of the device isolation layer 110. The conductive material layer 130 can be formed thicker than the high-k dielectric material layer 120.

[0046] For example, the conductive material layer 130 can include doped polysilicon, TiN, TiSiN, W, tungsten silicide, or any combination thereof, but the embodiments of the present disclosure are not limited thereto.

[0047] Reference Figure 7 , the high-k dielectric material layer 120 (see Figure 6 ) and the conductive material layer 130 (see Figure 6 ) can be removed from the top surface of the device isolation layer 110 and the top surface of the substrate 101 adjacent to the device isolation layer 110.

[0048] In order to pattern the high-k dielectric material layer 120 (see Figure 6 ) and the conductive material layer 130 (see Figure 6) to form a gate structure, the high-k dielectric material layer 120 (see Figure 6 ) and the conductive material layer 130 (see Figure 6 ) can be etched from the top surface of the device isolation layer 110 and the top surface of the substrate 101 adjacent to the device isolation layer 110.

[0049] In the etching process, since the device isolation layer 110 according to an embodiment of the present disclosure has a circular top surface 110R, the vertical thickness of the conductive material layer 130 (see Figure 6 ) located on the edge top surface 110E of the device isolation layer 110 can be relatively small. Therefore, the embodiments of the present disclosure can have the effect that the unwanted residues of the conductive material layer 130 (see Figure 6 ) are not retained on the top surface of the device isolation layer 110 in subsequent processes. In other words, no additional process may be performed to remove the unwanted residues of the conductive material layer 130 (see Figure 6 ) from the edge top surface 110E of the device isolation layer 110.

[0050] Finally, in the method of manufacturing the device isolation layer 110, according to an embodiment of the present disclosure, a device isolation layer 110 including a first insulating pattern 111 and a second insulating pattern 113 formed by different manufacturing methods (e.g., thermal oxidation process and ALD process) and having a circular top surface 110R can be formed on the substrate 101. Therefore, it can be expected that the unwanted residues of the conductive material layer 130 (see Figure 6 ) are not retained on the top surface of the device isolation layer 110 in subsequent processes.

[0051] Figure 8 is a graph showing the change in the etching amount according to the flow rate ratio of the process gas in the dry etching process used in the method of manufacturing a device isolation layer according to an embodiment.

[0052] In Figure 8 's graph, the X-axis represents the ratio of HF gas to NH3 gas, and the Y-axis represents the etching amount E / A of each insulating layer. Since the Y-axis refers to the etching amount at the same time, the etching amount can be interpreted as a concept corresponding to the etching rate. In addition, the etching amount E / A is an arbitrary unit representing a relative value rather than an absolute value.

[0053] The ratio of the first etching rate of the first insulating layer Th_Ox to the second etching rate of the second insulating layer ALD_Ox can be controlled during the dry etching process. Specifically, the etching rate can be controlled by the relative flow rate of the process gas used in the process conditions of the dry etching process, and the process gas can include HF gas and NH3 gas.

[0054] For example, when the ratio of the flow rate of HF gas to the flow rate of NH3 gas on the X-axis is about 6, the second etching rate of the second insulating layer ALD_Ox can be lower than the first etching rate of the first insulating layer Th_Ox.

[0055] Conversely, when the ratio of the flow rate of HF gas to the flow rate of NH3 gas on the X-axis is about 7, the second etching rate of the second insulating layer ALD_Ox can be higher than the first etching rate of the first insulating layer Th_Ox.

[0056] That is to say, there can be a partial SR where, according to the ratio of the flow rate of HF gas to the flow rate of NH3 gas, the selectivity ratio between the first insulating layer Th_Ox and the second insulating layer ALD_Ox is reversed. The inventors found that when dry etching is performed on the material constituting the device isolation layer 110 (see Figure 4 ) in the partial SR where the selectivity ratio is reversed, results similar to those obtained when wet etching is performed can be obtained.

[0057] In this way, a device isolation layer 110 (see Figure 4 ) having a circular top surface 110R (see Figure 4 ) can be formed by using a dry etching process in which the first insulating layer Th_Ox and the second insulating layer ALD_Ox formed by different manufacturing methods (e.g., thermal oxidation process and ALD process) are etched at different etching rates.

[0058] Figure 9 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment.

[0059] Referring to Figure 9 , the semiconductor device 200 can have a cell array region CA, a peripheral circuit region PA surrounding the cell array region CA, and an interface region IA disposed between the cell array region CA and the peripheral circuit region PA.

[0060] The substrate 201 can be a Si-containing wafer. In some embodiments, the substrate 201 can be a wafer including a semiconductor element (such as germanium (Ge)) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). In some embodiments, the substrate 201 can have a silicon-on-insulator (SOI) structure. Further, the substrate 201 can include a conductive region, such as a doped well or a doped structure.

[0061] In some embodiments, the cell array region CA may be a memory cell array region of the semiconductor device 200. The cell array region CA may constitute a memory cell array region of a volatile memory device or a memory cell array region of a non-volatile memory device. The memory cell array region may be a memory cell array region of a dynamic random access memory (DRAM), a magnetic RAM (MRAM), a static RAM (SRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM). The cell array region CA may include a unit memory cell having a transistor and a capacitor or a unit memory cell having a switching element and a variable resistor.

[0062] The peripheral circuit for driving the memory cells located in the cell array region CA may be arranged in the peripheral circuit region PA.

[0063] A plurality of conductive lines for electrical connection between the cell array region CA and the peripheral circuit region PA and an insulating structure for insulation between the cell array region CA and the peripheral circuit region PA may be arranged in the interface region IA.

[0064] Figure 10 is a plan layout view showing main elements of a memory cell array region of a semiconductor device according to an embodiment.

[0065] Reference Figure 10 , the semiconductor device 200 may include a plurality of first active regions 203A (see Figure 11 ), which are arranged to have a major axis in a diagonal direction with respect to a first direction (X direction) and a second direction (Y direction).

[0066] In the present specification, an active region formed in the cell array region CA of the semiconductor device 200 may be referred to as one of the first active regions 203A (see Figure 11 ), and an active region formed in the peripheral circuit region PA (see Figure 11 ) other than the cell array region CA may be referred to as one of the second active regions 203B (see Figure 11 ).

[0067] A plurality of word lines WL may extend parallel to each other in a first direction (X direction) across the first active regions 203A (see Figure 11 ). A plurality of bit lines BL may extend parallel to each other on the word lines WL in a second direction (Y direction) crossing the first direction (X direction).

[0068] The bit lines BL may be respectively connected to the first active regions 203A through direct contacts DC (see Figure 11)。In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines in the bit line BL. Each buried contact BC may extend to the upper portion of one of the two adjacent bit lines in the bit line BL. In some embodiments, the buried contacts BC may be arranged in rows in a first direction (X direction) and a second direction (Y direction).

[0069] A plurality of landing pads LP may be respectively formed on the buried contacts BC. The buried contacts BC and the landing pads LP may connect the lower electrode of the capacitor formed on the upper portion of the bit line BL to the first active region 203A (see Figure 11 ). The landing pads LP may be respectively arranged to partially overlap with the buried contacts BC.

[0070] Figures 11 to 22 is a cross-sectional view showing a process sequence of a method of manufacturing a semiconductor device according to an embodiment.

[0071] Referring to Figure 11 , a first insulating layer 211L may be conformally formed on the inner walls of the first trenches 201AT in the cell array region CA, the inner walls of the second trenches 201BT in the peripheral circuit region PA, and the top surface of the substrate 201.

[0072] The first insulating layer 211L may be a silicon oxide layer formed by a thermal oxidation process. The first insulating layer 211L formed by the thermal oxidation process may have excellent interface characteristics with respect to the substrate 201, and the quality of the silicon oxide layer may be excellent.

[0073] Subsequently, a second insulating layer 213L may be formed on the first insulating layer 211L to fill the first trenches 201AT and the second trenches 201BT. The second insulating layer 213L is a silicon oxide layer formed by an ALD process.

[0074] The first insulating layer 211L and the second insulating layer 213L may be manufactured by different processes, but may be formed of the same material. That is, both the first insulating layer 211L and the second insulating layer 213L may be silicon oxide layers.

[0075] Referring to Figure 12 , the second insulating layer 213L (see Figure 11 ) and the first insulating layer 211L (see Figure 11 ) may be dry-etched to expose the top surface of the substrate 201.

[0076] The dry etching may be performed when the second etching rate of the second insulating layer 213L (see Figure 11 ) is greater than that of the first insulating layer 211L (see Figure 11) is performed under the process conditions of the first etching rate. That is, the first insulating layer 211L (see Figure 11 ) and the second insulating layer 213L (see Figure 11 ) can perform dry etching under a single process condition with a selectivity ratio of the first etching rate to the second etching rate.

[0077] Through dry etching, the first insulating layer 211L (see Figure 11 ) can be formed into the first insulating pattern 211, and the second insulating layer 213L (see Figure 11 ) can be formed into the second insulating pattern 213.

[0078] Therefore, the first device isolation layer 210A can be formed in the cell array region CA, and the second device isolation layer 210B can be formed in the peripheral circuit region PA. Each of the first device isolation layer 210A and the second device isolation layer 210B can include the first insulating pattern 211 on the outer side and the second insulating pattern 213 on the inner side.

[0079] The second width of the second device isolation layer 210B in the horizontal direction in the peripheral circuit region PA can be greater than the first width of the first device isolation layer 210A in the horizontal direction in the cell array region CA. Therefore, compared with the first device isolation layer 210A, the second device isolation layer 210B can have a relatively circular top surface 210R.

[0080] Each of the first device isolation layer 210A and the second device isolation layer 210B can be a shallow trench isolation, but the embodiments of the present disclosure are not limited thereto.

[0081] Referring to Figure 13 , the first active region 203A can be defined by the first device isolation layer 210A in the cell array region CA, and the second active region 203B can be defined by the second device isolation layer 210B in the peripheral circuit region PA.

[0082] A plurality of word line trenches can be formed in the substrate 201 in the cell array region CA. The word line trenches can extend parallel to each other in the first direction (see Figure 10 the X direction), and each can have a line shape intersecting the first active region 203A.

[0083] A plurality of gate dielectric layers, a plurality of word lines WL (see Figure 10 ) and a plurality of buried insulating layers can be sequentially formed inside the word line trenches. The top surface of the buried insulating layer can be located at substantially the same level as the top surface of the substrate 201.

[0084] In some embodiments, after forming the word line WL, source / drain regions may be formed on the top surface of the first active region 203A by injecting dopants into the substrate 201 from both sides of the word line WL. In some embodiments, the dopant injection process for forming the source / drain regions may be performed before forming the word line WL.

[0085] The first surface insulating layer 220 and the second surface insulating layer 222 may be sequentially formed on the substrate 201 in the cell array region CA and the peripheral circuit region PA. Then, the substrate 201's second active region 203B may be exposed again by removing the first surface insulating layer 220 and the second surface insulating layer 222 in the peripheral circuit region PA. Subsequently, a gate dielectric layer 224 may be formed on the substrate 201 in the peripheral circuit region PA while the cell array region CA is covered with a mask pattern.

[0086] The first surface insulating layer 220 may include a silicon oxide layer and the second surface insulating layer 222 may include a silicon nitride layer, but embodiments of the present disclosure are not limited thereto. Before forming the gate dielectric layer 224, impurities may be removed from the surface of the substrate 201 in the peripheral circuit region PA by forming and removing the first surface insulating layer 220 and the second surface insulating layer 222 in the peripheral circuit region PA. Thus, the quality of the gate dielectric layer 224 in the peripheral circuit region PA may be improved.

[0087] The gate dielectric layer 224 may include at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high-k dielectric material layer having a dielectric constant higher than that of the silicon oxide layer. For example, the gate dielectric layer 224 may have a dielectric constant of about 10 to about 25.

[0088] In some embodiments, the gate dielectric layer 224 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0089] Reference Figure 14 ,a first conductive layer 226 may be formed on the substrate 201 in the cell array region CA and the peripheral circuit region PA.

[0090] The first conductive layer 226 may include doped polysilicon, but embodiments of the present disclosure are not limited thereto.

[0091] Reference Figure 15 , a mask pattern 228 may be formed on the first conductive layer 226 in the cell array region CA and the peripheral circuit region PA.

[0092] An opening may be formed in the mask pattern 228 to partially expose the first conductive layer 226 in the cell array region CA. In the peripheral circuit region PA, the first conductive layer 226 may be covered with the mask pattern 228 so as not to be exposed to the outside.

[0093] Subsequently, the first conductive layer 226 exposed through the opening of the mask pattern 228 may be etched. A portion of the substrate 201 and a portion of the first device isolation layer 210A exposed by the etching may be etched to form a direct contact hole DCH exposing the substrate 201 in the cell array region CA.

[0094] The mask pattern 228 may be a hard mask pattern including a silicon oxide layer or a silicon nitride layer. A lithography process may be used to form the mask pattern 228.

[0095] Reference Figure 16 , after removing the mask pattern 228, a second conductive layer having a thickness sufficient to fill the direct contact hole DCH may be formed inside the direct contact hole DCH and on the first conductive layer 226.

[0096] By back-etching the second conductive layer such that the second conductive layer remains only inside the direct contact hole DCH, a direct contact DC including the second conductive layer remaining inside the direct contact hole DCH may be formed. The second conductive layer may include doped polysilicon, but embodiments of the present disclosure are not limited thereto.

[0097] Reference Figure 17 , a third conductive layer 232, a fourth conductive layer 234, and a cap layer 236 may be sequentially formed on the first conductive layer 226 and the direct contact DC in the cell array region CA and the peripheral circuit region PA.

[0098] Each of the third conductive layer 232 and the fourth conductive layer 234 may include TiN, TiSiN, W, tungsten silicide, or any combination thereof, but embodiments of the present disclosure are not limited thereto. In some embodiments, the third conductive layer 232 may include TiSiN, and the fourth conductive layer 234 may include W. The cap layer 236 may include a silicon nitride layer.

[0099] Reference Figure 18, the gate dielectric layer 224, the first conductive layer 226, the third conductive layer 232, the fourth conductive layer 234, and the capping layer 236 can be patterned in the peripheral circuit region PA while the cell array region CA is covered with a mask pattern.

[0100] The gate electrodes 240 for the peripheral circuit, including the first conductive pattern 226B, the third conductive pattern 232B, and the fourth conductive pattern 234B formed as a result of the patterning, can be formed on the gate dielectric layer 224 in the peripheral circuit region PA. The gate electrodes 240 can be covered with the capping pattern 236B.

[0101] In the patterning process, since the second device isolation layer 210B according to an embodiment of the present disclosure has a circular top surface 210R, the thickness of the first conductive layer 226, the third conductive layer 232, and / or the fourth conductive layer 234 located on the edge top surface 210E of the second device isolation layer 210B in the vertical direction can be relatively small.

[0102] Therefore, the embodiment of the present disclosure has the effect that unnecessary residues of the first conductive layer 226, the third conductive layer 232, and / or the fourth conductive layer 234 are not left on and around the second device isolation layer 210B. In other words, an additional process for removing unnecessary residues of the first conductive layer 226, the third conductive layer 232, and / or the fourth conductive layer 234 does not need to be performed on and around the edge top surface 210E of the second device isolation layer 210B.

[0103] Reference Figure 19 , the insulating spacers 242 can be formed on two sidewalls of the gate structure of the stacked structure including the gate dielectric layer 224, the gate electrodes 240, and the capping pattern 236B. Then, the insulating film 244 can be formed on the entire surface of the peripheral circuit region PA to cover the gate structure.

[0104] Each of the insulating spacers 242 can include a silicon oxide layer, a silicon nitride layer, or any combination thereof, and the insulating film can include a silicon nitride layer, but the embodiments of the present disclosure are not limited thereto.

[0105] Subsequently, the planarized interlayer insulating layer 246 is formed to cover the gate structure and the insulating film 244. The interlayer insulating layer 246 can include a silicon oxide layer formed by a high density plasma (HDP) process or a flowable chemical vapor deposition (FCVD) process, but the embodiments of the present disclosure are not limited thereto.

[0106] Reference Figure 20 , the upper insulating layer 252 can be formed on the capping layer 236 and the interlayer insulating layer 246 in the cell array region CA and the peripheral circuit region PA.

[0107] In some embodiments, the upper insulating layer 252 may include a silicon nitride layer, but embodiments of the present disclosure are not limited thereto.

[0108] Reference Figure 21 , a photolithography process may be used to pattern the upper insulating layer 252 and the capping layer 236.

[0109] As a result of the patterning, a cell mask pattern 252A, a cap pattern 236A, and a core mask pattern to be used as an etch mask for forming a plurality of bit lines 260 may be formed in the cell array region CA.

[0110] By etching a part of the lower structure using the cell mask pattern 252A, the cap pattern 236A, and the core mask pattern as an etch mask, bit lines 260 may be formed in the cell array region CA.

[0111] More specifically, by etching exposed portions of the first conductive layer 226, the third conductive layer 232, and the fourth conductive layer 234 using the cell mask pattern 252A, the cap pattern 236A, and the core mask pattern as an etch mask, a plurality of bit lines 260 including a first conductive pattern 226A, a third conductive pattern 232A, and a fourth conductive pattern 234A may be formed in the cell array region CA. The bit lines 260 may be DC-connected to the first active region 203A of the substrate 201 through a direct contact DC.

[0112] Reference Figure 22 , a plurality of buried contacts BC and a plurality of conductive landing pads LP respectively connected to the buried contacts BC may be formed in a space between the bit lines 260 in the cell array region CA.

[0113] More specifically, insulating spacers S1 and S2 covering sidewalls of the bit lines 260 may be formed in the cell array region CA. A plurality of insulating patterns defining a plurality of holes for forming the buried contacts BC in the space between the bit lines 260 may be formed. The first active region 203A of the substrate 201 may be exposed through the holes. A first metal silicide layer 261 may be formed on an exposed surface of the first active region 203A. Subsequently, the buried contacts BC connected to the first active region 203A may be formed by partially filling a lower portion of the holes.

[0114] In some embodiments, the first metal silicide layer 261 may include cobalt silicide, but embodiments of the present disclosure are not limited thereto. In some embodiments, the first metal silicide layer 261 may be omitted. The buried contacts BC may include doped polysilicon.

[0115] In some embodiments, the insulating spacers S1 and S2 may include a silicon oxide layer, a silicon nitride layer, air, or any combination thereof. The case where each of the insulating spacers S1 and S2 is provided as a bilayer is shown, but the insulating spacers S1 and S2 may be provided as a single layer or a triple layer. The insulating pattern may include a nitride layer, an oxide layer, or any combination thereof.

[0116] Subsequently, a third metal silicide layer 263 may be formed on the buried contact BC inside the hole between the bit lines 260. In some embodiments, the third metal silicide layer 263 may include cobalt silicide, but embodiments of the present disclosure are not limited thereto. In some embodiments, the third metal silicide layer 263 may be omitted.

[0117] In addition, more specifically, a contact hole passing through a part of the upper insulating layer 252 and the interlayer insulating layer 246 to expose the second active region 203B may be formed in the peripheral circuit region PA. The second metal silicide layer 262 may be formed on the surface of the second active region 203B exposed through the contact hole. In some embodiments, the second metal silicide layer 262 may include cobalt silicide, but embodiments of the present disclosure are not limited thereto. In some embodiments, the second metal silicide layer 262 may be omitted.

[0118] Subsequently, a conduction blocking layer and a conductive layer may be formed in the cell array region CA and the peripheral circuit region PA. The conduction blocking layer and the conductive layer may be re-etched to expose the upper insulating layer 252.

[0119] As a result of the re-etching, in the cell array region CA, a part of the conduction blocking layer and a part of the conductive layer are respectively retained as the first conduction blocking layer 264A and the first conductive layer 266A, and the first conduction blocking layer 264A and the first conductive layer 266A cover the bit line 260 to vertically overlap a part of the bit line 260 while filling the hole on the third metal silicide layer 263.

[0120] In addition, as a result of the re-etching, in the peripheral circuit region PA, a part of the conduction blocking layer and a part of the conductive layer are retained as the second conduction blocking layer 264B and the second conductive layer 266B filling the contact hole.

[0121] Subsequently, in the cell array region CA, a mask pattern exposing a part of the first conductive layer 266A may be formed on the first conductive layer 266A. The first conduction blocking layer 264A, the first conductive layer 266A, and the surrounding insulating layer may be etched by using the mask pattern as an etching mask to form a plurality of conductive landing pads LP from the remaining parts of the first conduction blocking layer 264A and the first conductive layer 266A. In the peripheral circuit region PA, the second conduction blocking layer 264B and the second conductive layer 266B inside the contact hole may constitute a contact plug CNT.

[0122] Subsequently, a plurality of capacitor structures electrically connectable to the conductive landing pads LP may be formed in the cell array region CA, and a multilayer wiring structure may be formed in the peripheral circuit region PA. In this manner, the semiconductor device 200 may be formed.

[0123] Figure 23 is a configuration diagram of a system including a semiconductor device according to an embodiment.

[0124] Reference Figure 23 , the system 1000 includes a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050.

[0125] The system 1000 may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system may be a portable computer, a network tablet, a mobile phone, a digital music player, or a memory card.

[0126] The controller 1010 may be configured to control the execution programs in the system 1000 and may include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0127] The input / output device 1020 may be used to input data into the system 1000 or output data from the system 1000. The system 1000 may be connected to an external device (such as a personal computer or a network) by using the input / output device 1020 and may exchange data with the external device. The input / output device 1020 may be, for example, a touch screen, a touchpad, a keyboard, or a display.

[0128] The storage device 1030 may store data for the operation of the controller 1010 or store data processed by the controller 1010. The storage device 1030 may include the semiconductor device 200 manufactured by the method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0129] The interface 1040 may be a data transmission path between the system 1000 and an external device. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 may communicate with each other via the bus 1050.

[0130] Although non-limiting example embodiments have been specifically shown and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

[0131] This application is based on and claims priority to Korean Patent Application No. 10-2023-0197642, filed with the Korean Intellectual Property Office on December 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a device isolation layer, comprising: forming a trench in a substrate; conformally forming a first insulating layer on the top surface of the substrate and on the inner wall of the trench by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process, so that a portion of the second insulating layer is within the groove; performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate; as well as forming a device isolation layer inside the trench, the device isolation layer comprising a first insulation pattern formed by etching the first insulation layer and a second insulation pattern formed by etching the second insulation layer, The device isolation layer has a curved top surface. 2 . The method of claim 1 , wherein performing the dry etching process comprises etching the first insulating layer at a first etching rate and etching the second insulating layer at a second etching rate greater than the first etching rate. 3 . The method of claim 2 , wherein performing the dry etching process further comprises controlling the first etching rate and the second etching rate based on a flow rate of a process gas used in the dry etching process.

4. The method according to claim 3, wherein the process gas comprises HF gas and NH3 gas, and in, In the dry etching process, a flow rate of the HF gas is greater than a flow rate of the NH 3 gas.

5. The method according to claim 1, wherein the second insulating pattern is on an inner side of the first insulating pattern, and The curved top surface of the device isolation layer is continuously formed through an outermost edge of the first insulating pattern, an interface between the first insulating pattern and the second insulating pattern, and the second insulating pattern. 6 . The method of claim 5 , wherein a vertical level of a top surface of the first insulating pattern of the device isolation layer is higher than a vertical level of a top surface of the second insulating pattern of the device isolation layer.

7. The method according to claim 1, further comprising: After forming the device isolation layer, a high-k dielectric material layer and a conductive material layer are sequentially formed on the curved top surface of the device isolation layer and the top surface of the substrate.

8. The method according to claim 7, further comprising removing the high-k dielectric material layer and the conductive material layer from the device isolation layer, Wherein residues of the conductive material layer do not remain in a region where the curved top surface of the device isolation layer contacts the top surface of the substrate. 9 . The method of claim 1 , wherein the first insulating layer and the second insulating layer comprise a same material.

10. The method of claim 1, wherein the device isolation layer comprises a shallow trench isolation.

11. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of trenches in each of a cell array region and a peripheral circuit region of a substrate; conformally forming a first insulating layer on inner walls of the plurality of trenches and on a top surface of the substrate by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process, so that a portion of the second insulating layer is within the plurality of trenches; forming a plurality of device isolation layers by performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate; sequentially forming a high-k dielectric material layer and a conductive material layer on top surfaces of the plurality of device isolation layers and the top surface of the substrate; as well as patterning the high-k dielectric material layer and the conductive material layer, Wherein each of the plurality of device isolation layers formed in the peripheral circuit region has a curved top surface.

12. The method according to claim 11, wherein performing the dry etching process comprises etching the first insulating layer at a first etching rate and etching the second insulating layer at a second etching rate greater than the first etching rate, and Wherein performing the dry etching process further includes controlling the first etching rate and the second etching rate based on a flow rate of a process gas used in the dry etching process.

13. The method according to claim 12, wherein the process gas comprises HF gas and NH3 gas, and in, In the dry etching process, a flow rate of the HF gas is greater than a flow rate of the NH 3 gas.

14. The method according to claim 11, wherein: In the patterning, residues of the conductive material layer do not remain on the curved top surface of each of the multiple device isolation layers formed in the peripheral circuit area and do not remain in the area where the curved top surface of each of the multiple device isolation layers contacts the top surface of the substrate.

15. The method according to claim 11, wherein: In the peripheral circuit region, the high-k dielectric material layer forms a gate insulating layer, and the conductive material layer forms a gate electrode.

16. A method for manufacturing a semiconductor device, the method comprising: A first device isolation layer and a second device isolation layer are formed in a substrate, the substrate comprising: a cell array region, comprising a first active region defined by the first device isolation layer; and a peripheral circuit region, comprising a second active region defined by the second device isolation layer; forming a word line crossing the first active area and a direct contact connected to the first active area in the cell array region; forming a bit line structure in the cell array region connected to the direct contact and perpendicular to the word line; and In the peripheral circuit region, a peripheral circuit gate structure is formed on the second active region, The forming of the first device isolation layer and the second device isolation layer comprises: forming a trench in each of the cell array region and the peripheral circuit region; conformally forming a first insulating layer on an inner wall of the trench and a top surface of the substrate by a thermal oxidation process; forming a second insulating layer on the first insulating layer by an atomic layer deposition process to fill the trench; and performing a dry etching process on the second insulating layer and the first insulating layer to expose the top surface of the substrate, wherein the first device isolation layer has a flat top surface in the cell array region, and The second device isolation layer has a curved top surface in the peripheral circuit region. 17 . The method according to claim 16 , wherein a first width of the first device isolation layer in a horizontal direction is smaller than a second width of the second device isolation layer in the horizontal direction.

18. The method according to claim 17, wherein forming the second device isolation layer comprises: forming a first insulating pattern by etching the first insulating layer; as well as forming a second insulating pattern on an inner side of the first insulating pattern by etching the second insulating layer, and A vertical level of a top surface of the first insulating pattern of the second device isolation layer is higher than a vertical level of a top surface of the second insulating pattern of the second device isolation layer. 19 . The method of claim 16 , wherein performing the dry etching process further comprises performing the dry etching process using a predetermined selectivity ratio of a first etching rate of the first insulating layer to a second etching rate of the second insulating layer.

20. The method of claim 19, wherein performing the dry etching process further comprises etching the first insulating layer at the first etching rate and etching the second insulating layer at the second etching rate, the second etching rate being greater than the first etching rate, wherein performing the dry etching process further comprises controlling the first etching rate and the second etching rate based on a flow rate of a process gas used in the dry etching process, wherein the process gas comprises HF gas and NH3 gas, and in, In the dry etching process, a flow rate of the HF gas is greater than a flow rate of the NH 3 gas.

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