Semiconductor device and device preparation method

Abstract

The invention provides a semiconductor device and a device preparation method. The semiconductor device comprises the components of a first chip which is internally provided with a first heat conduction member; a first heat conduction piece is formed in the first chip, a second heat conduction piece which is in thermal communication with the first heat conduction piece is formed in the second chip, the first chip is jointed on the first side of the second chip, the area of the second chip is larger than that of the first chip so as to form an exposed part, the second heat conduction piece is partially located on the exposed part, and the second heat conduction piece is in thermal communication with the first heat conduction piece. To be partially exposed to the environment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the device. Background Art

[0002] When a semiconductor device is operating, it usually generates heat and causes the temperature to rise. If the semiconductor device cannot be cooled in time, it will cause the semiconductor device to operate in a high-temperature environment for a long time, resulting in performance degradation or failure.

[0003] Therefore, there is a need to dissipate heat from the semiconductor device. Summary of the Invention

[0004] One object of the present disclosure is to provide a semiconductor device and a method for manufacturing the device.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0006] A first chip, in which a first heat conducting member is formed;

[0007] A second chip, in which a second heat conducting member thermally connected to the first heat conducting member is formed,

[0008] wherein the first chip is bonded to a first side of the second chip, and the area of the second chip is larger than the area of the first chip to form an exposed portion, and the second heat conducting member is partially located in the exposed portion to be partially exposed to the environment.

[0009] In some embodiments, the first heat conducting member includes a first heat conducting portion and / or a second heat conducting portion,

[0010] wherein the first heat conducting portion is filled in a first through hole formed in the first chip,

[0011] One or more layers of first wirings extending in a plane perpendicular to the thickness direction are formed in the first chip, and at least a part of the one or more layers of first wirings is configured to serve as the second heat conducting portion.

[0012] In some embodiments, the second heat conducting member includes one or more layers of second wirings extending in a plane perpendicular to the thickness direction, and the one or more layers of second wirings are partially located in the exposed portion.

[0013] In some embodiments, the second chip includes a passivation layer, a first side of the passivation layer is for bonding with the first chip, and the one or more layers of second wirings are located on a second side of the passivation layer opposite to the first side,

[0014] Wherein, the second heat conducting member further includes a third heat conducting portion filled in a second through hole formed in the passivation layer, one end of the third heat conducting portion is in thermal communication with the first heat conducting member, and the other end is in thermal communication with the one or more second wirings.

[0015] In some embodiments, the semiconductor device further includes:

[0016] A heat dissipation device, wherein the heat dissipation device is located on a portion of the second heat conducting member exposed to the environment and is in thermal communication with the second heat conducting member.

[0017] In some embodiments, the semiconductor device further includes:

[0018] A bonding layer, the bonding layer is located between the first chip and the second chip and is configured to bond the first chip and the second chip,

[0019] Wherein, the first heat conducting member is in thermal communication with the second heat conducting member via a bonding pad in the bonding layer.

[0020] In some embodiments, the semiconductor device further includes a third chip, the third chip is bonded to a second side of the second chip opposite to the first side,

[0021] Wherein, the first chip is configured to perform computing tasks, or the second chip is configured to perform signal transmission, or the third chip is configured to store data.

[0022] According to a second aspect of the present disclosure, there is provided a method for manufacturing a device, including:

[0023] Forming a first heat conducting member in a first chip;

[0024] Forming a second heat conducting member in a second chip; and

[0025] Bonding the first chip and the second chip so that the first heat conducting member is in thermal communication with the second heat conducting member, wherein the area of the second chip is larger than the area of the first chip to form an exposed portion, and the second heat conducting member is partially located in the exposed portion to be partially exposed to the environment.

[0026] In some embodiments, forming the first heat conducting member in the first chip includes:

[0027] Forming a first through hole in a first preset layer of the first chip and filling the first through hole with a heat conducting material to form a first heat conducting portion of the first heat conducting member; and / or

[0028] Form one or more first wirings on a second predetermined layer of the first chip to form a second heat-conducting portion of the first heat-conducting member, wherein the one or more first wirings extend in a plane perpendicular to the thickness direction.

[0029] In some embodiments, forming the second heat-conducting member in the second chip includes:

[0030] Form one or more second wirings that extend in a plane perpendicular to the thickness direction on a third predetermined layer of the second chip, wherein the one or more second wirings are partially located in the exposed portion when the first chip and the second chip are joined.

[0031] In some embodiments, forming the second heat-conducting member in the second chip further includes:

[0032] Form a passivation layer on the one or more second wirings;

[0033] Form a patterned anti-etching layer on the passivation layer;

[0034] Etch the passivation layer under the protection of the anti-etching layer until at least part of the one or more second wirings are exposed; and

[0035] Remove the remaining anti-etching layer.

[0036] In some embodiments, etching the passivation layer under the protection of the anti-etching layer includes forming a second through hole formed in the passivation layer, wherein forming the second heat-conducting member in the second chip further includes:

[0037] Fill the second through hole with a heat-conducting material to form a third heat-conducting portion of the second heat-conducting member, one end of the third heat-conducting portion is used for thermal communication with the first heat-conducting member, and the other end is used for thermal communication with the one or more second wirings.

[0038] Through the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings, other features and advantages of the present disclosure will become clearer. Brief Description of the Drawings

[0039] The accompanying drawings that form a part of the specification depict the embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0040] Referring to the accompanying drawings, according to the following detailed description, the present disclosure can be more clearly understood, wherein:

[0041] Figure 1 Shows a schematic diagram of the temperature distribution before and after a reasonable layout of the chips in an example;

[0042] Figure 2Shows a schematic diagram of heat dissipation for a chip in one example;

[0043] Figure 3 Shows a schematic structural diagram of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0044] Figure 4 Shows a schematic layout diagram of a second wiring according to an exemplary embodiment of the present disclosure;

[0045] Figure 5 Shows a schematic flow diagram of a device manufacturing method according to an exemplary embodiment of the present disclosure;

[0046] Figure 6 Shows a schematic diagram of a first heat-conducting portion of a first heat-conducting member in a first chip according to an exemplary embodiment of the present disclosure;

[0047] Figure 7 Shows a schematic diagram of a second heat-conducting portion of a first heat-conducting member in a first chip according to an exemplary embodiment of the present disclosure;

[0048] Figure 8 Shows a schematic diagram of forming a second heat-conducting member according to an exemplary embodiment of the present disclosure.

[0049] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0050] For ease of understanding, the positions, sizes, and ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show details of specific components. Detailed Embodiments

[0051] Now, various exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0052] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way serves as a limitation on the present disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways.

[0053] Technologies, methods, and devices that are known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices shall be regarded as part of the specification.

[0054] Three-dimensional integrated chips have the advantages of high density, high performance, and small volume, and are thus widely used in a variety of modern electronic devices. In three-dimensional integrated chips, as the number of stacked structures increases, the thermal resistance between the internal hot spots and the outer surface of the chip increases significantly, hindering the effective dissipation of heat, making the heat generated during chip operation prone to accumulate inside, and overheating may occur, leading to performance degradation and reduced reliability.

[0055] In some examples, the components in the chip can be reasonably arranged to make the hot spot distribution in the chip uniform and reduce thermal coupling. For example, Figure 1 Figs. (a) and (b) in [reference] respectively show the schematic diagrams of the chip temperature before and after optimizing the layout of the chip. Among them, Figure 1 Fig. (c) in [reference] is the grayscale schematic diagram corresponding to Figure 1 Fig. (a) in [reference], Figure 1 Fig. (d) in [reference] is the grayscale schematic diagram corresponding to Figure 1 Fig. (b) in [reference]. Although this method can alleviate the problem of local overheating caused by overly concentrated hot spot distribution to a certain extent, the heat in each hot spot area is still prone to accumulate inside the chip, and the heat dissipation effect is not good. Alternatively, in some examples, as shown in Figure 2 Thermal interface materials (TIM) 3, integrated heat sinks 4, heat sinks 5, etc. can be used on the ball grid array (BGA) substrate 1 and silicon substrate 2 of the chip to reduce the thermal resistance from the chip to the boundary, so as to assist in heat dissipation on the chip surface. However, this method of dissipating heat on the chip surface by additionally introducing TIM materials, heat sinks, and heat sinks is difficult to effectively handle the heat accumulated inside the three-dimensional integrated chip. Alternatively, in some examples, microchannel technology can also be used to generate channels for the coolant to flow inside or around the chip, and the flowing coolant is used to cool the chip. However, this method additionally introduces a microchannel processing technology, which has great process difficulty and high cost.

[0056] To solve the above problems, the present disclosure provides a semiconductor device, which efficiently conducts the heat inside the chip to the environment through a heat conducting member in the exposed portion of the second chip relative to the first chip exposed to the environment, effectively reducing the accumulation of heat and improving the heat dissipation ability of the chip.

[0057] As shown in Figure 3As shown, a semiconductor device 400 according to some embodiments of the present disclosure may include a first chip 100 and a second chip 200, wherein the first chip 100 may be bonded to a first side of the second chip 200.

[0058] A first heat conducting member 130 may be formed in the first chip 100, and a second heat conducting member 230 thermally connected to the first heat conducting member 130 may be formed in the second chip 200, such that a heat conducting channel formed by the thermal connection between the first heat conducting member 130 and the second heat conducting member 230 can conduct the heat in the chips. In some embodiments, other components may also be formed in the first chip 100 and the second chip 200. For example, a first conductive member may be formed in the first chip 100, and a second conductive member may be formed in the second chip 200 for realizing corresponding circuit connections.

[0059] The area of the second chip 200 may be larger than the area of the first chip 100, such that a part of the second chip 200 forms an exposed portion 420 exposed to the environment relative to the first chip 100. Here, the area of the chip may be the maximum cross-sectional area of the chip. Among them, the second heat conducting member 230 may be partially located in the exposed portion 420 to be partially exposed to the environment.

[0060] Alternatively, in some other embodiments, the area of the first chip 100 may be larger than the area of the second chip 200, such that a part of the first chip 100 forms an exposed portion 420 exposed to the environment relative to the second chip 200. Among them, the first heat conducting member 130 may be partially located in the exposed portion 420 to be partially exposed to the environment.

[0061] In this way, the heat conducting channel formed by the thermal connection between the first heat conducting member 130 and the second heat conducting member 230 can timely conduct the heat in the first chip 100 and / or the second chip 200 from the exposed portion 420 to the environment, reducing the heat accumulation in the chips and improving the heat dissipation capacity.

[0062] In some embodiments, as Figure 3 and Figure 4 shown, when the area of the second chip 200 is larger than the area of the first chip 100, the first chip 100 may be located in the central region of the second chip 200, such that a part of the second chip 200 forms an exposed portion that is exposed to the environment all around the first chip 100. In this way, through the corresponding heat conducting members, the heat in the chips can be conducted to the environment via the exposed portion more quickly, improving the heat dissipation efficiency.

[0063] In some embodiments, as Figure 3 、 Figure 6As shown, the first heat conducting member 130 may include a first heat conducting portion 131 extending in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the first heat conducting member 130 may include a second heat conducting portion extending in a plane parallel or coincident with the main plane of the first chip 100, or in other words, extending in a plane perpendicular to the thickness direction, to conduct heat in a plane perpendicular to the thickness direction.

[0064] In some embodiments, the first chip 100 may include a first substrate 160, a first device layer 170, a first wiring layer 180, and a first passivation layer 190 stacked in sequence in the thickness direction. Among them, in a specific example, as Figure 3 shown, the first substrate 160 may be disposed close to the second chip 200 in the thickness direction to be bonded to the second chip 200. Alternatively, in another specific example, the first passivation layer 190 may be disposed close to the second chip 200 in the thickness direction to be bonded to the second chip 200.

[0065] As Figure 3 shown, the first heat conducting portion 131 of the first heat conducting member 130 may be filled in the first through hole 120. The first through hole 120 may be formed in at least one of the first substrate 160, the first device layer 170, the first wiring layer 180, and the first passivation layer 190. When the first substrate 160 is disposed close to the second chip 200, the first through hole 120 may be formed at least in the first substrate 160, and the first heat conducting portion 131 for thermally communicating with the second heat conducting member 230 is formed by filling a corresponding heat conducting material. For example, as Figure 3 shown, the first through hole 120 may be formed only in the first substrate 160, or in addition to being formed in the first substrate 160, the first through hole 120 may also be formed in one or more of the first device layer 170, the first wiring layer 180, and the first passivation layer 190. When the first passivation layer 190 is disposed close to the second chip 200, the first through hole 120 may be formed at least in the first passivation layer 190, and the first heat conducting portion 131 for thermally communicating with the second heat conducting member 230 is formed by filling a corresponding heat conducting material. For example, the first through hole 120 may be formed only in the first passivation layer 190, or in addition to being formed in the first passivation layer 190, the first through hole 120 may also be formed in one or more of the first substrate 160, the first device layer 170, and the first wiring layer 180.

[0066] Alternatively, in some other embodiments, the first passivation layer 190 may be omitted, that is, the first chip 100 may include a first substrate 160, a first device layer 170, and a first wiring layer 180 stacked in sequence in the thickness direction. Among them, the first substrate 160 or the first wiring layer 180 may be disposed close to the second chip 200 in the thickness direction to be bonded to the second chip 200. Correspondingly, when the first wiring layer 180 is disposed close to the second chip 200, the first via 120 may be formed at least in the first wiring layer 180.

[0067] In some embodiments, as Figure 7 shown, one or more layers of first wirings 132 extending in a plane perpendicular to the thickness direction may be formed in the first chip 100. Among them, at least a part of the one or more layers of first wirings may be configured to be used as the second heat-conducting part of the first heat-conducting member 130 to conduct heat in a plane perpendicular to the thickness direction. For example, a part of the one or more layers of first wirings 132 may be configured to be used as the second heat-conducting part of the first heat-conducting member 130, and another part may be configured to be used as a conductive part for realizing relevant circuit connections, and the two parts may be electrically isolated from each other to avoid short-circuiting of relevant circuits. In a specific example, the one or more layers of first wirings 132 may be located in the first wiring layer 180 of the first chip 100 as Figure 3 shown.

[0068] In a specific example, the position of the first via 120 to be formed in the first chip 100 may be determined in advance, for example, by thermal simulation, to determine the position of the first heat-conducting part 131 in the first chip 100. Through the corresponding first heat-conducting part 131 and / or the one or more layers of first wirings 132, the heat in the first chip 100 can be conducted to the second heat-conducting member 230 of the second chip 200.

[0069] As Figure 3 and Figure 4 shown, the second heat-conducting member 230 in the second chip 200 may include one or more layers of second wirings 232. Among them, the one or more layers of second wirings 232 may extend in a plane parallel or coincident with the main plane of the second chip 200, or may extend in a plane perpendicular to the thickness direction to conduct heat in a plane perpendicular to the thickness direction. Among them, the one or more layers of second wirings 232 may be partially located in the exposed portion 420 to be partially exposed to the environment. This arrangement increases the heat exchange area between the second wirings 232 and the environment, and the heat inside the chip can be quickly conducted to the outside of the chip through the part of the second wirings 232 exposed to the environment, improving the heat dissipation capacity.

[0070] In some embodiments, to avoid short-circuiting of relevant circuits, as Figure 3As shown, the second chip 200 may include a second passivation layer 290. Wherein, the first side of the second passivation layer 290 may be used for bonding with the first chip, and one or more second wirings 232 may be located on the second side of the second passivation layer 290 opposite to the first side.

[0071] In some embodiments, the second heat conducting member 230 may include a third heat conducting portion 231 extending in the thickness direction to conduct heat in the thickness direction. As Figure 3 shown, the second heat conducting member 230 may include a third heat conducting portion 231 filled in a second through hole 220 formed in the second passivation layer 290. One end of the third heat conducting portion 231 may be in thermal communication with the first heat conducting member 130, and the other end may be in thermal communication with one or more second wirings 232. Wherein, one or more second wirings 232 may achieve thermal communication with the first heat conducting member 130 via the third heat conducting portion 231 in the second passivation layer 290, so that the heat in the first chip 100 can be conducted to the second wiring 232 through the first heat conducting member 130, and then quickly dissipated into the environment by the portion of the second wiring 232 exposed to the environment. In this way, the heat dissipation capacity of the first chip 100 can be improved, and the service life of the first chip 100 can be increased.

[0072] As Figure 3 shown, the second chip may further include a second substrate 260, a second device layer 270, and a second wiring layer 280 stacked in sequence in the thickness direction. Wherein, the second wiring layer 280 is located between the second device layer 270 and the second passivation layer 290, and one or more second wirings 232 may be located in the second wiring layer. In some embodiments, in addition to being filled in the second through hole 220 formed in the second passivation layer 290, the third heat conducting portion 231 of the second heat conducting member 230 may also be filled in the second through hole 220 formed in one or more of the second substrate 260, the second device layer 270, and the second wiring layer 280. In a specific example, the position where the second through hole 220 is to be formed in the second chip 200 may be determined in advance through, for example, thermal simulation, so as to determine the position of the third heat conducting portion 231 in the second chip 200. The heat in the second chip 200 can also be quickly dissipated into the environment through one or more second wirings 232 and the corresponding third heat conducting portion 231, thereby improving the heat dissipation capacity of the second chip 200 and increasing the service life.

[0073] Alternatively, in some other embodiments, the second passivation layer 290 may be omitted. For example, one or more second wirings 232 may be directly in thermal communication with the first heat conducting member 130 of the first chip 100, which is not limited herein.

[0074] As Figure 3As shown, in some embodiments, the semiconductor device 400 may further include a bonding layer 410. The bonding layer 410 is located between the first chip 100 and the second chip 200 and may be configured to bond the first chip 100 and the second chip 200 to improve the packaging integration of the semiconductor device 300. The first heat conducting member 130 and the second heat conducting member 230 may be thermally connected via the bonding pads 411 in the bonding layer 410. In a specific example, as Figure 3 shown, the first heat conducting portion 131 of the first heat conducting member 130 may be thermally connected to the third heat conducting portion 231 of the second heat conducting member 230 via the bonding pad 411, so that the heat in the first chip 100 can be dissipated to the environment via the first heat conducting portion 131, the bonding pad 411, the third heat conducting portion 231, and one or more second wirings 232.

[0075] The heat distribution inside each chip in the semiconductor device is usually uneven during operation. For example, the area closer to the location of the devices in the chip (such as Figure 3 and Figure 4 the hot spot area 430 shown) usually has a higher heat generation. To reduce the heat accumulation in the hot spot area 430, in some embodiments, the heat conduction channels formed by the first heat conducting member 130 and the second heat conducting member 230 may be configured to transfer the heat in the hot spot area 430 of the first chip 100 and / or the second chip 200. The hot spot area 430 may be determined by thermal simulation according to the layout of the first chip 100 and / or the second chip 200. Specifically, in some embodiments, the first heat conducting member 130 may be configured to conduct the heat in the hot spot area 430 of the first chip 100 to the second heat conducting member 230 of the second chip 200, so that the heat in the hot spot area 430 of the first chip 100 is transferred from the exposed portion 420 to the environment via the first heat conducting member 130 and the second heat conducting member 230. One end of the first heat conducting member 130 may be configured to be close to the hot spot area 430, and the other end of the first heat conducting member 130 may be configured to be in thermal communication with the second heat conducting member 230. For example, as Figure 3 shown, one end of the first heat conducting portion 131 may be configured to be close to the hot spot area 430, and the other end may be configured to be in thermal communication with one or more second wirings 232, so that the heat in the hot spot area 430 of the first chip 100 can be conducted via the first heat conducting member 130 and the second heat conducting member 230. In Figure 3 and Figure 4In the illustrated example, the heat at the hot spot area 430 of the first chip 100 can be conducted to the bonding layer 410 via the first heat conducting part 131 of the first heat conducting member 130, and then conducted to one or more second wirings 232 of the second heat conducting member 230 via the bonding pad 411 of the bonding layer 410, and then dissipated to the environment through the part of the one or more second wirings 232 exposed to the environment. In this way, the heat accumulation in the hot spot area 430 of the first chip 100 can be reduced, the heat dissipation efficiency of the first chip 100 can be effectively improved, and thus the heat dissipation capacity and service life of the semiconductor device 400 can be improved.

[0076] Figure 4 Two arrangements in which one or more second wirings 232 extend in a plane perpendicular to the thickness direction are shown in some embodiments of the present disclosure. In some embodiments, one or more second wirings 232 can be flexibly arranged according to the actual space situation, so as to maximize the arrangement area of the one or more second wirings 232 while avoiding interference with signal transmission and hindrance to the device layout in the chip. Among them, the exposed part 420 of the second chip 200 relative to the first chip 100 can be used to increase the total area of the second wirings 232 exposed to the environment, thereby enhancing the heat dissipation capacity, and the second wirings 232 can be extended in the thickness direction according to the abundance of wiring resources, so as to bypass areas such as signal transmission dense areas and working device arrangement areas, thereby weakening the influence of the second wirings 232 on other components in the chip. In a specific example, the arrangement of the second wirings 232 can be flexibly adjusted according to the power consumption and heat management requirements of the chip to meet the requirements of different application scenarios.

[0077] To further improve the heat dissipation capacity of the semiconductor device, in some embodiments, the semiconductor device 400 may further include a heat dissipation device, wherein the heat dissipation device may be located on the part of the second heat conducting member 230 exposed to the environment and is in thermal communication with the second heat conducting member 230 to promote the second heat conducting member 230 to conduct heat to the environment. As Figure 3 shown, the exposed part 420 can provide an arrangement space for the setting of the heat dissipation device, and the heat dissipation device can be in thermal communication with the part of the second wirings 232 exposed to the environment to promote the second wirings 232 to conduct heat, thereby improving the heat dissipation efficiency of the chip.

[0078] As Figure 3As shown, in some embodiments, the semiconductor device 400 may further include a third chip 300, wherein the third chip 300 may be bonded to a second side of the second chip 200 opposite to the first side. In a specific example, the third chip 300 may be bonded to the second chip 200 via a bonding layer 440. In some embodiments, by forming corresponding thermally connected heat conducting portions in the third chip 300 and the second chip 200, heat within the third chip 300 can be conducted to one or more layers of the second wiring 232, and then dissipated to the environment through the portions of the second wiring 232 exposed to the environment.

[0079] The first chip 100 may be configured to perform computing tasks. In a specific example, the first chip 100 may be configured as a logic layer in a three-dimensional integrated chip. The second chip 200 may also be configured to perform signal transmission, such as transmitting data between the first chip 100 and the third chip 300. In a specific example, the second chip 200 may be configured as a buffer layer in a three-dimensional integrated chip. The third chip 300 may be configured to store data. In a specific example, the third chip 300 may be configured as a storage layer in a three-dimensional integrated chip.

[0080] In a three-dimensional integrated chip, the logic layer for performing computing tasks generally has a higher heat generation rate compared to other layers, and heat is more likely to accumulate. According to some embodiments of the present disclosure, heat in hot spot regions within the logic layer can be effectively conducted. For example, heat within the logic layer can be timely dissipated to the environment through the second wiring exposed to the environment in the second chip, reducing heat accumulation within the logic layer, thereby effectively improving the overall heat dissipation capacity and service life of the three-dimensional integrated chip. In addition, the logic layer usually has relatively complex computing circuits. By arranging the buffer layer to be exposed relative to the logic layer to form an exposed portion, corresponding heat conducting components can be arranged in the buffer layer and corresponding heat dissipating components can be arranged on the exposed portion of the buffer layer, so as to enable heat within the logic layer to be quickly conducted to the environment while providing more layout space for the computing circuits in the logic layer, facilitating the optimization of the layout of the computing circuits, reducing thermal coupling between the computing circuits, and being beneficial to reducing the local maximum temperature.

[0081] According to another aspect of the present disclosure, a method for manufacturing a device is also provided. As Figure 3 、 Figures 5 to 7 shown, the method for manufacturing a device according to the present disclosure may include:

[0082] Step S110, forming a first heat conducting member 130 in the first chip 100.

[0083] As Figure 6As shown, forming the first heat conducting member 130 in the first chip 100 may include: forming a first through hole 120 in a first preset layer 110 of the first chip 100, and filling the first through hole 120 with a heat conducting material to form a first heat conducting portion 131 of the first heat conducting member 130.

[0084] In a specific example, forming the first through hole 120 in the first preset layer 110 of the first chip 100 may include: forming a patterned first anti-etching layer on the first preset layer 110 of the first chip 100 by using a photolithography process, and etching the first preset layer 110 under the protection of the first anti-etching layer to form the first through hole 120. Among them, an anti-etching material may be deposited on the first preset layer 110, and then, a patterned first anti-etching layer may be formed on the first preset layer 110 of the first chip 100 by means of electron beam exposure or ion beam exposure and then development. Alternatively, based on a mask, a photolithography process may be used to transfer the pattern of the mask to the anti-etching material to form a patterned first anti-etching layer.

[0085] In some embodiments, the first preset layer 110 may be, for example, Figure 3 one or more of a first substrate 160, a first device layer 170, a first wiring layer 180, and a first passivation layer 190 of the first chip 100 as shown. For example, if the first preset layer 110 is the first substrate 160, only the first substrate 160 may be etched to form the first through hole 120 opened in the first substrate 160, or the first substrate 160 and the first device layer 170 of the first chip 100 may be etched in sequence to form the first through hole 120 opened in the first substrate 160 and the first device layer 170. Again, for example, if the first preset layer 110 is the first wiring layer 180, the first wiring layer 180 may be etched to form the first through hole 120 opened in the first wiring layer 180. Again, for example, if the first preset layer 110 is the first passivation layer 190, only the first passivation layer 190 may be etched to form the first through hole 120 opened in the first passivation layer 190, or the first passivation layer 190 and the first wiring layer 180 may be etched in sequence to form the first through hole 120 opened in the first passivation layer 190 and the first wiring layer 180.

[0086] In some embodiments, the heat conducting material may further include a conductive material, so that while forming the heat conducting member in the chip by depositing the heat conducting material, the conductive portion for realizing circuit connection in the chip may be formed synchronously. In a specific example, the heat conducting material may include, for example, a metal material. Metal materials generally have a high thermal conductivity, and forming the corresponding heat conducting member by the metal material can effectively improve the heat dissipation performance of the chip and reduce the thermal resistance.

[0087] As Figure 7As shown, forming the first heat conducting member 130 in the first chip 100 may include forming one or more layers of first wirings 132 on a second preset layer 140 of the first chip 100 to form a second heat conducting portion of the first heat conducting member 130, wherein the one or more layers of first wirings 132 may extend in a plane parallel or coincident with the main plane of the first chip 100, or in other words, may extend in a plane perpendicular to the thickness direction.

[0088] Specifically, in some embodiments, a heat conducting material in the form of a continuous thin film may be deposited on the second preset layer 140. Then, a patterned second anti-etching layer is formed on the heat conducting material by means of a photolithography process. Then, the portion of the heat conducting material not covered by the second anti-etching layer is etched to form one or more layers of first wirings 132. Then, the remaining second anti-etching layer may be removed to avoid the influence of the remaining second anti-etching layer on subsequent processes. Among them, the second anti-etching layer may be formed only of photoresist, or may also be formed of materials such as deposited silicon nitride. Forming a patterned second anti-etching layer on the heat conducting material by means of a photolithography process may include, for example, depositing an anti-etching material on the heat conducting material and transferring the pattern of the mask to the anti-etching material based on the mask by means of a photolithography process to form a patterned second anti-etching layer.

[0089] Alternatively, in some other embodiments, a patterned photoresist layer may be formed on the second preset layer 140 of the first chip 100 by means of a photolithography process. Then, a heat conducting material in the form of a continuous thin film is deposited. Then, a lift-off process is used to remove the photoresist layer and the heat conducting material thereon, so that the remaining heat conducting material forms one or more layers of first wirings 132. Among them, forming a patterned photoresist layer may include, for example, depositing a photoresist material on the second preset layer 140 and transferring the pattern of the mask to the photoresist material based on the mask by means of a photolithography process to form a patterned photoresist layer.

[0090] In some embodiments, the second preset layer 140 may be, for example, the first substrate 160 of the first chip 100 as shown in Figure 3 so that one or more layers of first wirings 132 can be formed on the first substrate 160. Alternatively, in some embodiments, the second preset layer may be, for example, the first device layer 170 of the first chip 100 as shown in Figure 3 and the first device layer 170 may be located above the first substrate 160, so that one or more layers of first wirings 132 can be formed on the first device layer 170. Among them, the one or more layers of first wirings 132 may be at least a part of the first wiring layer 180 of the first chip 100 as shown in Figure 3

[0091] At least a portion of one or more first wirings 132 can be used as a second heat-conducting portion of the first heat-conducting member 130 for subsequent thermal communication with the second heat-conducting member of the second chip. For example, a part of one or more first wirings 132 can be used as the second heat-conducting portion, and another part can be used as a conductive portion for realizing circuit connection, where the two parts can be electrically isolated to avoid short-circuiting of the relevant circuits. Alternatively, all parts of one or more first wirings 132 can be used as the second heat-conducting portion.

[0092] As Figure 3 , Figure 5 and Figure 8 shown, the method for manufacturing the device of the present disclosure may further include:

[0093] Step S120, forming the second heat-conducting member 230 in the second chip 200.

[0094] As Figure 8 shown in (a) of [], forming the second heat-conducting member 230 in the second chip 200 may include forming one or more second wirings 232 on a third preset layer 210 of the second chip 200, where the one or more second wirings 232 may extend in a plane parallel or coincident with the main plane of the second chip 200, or may extend in a plane perpendicular to the thickness direction.

[0095] Specifically, in some embodiments, a heat-conducting material in the form of a continuous thin film may be deposited on the third preset layer 210. Then, a patterned third anti-etching layer is formed on the heat-conducting material by means of a lithography process. Then, the portion of the heat-conducting material not covered by the third anti-etching layer is etched to form one or more second wirings 232. Then, the remaining third anti-etching layer can be removed to avoid the influence of the remaining third anti-etching layer on subsequent processes. Among them, the third anti-etching layer can be formed only by photoresist, or can also be formed by materials such as deposited silicon nitride. Forming a patterned third anti-etching layer on the heat-conducting material by means of a lithography process may include, for example, depositing an anti-etching material on the heat-conducting material and transferring the pattern of the mask to the anti-etching material by means of a lithography process based on the mask to form a patterned third anti-etching layer.

[0096] Alternatively, in some other embodiments, a patterned photoresist layer may be formed on the third preset layer 210 of the second chip 200 by means of a lithography process. Then, a heat-conducting material in the form of a continuous thin film is deposited, and then the photoresist layer and the heat-conducting material thereon are removed by means of a lift-off process, so that the remaining heat-conducting material forms one or more second wirings 232. Among them, forming a patterned photoresist layer may include, for example, depositing a photoresist material on the third preset layer 210 and transferring the pattern of the mask to the photoresist material by means of a lithography process based on the mask, so as to form a patterned photoresist layer.

[0097] In some embodiments, the third preset layer 210 may be, for example, the second substrate 260 of the second chip 200 as shown in Figure 3 . Thus, one or more layers of second wirings 232 can be formed on the second substrate 260. Alternatively, in some embodiments, the third preset layer 210 may be, for example, the second device layer 270 of the second chip 200 as shown in Figure 3 . And the second device layer 270 can be located above the second substrate 260. Thus, one or more layers of second wirings 232 can be formed on the second device layer 270. Wherein, one or more layers of second wirings 232 can be used as at least a part of the second wiring layer 280 of the second chip 200 as shown in Figure 3 .

[0098] Referring to Figure 3 , when the one or more layers of second wirings 232 formed above are joined between the first chip 100 and the second chip 200, they can be partially located in the exposed portion 420 of the second chip 200 relative to the first chip 100, so as to be partially exposed to the environment, so that the heat in the chip can be timely dissipated to the environment through the portion of the one or more layers of second wirings 232 exposed to the environment.

[0099] In some embodiments, in order to avoid short - circuiting of related circuits caused by the one or more layers of second wirings 232 formed above when the first chip 100 and the second chip 200 are joined, as shown in (b) of Figure 8 , forming the second heat - conducting member 230 in the second chip 200 may further include:

[0100] Step S121, forming a second passivation layer 290 on the one or more layers of second wirings.

[0101] Then, by performing local etching treatment on the second passivation layer 290, the one or more layers of second wirings 232 can be partially exposed to the environment when the second chip 200 is joined to the first chip 100, so that heat can be quickly dissipated to the environment. And an external heat - dissipating device can also be directly arranged on the portion of the one or more layers of second wirings 232 exposed to the environment, which is beneficial to increasing the heat - exchange efficiency and improving the heat - dissipating performance.

[0102] In a specific example, as shown in (c) and (d) of Figure 8 , forming the second heat - conducting member 230 in the second chip 200 may further include:

[0103] Step S122, forming a patterned fourth anti - etching layer 10 on the second passivation layer 290;

[0104] Step S123: Etch the second passivation layer 290 under the protection of the fourth anti-etching layer 10 until at least a part of one or more second wirings 232 is exposed.

[0105] Considering that the remaining anti-etching layer may affect subsequent processes, in some embodiments, the remaining anti-etching layer can be removed after step S122.

[0106] In some embodiments, after step S123, a patterned fifth anti-etching layer can be formed on the remaining second passivation layer 290, and the second passivation layer 290 can be etched under the protection of the fifth anti-etching layer to form a second through hole 220 opened in the second passivation layer 290. In this way, the second through hole 220 of the second passivation layer 290 and the part of the second wiring 232 exposed to the environment can be formed respectively. Alternatively, in some other embodiments, as shown in (c) and (d) of Figure 8 Etching the second passivation layer 290 in step S123 can include forming a second through hole 220 opened in the second passivation layer 290. In this way, considering the position where the second through hole 220 is to be opened in the second passivation layer 290 and the part of the second wiring 232 to be exposed to the environment, a corresponding patterned fourth anti-etching layer 10 can be formed. Then, through etching, the second through hole 220 and the part of the second wiring 232 exposed to the environment can be formed synchronously, thus simplifying the process flow and saving the manufacturing cost.

[0107] Next, as shown in (d) of Figure 8 A heat-conducting material can be filled in the second through hole 220 to form a third heat-conducting part 231 of the second heat-conducting member 230. One end of the third heat-conducting part 231 can be used for thermal communication with the first heat-conducting member 130, and the other end can be used for thermal communication with one or more second wirings 232. In the case where the first chip 100 and the second chip 200 are bonded, the third heat-conducting part 231 in the second passivation layer 290 can achieve thermal communication between the first heat-conducting member 130 and one or more second wirings 232.

[0108] In some embodiments, it can also be as shown in Figure 3A second via is formed in one or more of the second substrate 260, the second device layer 270, and the second wiring layer 280 of the second chip 200 shown. By filling the second via with a thermally conductive material, a corresponding third thermally conductive portion can be formed. And, through the corresponding third thermally conductive portion, the heat within the second chip 200 can be conducted to one or more layers of the second wiring 232, so that the heat within the second chip 200 can be quickly dissipated to the environment through the portions of one or more layers of the second wiring 232 that are exposed to the environment, reducing the heat accumulation within the second chip 200, improving the heat dissipation capacity of the second chip 200, and further improving the service life of the second chip 200.

[0109] As Figure 3 and Figure 5 shown, the method for manufacturing the device of the present disclosure may further include:

[0110] Step S130, bonding the first chip 100 and the second chip 200 to enable the first heat conducting member 130 to be in thermal communication with the second heat conducting member 230.

[0111] The area of the second chip 200 may be larger than the area of the first chip 100, so that a part of the second chip 200 forms an exposed portion 420 that is exposed to the environment relative to the first chip 100. Among them, the second heat conducting member 230 in the second chip 200 may be partially located in the exposed portion 420 to be partially exposed to the environment. In this way, the heat conduction path formed by the thermal communication between the first heat conducting member 130 and the second heat conducting member 230 can timely conduct the heat in the first chip 100 and the second chip 200 from the exposed portion 420 to the environment, reducing the heat accumulation in the chip and improving the heat dissipation capacity.

[0112] In some embodiments, bonding the first chip 100 and the second chip 200 may include bonding the first chip 100 to the central region of the second chip 200 that can be bonded, so that a part of the second chip 200 forms an exposed portion that is exposed to the environment all around relative to the first chip 100, so that the heat in the chip can be more quickly conducted to the environment through the corresponding heat conducting member via the exposed portion, improving the heat dissipation efficiency.

[0113] In some embodiments, bonding the first chip 100 and the second chip 200 may include: forming a bonding layer 410 on at least one of the first side of the second chip 200 and the second side of the first chip 100, wherein the first side of the second chip 200 and the second side of the first chip 100 may be arranged adjacent to each other face to face, and the first heat conducting member 130 of the first chip 100 and the second heat conducting member 230 of the second chip 200 may be in thermal communication via a bonding pad 411 in the bonding layer 410. In a specific example, a Hybrid Bonding process may be used to bond the first chip 100 and the second chip 200 to improve the packaging integration of the first chip 100 and the second chip 200 and form a corresponding bonding layer 410 between the first side of the second chip 200 and the second side of the first chip 100.

[0114] In some embodiments, bonding materials may be deposited on the first side of the first chip 100 and the second side of the second chip 200 respectively to form a bonding layer 410, so as to bond the first chip 100 and the second chip 200 through the bonding layer 410 on the first chip 100 and the second chip 200.

[0115] To further improve the heat dissipation effect of the semiconductor device, in some embodiments, a third heat conducting member thermally connected to the second heat conducting member 230 may also be formed on a portion of the second heat conducting member 230 exposed to the environment (such as Figure 3 the portion of one or more layers of the second wiring 232 exposed to the environment as shown), or a corresponding heat dissipation device may be thermally connected to the second heat conducting member 230 to cause the second wiring 232 to conduct heat to the environment.

[0116] In some embodiments, the position of the hot spot region 430 of at least one of the first chip 100 and the second chip 200 may be determined by thermal simulation, and the positions of the first heat conducting member 130 and the second heat conducting member 230 may be determined based on the position of the hot spot region 430 by thermal simulation, so that the heat conduction channel formed by the thermal communication between the first heat conducting member 130 and the second heat conducting member 230 can conduct the heat of the hot spot region 430 and reduce the heat accumulation in the hot spot region 430. For example, when the first chip 100 is used to perform a computing task, the heat generated by the operation of the devices in the first chip 100 may be relatively large. In a specific example, the position of the hot spot region 430 in the first chip 100 may be determined by thermal simulation, and the position of the first heat conducting member 130 in the first chip 100 may be determined based on the position of the hot spot region 430 by thermal simulation, so that the first heat conducting member 130 conducts the heat of the hot spot region 430 to the second heat conducting member 230 of the second chip 200, and then is dissipated to the environment through the exposed portion 420 via the second heat conducting member 230, thereby effectively reducing the heat accumulation in the first chip 100 and improving the heat dissipation effect.

[0117] In some embodiments, the method for manufacturing the device of the present disclosure may further include:

[0118] Step S210, obtaining the layout of the first chip 100 and the second chip 200;

[0119] Step S220, determining the positions of the hot spots inside at least one of the first chip 100 and the second chip 200 through thermal simulation;

[0120] Step S230, designing a heat conduction channel for transferring the heat of the hot spots out through the exposed part according to the layout of the first chip 100 and the second chip 200 and the positions of the hot spots, so as to determine the preset arrangement of the first heat conducting member 130 in the first chip 100 and the preset arrangement of the second heat conducting member 230 in the second chip 200;

[0121] Step S240, inserting the determined preset arrangements of the first heat conducting member 130 and the second heat conducting member 230 into the layouts of the first chip 100 and the second chip 200 respectively;

[0122] Step S250, determining whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements through thermal simulation. If they meet, execute Step S260 and perform subsequent device manufacturing according to the designed heat conduction channel. Otherwise, return to Step S230 and redesign the heat conduction channel.

[0123] In this way, the corresponding heat conduction channel can be flexibly constructed and the arrangement of the heat conducting member in the corresponding chip can be determined through thermal simulation, and the heat conduction channel can be effectively constructed under different chip stacking structures, improving the heat dissipation effect of the device.

[0124] In a specific example, determining whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements through thermal simulation may, for example, determine whether the chip temperature is less than or equal to the preset temperature.

[0125] In some embodiments, a heat conduction channel can be designed by selecting corresponding metal components in a Process Design Kit (PDK). In this way, without affecting the original chip layout, a heat conduction channel that efficiently transfers the heat from the hot spot area to the environment can be constructed using the metal components in the PDK. In a specific example, corresponding metal components can be pre-selected to form a preset heat conduction channel, and thermal simulation can be used to predict the heat transfer situation inside the chip under the preset heat conduction channel, so as to optimize the positions and interconnections of the metal components according to the heat transfer situation, thereby optimizing the heat conduction path and ensuring that the heat in the hot spot area can be quickly conducted to the environment, improving the heat dissipation efficiency. The metal components can include, for example, at least one of Through Silicon Via, via, metal wiring, thermal pad, bonding pad, Package ball, and Bump. Metal components generally have a high thermal conductivity. By constructing a heat conduction channel with metal components, the heat inside the chip can be quickly conducted to the outside, thereby effectively reducing the temperature of the hot spot area, reducing the thermal resistance of the chip, and improving the heat dissipation capacity. In some embodiments, at least some of the selected metal components can be configured to form the first heat conducting member 130 and / or the second heat conducting member 230 as shown in Figure 3 . Forming corresponding heat conducting members with the metal components inside the chip to construct a heat conduction channel does not require adding additional heat dissipation devices (such as heat sinks, fans, etc.), which enables the chip to maintain a small size and high integration design while ensuring high heat dissipation efficiency, meeting the strict requirements of modern electronic devices for volume and weight.

[0126] In this way, according to the results of the thermal simulation and combined with the device preparation method in some of the above embodiments, a corresponding semiconductor device (such as the semiconductor device 400 shown in Figure 3 ) can be prepared.

[0127] In some embodiments, the hot spot areas 430 of the chip can also be evenly distributed by reasonably arranging the first chip 100 and / or the second chip 200, for example, by avoiding the concentrated distribution of the working devices in the chip in the same area, so that the heat can quickly flow between the layers of the chip, thereby reducing the thermal coupling of the chip to lower the local maximum temperature on the chip, and further making the temperature distribution of the chip more uniform and reducing the possibility of overheating problems.

[0128] In addition, the device preparation method of the present disclosure can also prepare the semiconductor device 400 as described above.

[0129] In the technical solution of the present disclosure, heat in the chip is efficiently conducted to the environment through the heat-conducting member in the exposed portion of the second chip relative to the first chip exposed to the environment, effectively reducing the heat accumulated in the chip, enhancing the heat dissipation capacity, thereby improving the performance stability of the chip and extending the service life of the chip. Moreover, the technical solution of the present disclosure is compatible with the existing three-dimensional integrated manufacturing process, can be adapted to the existing three-dimensional integrated manufacturing process, does not require complex additional manufacturing processes, and can be conveniently mass-produced, having high production efficiency and feasibility.

[0130] The terms "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "high", "low", etc. in the specification and claims, if any, are used for descriptive purposes and not necessarily for describing invariant relative positions. It should be understood that such terms are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature originally described as "above" other features can then be described as "below" other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be correspondingly interpreted at this time.

[0131] In the specification and claims, when it is said that an element is "above", "attached" to, "connected" to, "coupled" to, or "in contact" with another element, etc., the element can be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or there can be one or more intermediate elements. In contrast, when it is said that an element is "directly" above, "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there will be no intermediate element. In the specification and claims, a feature being arranged "adjacent" to another feature can mean that one feature has a part overlapping with the adjacent feature or a part located above or below the adjacent feature.

[0132] As used herein, the term "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplarily is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the technical field, background art, summary of the invention, or detailed description.

[0133] As used herein, the term "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The term "substantially" also allows for differences from perfect or ideal situations due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0134] Additionally, for reference purposes only, terms such as "first", "second", etc. may also be used herein and are thus not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms "first", "second", and other such numerical terms referring to a structure or element do not imply an order or sequence.

[0135] It should also be understood that when the term "comprising / including" is used herein, it specifies the presence of the stated features, integers, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, units, and / or components and / or combinations thereof.

[0136] In the present disclosure, the term "provide" is used broadly to encompass all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0137] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0138] Those skilled in the art should be aware that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed over additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be varied in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all the embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0139] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. The various embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: a first chip, wherein a first heat conducting member is formed in the first chip; a second chip, wherein a second heat conducting member thermally connected to the first heat conducting member is formed in the second chip; The first chip is bonded to a first side of the second chip, the area of ​​the second chip is larger than that of the first chip to form an exposed portion, and the second heat conducting member is partially located in the exposed portion to be partially exposed to the environment.

2. The semiconductor device according to claim 1, wherein: The first heat-conducting member includes a first heat-conducting portion and / or a second heat-conducting portion, The first heat conducting portion is filled in a first through hole opened in the first chip. One or more layers of first wiring extending in a plane perpendicular to the thickness direction are formed in the first chip, and at least a portion of the one or more layers of first wiring is configured to function as the second heat conducting portion.

3. The semiconductor device according to claim 1, wherein: The second heat conductor includes one or more layers of second wiring extending in a plane perpendicular to the thickness direction, and the one or more layers of second wiring are partially located in the exposed portion.

4. The semiconductor device according to claim 3, wherein: The second chip includes a passivation layer, a first side of the passivation layer is used to bond with the first chip, and the one or more second wiring layers are located on a second side of the passivation layer opposite to the first side. The second heat conducting member further includes a third heat conducting portion filled in a second through hole opened in the passivation layer, one end of the third heat conducting portion is thermally connected to the first heat conducting member, and the other end is thermally connected to the one or more layers of second wiring.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A heat dissipation device, wherein the heat dissipation device is located on a portion of the second heat conducting member exposed to the environment and is thermally connected to the second heat conducting member.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a bonding layer, the bonding layer being located between the first chip and the second chip and being configured to bond the first chip and the second chip, The first heat conducting member is thermally connected to the second heat conducting member via a bonding pad in the bonding layer.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a third chip bonded on a second side of the second chip opposite to the first side, The first chip is configured to perform computing tasks, or the second chip is configured to perform signal transmission, or the third chip is configured to store data.

8. A method for preparing a device, characterized in that: The device preparation method comprises: forming a first heat conducting member in the first chip; forming a second heat conducting member in the second chip; and The first chip and the second chip are bonded to thermally connect the first heat conductor to the second heat conductor, wherein the area of ​​the second chip is larger than that of the first chip to form an exposed portion, and the second heat conductor is partially located in the exposed portion to be partially exposed to the environment.

9. The method for preparing the device according to claim 8, characterized in that: Forming a first heat conducting member in the first chip includes: forming a first through hole in the first predetermined layer of the first chip, and filling the first through hole with a heat-conducting material to form a first heat-conducting portion of the first heat-conducting member; and / or One or more layers of first wiring are formed on the second predetermined layer of the first chip to form a second heat conducting portion of the first heat conducting member, wherein the one or more layers of first wiring extend in a plane perpendicular to the thickness direction.

10. The method for preparing the device according to claim 8, characterized in that: Forming a second heat conducting member in the second chip includes: One or more layers of second wiring extending in a plane perpendicular to the thickness direction are formed on the third predetermined layer of the second chip, wherein the one or more layers of second wiring are partially located in the exposed portion when the first chip and the second chip are bonded.

11. The method for preparing the device according to claim 10, characterized in that: The second heat conducting member formed in the second chip further includes: forming a passivation layer on the one or more second wiring layers; forming a patterned anti-etching layer on the passivation layer; Etching the passivation layer under the protection of the anti-etching layer until the one or more layers of the second wiring are at least partially exposed; and The remaining resist layer is removed.

12. The method for preparing the device according to claim 11, characterized in that: Etching the passivation layer under the protection of the anti-etching layer includes forming a second through hole opened in the passivation layer, wherein forming the second heat conducting member in the second chip also includes: The second through hole is filled with a thermally conductive material to form a third thermally conductive portion of the second thermally conductive member, one end of the third thermally conductive portion is used for thermal communication with the first thermally conductive member, and the other end of the third thermally conductive portion is used for thermal communication with the one or more layers of second wiring.

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