Integrated circuit device

Abstract

The integrated circuit device may include: a semiconductor region; an insulating wall extending in the first lateral direction and passing in the vertical direction between a pair of semiconductor regions adjacent to each other in the second lateral direction among the semiconductor regions; a pair of nanosheet stacks overlapping the pair of semiconductor regions in a vertical direction and facing front side surfaces of the pair of semiconductor regions; a pair of source / drain regions; and a backside contact. Each nanosheet stack may include a nanosheet having an end contacting a sidewall of the insulating wall in a second lateral direction. A contact end of the backside contact may be connected to one of the pair of source / drain regions. A contact side wall of the backside contact may contact the insulating wall. The second lateral direction may be perpendicular to the first lateral direction.

Description

[0001] This application is based on and claims the priority of Korean Patent Application No. 10-2023-0187517, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to an integrated circuit (IC) device, and more particularly, to an IC device including a backside contact structure. Background Art

[0003] Due to the development of electronic technology, the miniaturization of IC devices has progressed rapidly. Since highly miniaturized IC devices require not only high operation speed but also high operation accuracy, it may be necessary to provide a wiring structure including conductive lines having a stable and optimized layout structure in a relatively small area and an insulating structure configured to limit and / or prevent an undesired short circuit between a plurality of conductive regions. Summary of the Invention

[0004] The inventive concept provides an integrated circuit (IC) device including a plurality of wiring structures disposed in a reduced area having a shrinking tendency and having a structure capable of improving the electrical characteristics and reliability of the plurality of wiring structures.

[0005] According to an embodiment of the inventive concept, the IC device may include a plurality of semiconductor regions, an insulating wall, a pair of nanosheet stacks, a pair of source / drain regions, and a backside contact. Each of the plurality of semiconductor regions may have a front surface and a back surface facing in a back-to-back direction. The insulating wall may extend in a first lateral direction. The insulating wall may vertically pass between a pair of semiconductor regions adjacent to each other in a second lateral direction among the plurality of semiconductor regions. The second lateral direction may be perpendicular to the first lateral direction. The pair of nanosheet stacks may be stacked on the pair of semiconductor regions in a vertical direction and may face the front surfaces of the pair of semiconductor regions. Each nanosheet stack of the pair of nanosheet stacks may include nanosheets having one end contacting a sidewall of the insulating wall. Each source / drain region of the pair of source / drain regions may include a portion contacting the nanosheets of a corresponding one of the pair of nanosheet stacks. The backside contact may have a contact end and a contact sidewall. The contact end may be connected to a corresponding source / drain region of the pair of source / drain regions. The contact sidewall may contact the sidewall of the insulating wall. The backside contact may extend in a vertical direction from the contact end toward the back surface of each of the pair of semiconductor regions.

[0006] According to an embodiment of the inventive concept, an IC device may include: a plurality of semiconductor regions spaced apart from each other in a first lateral direction and a second lateral direction perpendicular to each other, each of the plurality of semiconductor regions having a front surface and a back surface facing a back-to-back direction; a plurality of nanosheet stacks facing the plurality of semiconductor regions in a vertical direction, each of the plurality of nanosheet stacks including nanosheets; a plurality of source / drain regions, each of the plurality of source / drain regions being between a pair of nanosheet stacks adjacent to each other in the first lateral direction among the plurality of nanosheet stacks, and each of the plurality of source / drain regions contacting nanosheets in adjacent nanosheet stacks among the plurality of nanosheet stacks; an insulating wall passing between a pair of semiconductor regions adjacent to each other in the second lateral direction among the plurality of semiconductor regions in a vertical direction, the insulating wall passing between a pair of nanosheet stacks adjacent to each other in the second lateral direction among the plurality of nanosheet stacks, and the insulating wall passing between a pair of source / drain regions adjacent to each other in the second lateral direction among the plurality of source / drain regions; and a pair of back contacts. Each of the pair of back contacts may include a contact end portion connected to a corresponding one of the pair of source / drain regions and a contact sidewall contacting the insulating wall. Each of the pair of back contacts may extend in a vertical direction from the contact end portion toward the back surface of each of the pair of semiconductor regions.

[0007] According to an embodiment of the inventive concept, an IC device may include: a plurality of semiconductor regions spaced apart from each other in a first lateral direction and a second lateral direction perpendicular to each other, each of the plurality of semiconductor regions having a front surface and a back surface facing a back-to-back direction; a plurality of nanosheet stacks facing the plurality of semiconductor regions in a vertical direction, each of the plurality of nanosheet stacks including nanosheets; a plurality of source / drain regions, each of the plurality of source / drain regions being between a pair of nanosheet stacks adjacent to each other in the first lateral direction among the plurality of nanosheet stacks, and each of the plurality of source / drain regions contacting nanosheets in adjacent nanosheet stacks among the plurality of nanosheet stacks; an insulating wall passing through between a pair of semiconductor regions adjacent to each other in the second lateral direction among the plurality of semiconductor regions in a vertical direction, the insulating wall passing through between a pair of nanosheet stacks adjacent to each other in the second lateral direction among the plurality of nanosheet stacks, and the insulating wall passing through between a pair of source / drain regions adjacent to each other in the second lateral direction among the plurality of source / drain regions; and a plurality of back contact structures contacting the insulating wall, the plurality of back contact structures being arranged in a row in the first lateral direction. Each of the plurality of back contact structures may include a back contact having a contact end connected to a corresponding one of the plurality of source / drain regions and a contact sidewall contacting the insulating wall. The back contact may extend from the contact end toward the back surface in a vertical direction. A width of the back contact in the second lateral direction may gradually increase as the back contact becomes closer to the back surface. A width of the insulating wall in the second lateral direction may gradually decrease as the insulating wall becomes closer to the back surface. In each of the plurality of back contact structures, the contact sidewall of the back contact may extend in a straight line in the first lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a plan layout view of an integrated circuit (IC) device according to an embodiment; Figure 2A is a cross-sectional view taken along line Figure 1 X1-X1' of Figure 2B is a cross-sectional view taken along line Figure 1 Y1-Y1' of Figure 2C is a cross-sectional view taken along line Figure 1 Y2-Y2' of Figure 3 is a magnified cross-sectional view of a region corresponding to a portion “EX1” of Figure 2B ​ Figure 4 is Figure 1 a plan view of some components of the IC device shown in Figure 5 a plan view of an IC device according to an embodiment; Figure 6A and Figure 6B is a cross-sectional view of an IC device according to an embodiment; Figure 6C is Figure 6A and Figure 6B a plan view of some components of the IC device shown in Figure 7 is a cross-sectional view of an IC device according to an embodiment; Figures 8A to 20B is a diagram showing the process sequence of a method for manufacturing an IC device according to an embodiment, where Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A are example cross-sectional structures of portions corresponding to the cross-section taken along line X1-X1' of Figure 1 , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B are example cross-sectional structures of portions corresponding to the cross-section taken along line Y1-Y1' of Figure 1 , Figure 12C , Figure 14B , Figure 15B , Figure 16C , Figure 17C and Figure 18C are example cross-sectional structures of portions corresponding to the cross-section taken along line Y2-Y2' of Figure 1 , and Figure 8C and Figure 9C are plan views of some components according to the process sequence; Figures 21A to 21C is a plan view of the process sequence of a method for manufacturing an IC device according to an embodiment; Figures 22A to 24C is a diagram of the process sequence of a method for manufacturing an IC device according to an embodiment, where Figure 22A , Figure 23A and Figure 24A are cross-sectional views of an example cross-sectional structure of a portion corresponding to a cross-section taken along line X1-X1' of Figure 1 , Figure 22B , Figure 23B and Figure 24B are cross-sectional views of an example cross-sectional structure of a portion corresponding to a cross-section taken along line Y1-Y1' of Figure 1 , and Figure 22C , Figure 23C and Figure 24C are plan views of some components according to the process sequence; and Figures 25A to 26C is a diagram of the process sequence of a method for manufacturing an IC device according to an embodiment, where Figure 25A and Figure 26A are cross-sectional views of an example cross-sectional structure of a portion corresponding to a cross-section taken along line X1-X1' of Figure 1 , Figure 25B and Figure 26B are cross-sectional views of an example cross-sectional structure of a portion corresponding to a cross-section taken along line Y1-Y1' of Figure 1 , and Figure 25C and Figure 26C are plan views of some components according to the process sequence. DETAILED DESCRIPTION

[0009] As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0010] When the terms "about" or "substantially" are used in connection with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operating tolerances centered around the stated numerical value (e.g., ±10%). In addition, when the words "generally" and "substantially" are used in connection with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the tolerance of the shape is within the disclosed range. Further, whether the numerical value or shape is modified with "about" or "substantially", it is understood that these numerical values and shapes should be interpreted to include manufacturing or operating tolerances centered around the stated numerical value or shape (e.g., ±10%).

[0011] The concept of "substantially the same" for elements can indicate that the elements can be exactly the same, and can also indicate that the elements can be determined to be the same considering errors or deviations that occur during the process.

[0012] In the following, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and their repeated description is omitted.

[0013] Figure 1 is a plan layout diagram of an integrated circuit (IC) device 100 according to an embodiment. Figure 2A is a cross-sectional view taken along the line Figure 1 X1-X1'. Figure 2B is a cross-sectional view taken along the line Figure 1 Y1-Y1'. Figure 2C is a cross-sectional view taken along the line Figure 1 Y2-Y2'. Figure 3 is Figure 2B an enlarged cross-sectional view of a portion “EX1” of Figure 4 is Figure 1 a plan view of some components of the IC device 100 shown in Figures 1 to 4 Describing the IC device 100 including a field effect transistor (FET) having a gate-all-around structure including an active region of a nanowire or nanosheet type and a gate surrounding the active region with reference to

[0014] With reference to Figures 1 to 3 , the IC device 100 may include a plurality of semiconductor regions F1, the plurality of semiconductor regions F1 being separated from each other and arranged in rows in each of a first lateral direction (X direction) and a second lateral direction (Y direction) perpendicular to each other. In a view from the plane (X-Y plane), the plurality of semiconductor regions F1 may be arranged in a matrix form. Each of the plurality of semiconductor regions F1 may have a front surface 102F and a back surface FB facing in a back-to-back direction. In Figure 2A and Figure 2C , the front surface 102F of each of the plurality of semiconductor regions F1 may be a surface facing the positive direction of the vertical direction (Z direction), and the back surface FB of each of the plurality of semiconductor regions F1 may be a surface facing the negative direction of the vertical direction (Z direction). Each of the plurality of semiconductor regions F1 may include silicon (Si). The semiconductor region F1 may also be referred to as a semiconductor structure.

[0015] A plurality of nanosheet stacks NSS may be on the plurality of semiconductor regions F1. Each of the plurality of nanosheet stacks NSS may be stacked on the semiconductor region F1 in the vertical direction (Z direction) and face the semiconductor region F1, and include at least one nanosheet. As used herein, the term “nanosheet” refers to a conductive structure having a cross-section substantially perpendicular to the current flow direction. A nanosheet may be interpreted to include a nanowire.

[0016] Although each of the plurality of nanosheet stacks NSS is shown in this embodiment as including a first nanosheet N1, a second nanosheet N2, a third nanosheet N3, and a fourth nanosheet N4, the number of nanosheets included in each of the plurality of nanosheet stacks NSS can be variably changed. For example, each of the plurality of nanosheet stacks NSS can include at least one nanosheet or at least two nanosheets, and the number of nanosheets included in the nanosheet stack NSS is not specifically limited. Each of the first to fourth nanosheets N1, N2, N3, and N4 can have a channel region. In an embodiment, each of the first to fourth nanosheets N1, N2, N3, and N4 included in the nanosheet stack NSS can include a silicon (Si) layer (or, film), a silicon germanium (SiGe) film, or a combination thereof.

[0017] In an embodiment, each of the first to fourth nanosheets N1, N2, N3, and N4 can have a thickness selected in the range of about 4 nanometers (nm) to about 6 nm in the vertical direction. In an embodiment, the first to fourth nanosheets N1, N2, N3, and N4 can have substantially the same thickness. The first to fourth nanosheets N1, N2, N3, N4 can include the same material.

[0018] The IC device 100 can include a plurality of source / drain regions 130. The plurality of source / drain regions 130 can be respectively on both sides of the plurality of nanosheet stacks NSS in a first lateral direction (X direction), and are respectively adjacent to the plurality of nanosheet stacks NSS.

[0019] Each of the plurality of source / drain regions 130 can be between a pair of nanosheet stacks NSS that are adjacent to each other in the first lateral direction (X direction) among the plurality of nanosheet stacks NSS. Each of the plurality of source / drain regions 130 can be in contact with each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 included in the adjacent nanosheet stack NSS.

[0020] The IC device 100 can include a plurality of insulating walls VW, which are adjacent to the plurality of semiconductor regions F1, the plurality of nanosheet stacks NSS, and the plurality of source / drain regions 130 and extend in the first lateral direction (X direction). The plurality of insulating walls VW can be separated from each other in a second lateral direction (Y direction) and extend parallel to each other in the first lateral direction (X direction). In an embodiment, each of the plurality of insulating walls VW can include a silicon nitride layer, a silicon carbonitride (SiCN) film, a silicon oxycarbonitride (SiOCN) film, a silicon oxide layer, or a combination thereof, but is not limited thereto.

[0021] Each of the plurality of insulating walls VW can pass in the vertical direction (Z direction) through the following structures: between a pair of semiconductor regions F1 among the plurality of semiconductor regions F1 that are adjacent to each other in the second lateral direction (Y direction); between a pair of nanosheet stacks NSS among the plurality of nanosheet stacks NSS that are adjacent to each other in the second lateral direction (Y direction); and between a pair of source / drain regions 130 among the plurality of source / drain regions 130 that are adjacent to each other in the second lateral direction (Y direction).

[0022] A pair of semiconductor regions F1 adjacent to each other in the second lateral direction (Y direction) can each contact an insulating wall VW, and an insulating wall VW is disposed between the pair of semiconductor regions F1. The first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 included in each of a pair of nanosheet stacks NSS adjacent to each other in the second lateral direction (Y direction) can contact an insulating wall VW, and an insulating wall VW is disposed between the pair of nanosheet stacks NSS. The first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 can each contact an insulating wall VW at one end in the second lateral direction (Y direction). A pair of source / drain regions 130 adjacent to each other in the second lateral direction (Y direction) can each contact an insulating wall VW, and an insulating wall VW is disposed between the pair of source / drain regions 130.

[0023] The side wall (or referred to as the "first side wall") of each of the two side walls of each of the plurality of semiconductor regions F1 in the second lateral direction (Y direction) that faces away from the side wall facing the insulating wall VW can be covered by the device isolation film 112. Each of the plurality of device isolation films 112 can include a silicon oxide layer, but is not limited thereto.

[0024] The front surface 102F of the semiconductor region F1 can be covered by the bottom semiconductor layer BS between the semiconductor region F1 and the nanosheet stack NSS. The bottom semiconductor layer BS can include silicon (Si). In an embodiment, the thickness of the bottom semiconductor layer BS in the vertical direction (Z direction) can be less than the thickness of each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 included in the nanosheet stack NSS.

[0025] On the semiconductor region F1, a plurality of gate lines 160 can be separated from each other in the first lateral direction (X direction) and extend in the second lateral direction (Y direction). Each of the plurality of gate lines 160 can surround the first to fourth nanosheets N1, N2, N3, and N4 while covering the plurality of nanosheet stacks NSS on the bottom semiconductor layer BS.

[0026] Each of the plurality of source / drain regions 130 may be adjacent to at least one gate line 160 selected from the plurality of gate lines 160. The plurality of source / drain regions 130 arranged in rows in the first lateral direction (X direction) may each be between two adjacent gate lines 160 among the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface in contact with the first through fourth nanosheets N1, N2, N3, and N4 included in the nanosheet stack NSS adjacent to the source / drain region 130.

[0027] The plurality of source / drain regions 130 may each include an epitaxially grown semiconductor layer. In an embodiment, the plurality of source / drain regions 130 may include an epitaxially grown Si layer, an epitaxially grown SiC layer, or a plurality of epitaxially grown SiGe layers. When the source / drain region 130 is included in an NMOS transistor, the source / drain region 130 may include a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). When the source / drain region 130 is included in a PMOS transistor, the source / drain region 130 may include a SiGe layer doped with a p-type dopant. The p-type dopant may be selected from boron (B) and gallium (Ga).

[0028] As Figure 2A and Figure 2C shown in, each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the top surface of the nanosheet stack NSS and extend in the second lateral direction (Y direction). The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M and be respectively in the spaces between the first through fourth nanosheets N1, N2, N3, and N4. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0029] The plurality of gate lines 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may include titanium aluminum carbide (TiAlC). However, the materials included in the plurality of gate lines 160 are not limited to the above examples.

[0030] The gate dielectric film 152 can be between the nanosheet stack NSS and the gate line 160. The gate dielectric film 152 can have a stacked structure of an interfacial dielectric film and a high-k dielectric film. The interfacial dielectric film can include a low-k dielectric material film having a dielectric constant of about 9 or less (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof). In an embodiment, the interfacial dielectric film can be omitted. The high-k dielectric film can include a material having a dielectric constant higher than that of a silicon oxide film. For example, the high-k dielectric film can have a dielectric constant of about 10 to about 25. The high-k dielectric film can include hafnium oxide, but is not limited thereto.

[0031] As Figure 2A shown, two sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 can be separated from the source / drain regions 130, and the gate dielectric film 152 is disposed between the plurality of sub-gate portions 160S and the source / drain regions 130. The gate dielectric film 152 can be between each of the sub-gate portions 160S included in the gate line 160 and each of the first to fourth nanosheets N1, N2, N3, and N4, between the sub-gate portions 160S included in the gate line 160 and the source / drain regions 130, and between the lowermost sub-gate portion in the sub-gate portions 160S and the bottom semiconductor layer BS. The gate dielectric film 152 can include a portion in contact with the bottom semiconductor layer BS.

[0032] The plurality of gate lines 160, the plurality of nanosheet stacks NSS, and the plurality of source / drain regions 130 can form a plurality of nanosheet transistors. The plurality of nanosheet transistors can include NMOS transistors, PMOS transistors, or a combination thereof.

[0033] As Figure 2A shown, two sidewalls of the gate line 160 can be covered by a plurality of insulating spacers 118. Each of the plurality of insulating spacers 118 can cover the sidewalls of the main gate portion 160M on the top surface of the nanosheet stack NSS. Each of the plurality of insulating spacers 118 can be separated from the gate line 160, and the gate dielectric film 152 is disposed between the plurality of insulating spacers 118 and the gate line 160. Each of the plurality of insulating spacers 118 can include silicon nitride, silicon oxide, silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), SiOF, SiOCH, or a combination thereof. Each of the plurality of insulating spacers 118 can include a single-layer film or a multi-layer film. The single-layer film includes a material film selected from the above materials, and the multi-layer film includes a plurality of material films selected from the above materials.

[0034] As Figure 2A and Figure 2CAs shown, the top surfaces of each of the gate lines 160, the gate dielectric film 152, and the insulating spacers 118 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may include a silicon nitride layer.

[0035] The plurality of source / drain regions 130, the device isolation film 112, and the plurality of insulating spacers 118 may be covered by an insulating liner 142. The inter-gate dielectric film 144 may be on the insulating liner 142. The inter-gate dielectric film 144 may be between a pair of gate lines 160 adjacent to each other in a first lateral direction (X direction) and between a pair of source / drain regions 130 adjacent to each other. In an embodiment, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate dielectric film 144 may include a silicon oxide film, but is not limited thereto.

[0036] As Figure 2A and Figure 2B shown, the plurality of front-side source / drain contact members CA may be on the plurality of source / drain regions 130 between a pair of adjacent gate lines among the plurality of gate lines 160. Each of the plurality of front-side source / drain contact members CA may be electrically connected to at least one source / drain region 130 selected from the plurality of source / drain regions 130. For example, one front-side source / drain contact member CA may be connected to one source / drain region 130 or a plurality of source / drain regions 130 adjacent to each other.

[0037] A metal silicide film 172 may be between the source / drain region 130 and the front-side source / drain contact member CA. The metal silicide film 172 may be in contact with the source / drain region 130. The front-side source / drain contact member CA may pass through the inter-gate dielectric film 144 and the insulating liner 142 in a vertical direction (Z direction), and contact the metal silicide film 172 and the front-side source / drain contact member CA. The front-side source / drain contact member CA may be connected to the source / drain region 130 through the metal silicide film 172. The front-side source / drain contact member CA may pass through a part of the source / drain region 130 in a vertical direction (Z direction). The insulating liner 142 and the inter-gate dielectric film 144 may surround the sidewalls of the front-side source / drain contact member CA.

[0038] In an embodiment, the metal silicide film 172 may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide. In an embodiment, the front-side source / drain contact CA may include only a metal plug containing a single metal. In other embodiments, the front-side source / drain contact CA may include a metal plug and a conduction barrier film surrounding the metal plug. The metal plug may include a metal selected from molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), combinations thereof, or alloys thereof, but is not limited thereto. The conduction barrier film may include a metal or a conductive metal nitride. For example, the conduction barrier film may include titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), or combinations thereof, but is not limited thereto.

[0039] As Figure 2A , Figure 2B and Figure 3 shown, the IC device 100 may include a plurality of back-side contact structures DBCS. Each of the plurality of back-side contact structures DBCS may include a back-side contact DBC and a back-side insulating spacer BIS. The back-side insulating spacer BIS may be between the back-side contact DBC and the semiconductor region F1 closest to the back-side contact DBC. The back-side contact DBC may be separated from the semiconductor region F1 in a first lateral direction (X direction), and the back-side insulating spacer BIS is disposed between the back-side contact DBC and the semiconductor region F1.

[0040] As Figure 3 shown, the back-side contact DBC of each of the plurality of back-side contact structures DBCS may have a contact end CE and a contact sidewall CS, the contact end CE being connected to one of the source / drain regions 130 selected from the plurality of source / drain regions 130, and the contact sidewall CS facing the insulating wall VW. Each of the plurality of back-side contact structures DBCS may extend in a vertical direction (Z direction) from the contact end CE toward the back-side surface FB of the semiconductor region F1.

[0041] As Figure 4 shown, the plurality of back-side contact structures DBCS may include a plurality of groups of back-side contact structures DBCS arranged in rows in a first lateral direction (X direction). In each of the plurality of back-side contact structures DBCS, the contact sidewall CS of the back-side contact DBC and the sidewall SX facing away from the contact sidewall CS may each extend in a straight line in the first lateral direction (X direction). As Figure 2BAs shown in [FIGURE], in the back contact DBC included in each of the plurality of back contact structures DBCS, the contact sidewall CS facing the insulating wall VW adjacent to the back contact DBC may contact the adjacent insulating wall VW.

[0042] As Figure 2B shown in [FIGURE], the insulating wall VW may have a shape in which the width in the second lateral direction (Y direction) gradually decreases toward the back surface FB of the semiconductor region F1. The two sidewalls WS1 and WS2 of the insulating wall VW that contact the back contact DBC in the second lateral direction (Y direction) may each include an inclined surface inclined with respect to the vertical direction (Z direction). The back contact DBC may have a shape in which the width in the second lateral direction (Y direction) gradually increases toward the back surface FB of the semiconductor region F1. The contact sidewall CS of the back contact DBC that contacts the insulating wall VW may include an inclined surface corresponding to the inclined shape of the sidewalls WS1 and WS2 of the insulating wall VW.

[0043] The metal silicide film 190 may be between the source / drain region 130 and the back contact structure DBCS. The metal silicide film 190 may contact the source / drain region 130 and the back contact structure DBCS. As Figure 2A shown in [FIGURE], the back contact structure DBCS may contact the metal silicide film 190 by passing through a pair of semiconductor regions F1 adjacent to each other in the first lateral direction (X direction) among the plurality of semiconductor regions F1 in the vertical direction (Z direction).

[0044] The back contact DBC may be connected to the source / drain region 130 through the metal silicide film 190. The constituent material of the metal silicide film 190 is the same as that of the above-mentioned metal silicide film 172. In an embodiment, the back contact DBC may include only a metal plug containing a single metal. In other embodiments, the back contact DBC may include a metal plug and a conductive barrier film surrounding the metal plug. The metal plug may include molybdenum (Mo), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), or a combination thereof or an alloy thereof, but is not limited thereto. The conductive barrier film may include a metal or a conductive metal nitride. For example, the conductive barrier film may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0045] Each of the plurality of back contacts DBC may be connected to the surface of the selected source / drain region 130 among the plurality of source / drain regions 130 that faces away from the surface facing the gate dielectric film 144.

[0046] AsFigure 2B As shown, the device isolation film 112 may cover the sidewall of the backside contact DBC that faces away from the contact sidewall CS of the contact insulating wall VW (refer to Figure 4 SX in). The device isolation film 112 may contact the sidewall SX that faces away from the backside contact DBC. The device isolation lowermost surface 112B of the device isolation film 112 closest to the backside surface FB of the semiconductor region F1 and the wall lowermost surface VWB of the insulating wall VW closest to the backside surface FB of the semiconductor region F1 may extend in the same plane.

[0047] As Figure 1 , Figure 2B and Figure 2C shown, the IC device 100 may include a gate cut insulating pattern GC that defines the length of a plurality of gate lines 160 in the second lateral direction (Y direction). The gate cut insulating pattern GC may face one end of a corresponding one of the plurality of gate lines 160 in the second lateral direction (Y direction) and extend in the first lateral direction (X direction). The gate cut insulating pattern GC may pass through a portion of the device isolation film 112 in the vertical direction (Z direction). The lowermost surface GCB of the gate cut insulating pattern GC closest to the backside surface FB of the semiconductor region F1 may contact the device isolation film 112. The gate cut insulating pattern GC may include a silicon nitride layer, a silicon carbonitride film (SiCN film), a silicon oxycarbonitride film (SiOCN film), a silicon oxide layer, or a combination thereof, but is not limited thereto.

[0048] As Figure 2B and Figure 2C shown, the vertical level LV11 of the lowermost surface VWB of the insulating wall VW closest to the backside surface FB of the semiconductor region F1 may be closer to the backside surface FB of the semiconductor region F1 than the vertical level LV12 of the lowermost surface GCB of the gate cut insulating pattern GC closest to the backside surface FB of the semiconductor region F1. The vertical level LVT1 of the uppermost surface VWT of the insulating wall VW farthest from the lowermost surface VWB may be substantially the same as the vertical level LVT1 of the uppermost surface GCT of the gate cut insulating pattern GC. As used herein, the term "vertical level" refers to the relative distance in the vertical direction (Z direction). For example, the term "vertical level" as used herein may refer to the distance in the vertical direction (Z direction) from the backside surface FB of each of the plurality of semiconductor regions F1. As Figure 2B and Figure 3As shown, the lowermost surface VWB of the backside surface FB of the insulating wall VW closest to the semiconductor region F1 and the lowermost surface DBB of the backside contact DBC closest to the backside surface FB of the semiconductor region F1 may extend in the same plane (X-Y plane) that extends at a vertical height LV11. As used herein, the lowermost surface VWB of the insulating wall VW may be referred to as the wall lowermost surface, and the lowermost surface DBB of the backside contact DBC may be referred to as the contact lowermost surface. For example, the wall lowermost surface VWB of the insulating wall VW may be closer to the backside surface FB of the semiconductor region F1 than the upper surface of the insulating wall VW.

[0049] As Figures 2A to 2C As shown, the top surface of each of the front-side source / drain contact CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144 may be covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an upper insulating film 184 sequentially stacked on each of the plurality of front-side source / drain contacts CA, the plurality of capping insulating patterns 168, and the inter-gate dielectric film 144. The etch stop film 182 may include silicon carbide (SiC), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiOC), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), aluminum carbonitride (AlOC), or a combination thereof. The upper insulating film 184 may include an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the upper insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a silicon oxynitride (SiON) film, a silicon nitride (SiN) film, a silicon oxynitride (SiOC) film, a SiCOH film, or a combination thereof, but is not limited thereto.

[0050] The source / drain via contact VA may be on the front-side source / drain contact CA. Each of the plurality of source / drain via contacts VA may pass through the upper insulating structure 180 and contact the front-side source / drain contact CA. The source / drain region 130 among the plurality of source / drain regions 130 connected to the front-side source / drain contact CA may be electrically connected to the source / drain via contact VA through the metal silicide film 172 and the front-side source / drain contact CA. Each of the plurality of source / drain via contacts VA may include molybdenum (Mo) or tungsten (W), but is not limited thereto.

[0051] As Figure 2CAs shown, the gate contact CB may be on the gate line 160. The gate contact CB may pass through the upper insulating structure 180 and the cover insulating pattern 168 in the vertical direction (Z direction) and be connected to the gate line 160. The bottom surface of the gate contact CB may contact the top surface of the gate line 160. The gate contact CB may include a contact plug, and the contact plug includes molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), or a combination thereof or an alloy thereof, but the constituent material of the contact plug is not limited thereto. In an embodiment, the gate contact CB may further include a conduction blocking pattern surrounding a part of the contact plug. The conduction blocking pattern included in the gate contact CB may include a metal or a metal nitride. For example, the conduction blocking pattern may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0052] The top surface of the upper insulating structure 180 may be covered by the front-side interlayer insulating film 186. The constituent material of the front-side interlayer insulating film 186 is substantially the same as that of the upper insulating film 184 described above. A plurality of upper wiring layers M1 may pass through the front-side interlayer insulating film 186. The plurality of upper wiring layers M1 may include an upper wiring layer M1 connected to the source / drain via contact VA and an upper wiring layer M1 connected to the gate contact CB. The plurality of upper wiring layers M1 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), or a combination thereof or an alloy thereof, but is not limited thereto.

[0053] As Figures 2A to 2C As shown, the IC device 100 may include a back-side insulating film 194 covering the back-side surface FB of each of the plurality of semiconductor regions F1 and a plurality of back-side wiring structures MPR passing through the back-side insulating film 194 in the vertical direction. The plurality of back-side wiring structures MPR may include a back-side wiring structure MPR connected to the back-side contact DBC. In an embodiment, the constituent material of the back-side insulating film 194 is substantially the same as that of the upper insulating film 184 described above. The constituent material of each of the plurality of back-side wiring structures MPR is substantially the same as that of each of the plurality of upper wiring layers M1 described above.

[0054] Referring to Figures 1 to 4The described IC device 100 may include a plurality of backside contact structures DBCS, each of the plurality of backside contact structures DBCS including a backside contact DBC that is connected to the source / drain region 130 from the backside adjacent to the backside surface FB of each of the plurality of semiconductor regions F1. According to the IC device 100, the size deviation of the plurality of backside contact structures DBCS can be minimized, thereby reducing the deviation of the electrical characteristics between the plurality of backside contact structures DBCS. In addition, since the backside contact DBC included in each of the plurality of backside contact structures DBCS ensures a sufficient width in the lateral direction (X direction and / or Y direction), the contact resistance of each of the plurality of backside contacts DBC included in the plurality of backside contact structures DBCS can be reduced. In addition, a sufficient insulation distance can be ensured between two adjacent backside contacts DBC among the plurality of backside contacts DBC, and thus, an undesired short circuit between the plurality of backside contacts DBC can be restricted and / or prevented. Therefore, even when the IC device 100 has a reduced area in a shrinking trend, the IC device 100 can provide a wiring structure having a stable and optimized structure, and thus, the integration degree and reliability of the IC device 100 can be improved.

[0055] Figure 5 is a plan view of an IC device 200 according to an embodiment. Figure 5 The planar configuration of some components of the IC device 200 is shown. In Figure 5 the same reference numerals are used to denote the same elements as in Figures 1 to 4 and their detailed descriptions are omitted.

[0056] Referring to Figure 5 IC device 200 may have a configuration substantially the same as that of the IC device 100 described with reference to Figures 1 to 4 However, the IC device 200 may include a plurality of backside contact structures DBCS2. The plurality of backside contact structures DBCS2 may each have a configuration substantially the same as that of the plurality of backside contact structures DBCS described with reference to Figures 1 to 4 Similar to the backside contact structure DBCS described with reference to Figures 1 to 4 each of the plurality of backside contact structures DBCS2 may include a backside contact and a backside insulation spacer between the backside contact and the semiconductor region F1 closest to the backside contact. In the backside contact structure DBCS2, the backside contact and the backside insulation spacer may each have a configuration substantially the same as that of the backside contact DBC and the backside insulation spacer BIS described with reference to Figures 2A to 2C In each of the plurality of backside contact structures DBCS2, the backside contact may have a contact sidewall CS2 facing the insulating wall VW.

[0057] Multiple dorsal contact structures DBCS2 may include multiple groups of dorsal contact structures DBCS2 arranged in rows in a first lateral direction (X direction). In each of the multiple dorsal contact structures DBCS2, the contact sidewall CS2 of the dorsal contact that contacts the insulating wall VW may extend in a straight line in the first lateral direction (X direction). In each of the multiple dorsal contact structures DBCS2, at least a portion of the sidewall SR2 facing away from the contact sidewall CS2 may extend in a curved shape in the first lateral direction (X direction).

[0058] Figure 6A , Figure 6B and Figure 6C are diagrams of an IC device 300 according to an embodiment. Figure 6A is a cross-sectional view of a portion of the IC device 300 corresponding to a cross-section taken along line X1-X1' along Figure 1 . Figure 6B is a cross-sectional view of a portion of the IC device 300 corresponding to a cross-section taken along line Y2-Y2' along Figure 1 . Figure 6C is a plan view of some components of the IC device 300. In Figure 6A , Figure 6B and Figure 6C , the same reference numerals are used to denote the same elements as in Figures 1 to 4 , and their detailed descriptions are omitted.

[0059] Referring to Figure 6A , Figure 6B and Figure 6C , the IC device 300 may have a construction substantially the same as that of the IC device 100 described with reference to Figures 1 to 4 . However, the IC device 300 may further include multiple alternative semiconductor regions 303 between the multiple semiconductor regions F1 and the multiple nanosheet stacks NSS. Each of the multiple alternative semiconductor regions 303 may contact a corresponding one of the multiple semiconductor regions F1. Each of the multiple alternative semiconductor regions 303 may include silicon (Si).

[0060] Each of the multiple dorsal contact structures DBCS may be between a pair of semiconductor regions F1 adjacent to each other in a first lateral direction (X direction) and between a pair of alternative semiconductor regions 303 adjacent to each other in a first lateral direction (X direction). Each of the multiple dorsal contact structures DBCS may face a pair of alternative semiconductor regions 303 adjacent to each other in a first lateral direction (X direction). Each of the multiple dorsal contact structures DBCS may contact a pair of alternative semiconductor regions 303 adjacent to each other in a first lateral direction (X direction).

[0061] As Figure 6AAs shown, a dorsal contact DBC included in each of a plurality of dorsal contact structures DBCS may be separated from each of a semiconductor region F1 and an alternative semiconductor region 303 adjacent to each other in a first lateral direction (X direction), and a dorsal insulating spacer BIS is disposed between the dorsal contact DBC and the semiconductor region F1 and the alternative semiconductor region 303.

[0062] As Figure 6B shown, a vertical height LV31 of a lowermost surface VWB of a dorsal surface FB of an insulating wall VW closest to the semiconductor region F1 may be closer to the dorsal surface FB of the semiconductor region F1 than a vertical height LV32 of a lowermost surface GCB of a gate cut insulating pattern GC closest to the dorsal surface FB of the semiconductor region F1. A vertical height LV33 of a lowermost surface 303B of each of the plurality of alternative semiconductor regions 303 may be closer to the dorsal surface FB of the semiconductor region F1 than the vertical height LV32 of the lowermost surface GCB of the gate cut insulating pattern GC, and farther from the dorsal surface FB of the semiconductor region F1 than the vertical height LV31 of the lowermost surface VWB of the insulating wall VW.

[0063] As Figure 6C shown, the plurality of dorsal contact structures DBCS may include a plurality of groups of dorsal contact structures DBCS arranged in rows in a first lateral direction (X direction), and one alternative semiconductor region 303 may be between a pair of adjacent groups among the plurality of groups of dorsal contact structures DBCS. A plurality of dorsal contact structures DBCS and a plurality of alternative semiconductor regions 303 arranged in a straight line in the first lateral direction (X direction) among the plurality of dorsal contact structures DBCS and the plurality of alternative semiconductor regions 303 may be in contact with an adjacent insulating wall VW.

[0064] Figure 7 is a cross-sectional view of an IC device 400 according to an embodiment. Figure 7 is an enlarged cross-sectional view of a region in the IC device 400 corresponding to a portion “EX1” of Figure 2B . In Figure 7 the same reference numerals are used to denote the same elements as in Figures 1 to 4 and their detailed description is omitted.

[0065] Referring to Figure 7 , the IC device 400 may have substantially the same configuration as the IC device 100 described with reference to Figures 1 to 4 . However, the IC device 400 may include a plurality of dorsal contacts DBC4. Among the plurality of dorsal contacts DBC4, the one closest to the dorsal surface of the semiconductor region F1 (refer to Figure 2CThe vertical height LV42 of the lowermost surface DBB4 of the FB in ) can be farther from the backside surface FB of the semiconductor region F1 than the vertical height LV11 of the lowermost surface VWB of the backside surface FB of the insulating wall VW closest to the semiconductor region F1. As used herein, the lowermost surface DBB4 of each of the plurality of backside contacts DBC4 can be referred to as the contact lowermost surface, and the lowermost surface VWB of the insulating wall VW can be referred to as the wall lowermost surface. The lowermost surface DBB4 of each of the plurality of backside contacts DBC4 can be covered by a gap-fill insulating film 492. The gap-fill insulating film 492 can be between the backside contacts DBC4 and the backside insulating film 194 in the vertical direction (Z direction). The constituent material of the gap-fill insulating film 492 is substantially the same as the constituent material of the backside insulating film 194 already described with reference to Figures 2A to 2C The description of the backside insulating film 194 is substantially the same.

[0066] The backside wiring structure MPR4 can pass through the gap-fill insulating film 492 in the vertical direction (Z direction) and contact the backside contacts DBC4. The details of the backside contacts DBC4 and the backside wiring structure MPR4 are substantially the same as the details of the backside contacts DBC and the backside wiring structure MPR described above with reference to Figures 1 to 4 The description is substantially the same.

[0067] Similar to the IC device 100 described with reference to Figures 1 to 4 The description, with reference to Figures 5 to 7The described IC devices 200, 300, and 400 may include a plurality of backside contact structures DBCS or DBCS2, each of the plurality of backside contact structures DBCS or DBCS2 including a backside contact DBC or DBC4 that is backside-connected to a source / drain region 130 from a backside adjacent to a backside surface FB of each of the plurality of semiconductor regions F1. According to the IC devices 200, 300, and 400, it is possible to minimize the size deviation of the plurality of backside contact structures DBCS or DBCS2, thereby reducing the deviation of electrical characteristics between the plurality of backside contact structures DBCS or DBCS2. In addition, since the backside contact DBC or DBC4 included in each backside contact structure among the plurality of backside contact structures DBCS or DBCS2 ensures a sufficient width in the lateral direction (X direction and / or Y direction), the contact resistance of each backside contact among the plurality of backside contacts DBC or DBC4 included in the plurality of backside contact structures DBCS or DBCS2 can be reduced. In addition, a sufficient insulation distance can be ensured between two adjacent backside contacts among the plurality of backside contacts DBC and DBC4, and thus, an undesired short circuit between the plurality of backside contacts DBC and DBC4 can be restricted and / or prevented. Therefore, even when each of the IC devices 200, 300, and 400 has a reduced area in a shrinking trend, each of the IC devices 200, 300, and 400 can provide a wiring structure having a stable and optimized structure, and thus, the integration degree and reliability of each of the IC devices 200, 300, and 400 can be improved.

[0068] An example of a method of manufacturing an IC device according to an embodiment will now be described in detail.

[0069] Figures 8A to 20B is a diagram showing a process sequence of a method of manufacturing an IC device according to an embodiment. More specifically, Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A and Figure 20A are examples of cross-sectional structures of portions corresponding to a cross-section taken along line X1-X1' of Figure 1 . Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 16B 、 Figure 17B 、Figure 18B , Figure 19B and Figure 20B are cross-sectional views of an exemplary cross-sectional structure of a part corresponding to a cross-section taken along line Y1 - Y1' of Figure 1 . Figure 12C , Figure 14B , Figure 15B , Figure 16C , Figure 17C and Figure 18C are cross-sectional views of an exemplary cross-sectional structure of a part corresponding to a cross-section taken along line Y2 - Y2' of Figure 1 . Figure 8C and Figure 9C are plan views of some components in process sequence. Refer to Figures 8A to 20B for an example of a method of manufacturing the IC device 100 described with reference to Figures 1 to 4 . In Figures 8A to 20B , the same reference numerals are used to denote the same elements as in Figures 1 to 4 , and their detailed descriptions are omitted.

[0070] Refer to Figure 8A , Figure 8B and Figure 8C . A substrate 102 having a front surface 102F and a back surface 102B facing each other can be provided, and a partial area can be etched from the front surface 102F of the substrate 102 by using a lithography process. Thus, a plurality of placeholder spaces PHS can be formed in the substrate 102. The plurality of placeholder spaces PHS can be at the same positions as the positions of a plurality of backside contact structures (refer to Figure 1 for DBCS) to be finally formed.

[0071] As shown in Figure 8C , the planar shape of each of the plurality of placeholder spaces PHS can have a rectangular shape with each side extending in a straight line. In the planar shape of each of the plurality of placeholder spaces PHS, the size of the side HX in the first lateral direction (X direction) can be substantially equal to the size of each of the plurality of backside contact structures (refer to Figure 1 for DBCS) in the first lateral direction (X direction) to be finally formed. In the planar shape of each of the plurality of placeholder spaces PHS, the size of the side HY in the second lateral direction (Y direction) can be greater than the size of each of the plurality of backside contact structures (refer to Figure 1 for DBCS) in the second lateral direction (Y direction) to be finally formed.

[0072] Refer to Figure 9A , Figure 9B and Figure 9C . In Figure 8A , Figure 8B andFigure 8C In the resulting structure, a plurality of placeholder PHs can be formed to fill a plurality of placeholder spaces PHSs. Each of the plurality of placeholder PHs can be formed to have a planarized top surface at the same vertical height of the front surface 102F of the substrate 102.

[0073] In an embodiment, each of the plurality of placeholder PHs can include a doped SiGe film, an undoped SiGe film, a polysilicon film, a silicon nitride layer, a silicon carbonitride film (SiCN film), a silicon oxycarbonitride film (SiOCN film), a silicon oxide layer, or a combination thereof, but is not limited thereto.

[0074] Referring to Figure 10A and Figure 10B In Figure 9A , Figure 9B and Figure 9C In the resulting structure, a bottom semiconductor layer BS can be formed on the plurality of placeholder PHs and the front surface 102F of the substrate 102, and a stacked structure in which a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS can be alternately stacked one by one can be formed on the bottom semiconductor layer BS.

[0075] In the stacked structure, the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS can include semiconductor materials having different etching selectivities from each other. In an embodiment, each of the plurality of nanosheet semiconductor layers NS can include a silicon (Si) layer, and each of the plurality of sacrificial semiconductor layers 104 can include a silicon germanium (SiGe) film. The SiGe film included in the sacrificial semiconductor layer 104 can have a Ge content selected in the range of about 5 atomic percent (at%) to about 50 at% (for example, about 10 at% to about 40 at%).

[0076] Referring to Figure 11A and Figure 11B A mask pattern MP1 having an opening exposing the top surface of the stacked structure can be formed on the resulting structure of Figure 10A and Figure 10B The mask pattern MP1 can include a stacked structure of a silicon oxide layer pattern and a silicon nitride layer pattern. The mask pattern MP1 can include portions extending parallel to each other in a first lateral direction (X direction) on the substrate 102.

[0077] A portion of each of the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, the bottom semiconductor layer BS, the plurality of placeholder PHs, and the substrate 102 can be etched by using the mask pattern MP1 as an etching mask. Thus, a plurality of wall spaces WS for forming insulating walls (refer to VW in Figures 1 to 4 ) and a device isolation film (refer to Figure 2B andFigure 2C a plurality of device isolation spaces IS of 112) therein. By partially removing the substrate 102, a plurality of semiconductor regions F1 protruding upward from the substrate 102 in the vertical direction (Z direction) can be formed, and corresponding portions of the plurality of wall spaces WS and the plurality of device isolation spaces IS can be defined by the plurality of semiconductor regions F1.

[0078] As Figure 11B shown, the depth of each of the plurality of device isolation spaces IS can be greater than the depth of each of the plurality of wall spaces WS. As a result, the vertical height LV1 of the substrate 102 exposed at the bottom of each of the plurality of device isolation spaces IS can be closer to the back surface 102B of the substrate 102 than the vertical height LV2 of the substrate 102 exposed at the bottom of each of the plurality of wall spaces WS.

[0079] Referring to Figure 12A , Figure 12B and Figure 12C , after removing the mask pattern MP1 from the resulting structure of Figure 11A and Figure 11B , a plurality of device isolation films 112 can be formed on the substrate 102 to fill the plurality of device isolation spaces IS. The device isolation films 112 can be formed to cover sidewalls of each of the semiconductor regions F1 and the dummy bodies PH in the device isolation spaces IS. The formation of the device isolation films 112 can include forming an insulating film having a thickness sufficient to fill the plurality of device isolation spaces IS on the resulting structure of Figure 11A and Figure 11B , and performing a recess process of removing a portion of the insulating film to form the device isolation films 112 including the remaining portions of the insulating film. After forming the device isolation films 112, the stacked structure including the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS remaining on the substrate 102 can protrude above the top surface of the device isolation films 112, and the top surface of the uppermost nanosheet semiconductor layer NS among the plurality of nanosheet semiconductor layers NS can be exposed.

[0080] Thereafter, a plurality of dummy gate structures DGS covering the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS and a plurality of insulating spacers 118 covering two sidewalls of each of the plurality of dummy gate structures DGS can be formed. Each of the plurality of dummy gate structures DGS can be formed to extend in the second lateral direction (Y direction). Each of the plurality of dummy gate structures DGS can include a dummy oxide film D122, a dummy gate layer D124, and a cap layer D126 sequentially stacked on the stacked structure including the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS. In an embodiment, the dummy gate layer D124 can include polysilicon, and the cap layer D126 can include a silicon nitride layer.

[0081] Thereafter, a portion of each of the plurality of sacrificial semiconductor layers 104 and a portion of the plurality of nanosheet semiconductor layers NS and a portion of the bottom semiconductor layer BS can be etched by using the plurality of dummy gate structures DGS and the plurality of insulating spacers 118 as an etch mask. As a result, the plurality of nanosheet semiconductor layers NS can be divided into a plurality of nanosheet stacks NSS including first to fourth nanosheets N1, N2, N3, and N4.

[0082] Thereafter, a plurality of insulating walls VW can be formed to fill the plurality of wall spaces WS. The plurality of insulating walls VW can be formed by using various methods. In an embodiment, the formation of the plurality of insulating walls VW can include forming a planarization sacrificial film that covers the resulting structure including the plurality of dummy gate structures DGS, the plurality of insulating spacers 118, and the plurality of nanosheet stacks NSS. The planarization sacrificial film can include a material having an etch selectivity with respect to the material included in the outer surface of the dummy gate structure DGS. For example, the planarization sacrificial film can include a silicon oxide layer. Thereafter, a portion of each of the planarization sacrificial film, the plurality of dummy gate structures DGS, and the plurality of device isolation films 112 can be etched to form a plurality of openings corresponding to the spaces in which the plurality of insulating walls VW are to be formed, the plurality of insulating walls VW can be formed to fill the plurality of openings, and then the planarization sacrificial film can be removed. After removing the planarization sacrificial film, the plurality of placeholders PH can be exposed on both sides of each of the plurality of insulating walls VW in the second lateral direction (Y direction). Although the process of forming the plurality of insulating walls VW by using the planarization sacrificial film is described as an example, the inventive concept is not limited thereto, and various modifications and changes can be made within the scope of the inventive concept.

[0083] Referring to Figure 13A and Figure 13B and Figures 12A to 12C in the resulting structure of

[0084] , a plurality of source / drain regions 130 can be formed on the exposed top surfaces of the plurality of placeholders PH. To form the plurality of source / drain regions 130, semiconductor materials can be epitaxially grown from the bottom semiconductor layer BS and the sidewalls of each of the first to fourth nanosheets N1, N2, N3, and N4 exposed on the plurality of placeholders PH. When the plurality of placeholders PH include SiGe films, semiconductor materials can be epitaxially grown from the surfaces of the plurality of placeholders PH during the formation of the plurality of source / drain regions 130.

[0084] Thereafter, an insulating liner 142 can be formed to cover the surface of the resulting structure including the plurality of source / drain regions 130, and a gate dielectric film 144 can be formed on the insulating liner 142. Next, a portion of each of the insulating liner 142 and the gate dielectric film 144 can be etched to expose the plurality of capping layers (refer to Figure 12A , Figure 12B and Figure 12CThe top surfaces of each of the D126) in and each of the multiple insulating walls VW. Thereafter, a portion of each of the multiple insulating walls VW and the multiple capping layers D126 can be removed to expose the dummy gate layer D124. The insulating liner 142 and the inter-gate dielectric film 144 can be partially removed such that the top surfaces of the inter-gate dielectric film 144, the top surfaces of the multiple insulating walls VW, and the top surface of the dummy gate layer D124 are at substantially the same height.

[0085] Referring to Figure 14A and Figure 14B , the dummy gate layer D124 and the dummy oxide film D122 can be removed from the resulting structure of Figure 13A and Figure 13B to prepare the gate space GS.

[0086] Referring to Figure 15A and Figure 15B , the multiple sacrificial semiconductor layers 104 remaining on the substrate 102 can be removed through the gate space GS from the resulting structure of Figure 14A and Figure 14B Thus, the gate space GS can extend to the corresponding spaces between the first to fourth nanosheets N1, N2, N3, and N4 and the space between the bottom semiconductor layer BS and the first nanosheet N1.

[0087] In an embodiment, the differences in etch selectivity between each of the first to fourth nanosheets N1, N2, N3, and N4 and between the bottom semiconductor layer BS and the multiple sacrificial semiconductor layers 104 can be used to selectively remove the multiple sacrificial semiconductor layers 104. A liquid etchant or a gaseous etchant can be used to selectively remove the multiple sacrificial semiconductor layers 104. In an embodiment, a CH3COOH-based etchant (e.g., an etchant including a mixture of CH3COOH, HNO3, and HF or an etchant including a mixture of CH3COOH, H2O2, and HF) can be used to selectively remove the multiple sacrificial semiconductor layers 104, but is not limited thereto.

[0088] Referring to Figure 16A , Figure 16B and Figure 16C , in the resulting structure of Figure 15A and Figure 15B , a gate dielectric film 152 can be formed to cover the corresponding exposed surfaces of the first to fourth nanosheets N1, N2, N3, and N4 and the bottom semiconductor layer BS. The gate dielectric film 152 can be formed by using an atomic layer deposition (ALD) process.

[0089] Thereafter, a fill gate space (referring to Figure 15A and Figure 15BThe gate line 160 of the GS) in. Thereafter, the height of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118 can be reduced by removing a part of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118 from the top surface of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118, and a plurality of cover insulating patterns 168 can be formed to cover the top surface of each of the gate line 160, the gate dielectric film 152, and the insulating spacer 118.

[0090] Subsequently, a source / drain contact hole exposing the source / drain region 130 can be formed between two adjacent gate lines 160 among the plurality of gate lines 160, a metal silicide film 172 can be formed on the surface of the source / drain region 130 through the source / drain contact hole, and a front-side source / drain contact CA filling the source / drain contact hole can be formed on the metal silicide film 172. In an embodiment, a gate cutting insulating pattern GC can be formed to define the plurality of gate lines 160.

[0091] Refer to Figure 17A 、 Figure 17B and Figure 17C In Figure 16A 、 Figure 16B and Figure 16C In the resulting structure of, an etch stop film 182 and an upper insulating film 184 can be sequentially formed to cover the top surface of each of the front-side source / drain contact CA, the plurality of cover insulating patterns 168, the plurality of insulating walls VW, and the inter-gate dielectric film 144 to form an upper insulating structure 180. Thereafter, a source / drain via contact VA and a gate contact CB can be formed. The source / drain via contact VA can pass through the upper insulating structure 180 in the vertical direction (Z direction) and be connected to the front-side source / drain contact CA. The gate contact CB can pass through the upper insulating structure 180 and the cover insulating pattern 168 in the vertical direction (Z direction) and be connected to the gate line 160. The source / drain via contact VA and the gate contact CB can be formed simultaneously or by using separate processes. Thereafter, a front-side interlayer insulating film 186 covering the upper insulating structure 180 and a plurality of upper wiring layers M1 passing through the front-side interlayer insulating film 186 can be formed. The plurality of upper wiring layers M1 can include an upper wiring layer M1 connected to the source / drain via contact VA and an upper wiring layer M1 connected to the gate contact CB. Thereafter, a front-side wiring structure can be formed on the front-side interlayer insulating film 186 and the plurality of upper wiring layers M1.

[0092] Refer to Figure 18A 、 Figure 18B and Figure 18C In Figure 17A 、 Figure 17B and Figure 17CIn the resulting structure, the back surface 102B of the substrate 102 can be polished to expose the back surface FB of the semiconductor region F1, and portions of the plurality of semiconductor regions F1 can be removed to expose the plurality of placeholders PH.

[0093] Referring to Figure 19A and Figure 19B , the plurality of placeholders PH can be removed from the Figure 18A , [[ID=2 and ​ resulting structure to form a plurality of back contact holes BCH exposing the plurality of source / drain regions 130.

[0094] Each of the plurality of back contact holes BCH can have a width in a first lateral direction (X direction) defined by two adjacent semiconductor regions F1 among the plurality of semiconductor regions F1, and each of the plurality of back contact holes BCH can have a width in a second lateral direction (Y direction) defined by the device isolation film 112 and the insulating wall VW. In the first lateral direction (X direction) and the second lateral direction (Y direction), the width of each of the plurality of back contact holes BCH can gradually increase toward the back surface FB of the semiconductor region F1.

[0095] During the etching process for removing the plurality of placeholders PH, the exposed portions of the source / drain regions 130 may be consumed, and thus, the surface shape of the source / drain regions 130 facing the back surface FB of the semiconductor region F1 may be deformed.

[0096] Referring to ​ and ​ , in the ​ and ​ resulting structure, a back insulating spacer BIS can be formed to cover the surfaces of the semiconductor regions F1 exposed at the inner sidewalls of the plurality of back contact holes BCH, and a plurality of back contact structures DBCS can be formed by filling the plurality of back contact holes BCH with a conductive material, each of the plurality of back contact holes BCH being defined by the back insulating spacer BIS, the device isolation film 112, and the insulating wall VW. In addition, a metal silicide film 190 can be formed between the source / drain regions 130 and the back contact structures DBCS.

[0097] According to what has been referred to Figures 8A to 20BThe method of manufacturing the IC device 100 described herein is such that, before forming a stacked structure including a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS on a substrate 102 to form a plurality of nanosheet stacks NSS, a plurality of placeholder spaces PHS can be formed by etching a partial region from the front surface 102F of the substrate 102, and subsequently a plurality of placeholders PH can be formed to fill the plurality of placeholder spaces PHS. As described above, when there are no spatial obstacles (such as a plurality of insulating walls VW, a plurality of nanosheet stacks NSS, and a plurality of dummy gate structures DGS) on the substrate 102, a plurality of placeholder spaces PHS can be formed by etching the substrate 102, and a plurality of placeholders PH filling the plurality of placeholder spaces PHS can be formed. Therefore, the difficulty of the etching process for forming the plurality of placeholder spaces PHS can be reduced, the desired size of each of the plurality of placeholders PH can be ensured, and the size deviation of the plurality of placeholders PH can be minimized. Thus, by using the plurality of placeholders PH, a sufficient width in the lateral direction (X direction and / or Y direction) of the back contact DBC included in each of the plurality of back contact structures DBCS to be finally formed can be ensured. As a result, the contact resistance of each of the plurality of back contacts DBC included in the plurality of back contact structures DBCS can be reduced.

[0098] Figures 21A to 21C is a plan view of the process sequence of the method of manufacturing an IC device according to an embodiment. Referring to Figures 21A to 21C described with reference to Figure 5 an example of the method of manufacturing the IC device 200 described. In Figures 21A to 21C the same reference numerals are used to denote the same elements as in Figures 1 to 5 and a detailed description thereof is omitted.

[0099] Referring to Figure 21A it is possible to etch a partial region from the front surface 102F of the substrate 102 by using a method similar to the process of forming the plurality of placeholder spaces PHS already described with reference to Figure 8A , Figure 8B and Figure 8C described. Thus, a plurality of placeholder spaces PHS2 can be formed in the substrate 102. Each of the plurality of placeholder spaces PHS2 can have a configuration substantially the same as that of the placeholder space PHS described with reference to Figure 8A , Figure 8B and Figure 8C described. However, each of the plurality of placeholder spaces PHS2 can have sidewalls PSR2, and a part of the sidewalls PSR2 extends in a curved shape in the first lateral direction (X direction).

[0100] Referring to Figure 21B it is possible to etch a partial region from the front surface 102F of the substrate 102 by using a method similar to the process already described with reference to Figure 9A , Figure 9Band Figure 9C A method similar to the process of forming multiple placeholder bodies PH is used to form multiple placeholder bodies PH2 to fill Figure 21A the multiple placeholder spaces PHS2 in the resulting structure of

[0101] It is possible to perform processes similar to those described with reference to Figure 21B on the resulting structure of Figures 10A to 17C As a result, as shown in Figure 21C structures including multiple placeholder bodies PH2 in contact with the insulating wall VW can be obtained on both sides of the insulating wall VW in the second lateral direction (Y direction).

[0102] In the resulting structure obtained according to the processes described with reference to Figure 17A , Figure 17B and Figure 17C it is possible to perform the processes described with reference to Figure 21C on the structure shown in Figures 18A to 20B which includes multiple placeholder bodies PH2 instead of multiple placeholder bodies PH. Therefore, it is possible to manufacture the IC device 200 described with reference to Figure 5

[0103] Figures 22A to 24C is a diagram of the process sequence of a method for manufacturing an IC device according to an embodiment. More specifically, Figure 22A , Figure 23A and Figure 24A are cross-sectional views of example cross-sectional structures corresponding to the cross-section taken along the line X1-X1' of Figure 1 Figure 22B , Figure 23B and Figure 24B are cross-sectional views of example cross-sectional structures corresponding to the cross-section taken along the line Y1-Y1' of Figure 1 Figure 22C , Figure 23C and Figure 24C are plan views of some components according to the process sequence. Refer to Figures 22A to 24C for a description of an example of the manufacturing method of the IC device 300 described with reference to Figure 6A , Figure 6B and Figure 6C In Figures 22A to 24C , the same reference numerals are used to denote the same elements as in Figures 1 to 6C , and their detailed descriptions are omitted.

[0104] Refer to Figure 22A , Figure 22B and Figure 22C , it is possible to use processes similar to those already referred to Figure 8A , Figure 8B and Figure 8C ​​​A method similar to the described process of forming multiple placeholder spaces PHS etches a partial area from the front surface 102F of the substrate 102, so that multiple placeholder spaces PHS3 can be formed in the substrate 102.

[0105] Each of the multiple placeholder spaces PHS32 can have a structure substantially the same as the placeholder space PHS described with reference to Figure 8A 、 Figure 8B and Figure 8C . However, as shown in Figure 22C , each of the multiple placeholder spaces PHS3 can have a bar shape linearly extending in the first lateral direction (X direction).

[0106] As shown in Figure 23A 、 Figure 23B and Figure 23C , in the resulting structure of Figure 22A 、 Figure 22B and Figure 22C , multiple placeholder layers PHL3 can be formed to fill the multiple placeholder spaces PHS3. Each of the multiple placeholder layers PHL3 can be formed to have a planarized top surface at the same vertical height as the front surface 102F of the substrate 102.

[0107] Referring to Figure 24A 、 Figure 24B and Figure 24C , in the resulting structure of Figure 23A 、 Figure 23B and Figure 23C , a part of each of the substrate 102 and the multiple placeholder layers PHL3 can be etched to form multiple strip-shaped trenches extending in the second lateral direction (Y direction), and multiple alternative semiconductor regions 303 can be formed by filling the multiple strip-shaped trenches with a semiconductor material. As a result, one placeholder layer PHL3 can be divided into multiple placeholders PH3 by the multiple alternative semiconductor regions 303. To form the multiple alternative semiconductor regions 303, an epitaxial growth process can be used to form a semiconductor layer. The semiconductor layer can include silicon (Si).

[0108] After that, a process similar to the process described with reference to Figure 24A 、 Figure 24B and Figure 24C can be performed on the resulting structure of Figures 10A to 20B , and the IC device 300 described with reference to Figure 6A 、 Figure 6B and Figure 6C can be manufactured.

[0109] Figures 25A to 26C is a diagram showing the process sequence of a method for manufacturing an IC device according to an embodiment. More specifically, Figure 25A andFigure 26A is an example cross-sectional view of a cross-sectional structure corresponding to a part taken along line X1-X1' according to the process sequence. Figure 1 Figure 25B and Figure 26B is an example cross-sectional view of a cross-sectional structure corresponding to a part taken along line Y1-Y1' according to the process sequence. Figure 1 Figure 25C and Figure 26C are plan views of some components according to the process sequence. Refer to Figures 25A to 26C for a description of the reference Figure 6A , Figure 6B and Figure 6C for an example of a method of manufacturing the IC device 300 described. In Figures 25A to 26C , the same reference numerals are used to denote the same elements as in Figures 1 to 6C , and their detailed description is omitted.

[0110] Refer to Figure 25A , Figure 25B and Figure 25C to perform a process similar to the process of forming the plurality of dummy layers PHL3 already described with reference to Figures 22A to 23C , so that a plurality of dummy layers PHL3A can be formed in the substrate 102.

[0111] Each of the plurality of dummy layers PHL3A can have a structure substantially the same as that of the dummy layer PHL3 described with reference to Figure 23A , Figure 23B and Figure 23C . However, the length of each of the plurality of dummy layers PHL3A in the second lateral direction (Y direction) can be greater than Figure 23A , Figure 23B and Figure 23C the length of each of the dummy layers PHL3 shown in Figure 23A , Figure 23B and Figure 23C in the second lateral direction (Y direction). In an embodiment, the length of each of the plurality of dummy layers PHL3A in the second lateral direction (Y direction) can correspond to the length of a region in the second lateral direction (Y direction) that includes

[0112] Refer to Figure 26A , Figure 26B and Figure 26C . In Figure 25A , Figure 25B and Figure 25CIn the resulting structure, a portion of each of the substrate 102 and the plurality of dummy layers PHL3A can be etched to form a plurality of strip trenches extending in the second lateral direction (Y direction). Additionally, the plurality of strip trenches can be filled with a semiconductor material by a method similar to the method described with reference to Figure 24A 、 Figure 24B and Figure 24C to form a plurality of alternative semiconductor regions 303. As a result, one dummy layer PHL3A can be divided into a plurality of preliminary dummies PHP3 by the plurality of alternative semiconductor regions 303.

[0113] After that, the resulting structure of Figure 26A 、 Figure 26B and Figure 26C can be subjected to a process similar to the process described with reference to Figures 10A to 11B . Here, as described above with reference to Figure 11A and Figure 11B , during the etching process of forming the plurality of wall spaces WS and the plurality of device isolation spaces IS, the plurality of wall spaces WS can be formed to respectively pass through the plurality of preliminary dummies PHP3 and the plurality of alternative semiconductor regions 303 shown in Figure 26A 、 Figure 26B and Figure 26C in the second lateral direction (Y direction). As a result, one preliminary dummy PHP3 can be divided into two, and thus, the plurality of dummies PH3 shown in Figure 24A 、 Figure 24B and Figure 24C can be obtained. The resulting structure can be subjected to a process similar to the process described with reference to Figures 12A to 20B , and thus, the IC device 300 described with reference to Figure 6A 、 Figure 6B and Figure 6C can be manufactured.

[0114] Similar to the method of manufacturing the IC device 100 already described with reference to Figures 8A to 20B , according to what has been already referred to Figures 21A to 26CThe described method of manufacturing the IC devices 200 and 300, before forming a stacked structure including a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS to form a plurality of nanosheet stacks NSS, a structure required to form a plurality of placeholders can be formed in the substrate 102. As described above, when there are no spatial obstacles (such as a plurality of insulating walls VW, a plurality of nanosheet stacks NSS, and a plurality of dummy gate structures DGS) on the substrate 102, a structure required to form a plurality of placeholders can be formed in the substrate 102. Therefore, the difficulty of the etching process for forming a space for the plurality of placeholders can be reduced, a desired size of each of the plurality of placeholders can be ensured, and the size deviation of the plurality of placeholders can be minimized. Accordingly, by using the plurality of placeholders, a sufficient width in the lateral direction (X direction and / or Y direction) can be ensured for the plurality of backside contacts that will ultimately be formed. As a result, the contact resistance of each of the plurality of backside contacts can be reduced.

[0115] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: a plurality of semiconductor regions, each of the plurality of semiconductor regions having a front side surface and a back side surface facing in opposite directions; an insulating wall extending in the first lateral direction, the insulating wall passing in a vertical direction between a pair of semiconductor regions adjacent to each other in a second lateral direction among the plurality of semiconductor regions, the second lateral direction being perpendicular to the first lateral direction, and the vertical direction being perpendicular to the first lateral direction and the second lateral direction; a pair of nanosheet stacks vertically overlapping the pair of semiconductor regions and facing the front side surfaces of the pair of semiconductor regions, each of the pair of nanosheet stacks comprising a nanosheet having one end contacting the side wall of the insulating wall; a pair of source / drain regions, each of the pair of source / drain regions including a portion in contact with a nanosheet of a corresponding one of the pair of nanosheet stacks; as well as A back contact has a contact end and a contact sidewall, wherein the contact end is connected to a corresponding source / drain region among the pair of source / drain regions, the contact sidewall contacts the sidewall of the insulating wall, and the back contact extends in a vertical direction from the contact end toward a back surface of each of the pair of semiconductor regions.

2. The integrated circuit device according to claim 1, wherein: The width of the insulating wall in the second lateral direction gradually decreases as the insulating wall becomes closer toward the backside surface of each of the pair of semiconductor regions, and The width of the backside contact in the second lateral direction gradually increases as the backside contact becomes closer toward the backside surface of each of the pair of semiconductor regions.

3. The integrated circuit device according to claim 1, further comprising: A metal silicide film between the corresponding source / drain region and the contact end of the back contact, wherein The metal silicide film contacts the insulating wall, and The contact end of the backside contact is connected to the corresponding source / drain region through the metal silicide film.

4. The integrated circuit device according to claim 1, further comprising: a gate line surrounding a nanosheet in each of the pair of nanosheet stacks over the pair of semiconductor regions, the gate line extending in a second lateral direction; as well as A gate cut insulating pattern faces an end of the gate line in the second lateral direction, and the gate cut insulating pattern extends in the first lateral direction, wherein a vertical height of a lowermost surface of the insulating wall is closer to a back surface of each of the pair of semiconductor regions than a vertical height of a lowermost surface of the gate cut insulating pattern.

5. The integrated circuit device according to claim 1, wherein: The wall lowermost surface of the insulating wall is coplanar with the contact lowermost surface of the back contact, and A wall lowermost surface of the insulating wall is closer to the backside surface of each of the pair of semiconductor regions than an upper surface of the insulating wall.

6. The integrated circuit device according to claim 1, wherein: A distance between a contact lowermost surface of the backside contact and a backside surface of each of the pair of semiconductor regions is greater than a distance between a wall lowermost surface of the insulating wall and the backside surface of each of the pair of semiconductor regions.

7. The integrated circuit device according to claim 1, wherein: In the back side contact, the contact side wall and the side wall facing away from the contact side wall extend in a straight line in a first lateral direction.

8. The integrated circuit device according to claim 1, further comprising: A backside insulating spacer is between the backside contact and a semiconductor region adjacent to the backside contact among the pair of semiconductor regions.

9. The integrated circuit device according to claim 1, further comprising: a pair of replacement semiconductor regions between the pair of semiconductor regions and the pair of nanosheet stacks, wherein the pair of replacement semiconductor regions contacting the pair of semiconductor regions, Each of the pair of semiconductor regions and the pair of replacement semiconductor regions includes silicon, and The backside contact faces one of the pair of replacement semiconductor regions in a first lateral direction.

10. The integrated circuit device according to any one of claims 1 to 9, further comprising: a device isolation film covering a first side wall of each semiconductor region of the pair of semiconductor regions, wherein each semiconductor region of the pair of semiconductor regions includes a second side wall, The second side wall faces the insulating wall and is opposite to the first side wall in the second lateral direction, and The device isolation film covers the other contact sidewall of the back contact, and The other contact side wall of the rear contact faces away from the contact side wall of the rear contact that is in contact with the insulating wall.

11. An integrated circuit device comprising: a plurality of semiconductor regions spaced apart from one another in first and second lateral directions perpendicular to one another, each of the plurality of semiconductor regions having a front side surface and a back side surface facing in the opposite direction; a plurality of nanosheet stacks facing the plurality of semiconductor regions in a vertical direction, each of the plurality of nanosheet stacks comprising a nanosheet, the vertical direction being perpendicular to the first lateral direction and the second lateral direction; a plurality of source / drain regions, each of the plurality of source / drain regions being between a pair of nanosheet stacks adjacent to each other in a first lateral direction among the plurality of nanosheet stacks, and each of the plurality of source / drain regions contacting a nanosheet in an adjacent adjacent nanosheet stack among the plurality of nanosheet stacks; an insulating wall, the insulating wall passing through a pair of semiconductor regions adjacent to each other in the second lateral direction among the plurality of semiconductor regions in the vertical direction, the insulating wall passing through a pair of nanosheet stacks adjacent to each other in the second lateral direction among the plurality of nanosheet stacks, and the insulating wall passing through a pair of source / drain regions adjacent to each other in the second lateral direction among the plurality of source / drain regions; as well as A pair of back side contacts, wherein each of the pair of back side contacts includes a contact end connected to a corresponding one of the pair of source / drain regions and a contact side wall contacting an insulating wall, and each of the pair of back side contacts extends in a vertical direction from the contact end toward a back side surface of each of the pair of semiconductor regions.

12. The integrated circuit device according to claim 11, wherein: The width of the insulating wall in the second lateral direction gradually decreases as the insulating wall becomes closer toward the backside surface of each of the pair of semiconductor regions, and A width of each of the pair of backside contacts in the second lateral direction gradually increases as the pair of backside contacts becomes closer toward a backside surface of each of the pair of semiconductor regions.

13. The integrated circuit device according to claim 11, further comprising: a plurality of gate lines extending in a second lateral direction on a front side surface of each of the plurality of semiconductor regions; as well as A gate cutting insulating pattern faces one end of at least one gate line of the plurality of gate lines in the second lateral direction, and the gate cutting insulating pattern extends in the first lateral direction, wherein: A vertical height of a lowermost surface of the insulating wall is closer to a backside surface of each of the pair of semiconductor regions than a vertical height of a lowermost surface of the gate cutting insulating pattern.

14. The integrated circuit device according to claim 11, wherein: In each of the pair of backside contacts, the contact side wall and the side wall opposite to the contact side wall extend in a straight line in the first lateral direction.

15. The integrated circuit device according to claim 11, wherein: Each of the pair of backside contacts is separated from a most adjacent one of the plurality of semiconductor regions in a first lateral direction.

16. The integrated circuit device according to claim 11, further comprising: a plurality of replacement semiconductor regions, between the plurality of semiconductor regions and the plurality of nanosheet stacks, the plurality of replacement semiconductor regions contacting the plurality of semiconductor regions, wherein Each of the plurality of semiconductor regions and the plurality of replacement semiconductor regions comprises silicon, and Each of the pair of backside contacts is between an adjacent pair of replacement semiconductor regions among the plurality of replacement semiconductor regions in the first lateral direction.

17. The integrated circuit device according to any one of claims 11 to 16, further comprising: a device isolation film covering a first side wall of each semiconductor region in the pair of semiconductor regions, wherein: Each semiconductor region of the pair of semiconductor regions includes a second sidewall, The second side wall faces the insulating wall and is opposite to the first side wall in the second lateral direction. a device isolation film covering the other contact side wall of each of the pair of backside contacts, The other contact side wall faces away from the contact side wall in each of the pair of back-side contacts, and The device isolation lowermost surface of the device isolation film is coplanar with the wall lowermost surface of the insulating wall.

18. An integrated circuit device comprising: a plurality of semiconductor regions spaced apart from one another in first and second lateral directions perpendicular to one another, each of the plurality of semiconductor regions having a front side surface and a back side surface facing in the opposite direction; a plurality of nanosheet stacks facing the plurality of semiconductor regions in a vertical direction, each of the plurality of nanosheet stacks comprising a nanosheet, the vertical direction being perpendicular to the first lateral direction and the second lateral direction; a plurality of source / drain regions, each of the plurality of source / drain regions being between a pair of nanosheet stacks adjacent to each other in a first lateral direction among the plurality of nanosheet stacks, and each of the plurality of source / drain regions contacting a nanosheet in an adjacent nanosheet stack among the plurality of nanosheet stacks; an insulating wall, the insulating wall passing through a pair of semiconductor regions adjacent to each other in the second lateral direction among the plurality of semiconductor regions in the vertical direction, the insulating wall passing through a pair of nanosheet stacks adjacent to each other in the second lateral direction among the plurality of nanosheet stacks, and the insulating wall passing through a pair of source / drain regions adjacent to each other in the second lateral direction among the plurality of source / drain regions; as well as A plurality of back side contact structures contact the insulating wall, wherein the plurality of back side contact structures are arranged in a row in a first lateral direction, wherein: Each of the plurality of backside contact structures includes a backside contact having a contact end connected to a corresponding one of the plurality of source / drain regions and a contact sidewall contacting an insulating wall, a backside contact extending in a vertical direction from a contact end toward a backside surface of each of the plurality of semiconductor regions, The width of the backside contact in the second lateral direction gradually increases as the backside contact becomes closer to the backside surface of each of the plurality of semiconductor regions, The width of the insulating wall in the second lateral direction gradually decreases as the insulating wall becomes closer toward the backside surface of each of the plurality of semiconductor regions, and In each of the plurality of backside contact structures, a contact sidewall of the backside contact extends in a straight line in the first lateral direction.

19. The integrated circuit device according to claim 18, further comprising: a plurality of gate lines extending in a second lateral direction on a front side surface of each of the plurality of semiconductor regions; a device isolation film covering a first side wall of each of the plurality of semiconductor regions, the first side wall being opposite to a second side wall of each of the plurality of semiconductor regions in a second lateral direction, and the second side wall facing the insulating wall; as well as a gate cutting insulating pattern facing one end of each of the plurality of gate lines in the second lateral direction and extending in the first lateral direction, the gate cutting insulating pattern passing through a portion of the device isolation film in the vertical direction, wherein The device isolation lowermost surface of the device isolation film is coplanar with the lowermost surface of the insulating wall, and A lowermost surface of the gate cutting insulation pattern closest to the backside surface is in contact with the device isolation film.

20. The integrated circuit device according to claim 18, wherein: In each of the plurality of backside contact structures, a contact sidewall and a sidewall opposite to the contact sidewall extend in a straight line in a first lateral direction.

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