Microelectronic assembly including cavity-free encapsulated die

Abstract

Microelectronic assemblies including a cavity-free encapsulated die, related devices, and methods are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a material and a conductive path through the material, where the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, where the first surface of the microelectronic component is electrically coupled to conductive vias in the material by an interconnect, where the interconnect includes solder and is surrounded by a capillary underfill material, and where the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.

Description

BACKGROUND OF THE INVENTION

[0001] Integrated circuit (IC) devices (e.g., dies) are typically coupled together in a multi-die IC package to integrate features or functions and to facilitate connection to other components (e.g., a package substrate). An IC package can include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For the sake of description, like reference numerals refer to like structural elements. In the figures of the drawings, embodiments are shown by way of example and not by way of limitation.

[0003] Figure 1A is a side cross-sectional view of an exemplary microelectronic component in accordance with various embodiments.

[0004] Figure 1B is a side cross-sectional view of another exemplary microelectronic component in accordance with various embodiments.

[0005] Figure 2 is a side cross-sectional view of an exemplary microelectronic component in accordance with various embodiments.

[0006] Figure 3 is a side cross-sectional view of an exemplary microelectronic component in accordance with various embodiments.

[0007] Figures 4A - 4I is for manufacturing in accordance with various embodiments Figure 1A side cross-sectional views of respective stages in an exemplary process for a microelectronic component in.

[0008] Figures 5A - 5F is for manufacturing in accordance with various embodiments similar to Figure 2 side cross-sectional views of respective stages in an exemplary process for a microelectronic component in.

[0009] Figures 6A - 6E is for manufacturing in accordance with various embodiments Figure 3 side cross-sectional views of respective stages in an exemplary process for a microelectronic component in.

[0010] Figure 7 is a top view of a wafer and dies that can be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

[0011] Figure 8 is a cross-sectional side view of an IC device that can be included in a microelectronic component in accordance with any of the embodiments disclosed herein.

[0012] Figure 9Is a cross-sectional side view of an IC device assembly that may include a microelectronic component according to any of the embodiments disclosed herein.

[0013] Figure 10 Is a block diagram of an exemplary electrical device that may include a microelectronic component according to any of the embodiments disclosed herein. Detailed Description

[0014] Overview

[0015] Due to the increasingly smaller sizes of two or more dies in a multi-die IC package and the increasing use of stacked dies, it is challenging to transfer a large number of signals between such dies. A multi-die IC package typically requires increased die isolation, additional power delivery requirements, and more stringent wiring and alignment tolerances throughout the package. A greater number of embedded dies and smaller-sized embedded dies (i.e., dies, passive devices, etc.) greatly increase the manufacturing complexity as well as the wiring complexity. For example, a multi-die IC package may include an encapsulated bridge die (e.g., a die embedded within a substrate, such as an EMIB) and a top die (e.g., a die coupled to the embedded die at the surface of the substrate). Typically, a multi-die IC package includes a cavity formed in the substrate, and the bridge die is at least partially embedded within the cavity and surrounded by a dielectric material (e.g., a build-up material or a molding material (e.g., an epoxy-based resin with fillers)). The bridge die may be electrically coupled to a conductive contact at the bottom surface of the cavity via solder bumps. Such an interconnect typically utilizes a non-conductive film (NCF) located at the bottom surface of the bridge die to act as an underfill material that flows around and between the solder bumps and then cures. NCF materials generally include inorganic fillers to improve the mechanical and reliability properties of the material; however, during the bonding and solder reflow processes, these inorganic fillers are often trapped at the interface between the solder and the conductive contact, which prevents the solder bumps from forming an interconnect and is likely to cause faults, failures, and other reliability issues in the multi-die IC package during use. Additionally, the use of NCF materials requires a surface finish material (e.g., gold) on the conductive contact, which is volatile (e.g., has a short shelf life between lamination on the bottom surface of the bridge die and solder bump bonding), which limits the manufacturing time frame and involves a complex preparation process to perform bridge die lamination at the wafer level and then singulation. By encapsulating the bridge die within the substrate without forming a cavity and without using NCF materials as an underfill material around and between the solder interconnects, various embodiments disclosed herein can help reduce the cost and complexity associated with assembling a multi-die IC package as compared to conventional methods.

[0016] Accordingly, microelectronic components, related devices, and methods are disclosed herein. In some embodiments, a microelectronic component can include: a substrate having a material and a conductive via passing through the material, where the material includes an organic dielectric material or an organic build-up material; and a microelectronic component having a first surface and an opposite second surface, where the first surface of the microelectronic component is electrically coupled to the conductive via in the material by an interconnect, where the interconnect includes solder and is surrounded by a capillary underfill material, and where the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.

[0017] In some embodiments, a microelectronic component can include: a first layer of a substrate, the first layer including a first material and a first conductive via passing through the first material, the first material including a dielectric material; a second layer of the substrate located on the first layer, the second layer including a second material and a second conductive via passing through the second material, the second material including a molded underfill material; and a microelectronic component having a first surface and an opposite second surface, where the microelectronic component is located in the second layer of the substrate, where the first surface of the microelectronic component is electrically coupled to the first conductive via in the first layer by an interconnect, the interconnect including solder, where the microelectronic component and the interconnect are surrounded by the second material, and where the first conductive via includes a conductive via and a conductive trace, and the second conductive via includes a conductive via.

[0018] In some embodiments, a microelectronic component can include: a first layer of a substrate, the first layer including a material and a first conductive via passing through the material, the material including a dielectric material; a second layer of the substrate located on the first layer, the second layer including a material and a second conductive via passing through the material; and a microelectronic component having a first surface and an opposite second surface, where the microelectronic component is located in the second layer of the substrate, where the first surface of the microelectronic component is electrically coupled to the first conductive via in the first layer by an interconnect, where the interconnect includes solder and is surrounded by a capillary underfill material, where the microelectronic component and the capillary underfill material are surrounded by the material, and where the first conductive via includes a conductive via and a conductive trace, and the second conductive via includes a conductive via.

[0019] Each of the structures, components, packages, methods, devices, and systems of the present disclosure can have several innovative aspects, and no single aspect alone is responsible for all of the desired attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the drawings.

[0020] In the following detailed description, common terms used by those skilled in the art will be used to describe various aspects of the illustrative embodiments to convey the substance of their work to other technicians in the art.

[0021] The term "circuit" or "circuitry" means one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. The term also refers to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0022] The term "integrated circuit (IC)" means a circuit that is integrated into a single piece of semiconductor or similar material.

[0023] In some embodiments, the IC die disclosed herein may include a substantially single-crystalline semiconductor (e.g., silicon and germanium) as a substrate material (e.g., substrate, body), and the integrated circuit is fabricated on the substrate material using conventional semiconductor processing methods. The semiconductor substrate material may include, for example, an N-type material or a P-type material. The die may include, for example, a crystalline substrate material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the substrate material of one or more of the IC dies may include alternative materials that may or may not be combined with silicon, including but not limited to: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N group materials, III-V group materials, II-VI group materials, or IV group materials. In still other embodiments, the substrate material may include a compound semiconductor, for example, the compound semiconductor having a first sublattice of at least one element from Group III (e.g., Al, Ga, In) of the periodic table and a second sublattice of at least one element from Group V (e.g., P, As, Sb) of the periodic table. In still other embodiments, the substrate material may include an intrinsic Group IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may include silica-filled epoxy resin. In other embodiments, the substrate material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the substrate material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, cupric peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although some examples of materials for the die are described herein, any material or structure that can serve as a basis (e.g., substrate material) on which the IC circuits and structures described herein can be built falls within the spirit and scope of the present disclosure.

[0024] Unless otherwise described, the IC die described herein includes one or more IC structures (or simply, "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, a control logic unit configured to control the memory device and the memory array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., an IC that implements one or more of an I / O function, arithmetic operations, pipelining of data, etc.).

[0025] In another example, like the terms "die", "IC", and "IC die", the terms "package" and "IC package" are synonymous. Note that the terms "microelectronic component", "chip", "dielet", "die", and "IC die" and similar variants may be used interchangeably herein. The terms "interconnect component", "bridge die", "interconnect bridge", and "interconnect die" and similar variants may be used interchangeably herein.

[0026] Unless otherwise stated, the term "insulate" means "electrically insulate", and the term "conduct" means "electrically conduct". With respect to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conduct" may also mean "optically conduct".

[0027] The terms "oxide", "carbide", "nitride", etc. refer to compounds containing oxygen, carbon, nitrogen, etc., respectively.

[0028] The term "high-k dielectric" refers to a material having a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to a material having a dielectric constant lower than that of silicon oxide.

[0029] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that solidifies after processing as described herein) that is substantially non-conductive. By way of example and not limitation, it can include organic polymers and plastics, as well as inorganic materials (such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or combinations thereof). It can include dielectric materials, high polarizability materials, and / or piezoelectric materials. Dielectric materials can include any suitable dielectric materials commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); polyimide materials; or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). Without departing from the scope of the present disclosure, it can be transparent or opaque. Further examples of insulating materials are underfills and moldings or molding-like materials used in encapsulation applications, such as materials included in organic interposers, encapsulation supports, and other such components.

[0030] In various embodiments, elements associated with an IC can include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC can include those elements that are monolithically integrated within, mounted on, or connected to the IC. Depending on the components associated with the IC, the ICs described herein can be analog or digital and can be used in a variety of applications (such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc.). The ICs described herein can be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0031] In various embodiments of the present disclosure, the transistors described herein can be field effect transistors (FETs), e.g., MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator or nanoribbon or gate-all-around (GAA) FETs, the FET is a three-terminal device that includes a source terminal, a drain terminal, and a gate terminal and uses an electric field to control the current flowing through the device. The FET typically includes a channel material, source and drain regions provided in and / or above the channel material, and a gate stack that includes a gate electrode material (alternatively referred to as a "work function" material) provided over a portion of the channel material ("channel portion") between the source and drain regions, and optionally, also includes a gate dielectric material located between the gate electrode material and the channel material.

[0032] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, thereby facilitating the transmission of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, thereby facilitating the transmission of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". In this document, the nature of the described interconnects should be understood with reference to the signal medium associated with the interconnects. Thus, when used in reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing electrical connectivity to one or more elements associated with the IC and / or electrical connectivity between various such elements. In such cases, the term "interconnect" can refer to both electrical traces (sometimes also referred to as "lines", "wires", "metal lines", or "trenches") and conductive vias (sometimes also referred to as "vias" or "metal vias"). Sometimes, electrical conduction traces and electrical conduction vias can be referred to as "conductive traces" and "conductive vias" respectively, to emphasize the fact that these elements include a conductive material (e.g., metal). Similarly, when used in reference to a device that also operates on optical signals (e.g., a PIC), "interconnect" can also describe any element formed of an optically conductive material for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0033] As used herein, the term "optical element" includes arrangements fabricated in an IC for receiving, transforming, and / or transmitting optical signals as described herein. It can include optical conductors (e.g., waveguides), grating couplers, sources of electromagnetic radiation (e.g., lasers), and electro-optic devices (e.g., photodetectors).

[0034] The term "waveguide" refers to any structure that typically serves to confine and guide light from one location to another through a substrate material (e.g., silicon or glass). In various examples, the waveguide can be formed of silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70 - 80% (by weight) SiO2, 7 - 13% (by weight) B2O3, 4 - 8% (by weight) Na2O or K2O, and 2 - 8% (by weight) Al2O3), etc. Various techniques can be used to form waveguides, including but not limited to in-situ formation of waveguides. For example, in some embodiments, waveguides can be formed in-situ in glass using low-temperature glass-to-glass bonding or by laser direct writing (e.g., laser writing waveguides). In-situ formed waveguides can have lower loss characteristics.

[0035] The term "conductive trace" can be used to describe conductive elements isolated by an insulating material. Within an IC die, such insulating materials include the interlayer low-k dielectrics provided within the IC die. Within a package substrate and a printed circuit board (PCB), such insulating materials include organic materials (e.g., Ajinomoto Buildup Film (ABF), polyimide, or epoxy resin). Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0036] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To this end, vias can be provided that are substantially perpendicular to the plane of the IC die / chip or above the support structure of the IC structure, and the vias can interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0037] The term "package substrate" can be used to describe any substrate material that facilitates the encapsulation together of any collection of semiconductor dies and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate can be formed of any material, including but not limited to: insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. Additionally, as used herein, a package substrate can refer to a substrate that includes build-up layers (e.g., ABF layers).

[0038] The term "metallization stack" can be used to refer to one or more stacked interconnects used to provide connectivity to different circuit components of an IC die / chip and / or a package substrate.

[0039] As used herein, the "pitch" of an interconnect refers to the center-to-center distance between adjacent interconnects.

[0040] Based on the circumstances of a particular value as described herein or as known in the art, the terms "substantially", "close to", "about", "near to", and "approximate" generally refer to within + / - 20% of the target value (e.g., within + / - 5% or 10% of the target value).

[0041] Based on the circumstances of a particular value as described herein or as known in the art, terms indicating the orientation of individual elements (e.g., "coplanar", "perpendicular", "orthogonal", "parallel", or any other angle between elements) generally refer to within + / - 5% - 20% of the target value.

[0042] The term "connected" means a direct connection between the connected things (which can be one or more of a mechanical connection, an electrical connection, and / or a thermal connection) without any intermediate device, while the term "coupled" means a direct connection between the connected things or an indirect connection through one or more passive or active intermediate devices.

[0043] This specification uses the phrase "in an embodiment", which can refer to one or more embodiments in the same or different embodiments.

[0044] In addition, as used with respect to the embodiments of the present disclosure, the terms "comprising", "including", "having", etc. are synonymous.

[0045] The present disclosure may use perspective-based descriptions (such as "above", "below", "top", "bottom", and "side"); such descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments.

[0046] As used herein, the terms "on", "under", "between", and "upon" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. In addition, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as "on" a second layer refers to a layer in direct contact with the second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0047] As used herein, the term "disposed" means positioned, located, placed, and / or arranged, rather than any particular formation method.

[0048] When used with reference to a measurement range, the term "between" includes the end values of the measurement range.

[0049] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0050] Although certain elements may be referred to herein in the singular, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0051] Unless otherwise indicated, the use of ordinal adjectives such as "first", "second", and "third" to describe a common object only indicates different instances of similar objects being referenced and is not intended to imply that the objects so described must be in a given sequence in terms of time, space, rank, or in any other way.

[0052] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which embodiments that may be practiced are shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0053] The accompanying drawings are not necessarily to scale.

[0054] In the drawings, like reference numerals refer to the same or similar elements / materials shown, whereby, unless otherwise specified, the explanation of an element / material with a given reference numeral provided in the context of one drawing applies to other drawings in which an element / material with the same reference numeral may be shown. Additionally, the singular and plural forms of the reference numerals may be used with the reference numerals to denote a single element and multiple elements, respectively, of the same or similar type, kind, or category of elements.

[0055] Furthermore, in the drawings, some schematic illustrations of exemplary structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic illustrations may not reflect real-life process limitations, which may cause features not to appear so "ideal" when using images of, for example, appropriate characterization tools (such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometers) to examine any structure described herein. In such images of actual structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviation, dents or scratches, imperfect straight edges of materials, tapered vias or other openings, rounding of corners, or variations in the thickness of different material layers, accidental screw dislocations, edge dislocations, or combined dislocations within a (multiple) crystal region, and / or accidental dislocation defects of single atoms or atomic clusters. There may be other defects not listed here but common in the field of device fabrication and / or packaging.

[0056] Note that in the figures, various components (e.g., interconnections) are shown as aligned (e.g., at corresponding interfaces) merely for ease of illustration; in reality, some or all of them may be misaligned. Additionally, there may be other components in the assemblies (e.g., bonding pads, connection pads, metallizations, etc.) that are not shown in the figures to avoid clutter. Further, the figures are intended to show the relative arrangement of components within their assemblies, and, in general, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functionality, electrical connectivity, or thermal mitigation). For example, in some other embodiments, the assemblies shown in the figures may include more die and other electrical components. Additionally, although some components of the assemblies are shown in the figures as being planar rectangles or formed by rectangular parallelepipeds, this is merely for ease of illustration, and embodiments of these assemblies may be curved, circular, or other irregular shapes determined by and sometimes inevitable in the manufacturing processes used to fabricate the various components.

[0057] In the figures, specific numbers and arrangements of structures and components are presented for purposes of illustration, and any desired number or arrangement of such structures and components may exist in various embodiments.

[0058] Furthermore, unless otherwise specified, the structures shown in the figures may take any suitable form or shape depending on material characteristics, manufacturing processes, and operating conditions.

[0059] For convenience, if there is a series of figures designated by different letters (e.g., Figures 4A - 4I ), such a series may be referred to herein without using the letters. Similarly, if there is a series of reference numerals designated by different numbers or letters (e.g., 114-1, 114-2, 114-3, etc.), such a series may be referred to herein without using the numbers or letters (e.g., referred to as "114").

[0060] The various operations may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0061] Exemplary Embodiment

[0062] Figure 1A is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments. As Figure 1AAs shown, the microelectronic component 100 may include a die 114-1 located within a substrate 107, where the die 114-1 is not embedded within a cavity formed in the substrate 107. Instead, the die 114-1 is conformally coated with a dielectric material 112A (e.g., as indicated by the dashed line). Specifically, as Figure 1B shown, the substrate 107 may include a die 114-1 electrically coupled to a conductive via 108 in the substrate 107 through an interconnect 125, where the interconnect 125 is surrounded by an underfill material 126, and subsequently, the die 114-1 and the interconnect 125 are surrounded by a dielectric material 112A. The substrate 107 may include a dielectric material 112 and a conductive material 108 (e.g., as shown, lines / traces / pads / contacts (e.g., 108A) and vias (e.g., 108B)) located around the die 114-1 (e.g., above, below, and along the sides of the die 114-1), where the conductive material 108 is disposed within the dielectric material 112 to provide conductive vias horizontally (e.g., in the x and y directions) and vertically (e.g., in the z direction) through the substrate 107. As Figure 1B shown, the dielectric material 112A may be formed over and around the die 114-1, and subsequently, the dielectric material 112 of the substrate 107 may be formed in layers around the die 114-1 (e.g., at least a first dielectric material layer 112B, a second dielectric material layer 112C, and a third dielectric material layer 112D), and as Figure 1AAs shown, the layers of dielectric material 112 (e.g., layers 112A, 112B, 112C, and 112D of dielectric material) may be indistinguishable after formation. In some embodiments, dielectric material 112 may include an organic dielectric material, such as an organic stack film, polyimide, polyamide, polyacrylate, epoxy resin, polybenzoxazole, polyphenylene ether, polysiloxane, polynorbornene, or polyolefin. In some embodiments, the organic dielectric material is photoimageable, such as a photoimageable dielectric (PID), a liquid photoimageable polymer, or a dry film photoimageable polymer. In some embodiments, dielectric material 112 may include, for example, ceramics, an epoxy resin film with filler particles therein, glass, inorganic materials, or a combination of organic and inorganic materials. In some embodiments, dielectric material 112A may include the same dielectric material 112 in liquid form (which may be deposited to conformally cover die 114-1). Dielectric material 112A may include dielectric material 112 in liquid form. In some embodiments, dielectric material 112A is the same material as dielectric material 112. In some embodiments, dielectric material 112A is a different material from dielectric material 112. In some embodiments, conductive material 108 may include a metal (e.g., copper). In some embodiments, substrate 107 may include layers of dielectric material 112 / conductive material 108, wherein the lines / traces / pads / contacts (e.g., 108A) of conductive material 108 in one layer are electrically coupled to the lines / traces / pads / contacts (e.g., 108A) of conductive material 108 in an adjacent layer through vias (e.g., 108B) of conductive material 108 extending through dielectric material 112. Conductive element 108A may be referred to herein as a "conductive wire", "conductive trace", "conductive pad", or "conductive contact". Any suitable technique (e.g., as described below with reference to Figures 4A - 4I may be used to form substrate 107 including such layers.

[0063] Return Figure 1A, the substrate 107 may include a first surface 170-1 (e.g., a bottom surface) and an opposite second surface 170-2 (e.g., a top surface). The microelectronic component 100 may further include a material 104 located at the top surface 170-2 of the substrate 107 and / or at the bottom surface 170-1 of the substrate 107. The material 104 may include a solder mask material, such as an epoxy resin and an acrylic copolymer. In some embodiments, the thickness (e.g., z-height) of the material 104 may be between 2 microns and 100 microns (e.g., between 2 microns and 20 microns). The material 104 located at the top surface 170-1 and / or bottom surface 170-2 of the substrate 107 may act as a molded encapsulation layer and a surface insulation layer (e.g., a passivation layer), which may provide surface electrical insulation and may be compatible with solder-based or non-solder-based interconnections, as appropriate.

[0064] As Figure 1A shown, the substrate 107 may include a core 109 having a via-through-core 115, and a dielectric material 112 and a conductive material 108 may be present below the core 109. In some embodiments, as Figure 1B shown, the substrate 107 may not include the core 109 and / or the dielectric layer 112 located below the core 109. The core 109 may be formed of any suitable material, including glass, fiber-reinforced epoxy resin, organic dielectric material (such as epoxy resin, or phenolic resin, or polyimide resin reinforced with glass, polyaramide or nylon).

[0065] The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to one; in the figures, the layers are labeled in descending order from the respective first surface 170-1 and second surface 170-2 of the substrate 107 (e.g., layer N, layer N-1, layer N-2, layer N-3, etc.). Specifically, as Figure 1A shown, the substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3) located on the top and bottom surfaces of the core 109. A conductive via 111 passing through the material 104 located at the top surface 170-2 of the substrate 107 may be coupled (e.g., at the top surface of the dielectric material 112) to a conductive contact 108A in the N metal layers of the substrate 107.

[0066] Die 114-1 can be surrounded by the dielectric material 112 of the substrate 107. Die 114-1 can include a bottom surface (e.g., the surface facing the first surface 170-1) having conductive contacts 122, an opposite top surface (e.g., the surface facing the second surface 170-2) having conductive contacts 124, and through-silicon vias (TSVs) 117 that couple the respective conductive contacts 122, 124. Die 114-1 can be electrically coupled to a conductive trace 108A in metal layer N-2 of the substrate 107 located beneath the bottom of die 114-1 through an interconnect 125. In some embodiments, as shown, the interconnect 125 includes solder. In some embodiments, the pitch of the conductive contacts 122 located on the first die 114-1 can be between 25 microns and 250 microns. In some embodiments, the pitch of the conductive contacts 124 located on the first die 114-1 can be between 25 microns and 250 microns.

[0067] Figure 1A The microelectronic assembly 100 in [description] can further include an underfill material 126. In some embodiments, the underfill material 126 can extend around the associated interconnect 125 between the bottom surface of die 114-1 and the dielectric material 112 of layer N-2 of the substrate 107. The underfill material 126 can be an insulating material that flows between and around the interconnects 125 and then cures or solidifies to encapsulate the interconnects 125. The underfill material 126 can include any suitable material, such as capillary underfill, liquid dielectric material, epoxy-based underfill material with fillers. In some embodiments, the underfill material 126 does not include NCF. In some embodiments, as Figure 1A shown, the underfill material 126 can have a trapezoidal shape (e.g., sloping outward on the side facing the bottom surface). In some embodiments, as Figure 1B shown, the underfill material 126 can have a rectangular shape (e.g., having straight edges instead of sloping edges), where the outer rounded corners of the underfill material 126 are removed (e.g.) by an excimer laser.

[0068] Die 114-2 and 114-3 may include a set of conductive contacts 122 located on the bottom surface of the die (e.g., the surface facing the first surface 170-1). Die 114-1 may be electrically coupled to die 114-2 and 114-3 at the second surface 170-2 through an interconnect 120. Specifically, the conductive contacts 124 located on the top surface of die 114-1 may be coupled to the conductive contacts 122 located on the bottom surfaces of die 114-2 and 114-3 through the interconnect 120, through conductive vias 111 passing through the material 104, and through conductive vias 123 passing through the dielectric material 112 located at the top surface of die 114-1. The conductive contacts 122 located on the bottom surfaces of die 114-2 and 114-3 may also be electrically coupled to the conductive material 108 in the substrate 107 through the interconnect 120 and the conductive vias 111, and the conductive vias 111 pass through the material 104 to reach the conductive pads 108A in the N-metal layer adjacent to the top surface 170-2 of the substrate 107.

[0069] Die 114 may include other conductive paths (e.g., including lines and vias) and / or other circuitry (not shown) coupled to corresponding conductive contacts (e.g., conductive contacts 122, 124) located on the surface of die 114. The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, nitrogen oxides, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). In some embodiments, the insulating material of die 114 may include a semiconductor material, such as silicon, germanium, or group III-V materials (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in die 114 may include conductive traces and / or conductive vias, and may connect any of the conductive contacts (e.g., connecting multiple conductive contacts located on the same surface or different surfaces of die 114) in any suitable manner. Refer to the following Figure 8Discuss exemplary structures that may be included in die 114 disclosed herein. Conductive vias located in die 114 may be bounded by a liner material, such as an adhesive liner and / or a barrier liner as appropriate. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a monolithic silicon, fan-out or fan-in packaged die, or a die stack (e.g., stacked wafers, stacked dies, or stacked multi-layer dies).

[0070] In some embodiments, die 114 may include conductive vias to route power, ground, and / or signals to / from other dies 114 included in the microelectronic assembly 100. For example, die 114-1 may include: TSVs that include conductive material vias (e.g., metal vias that are isolated from the surrounding silicon or other semiconductor material by a barrier oxide); or other conductive vias through which power, ground, and / or signals may be transferred between the circuit board 102 and one or more dies 114 located "on top of" die 114-1 (e.g., in Figures 1A - 1B the embodiments, dies 114-2, 114-3). In some embodiments, die 114-1 may not route power and / or ground to dies 114-2; 114-3; instead, dies 114-2, 114-3 may be directly coupled to the power and / or ground lines located in the circuit board 102 through interconnects 150, conductive material 108, and interconnects 120 that are electrically coupled to the N metal layer in the substrate 107. In some embodiments, die 114-1 may be thicker than dies 114-2, 114-3. In some embodiments, die 114-1 may be thinner than dies 114-2, 114-3. In some embodiments, die 114-1 may be a memory device (e.g., as described below with reference to Figure 7 die 1502), or a high-speed serializer and deserializer (SerDes), such as a high-speed peripheral component interconnect (PCI). In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, dies 114-2, 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor.

[0071] Although specific numbers and arrangements of layers of dielectric material 112 / conductive material 108 are shown in the various figures in the drawings, these specific numbers and arrangements are illustrative only, and any desired number and arrangement of dielectric material 112 / conductive material 108 may be used. Additionally, although a specific number of layers (e.g., four layers) are shown in substrate 107, these layers may represent only a portion of substrate 107, e.g., additional layers (e.g., layers N-4, N-5, N-6, etc.) may be present.

[0072] Substrate 107 may be coupled to circuit board 102 via interconnect 150. Specifically, the top surface of circuit board 102 may include a set of conductive contacts 146. Conductive contacts 144 located on the bottom surface of substrate 107 may be electrically and mechanically coupled via interconnect 150 to conductive contacts 146 located on the top surface of circuit board 102. Interconnect 150 may be any suitable interconnect, including solder balls for a ball grid array arrangement (as shown), pins in a pin grid array arrangement, or pads in a land grid array arrangement. In some embodiments, interconnect 150 may not couple substrate 107 to circuit board 102, but may instead couple substrate 107 to another IC package, an interposer, or any other suitable component. Circuit board 102 may include an insulating material (e.g., a dielectric material formed in multiple layers as is known in the art) and one or more conductive vias (e.g., including conductive traces and / or conductive vias as shown) for routing power, ground, and signals through the dielectric material. For example, the circuit board may be a motherboard. When circuit board 102 is formed using standard printed circuit board (PCB) processes, circuit board 102 may include FR-4, and the conductive vias in circuit board 102 may be formed by patterned copper sheets separated by stacked layers of FR-4. The conductive vias located in circuit board 102 may be bounded by a liner material, such as an adhesive liner and / or a barrier liner (as appropriate). Any method known in the art for manufacturing circuit board 102 may be used, and such methods will not be discussed further herein for the sake of brevity.

[0073] In some embodiments, the circuit board 102 can be a lower density medium, and the die 114 can be a higher density medium or include regions with a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms that indicate that the conductive vias (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower density medium are larger and / or have a larger pitch than the conductive vias in the higher density medium. In some embodiments, an improved semi-additive process or semi-additive build-up process using advanced lithography (where small vertical interconnect features are formed through an advanced laser or lithography process) can be used to fabricate the higher density medium, while the lower density medium can be a PCB that can be fabricated using standard PCB processes (e.g., a standard subtractive process where unwanted copper is removed using an etching chemistry, and where rough vertical interconnect features are formed through a standard laser process). In other embodiments, semiconductor manufacturing processes (e.g., single damascene process or dual damascene process) can be used to fabricate the higher density medium. In some embodiments, additional dies can be disposed on the top surface of die 114-2. In some embodiments, additional components can be disposed on the top surfaces of dies 114-2, 114-3. Additional passive components (e.g., surface mount resistors, capacitors, and / or inductors) can be disposed on the top or bottom surface of the circuit board 102.

[0074] Figure 1A The microelectronic assembly 100 in Figure 1A can further include an underfill material 127. In some embodiments, the underfill material 127 can extend around the associated interconnects 120 between the dies 114-2, 114-3 and the top surface 170-2 of the substrate 107. The underfill material 127 can be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 can include capillary underfill, NCF, or molded underfill. In some embodiments, the underfill material 127 can include an epoxy flux that helps solder the die 114-2 to the substrate 107 when the interconnects 120 are formed and then polymerizes and encapsulates the interconnects 120. The underfill material 127 can be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize the stress caused by non-uniform thermal expansion in the microelectronic assembly 100 between the substrate 107 and the die 114-2. In some embodiments, the CTE of the underfill material 127 can have a value between the CTE of the substrate 107 (e.g., the CTE of the dielectric material 112 of the substrate 107) and the CTE of the die 114.

[0075] The interconnections disclosed herein (e.g., interconnections 120, 125, 150) can take any suitable form. Interconnection 120 can have a finer pitch than interconnection 150 in a microelectronic component. In some embodiments, a set of interconnections can include solder (e.g., solder bumps or solder balls that are subjected to thermal reflow to form the interconnections), e.g., as Figure 1A shown, interconnection 120 can include solder between a conductive contact 122 on the bottom surface of dies 114-2, 114-3 and a conductive via 111 on the top surface of substrate 107, and interconnection 150 can include solder between a conductive contact 144 on the bottom surface of substrate 107 and a conductive contact 146 on the top surface of circuit board 102. In some embodiments, a set of interconnections (e.g., interconnections 120, 125) can include small conductive bumps (e.g., copper bumps). In some embodiments, a set of interconnections can include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. An anisotropic conductive material can include conductive materials dispersed in a non-conductive material.

[0076] In some embodiments, the interconnections in microelectronic component 100 (e.g., the interconnection between conductive via 123 and conductive contact 124 on the top surface of die 114-1) can be metal-to-metal interconnections (e.g., copper-to-copper interconnections, or plated interconnections). In such embodiments, the interconnections can be joined together (e.g., at elevated pressure and / or temperature) without using an intervening solder or anisotropic conductive material. For example, any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) can include bonding pads, solder bumps, conductive pillars, or any other suitable conductive contact. In some embodiments, interconnections 120, 125 in microelectronic component 100 can be solder interconnections that include solder having a higher melting point than the solder included in some or all of the interconnections in interconnection 150. For example, when interconnections 120, 125 in microelectronic component 100 are formed before interconnection 150, the solder-based interconnections 120, 125 can use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while interconnection 150 can use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder can include: tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder can include: tin and bismuth (e.g., eutectic tin bismuth), or tin, silver, and bismuth. In some embodiments, the lower temperature solder can include indium, indium and tin, or gallium.

[0077] In some embodiments, the interconnects 125 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the interconnects 150 disclosed herein may have a pitch between 55 microns and 2000 microns, while the interconnects 120 disclosed herein may have a pitch between 25 microns and 250 microns (for the interconnects from die 114-2 to die 114-1) and may have a pitch between 25 microns and 250 microns (for the interconnects from die 114-2 to the substrate 107 (e.g., to the N metal layer)).

[0078] Although Figure 1A the microelectronic assembly 100 is depicted with a substrate having a particular number of dies 114 and conductive vias 108, the number and arrangement are illustrative only, and the microelectronic assembly 100 may include any desired number and arrangement of dies 114. Although Figure 1A die 114-1 is shown as a bilateral die and dies 114-2, 114-3 are shown as unilateral dies, dies 114-2, 114-3 may be bilateral dies, and die 114 may be a single-pitch die or a mixed-pitch die. In this context, a bilateral die refers to a die having connections on two surfaces. In some embodiments, a bilateral die may include through-silicon vias (TSVs) to form connections on two surfaces. Depending on design requirements and electrical requirements, the active surface of the bilateral die (which is the surface containing one or more active devices and most of the interconnects) may face either direction.

[0079] Figure 1A Many of the elements of the microelectronic assembly 100 in are included in other figures of the drawings; the discussion of these elements will not be repeated when discussing those figures, and any of these elements may take any form disclosed herein. Additionally, Figure 1A a number of elements included in the microelectronic assembly 100 are shown, but many of these elements may not be present in the microelectronic assembly 100. For example, in various embodiments, the core 109, the underfill material 127, and the circuit board 102 may not be included. In some embodiments, each microelectronic assembly in the microelectronic assemblies 100 disclosed herein may act as a system-in-package (SiP) that includes multiple dies 114 having different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0080] Figure 2 is a schematic cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. Except for the differences further described, the construction of the embodiment shown in the figure is similar to Figure 1AThe structure in. The microelectronic component 100 may include a substrate 107 having a molded underfill material (MUF) 113, and die 114-1 may be surrounded by the MUF material 113. The MUF material 113 may further surround the interconnect 125 (e.g., the MUF material 113 is located between the bottom surface of die 114-1 and the top surface of the dielectric material 112). The MUF material 113 may include a resin material with fillers or an epoxy-based material with fillers. The MUF material 113 may have a thickness (e.g., z-height) between 5 microns and 500 microns. As Figure 2 shown, the MUF material 113 may surround die 114-1 and may be located around and between the interconnects 125. Any suitable technique (e.g., as described below with reference to Figures 5A - 5F ) may be used to deposit the MUF material 113. The microelectronic component 100 may further include a conductive via 111 (e.g., a vertical conductive path in the z-direction) passing through the MUF material 113 and the material 104. Figure 2 The microelectronic component 100 in also shows three layers (e.g., layer N, layer N-1, and layer N-2) and a single underfill material 127 located between the bottom surfaces of die 114-2, 114-3 and the top surface 170-2 of the substrate 107.

[0081] Figure 3 is a schematic cross-sectional view of another exemplary microelectronic component according to some embodiments of the present disclosure. Except for the differences further described, the structure of the embodiment shown in the figure is similar to Figure 1A the structure in. The microelectronic component 100 may include a substrate 107 having die 114-1 encapsulated in a dielectric material 112, where die 114-1 is not located within a cavity or conformally coated with a dielectric material 112A (e.g., as shown in Figures 1A - 1B ). The microelectronic component 100 may further include a conductive via 111 (e.g., a vertical conductive path in the z-direction) passing through the dielectric material 112 and the material 104.

[0082] Exemplary Method

[0083] Any suitable technique may be used to fabricate the microelectronic component 100 disclosed herein. For example, Figures 4A - 4I is a side cross-sectional view of various stages of an exemplary process for manufacturing Figure 1A the microelectronic component 100 in according to various embodiments. Although the operations discussed below with reference to Figures 4A - 4I (and other figures in the drawings representing the manufacturing process) are shown in a specific order, these operations may be performed in any suitable order. Additionally, additional operations not shown may also be performed without departing from the scope of the present disclosure. Moreover, herein regardingFigures 4A - 4I Each of the operations discussed can be modified in accordance with the present disclosure to fabricate other portions of the microelectronic component 100 disclosed herein.

[0084] Figure 4A Shown is a component including a substrate 107 (e.g., a primary substrate 107) having portions of dielectric material 112 and patterned conductive material 108 on top and bottom surfaces of a core 109 having through-core vias 115. The patterned conductive material 108 can include at least N-2 metal layers having conductive traces 108A. In some embodiments, the substrate 107 may not include the core 109, and the primary substrate 107 may be formed directly on a carrier 401. The carrier 401 can include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments, can include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The component in Figure 4A can be fabricated using conventional package substrate manufacturing techniques (e.g., lamination of layers of dielectric material 112, etc.). The top surface of the dielectric material 112 can be planarized using chemical mechanical polishing (CMP) or any other suitable process.

[0085] Figure 4B Shown is the component after placing die 114-1 on the Figure 4A top surface of the component and forming an interconnect 125 between conductive contacts 122 located on the bottom surface of die 114-1 and conductive traces 108A in the N-2 metal layer of the substrate 107. Die 114-1 can also include conductive contacts 124 located on the top surface and TSVs (not shown). Die 114-1 can be placed using any suitable technique (e.g., an automated pick and place tool). The interconnect 125 can include solder such that the component can be subjected to a thermal reflow to form the interconnect 125. For example, the thermal reflow process can include a thermocompression bonding (TCB) process employing a flux and then a defluxing process to remove flux residues after bonding. Different from the manufacturing operation of embedding a bridge die in a cavity, since there are no space limitations for die placement and defluxing, the TCB process can be used for this process.

[0086] Figure 4C Shown is the component after dispensing underfill material 126 around and between the interconnects 125. The underfill material 126 can completely encapsulate each interconnect 125 after curing.

[0087] Figure 4DShows the assembly after removing the underfill material 126 that extends beyond the footprint of die 114-1. Any suitable technique (e.g., excimer laser process) can be used to remove the underfill material 126. In some embodiments, the excess underfill material 126 may not be removed (e.g., as shown in Figure 1A shown and subsequently Figures 4E - 4I shown).

[0088] Figure 4E Shows the assembly after conformally coating die 114-1 including the underfill material 126 with the dielectric material 112A. The dielectric material 112A can be deposited using any suitable technique (e.g., slit coating, spraying, jet dispensing, or lamination, among others). In some embodiments, for example, when die 114-1 is thin and the z-height difference between the top surface of die 114-1 and the top surface of the dielectric material 112 at this portion of the substrate 107 is minimized, the dielectric material 112A can be conformally coated by vacuum lamination.

[0089] Figure 4F Shows the assembly after forming a lower portion of the substrate 107 on the top surface of the assembly in Figure 4E by forming a layer of the dielectric material 112 and forming an N-1 metal layer. The assembly in Figure 4F can be fabricated using conventional packaged substrate manufacturing techniques.

[0090] Figure 4G Shows the assembly after forming a lower portion of the substrate 107 on the top surface of the assembly in Figure 4F by forming a layer of the dielectric material 112 and forming an N metal layer. The assembly in Figure 4G can be fabricated using conventional packaged substrate manufacturing techniques. In some embodiments, the top surfaces of the dielectric materials 112, 112A can be planarized using CMP or any other suitable process.

[0091] Figure 4H Shows the assembly in Figure 4GOn the top surface of the components in, material 104 is formed, a via opening is formed to expose the underlying conductive material 108 of the N metal layer, and the conductive contact 124 located on the top surface of die 114-1. After depositing conductive material in the via opening to form the conductive via 111, the components. Material 104 can be deposited using any suitable technique (e.g., including by lamination, spraying, spin coating, or slot coating). The via opening can be formed using any suitable process (including photolithography, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching). The via opening can have any suitable shape. For example, as shown, the via opening can have substantially vertical sidewalls to form a rectangular via; or can have slanted sidewalls to form a conical via. The shape of the via opening can depend on the process used to form the via opening (e.g., photolithography process for rectangular vias and laser drilling process for conical vias). The conductive material can include any suitable metal (e.g., copper) and can be deposited using any suitable technique (e.g., electroplating).

[0092] Figure 4I Shows the die 114-2, 114-3 electrically coupled to the Figure 4H top surface of the components in, depositing the underfill material 127, from Figure 4H removing the carrier 401 from the components in, forming a portion of the substrate 107 under the core 109, and depositing solder 136 on the bottom surface of the conductive contact 144. If multiple components are manufactured together, these components can be singulated. As shown, Figure 4I the components in themselves can be the microelectronic component 100. Further manufacturing operations can be performed on Figure 4I the microelectronic component 100 in to form other microelectronic components 100; for example, similar to Figure 1A by forming the interconnect 150 to attach the circuit board 102 to the Figure 4I bottom surface of the microelectronic component 100 in.

[0093] Figures 5A - 5F is a side cross-sectional view of various stages in an exemplary process for manufacturing a microelectronic component 100 similar to the Figure 2 microelectronic component 100 in according to various embodiments. Figure 5A Shows a component including a substrate 107 (e.g., the primary substrate 107) having dielectric material 112 and patterned conductive material 108 on the top and bottom surfaces of a core 109 having through-core vias 115. The patterned conductive material 108 can include at least N-1 metal layers having conductive traces 108A. The primary substrate 107 does not include a core (e.g., Figure 2The core 109) therein and is formed directly on the carrier 501. The carrier 501 can include any suitable material for providing mechanical stability during manufacturing operations and, in some embodiments, can include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). Conventional packaging substrate manufacturing techniques (e.g., lamination of layers of dielectric material 112, etc.) can be used to manufacture Figure 5A the components therein. The top surface of the dielectric material 112 can be planarized using chemical mechanical polishing (CMP) or any other suitable process.

[0094] Figure 5B shows the components after placing die 114-1 on Figure 5A the top surface of the components therein and forming an interconnect 125 between the conductive contact 122 located on the bottom surface of die 114-1 and the conductive trace 108A in the N-1 metal layer of the substrate 107. Die 114-1 can also include a conductive contact 124 located on the top surface and TSVs (not shown). Die 114-1 can be placed using any suitable technique (e.g., an automated pick and place tool). The interconnect 125 can include solder such that the components can undergo a thermal reflow to form the interconnect 125. For example, the thermal reflow process can include a thermocompression bonding (TCB) process using a flux and then a defluxing process to remove flux residues after bonding. Different from the manufacturing operation of embedding a bridge die in a cavity, since there are no spatial limitations on die placement and defluxing, the TCB process can be used for this process.

[0095] Figure 5C shows the components after Figure 5B depositing the MUF material 113 on the top surface of the components in Figure 2 therein, around die 114-1, and around and between the interconnects 125. The MUF material 113 can be deposited using any suitable technique (e.g., a compression molding process). As described above with reference to

[0096] Figure 5D shows the components after Figure 5CA component in which material 104 is formed on the top surface of the component and after forming the N-metal layer. The N-metal layer can be formed by forming via openings to expose the underlying conductive material 108 of the N-1 metal layer and the conductive contact 124 on the top surface of die 114-1, and depositing conductive material in the via openings to form conductive vias 111. The material 104 can be deposited using any suitable technique (e.g., including by lamination, spraying, spin coating, or slot coating). The via openings can be formed using any suitable process (including photolithography, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching). The via openings can have any suitable shape. For example, as shown, the via openings can have substantially vertical sidewalls to form rectangular vias; or can have slanted sidewalls to form conical vias. The shape of the via openings can depend on the process used to form the via openings (e.g., photolithography process for rectangular vias and laser drilling process for conical vias). The conductive material can include any suitable metal (e.g., copper) and can be deposited using any suitable technique (e.g., electroplating).

[0097] Figure 5E Shows a component after electrically coupling die 114-2, 114-3 to the Figure 5D top surface of the component in and depositing underfill material 127 around the interconnect 120.

[0098] Figure 5F Shows a component after Figure 5E removing the carrier 501 from the component in and depositing solder 136 on the bottom surface of the conductive contact 144. If multiple components are fabricated together, the components can be singulated. As shown, Figure 5F the component in itself can be a microelectronic component 100. Further manufacturing operations can be performed on Figure 5F the microelectronic component 100 in to form other microelectronic components 100; for example, similar to Figure 1B , by forming an interconnect 150 to attach a circuit board 102 to the Figure 5F bottom surface of the microelectronic component 100 in.

[0099] Figures 6A - 6E Is a side cross-sectional view of various stages in an exemplary process for manufacturing Figure 3 the microelectronic component 100 in according to various embodiments. Figure 6AShows an assembly including a substrate 107 (e.g., a primary substrate 107) having portions of dielectric material 112 and patterned conductive material 108 on the top and bottom surfaces of a core 109 with through-core vias 115. The patterned conductive material 108 may include at least N-2 metal layers having conductive traces 108A. In some embodiments, the substrate 107 may not include the core 109, and the primary substrate 107 may be formed directly on a carrier 601. The carrier 601 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The assembly in Figure 6A can be manufactured using conventional package substrate manufacturing techniques (e.g., lamination of layers of dielectric material 112, etc.). The top surface of the dielectric material 112 can be planarized using chemical mechanical polishing (CMP) or any other suitable process.

[0100] Figure 6B Shows the assembly after placing die 114-1 on the top surface of the assembly in Figure 4A , forming an interconnect 125 between a conductive contact 122 on the bottom surface of die 114-1 and a conductive trace 108A in the N-2 metal layer of substrate 107, and dispensing an underfill material 126 around and between the interconnects 125. Die 114-1 may also include conductive contacts 124 on the top surface and TSVs (not shown). Die 114-1 can be placed using any suitable technique (e.g., an automated pick and place tool). The interconnect 125 may include solder such that the assembly can undergo a thermal reflow to form the interconnect 125. For example, the thermal reflow process may include a thermocompression bonding (TCB) process using a flux and then a defluxing process to remove flux residues after bonding. Different from the manufacturing operation of embedding a bridge die in a cavity, the TCB process can be used for this process since there are no space limitations for die placement and defluxing. The underfill material 126 can completely encapsulate each interconnect 125 after curing. In some embodiments, as described above with reference to Figure 4D , the underfill material 126 extending beyond the footprint of die 114-1 can be removed.

[0101] Figure 6C Shows the assembly after depositing a layer of dielectric material 112 on the top surface of the assembly in Figure 6B , around die 114-1 and the underfill material 126. The assembly in Figure 4GComponents in. In some embodiments, the dielectric material 112 can be deposited over the top surface of die 114-1 and can be removed and planarized by mechanical grinding or CMP.

[0102] Figure 6D Shows after forming material 104 on the top surface of the components in Figure 6C forming via openings to expose the underlying conductive material 108 of the N-1 metal layer, and the conductive contacts 124 located on the top surface of die 114-1, depositing conductive material in the via openings to form conductive vias 111 to form the N metal layer. Material 104 can be deposited using any suitable technique (e.g., including by lamination, spraying, spin coating, or slot coating). The via openings can be formed using any suitable process (including photolithography, laser drilling (e.g., laser ablation using an excimer laser), or plasma etching). The via openings can have any suitable shape. For example, as shown, the via openings can have substantially vertical sidewalls to form rectangular vias; or can have slanted sidewalls to form conical vias. The shape of the via openings can depend on the process used to form the via openings (e.g., photolithography for rectangular vias and laser drilling for conical vias). The conductive material can include any suitable metal (e.g., copper) and can be deposited using any suitable technique (e.g., electroplating).

[0103] Figure 6E Shows after electrically coupling die 114-2, 114-3 to Figure 6D the top surface of the components in, depositing underfill material 127, removing the carrier 601 from Figure 6D the components in, forming the portion of substrate 107 located beneath core 109, and depositing solder 136 on the bottom surface of the conductive contacts 144. If multiple components are fabricated together, the components can be singulated. As shown, Figure 6E the components in themselves can be the microelectronic component 100. Further manufacturing operations can be performed on Figure 6E the microelectronic component 100 in to form other microelectronic components 100; for example, similar to Figure 3 , by forming interconnects 150 to attach the circuit board 102 to the Figure 6E bottom surface of the microelectronic component 100 in.

[0104] Exemplary Apparatus and Components

[0105] The microelectronic component 100 disclosed herein can be included in any suitable electronic component. Figures 7 - 10Various examples of devices that may include or be included in any of the microelectronic assemblies 100 disclosed herein are shown.

[0106] Figure 7 1 is a top view of a wafer 1500 and die 1502 (e.g., any suitable die 114) that may be included in any of the microelectronic assemblies 100 disclosed herein. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete “chips” of a semiconductor product. Die 1502 may be any of the die 114 disclosed herein. Die 1502 may include one or more transistors (e.g., the transistors discussed below). Figure 8 1640), supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed of multiple memory devices may be coupled to a processing device (e.g., Figure 10 The processing device 1802 in the memory device or other logic units configured to store information in the memory device or execute instructions stored in the storage array are formed on the same die 1502. In some embodiments, the die 1502 (e.g., die 114) can be a central processing unit, a radio frequency chip, a power converter, or a network processor. The individual microelectronic assemblies in the microelectronic assemblies 100 disclosed herein can be manufactured using die-to-wafer assembly technology, in which some of the dies 114 are attached to the wafer 1500 including other dies in the die 114, and the wafer 1500 is then singulated.

[0107] Figure 8is a cross-sectional side view of an IC device 1600 that can be included in any of the microelectronic components (e.g., in any of the dies 114) of the microelectronic component 100 disclosed herein. One or more of the IC devices in the IC device 1600 can be included in one or more dies 1502 ( Figure 7 ). The IC device 1600 can be formed on a die substrate 1602 (e.g., Figure 7 the wafer 1500 in), and can be included in a die (e.g., Figure 7 the die 1502 in). The die substrate 1602 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). For example, the die substrate 1602 can include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, an alternative material can be used to form the die substrate 1602, which can or cannot be combined with silicon, including but not limited to: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the die substrate 1602. Although some examples of materials that can form the die substrate 1602 are described herein, any material that can serve as a basis for the IC device 1600 can be used. The die substrate 1602 can be a singulated die (e.g., Figure 7 the die 1502 in) or a part of a wafer (e.g., Figure 7 the wafer 1500 in).

[0108] The IC device 1600 can include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 can include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 can include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the current flow between the S / D regions 1620 in the transistor 1640, and one or more S / D contacts 1624 for routing electrical signals to / from the S / D regions 1620. The transistor 1640 can include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 1640 is not limited to Figure 8The types and configurations depicted, and may include a wide variety of other types and configurations (e.g., planar transistors, non-planar transistors, or a combination of both). Non-planar transistors can include FinFET transistors (e.g., double-gate transistors or triple-gate transistors) and gate-all-around transistors or fully gate-all-around transistors (e.g., nanoribbon and nanowire transistors).

[0109] Each transistor 1640 can include a gate 1622 formed by at least two layers (i.e., a gate dielectric and a gate electrode). The gate dielectric can include a single layer or a stack of layers. One or more layers can include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric to improve its quality when using high-k materials.

[0110] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode can be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers can be included for other purposes, such as barrier layers. For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to: ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0111] In some embodiments, when viewed in cross-section along the source-channel-drain direction of the transistor 1640, the gate electrode may be composed of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1602 and not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0112] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack therebetween. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The processes for forming the sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0113] The S / D regions 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 1602 to form the S / D regions 1620. An annealing process may follow the ion implantation process, which activates the dopant and causes it to diffuse further into the die substrate 1602. In the latter process, the die substrate 1602 may first be etched to form a recess at the location of the S / D regions 1620. Then, an epitaxial deposition process may be performed to fill the recess with the material used to fabricate the S / D regions 1620. In some embodiments, the S / D regions 1620 may be made using a silicon alloy (such as silicon germanium or silicon carbide). In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (such as germanium or III-V materials or alloys) may be used to form the S / D regions 1620. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1620.

[0114] It can be achieved through one or more interconnect layers disposed on the device layer 1604 (at Figure 8The interconnect layers 1606-1610 (shown in ) route electrical signals (such as power and / or input / output (I / O) signals) to the devices (such as transistor 1640) of the device layer 1604 and / or route electrical signals from the devices of the device layer 1604. For example, the conductive features (such as gate 1622 and S / D contact 1624) of the device layer 1604 can be electrically coupled to the interconnect structure 1628 of the interconnect layers 1606-1610. One or more interconnect layers 1606-1610 can form the metallization stack (also referred to as the "ILD stack") 1619 of the IC device 1600.

[0115] The interconnect structure 1628 can be arranged within the interconnect layers 1606-1610 to route electrical signals according to a variety of designs; specifically, the arrangement is not limited to Figure 8 the specific configuration of the interconnect structure 1628 depicted in. Although Figure 8 a specific number of interconnect layers 1606-1610 are depicted in, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than the depicted interconnect layers.

[0116] In some embodiments, the interconnect structure 1628 can include wires 1628a and / or vias 1628b filled with a conductive material (such as metal). The wires 1628a can be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of the die substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a can route electrical signals in a direction in and out of the page from the Figure 8 perspective. The vias 1628b can be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b can electrically couple the wires 1628a of different interconnect layers 1606-1610 together.

[0117] As Figure 8 shown, the interconnect layers 1606-1610 can include a dielectric material 1626 disposed between the interconnect structures 1628. In some embodiments, the dielectric material 1626 between the interconnect structures 1628 in different interconnect layers disposed in the interconnect layers 1606-1610 can have different compositions; in other embodiments, the compositions of the dielectric material 1626 between different interconnect layers 1606-1610 can be the same.

[0118] The first interconnect layer 1606 (referred to as Metal 1 or "M1") can be formed directly on the device layer 1604. In some embodiments, as shown, the first interconnect layer 1606 can include lines 1628a and / or vias 1628b. The lines 1628a of the first interconnect layer 1606 can be coupled to the contacts of the device layer 1604 (e.g., S / D contacts 1624).

[0119] The second interconnect layer 1608 (referred to as Metal 2 or "M2") can be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 can include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 to the lines 1628a of the first interconnect layer 1606. Although, for clarity, the lines 1628a and vias 1628b are structurally delineated within each interconnect layer (e.g., within the second interconnect layer 1608) by lines, in some embodiments, the lines 1628a and vias 1628b can be continuous structurally and / or materially (e.g., filled simultaneously during a dual-damascene process).

[0120] The third interconnect layer 1610 (referred to as Metal 3 or "M3") (and additional interconnect layers, as needed) can be continuously formed on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher in the hierarchy" (i.e., farther from the device layer 1604) in the metallization stack 1619 in the IC device 1600 can be thicker.

[0121] The IC device 1600 can include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606 - 1610. In Figure 8 which, the conductive contacts 1636 are shown as taking the form of bond pads. The conductive contacts 1636 can be electrically coupled to the interconnect structure 1628 and are configured to route the electrical signals of the (multiple) transistors 1640 to other external devices. For example, a solder joint can be formed on one or more of the conductive contacts 1636 to mechanically couple and / or electrically couple the chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 can include additional or alternative structures for routing the electrical signals from the interconnect layers 1606 - 1610; for example, the conductive contacts 1636 can include other similar features (e.g., pillars) for routing the electrical signals to external components.

[0122] In some embodiments where the IC device 1600 is a dual-sided die (e.g., similar to die 114-1), the IC device 1600 may include another metallization stack (not shown) located on opposite sides of the (one or more) device layers 1604. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1606-1610 to provide a conductive path (e.g., including conductive lines and vias) between the (one or more) device layers 1604 and additional conductive contacts (not shown) located on a side of the IC device 1600 opposite the conductive contact 1636.

[0123] In other embodiments where the IC device 1600 is a dual-sided die (e.g., similar to die 114-1), the IC device 1600 may include one or more TSVs that pass through the die substrate 1602; these TSVs may contact the (one or more) device layers 1604 and may provide a conductive path between the (one or more) device layers 1604 and additional conductive contacts (not shown) located on a side of the IC device 1600 opposite the conductive contact 1636.

[0124] Figure 9 FIG. 17A is a cross-sectional side view of an IC device assembly 1700 that may include any of the microelectronic components 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be the microelectronic component 100. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and on an opposite second side 1742 of the circuit board 1702; generally, components may be disposed on one or both of the sides 1740 and 1742. Any IC package in the IC package discussed below with reference to the IC device assembly 1700 may take the form of any suitable embodiment of the microelectronic component 100 disclosed herein.

[0125] In some embodiments, the circuit board 1702 may be a PCB that includes a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally, in combination with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments, the circuit board 1702 may be, for example, a circuit board.

[0126] Figure 9The IC device assembly 1700 shown in [Figure] includes an on - interposer package structure 1736 coupled to the first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 can electrically and mechanically couple the on - interposer package structure 1736 to the circuit board 1702 and can include solder balls (as Figure 9 shown), male and female parts of a socket, an adhesive, underfill material, and / or any other suitable electrical coupling and / or mechanical coupling structure.

[0127] The on - interposer package structure 1736 can include an IC package 1720 coupled to an interposer 1704 by a coupling component 1718. The coupling component 1718 can take any suitable form for the application, such as the form discussed above with reference to the coupling component 1716. Although Figure 9 a single IC package 1720 is shown, multiple IC packages can be coupled to the interposer 1704; in fact, additional interposers can be coupled to the interposer 1704. The interposer 1704 can provide an intermediate substrate for bridging the circuit board 1702 and the IC package 1720. For example, the IC package 1720 can be or include a die ( Figure 7 the die 1502 in [Figure]), an IC device (e.g., Figure 8 the IC device 1600 in [Figure]) or any other suitable component. Generally, the interposer 1704 can extend connections to a wider pitch or re - route connections to different connections. For example, the interposer 1704 can couple the IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling component 1716 for coupling to the circuit board 1702. In the Figure 9 illustrated embodiment, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 can be attached to the same side of the interposer 1704. In some embodiments, three or more components can be interconnected by means of the interposer 1704.

[0128] In some embodiments, the interposer 1704 can be formed as a printed circuit board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the interposer 1704 can be formed of epoxy resin, glass fiber-reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials (such as polyimide). In some embodiments, the interposer 1704 can be formed of alternative rigid or flexible materials that can include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 can include metal interconnects 1708 and vias 1710, which include but are not limited to TSVs 1706. The interposer 1704 can also include embedded devices 1714, which include both passive and active devices. Such devices can include but are not limited to: capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 1704. The on-interposer package structure 1736 can take the form of any on-interposer package structure known in the art.

[0129] The IC device assembly 1700 can include an IC package 1724 coupled to a first side 1740 of the circuit board 1702 by a coupling component 1722. The coupling component 1722 can take the form of any of the embodiments discussed above with reference to the coupling component 1716, and the IC package 1724 can take the form of any of the embodiments discussed above with reference to the IC package 1720.

[0130] Figure 9 The IC device assembly 1700 shown in includes a stacked package structure 1734 coupled to a second side 1742 of the circuit board 1702 by a coupling component 1728. The stacked package structure 1734 can include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 can take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 can take the form of any of the embodiments of the IC package 1720 discussed above. The stacked package structure 1734 can be constructed according to any stacked package structure known in the art.

[0131] Figure 10is a block diagram of an exemplary electrical device 1800 that can include one or more of the microelectronic components 100 disclosed herein. For example, any suitable component of the components of the electrical device 1800 can include one or more of the IC device components 1700, IC devices 1600, or die 1502 disclosed herein and can be disposed in any of the microelectronic components 100 disclosed herein. Figure 10 A number of components included in the electrical device 1800 are shown, but any one or more of these components can be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1800 can be attached to one or more motherboards. In some embodiments, some or all of these components can be fabricated onto a single system-on-chip (SoC) die.

[0132] Additionally, in various embodiments, the electrical device 1800 may not include Figure 10 one or more of the components shown, but the electrical device 1800 can include interface circuitry for coupling to one or more components. For example, the electrical device 1800 may not include the display device 1806, but can include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 can be coupled. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but can include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 can be coupled.

[0133] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The electrical device 1800 may include a memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drives. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. The memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0134] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for transmitting data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain wires.

[0135] The communication chip 1812 can implement any wireless standard or protocol among a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). A broadband wireless access (BWA) network compatible with IEEE 802.16 is generally referred to as a WiMAX network. WiMAX is an acronym representing Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed the compliance and interoperability tests for the IEEE 802.16 standard. The communication chip 1812 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 1812 can operate according to Enhanced Data rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN) or Evolved UTRAN (E-UTRAN). The communication chip 1812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and later generations. In other embodiments, the communication chip 1812 can operate according to other wireless protocols. The electrical device 1800 can include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0136] In some embodiments, the communication chip 1812 can manage wired communications, such as electrical, optical or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 can include multiple communication chips. For example, the first communication chip 1812 can be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 1812 can be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, the first communication chip 1812 can be dedicated to wireless communications, and the second communication chip 1812 can be dedicated to wired communications.

[0137] The electrical device 1800 may include a battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1800 to an energy source (e.g., an AC line power) separate from the electrical device 1800.

[0138] The electrical device 1800 may include a display device 1806 (or a corresponding interface circuitry as discussed above). The display device 1806 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0139] The electrical device 1800 may include an audio output device 1808 (or a corresponding interface circuitry as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0140] The electrical device 1800 may include an audio input device 1824 (or a corresponding interface circuitry as discussed above). The audio input device 1824 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0141] The electrical device 1800 may include a GPS device 1818 (or a corresponding interface circuitry as discussed above). As is known in the art, the GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800.

[0142] The electrical device 1800 may include other output devices 1810 (or a corresponding interface circuitry as discussed above). Examples of the other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0143] The electrical device 1800 may include other input devices 1820 (or a corresponding interface circuitry as discussed above). Examples of the other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (e.g., a mouse), a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0144] The electrical device 1800 can have any desired form factor, such as a computing device or a handheld, portable, or mobile computing device (e.g., a cell phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing components, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 can be any other electronic device that processes data.

[0145] The following paragraphs provide various examples of the embodiments disclosed herein.

[0146] Example 1 is a microelectronic component, comprising: a substrate including a material and a conductive via through the material, the material including an organic dielectric material; and a microelectronic component having a first surface and an opposite second surface, the first surface of the microelectronic component being electrically coupled to the conductive via in the material through an interconnect, the interconnect including solder and being surrounded by a capillary underfill material, and the microelectronic component and the capillary underfill material being surrounded by the material of the substrate.

[0147] Example 2 can include the subject matter of Example 1 and can further specify that the organic dielectric material includes a build-up material, polyimide, polyamide, polyacrylate, epoxy resin, polybenzoxazole, polyphenylene ether, polysiloxane, polynorbornene, polyolefin, or a photoimageable polymer.

[0148] Example 3 can include the subject matter of Example 1 or 2 and can further specify that the material includes a plurality of organic dielectric materials.

[0149] Example 4 can include the subject matter of Example 1 or 2 and can further specify that the material includes a first organic dielectric material and a second organic dielectric material different from the first organic dielectric material, and the second organic dielectric material surrounds the microelectronic component and the capillary underfill material and is located between the microelectronic component and the capillary underfill material and the first organic dielectric material.

[0150] Example 5 can include the subject matter of any one of Examples 1-4 and can further specify that the interconnect has a pitch between 25 micrometers and 250 micrometers.

[0151] Example 6 can include the subject matter of any one of Examples 1-5 and can further specify that the interconnect does not include a non-conductive film.

[0152] Example 7 may include the subject matter of any one of Examples 1-6, and may further specify that the microelectronic component is a first microelectronic component, and the interconnect is a first interconnect, and the microelectronic assembly may further include a second microelectronic component that is electrically coupled to a second surface of the first microelectronic component through a second interconnect, and the second interconnect includes solder.

[0153] Example 8 may include the subject matter of Example 7, and may further specify that the second interconnect has a pitch between 25 micrometers and 250 micrometers.

[0154] Example 9 may include the subject matter of any one of Examples 1-8, and may further specify that the conductive via includes a conductive trace that is parallel to a first surface and a second surface of the microelectronic component and extends through the material along a side surface of the microelectronic component.

[0155] Example 10 may include the subject matter of any one of Examples 1-9, and may further specify that the substrate further includes: a core; and conductive vias that pass through the core and are electrically coupled to the microelectronic component through conductive vias passing through the material.

[0156] Example 11 may include the subject matter of any one of Examples 1-10, and may further specify that the substrate includes a third surface and an opposite fourth surface, and the microelectronic assembly may further include a circuit board that is electrically coupled to the third surface of the substrate.

[0157] Example 12 is a microelectronic assembly including: a first layer of a substrate, the first layer including a first material and a first conductive via passing through the first material, the first material including an organic dielectric material; a second layer of the substrate located on the first layer, the second layer including a second material and a second conductive via passing through the second material, the second material including a molded underfill material; and a microelectronic component having a first surface and an opposite second surface, the microelectronic component being located in the second layer of the substrate, the first surface of the microelectronic component being electrically coupled to the first conductive via in the first layer through an interconnect, the interconnect including solder, and the microelectronic component and the interconnect being surrounded by the second material.

[0158] Example 13 may include the subject matter of Example 12, and may further specify that the interconnect has a pitch between 25 micrometers and 250 micrometers.

[0159] Example 14 may include the subject matter of Example 12 or 13, and may further specify that the interconnect does not include a non-conductive film.

[0160] Example 15 may include the subject matter of any one of Examples 12-14, and may further specify that the microelectronic component is a first microelectronic component, and the interconnect is a first interconnect, and the microelectronic assembly may further include a second microelectronic component, the second microelectronic component being electrically coupled to a second surface of the first microelectronic component through a second interconnect, the second interconnect including solder.

[0161] Example 16 may include the subject matter of Example 15, and may further specify that the second interconnect has a pitch between 25 microns and 250 microns.

[0162] Example 17 may include the subject matter of any one of Examples 12-16, and may further specify that the first conductive via includes a conductive via and a conductive trace, and the second conductive via includes a conductive via and does not include a conductive trace.

[0163] Example 18 may include the subject matter of any one of Examples 12-17, and may further specify that the substrate further includes: a core; and a conductive via, the conductive via passing through the core and being electrically coupled to the microelectronic component through a first conductive via passing through a first material.

[0164] Example 19 may include the subject matter of any one of Examples 12-18, and may further include a circuit board electrically coupled to a first layer of the substrate.

[0165] Example 20 is a microelectronic assembly, including: a first layer of a substrate, the first layer including a material and a first conductive via passing through the material, the material including an organic dielectric material; a second layer of the substrate located on the first layer, the second layer including a material and a second conductive via passing through the material; and a microelectronic component, the microelectronic component having a first surface and an opposite second surface, the microelectronic component being located in the second layer of the substrate, the first surface of the microelectronic component being electrically coupled to the first conductive via in the first layer through an interconnect, the interconnect including solder and being surrounded by a capillary underfill material, and the microelectronic component and the capillary underfill material being surrounded by the material.

[0166] Example 21 may include the subject matter of Example 20, and may further specify that the interconnect has a pitch between 25 microns and 250 microns.

[0167] Example 22 may include the subject matter of Example 20 or 21, and may further specify that the interconnect does not include a non-conductive film.

[0168] Example 23 may include the subject matter of any one of Examples 20-22, and may further specify that the microelectronic component is a first microelectronic component, and the interconnect is a first interconnect, and the microelectronic assembly may further include a second microelectronic component, the second microelectronic component being electrically coupled to a second surface of the first microelectronic component through a second interconnect, the second interconnect including solder.

[0169] Example 24 may include the subject matter of Example 23 and may also specify that the second interconnect has a pitch between 25 microns and 250 microns.

[0170] Example 25 may include the subject matter of any one of Examples 20-24 and may also specify that the first conductive via includes a conductive via and a conductive trace, and the second conductive via includes a conductive via and does not include a conductive trace.

[0171] Example 26 may include the subject matter of any one of Examples 20-25 and may also specify that the substrate further includes: a core; and a conductive via that passes through the core and is electrically coupled to the microelectronic component through the first conductive via passing through the material.

[0172] Example 27 may include the subject matter of any one of Examples 20-26 and may also include a circuit board electrically coupled to the first layer of the substrate through a third interconnect.

[0173] Example 28 may include the subject matter of Example 27 and may also specify that the pitch of the third interconnect is between 55 microns and 2000 microns.

[0174] Example 29 may include the subject matter of any one of Examples 20-28 and may also specify that the material includes a plurality of organic dielectric materials.

[0175] Example 30 may include the subject matter of any one of Examples 20-29 and may also specify that the microelectronic component includes a semiconductor die.

Claims

1. A microelectronic assembly comprising: a substrate comprising a material and a conductive path through the material, wherein the material comprises an organic dielectric material; and A microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive path in the material through an interconnect, wherein the interconnect comprises solder and is surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.

2. The microelectronic assembly according to claim 1, wherein: The organic dielectric material includes a build-up material, polyimide, polyamide, polyacrylate, epoxy resin, polybenzoxazole, polyphenylene ether, polysiloxane, polynorbornene, polyolefin or a photoimageable polymer.

3. The microelectronic assembly according to claim 1, wherein: The materials include various organic dielectric materials.

4. The microelectronic assembly according to claim 1, wherein: The material includes a first organic dielectric material and a second organic dielectric material different from the first organic dielectric material, and wherein the second organic dielectric material surrounds the microelectronic component and the capillary underfill material and is located between the microelectronic component and the capillary underfill material and the first organic dielectric material.

5. The microelectronic assembly according to claim 1, wherein: The interconnects have a pitch between 25 and 250 microns.

6. The microelectronic assembly according to claim 1, wherein: The interconnect does not include a non-conductive film.

7. The microelectronic assembly of claim 1, wherein: The microelectronic component is a first microelectronic component, and wherein the interconnect is a first interconnect, and the microelectronic assembly further comprises: A second microelectronic component is electrically coupled to the second surface of the first microelectronic component by a second interconnect, the second interconnect comprising solder.

8. The microelectronic assembly according to claim 7, wherein: The second interconnect has a pitch between 25 microns and 250 microns.

9. A microelectronic assembly according to any one of claims 1 to 8, wherein: The conductive pathway includes a conductive trace parallel to the first and second surfaces of the microelectronic component and extending through the material along a side surface of the microelectronic component.

10. A microelectronic assembly according to any one of claims 1 to 8, wherein: The substrate further comprises: core; and A conductive via passes through the core and is electrically coupled to the microelectronic component through the conductive path through the material.

11. A microelectronic assembly comprising: a first layer of a substrate, the first layer comprising a first material and a first conductive path through the first material, the first material comprising an organic dielectric material; a second layer of the substrate located on the first layer, the second layer comprising a second material and a second conductive path through the second material, the second material comprising a molded underfill material; as well as A microelectronic component having a first surface and an opposing second surface, wherein the microelectronic component is located in the second layer of the substrate, wherein the first surface of the microelectronic component is electrically coupled to the first conductive path in the first layer through an interconnect, the interconnect comprising solder, and wherein the microelectronic component and the interconnect are surrounded by the second material.

12. The microelectronic assembly of claim 11, wherein: The interconnects have a pitch between 25 and 250 microns.

13. The microelectronic assembly of claim 11, wherein: The interconnect does not include a non-conductive film.

14. The microelectronic assembly of claim 11, wherein: The microelectronic component is a first microelectronic component, and wherein the interconnect is a first interconnect, and the microelectronic assembly further comprises: A second microelectronic component is electrically coupled to the second surface of the first microelectronic component by a second interconnect, the second interconnect comprising solder.

15. The microelectronic assembly of claim 14, wherein: The second interconnect has a pitch between 25 microns and 250 microns.

16. A microelectronic assembly according to any one of claims 11 to 15, wherein: The first conductive path includes a conductive via and a conductive trace, and the second conductive path includes a conductive via and does not include a conductive trace.

17. A microelectronic assembly according to any one of claims 11 to 15, wherein: The substrate further comprises: core; and A conductive via passes through the core and is electrically coupled to the microelectronic component through the first conductive path through the first material.

18. A microelectronic assembly comprising: a first layer of a substrate, the first layer comprising a material and a first conductive path through the material, the material comprising an organic dielectric material; a second layer of the substrate located on the first layer, the second layer comprising the material and a second conductive path passing through the material; as well as A microelectronic component having a first surface and an opposing second surface, wherein the microelectronic component is located in the second layer of the substrate, wherein the first surface of the microelectronic component is electrically coupled to the first conductive path in the first layer through an interconnect, wherein the interconnect comprises solder and is surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material.

19. The microelectronic assembly of claim 18, wherein: The interconnects have a pitch between 25 and 250 microns.

20. The microelectronic assembly of claim 18, wherein: The interconnect does not include a non-conductive film.

21. The microelectronic assembly of claim 18, wherein: The microelectronic component is a first microelectronic component, and wherein the interconnect is a first interconnect, and the microelectronic assembly further comprises: A second microelectronic component is electrically coupled to the second surface of the first microelectronic component by a second interconnect, the second interconnect comprising solder.

22. A microelectronic assembly according to any one of claims 18 to 21, wherein: The first conductive path includes a conductive via and a conductive trace, and the second conductive path includes a conductive via and does not include a conductive trace.

23. A microelectronic assembly according to any one of claims 18 to 21, wherein: The substrate further comprises: core; and A conductive via passes through the core and is electrically coupled to the microelectronic component through the first conductive path through the material.

24. A microelectronic assembly according to any one of claims 18 to 21, wherein: The materials include various organic dielectric materials.

25. A microelectronic assembly according to any one of claims 18 to 21, wherein: The microelectronic component includes a semiconductor die.

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