Semiconductor device

Abstract

A semiconductor device includes a first semiconductor element, a second semiconductor element, and a damage detection structure. The first semiconductor element includes a first edge region. The second semiconductor element is stacked below the first semiconductor element and includes a second edge region. The damage detection structure includes a plurality of first conductive paths and a plurality of second conductive paths. The first conductive path is disposed in the first edge region. The second conductive path is arranged in the second edge area and is electrically coupled with the first conductive path.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular, to a semiconductor device including a damage detection structure. Background Art

[0002] Semiconductor devices are widely used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As the size of semiconductor devices shrinks, the difficulty of manufacturing semiconductor devices has increased significantly. During the manufacturing process of semiconductor devices, defects may occur, which may lead to malfunctions or may cause the performance of semiconductor devices to be impaired.

[0003] For example, semiconductor chips are often separated from a wafer during a cutting process, and the edges of these semiconductor chips may have cracks or damages during the cutting process. These cracks and damages may spread and become significant during subsequent manufacturing processes or during the service life of the semiconductor chips. Therefore, it is necessary to detect such cracks and other damages at an early stage. Summary of the Invention

[0004] The present invention provides a semiconductor device. An exemplary semiconductor device includes a first semiconductor element, a second semiconductor element, and a damage detection structure. The first semiconductor element includes a first edge region. The second semiconductor element is stacked below the first semiconductor element and includes a second edge region. The damage detection structure includes a plurality of first conductive paths and a plurality of second conductive paths. The first conductive paths are disposed in the first edge region. The second conductive paths are disposed in the second edge region and are electrically coupled to the first conductive paths.

[0005] In some embodiments, the plurality of first conductive paths are spaced apart from each other, and the plurality of second conductive paths are spaced apart from each other.

[0006] In some embodiments, the plurality of first conductive paths include a plurality of first conductive pads, the plurality of second conductive paths include a plurality of second conductive pads, and each of the plurality of first conductive pads is in direct contact with a corresponding one of the plurality of second conductive pads.

[0007] In some embodiments, the first conductive path has an inverted V shape, an inverted U shape, an inverted M shape, an inverted W shape, an inverted stepped shape, or a combination thereof, and the second conductive path has a V shape, a U shape, an M shape, a W shape, a stepped shape, or a combination thereof.

[0008] In some embodiments, the first semiconductor element and the second semiconductor element are semiconductor chips.

[0009] In some embodiments, the first semiconductor element is a semiconductor chip, and the second semiconductor element is an interposer.

[0010] In some embodiments, the semiconductor device further includes: a conductive wire extending along the top surface of the second semiconductor element for electrically coupling the plurality of second conductive paths to the plurality of first conductive paths.

[0011] In some embodiments, the semiconductor device further includes: a substrate stacked below the second semiconductor element, wherein the damage detection structure further includes a plurality of third conductive paths disposed in the substrate for electrically coupling to the plurality of first conductive paths and / or the plurality of second conductive paths.

[0012] Another embodiment of a semiconductor device includes a first semiconductor element, a second semiconductor element, and a damage detection structure. The first semiconductor element vertically overlaps the second semiconductor element. The damage detection structure includes a plurality of first conductive paths and a plurality of second conductive paths. The first conductive paths extend along a first edge of the first semiconductor element. The second conductive paths extend along a second edge of the second semiconductor element and are electrically coupled to the first conductive paths. The first conductive paths and the second conductive paths are arranged in a first staggered pattern.

[0013] In some embodiments, the first semiconductor element and the second semiconductor element are assembled face to face.

[0014] In some embodiments, the semiconductor device further includes: conductive terminals disposed above the top surface of the first semiconductor element and / or below the bottom surface of the second semiconductor element, wherein the conductive terminals are electrically coupled to the plurality of first conductive paths and the plurality of second conductive paths.

[0015] In some embodiments, the semiconductor device further includes: a plurality of first dielectric layers for separating adjacent first conductive paths; and a plurality of second dielectric layers for separating adjacent second conductive paths; wherein the plurality of first dielectric layers and the plurality of second dielectric layers are arranged in a second staggered pattern.

[0016] In some embodiments, the semiconductor device further includes: a package ring surrounding the damage detection structure.

[0017] In some embodiments, the first edge of the first semiconductor element vertically overlaps the second edge of the second semiconductor element.

[0018] In some embodiments, in a top view, the second edge of the second semiconductor element surrounds the first edge of the first semiconductor element.

[0019] Another embodiment of the semiconductor packaging structure includes a first stacked structure and a damage detection structure. The first stacked structure includes a first semiconductor element and a second semiconductor element. The damage detection structure is disposed in an edge region of the first stacked structure and includes a first conductive path. The first conductive path continuously surrounds a first active region of the first semiconductor element and a second active region of the second semiconductor element in a zigzag shape.

[0020] In some embodiments, the zigzag shape includes a plurality of inverted V shapes adjacent to the first active region of the first semiconductor element and a plurality of V shapes adjacent to the second active region of the second semiconductor element.

[0021] In some embodiments, in a top view, each of the plurality of inverted V shapes is located between two V shapes.

[0022] In some embodiments, the semiconductor device further includes: a substrate located below the first stacked structure; and a second stacked structure located above the substrate and including a third semiconductor element and a fourth semiconductor element, wherein the damage detection structure further includes: a second conductive path surrounding a third active region of the third semiconductor element and a fourth active region of the fourth semiconductor element; and a third conductive path located in the substrate and configured to electrically couple the second conductive path to the first conductive path.

[0023] In some embodiments, the first conductive path includes conductive vias and conductive pads.

[0024] Those skilled in the art can undoubtedly understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the drawings. The detailed description will be given in the following embodiments with reference to the drawings. Description of the Drawings

[0025] The present invention can be more fully understood by reading the subsequent detailed description and referring to the examples given in the drawings.

[0026] Figure 1A is a top view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0027] Figure 1B is a perspective view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0028] Figure 2A is a top view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0029] Figure 2B is a perspective view of an exemplary semiconductor device according to some embodiments of the present disclosure.

[0030] Figure 3A is a top view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure.

[0031] Figure 3B is a perspective view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure.

[0032] Figure 4 is a cross-sectional view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure.

[0033] Figures 5 to 9 is a perspective view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure.

[0034] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order for those skilled in the art to better understand embodiments of the present invention. However, it is apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined according to requirements and should not be limited to the embodiments listed in the figures. Detailed Description

[0035] The following description is a preferred embodiment of the implementation of the present invention, which is only used to illustrate and explain the technical features of the present invention, and is not used to limit the scope of the present invention. Certain terms are used throughout the specification and claims to refer to particular elements. Those skilled in the art should understand that manufacturers may use different names to refer to the same element. Therefore, this specification and claims do not distinguish elements by the difference in name, but by the difference in function of the elements. The terms "element", "system" and "device" used in the present invention may be entities related to a computer, where the computer may be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" mentioned in the following description and claims are open-ended terms, and should be interpreted as meaning "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as being coupled to another device in the text, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0036] Wherein, unless otherwise indicated, corresponding numbers and symbols in different figures of the drawings generally refer to corresponding parts. The drawings drawn clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0037] The present disclosure will be described with respect to specific embodiments and with reference to certain drawings, but the present disclosure is not limited thereto and is only limited by the claims. The drawings are merely illustrative and non - restrictive. In the drawings, the sizes of some components may be exaggerated for illustrative purposes and are not drawn to scale. The sizes and relative sizes do not correspond to the actual sizes in the practice of the present disclosure.

[0038] Additional components may be added based on the embodiments described below. For example, the description “the first component is on / above the second component” may include embodiments where the first component is in direct contact with the second component, and may also include embodiments where additional components are provided between the first component and the second component such that the first component and the second component are not in direct contact.

[0039] The relative spatial description of the first component and the second component may change as the structure operates or is used in different directions. In addition, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments being discussed.

[0040] A semiconductor device including a damage detection structure is described according to some embodiments of the present disclosure. The damage detection structure may be provided in an edge region and may surround an active region of a stacked semiconductor element, and the semiconductor element may include a semiconductor chip, an interposer, etc. or a combination thereof. Thus, damage in the edge region of the stacked semiconductor element can be detected before the damage reaches the active region.

[0041] Figure 1A is a top view of a first semiconductor device 100 according to some embodiments of the present disclosure. Figure 1B is a perspective view of a first semiconductor device 100 according to some embodiments of the present disclosure. Additional features may be added to the first semiconductor device 100. Some of the features described below may be replaced or omitted in different embodiments. For simplicity of the drawings, only a part of the first semiconductor device 100 is shown.

[0042] As Figure 1A shown, a first semiconductor device 100 is provided according to some embodiments. The first semiconductor device 100 includes a first semiconductor component 102. The first semiconductor component 102 includes an active region 101a and an edge region 101b surrounding the active region 101a.

[0043] In some embodiments, the first semiconductor element 102 is a semiconductor die, including a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, etc., or a combination thereof. For example, the first semiconductor element 102 may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a radio frequency front end (RFFE) die, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (IO) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) die, an application specific integrated circuit (ASIC) die, etc., or a combination thereof.

[0044] According to some embodiments, the first semiconductor device 100 includes a plurality of first conductive paths 104 disposed in an edge region 101b of the first semiconductor element 102. The first conductive paths 104 may include a plurality of separate segments disposed along the edge of the first semiconductor element 102. A plurality of first dielectric layers 106 may be disposed between two first conductive paths 104 and separate the two first conductive paths 104 from each other.

[0045] As Figure 1BAs shown, the first conductive path 104 is spaced apart from each other in directions D1 and D2, but is continuous in direction D3. Directions D1, D2, and D3 are different from each other. Directions D1, D2, and D3 may be substantially perpendicular to each other. In some embodiments, the angle between any two of directions D1, D2, and D3 is about 85° to 90°, which can be understood as being substantially perpendicular to each other.

[0046] The first semiconductor device 100 includes a seal ring 108 surrounding the first semiconductor element 102. The seal ring 108 may laterally enclose the first semiconductor element 102 to provide protection against water, chemicals, residues, contaminants, etc. that may be present during the processing of the first semiconductor element 102. The seal ring 108 may be made of a conductive material, such as a metal, including copper, copper alloy, or any suitable material.

[0047] Figure 2A is a top view of a second semiconductor device 200 according to some embodiments of the present disclosure. Figure 2B is a perspective view of a second semiconductor device 200 according to some embodiments of the present disclosure. Additional features may be added to the second semiconductor device 200. Some of the features described below may be replaced or omitted in different embodiments. For the sake of simplicity of the drawings, only a part of the second semiconductor device 200 is shown.

[0048] As Figure 2A shown, a second semiconductor device 200 is provided according to some embodiments. The second semiconductor device 200 includes a seal ring 208 surrounding the second semiconductor element 202. The second semiconductor device 200 may include the second semiconductor element 202. The second semiconductor element 202 may include an active region 201a and an edge region 201b surrounding the active region 201a.

[0049] In some embodiments, the second semiconductor element 202 is a semiconductor chip, including a system-on-chip (SoC) chip, a logic device, a storage device, a radio frequency (RF) device, etc. or a combination thereof. For example, the second semiconductor element 202 may include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency front end (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (IO) chip, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, an application specific integrated circuit (ASIC) chip, etc. or a combination thereof.

[0050] In some other embodiments, the second semiconductor element 202 is an interposer. The interposer may include a bulk semiconductor, a compound semiconductor, an alloy semiconductor, etc. or a combination thereof, and may be made of silicon, germanium, or any suitable semiconductor material. The interposer may include a wiring structure inside thereof.

[0051] The first semiconductor element 102 and the second semiconductor element 202 may include the same or different components.

[0052] According to some embodiments, the second semiconductor device 200 includes a plurality of second conductive paths 204 disposed in an edge region 201b of the second semiconductor element 202. The second conductive paths 204 may include a plurality of separate segments disposed along the edge of the second semiconductor element 202. A plurality of second dielectric layers 206 may be disposed between two second conductive paths 204 and spaced the two second conductive paths 204 apart from each other.

[0053] As Figure 2B shown, the second conductive paths 204 are spaced apart from each other in directions D1 and D2, but are continuous in direction D3. Directions D1, D2, and D3 are different from each other. Directions D1, D2, and D3 are substantially perpendicular to each other. In some embodiments, the angle between any two of D1, D2, and D3 is about 85° to 90°.

[0054] Figure 3A is a top view of a semiconductor device 300 according to some embodiments of the present disclosure. Figure 3B is a perspective view of a semiconductor device 300 according to some embodiments of the present disclosure. It should be noted that the semiconductor device 300 may include components the same as or similar to those of the first semiconductor device 100 and the second semiconductor device 200, and for simplicity, these components will not be discussed in detail.

[0055] According to some embodiments, as Figure 3B shown, the semiconductor device 300 includes a first semiconductor device 100 and a second semiconductor device 200. The first semiconductor device 100 and the second semiconductor device 200 are stacked in direction D3. The first semiconductor element 102 is flipped and disposed above the second semiconductor element 202 such that the first semiconductor element 102 and the second semiconductor element 202 are assembled face-to-face.

[0056] The first semiconductor device 100 may vertically overlap the second semiconductor device 200. The first semiconductor device 100 and the second semiconductor device 200 may include similar areas. In particular, the active region 101a of the first semiconductor element 102 vertically overlaps the active region 201a of the second semiconductor element 202, and the edge region 101b of the first semiconductor element 102 vertically overlaps the edge region 201b of the second semiconductor element 202.

[0057] The first conductive paths 104 are spaced apart from each other, and the second conductive paths 204 are spaced apart from each other. In some embodiments, the first conductive paths 104 and the second conductive paths 204 are in a staggered arrangement. Thus, in a top view, as Figure 3AAs shown, each first conductive path 104 is located between two second conductive paths 204, and each second conductive path 204 is located between two first conductive paths 104.

[0058] The staggered first conductive paths 104 and second conductive paths 204 are used to form a damage detection structure 302. As Figure 3B shown, the damage detection structure 302 can continuously surround the active regions of the stacked first semiconductor element 102 and second semiconductor element 202.

[0059] Figure 4 FIG. Figure 3A is a cross-sectional view of the semiconductor device 300 taken along the line I-I' as shown. As Figure 4 shown, the two first conductive paths 104 are separated by a first dielectric layer 106, and the two second conductive paths 204 are separated by a second dielectric layer 206. In some embodiments, the first dielectric layer 106 and the second dielectric layer 206 are arranged in a staggered manner.

[0060] According to some embodiments, each first conductive path 104 may include a plurality of conductive vias 110 and a plurality of conductive pads 112. The conductive vias 110 and the conductive pads 112 may be made of metal, including copper, silver, gold, etc., their alloys or combinations thereof. The conductive pads 112 may be disposed on the frontside surface 102f of the first semiconductor element 102. The conductive vias 110 are stacked above the conductive pads 112 in the direction D3. The conductive vias 110 are electrically coupled to the conductive pads 112.

[0061] As Figure 4 shown, the first conductive path 104 may have an inverted V shape. However, the present disclosure is not limited thereto, and the first conductive path 104 may have any suitable shape, such as an inverted U shape, an inverted M shape, an inverted W shape, an inverted ladder shape, etc.

[0062] Similarly, according to some embodiments, each second conductive path 204 may include a plurality of conductive vias 210 and a plurality of conductive pads 212. The conductive vias 210 and the conductive pads 212 may be made of metal, including copper, silver, gold, etc., their alloys, or combinations thereof. The conductive pads 212 may be disposed on the front surface 202f of the second semiconductor element 202. The conductive vias 210 may be stacked below the conductive pads 212 along the direction D3. The conductive vias 210 are electrically coupled to the conductive pads 212.

[0063] As Figure 4 shown, the second conductive path 204 may have a V shape. Similar to the discussion of the first conductive path 104, the second conductive path 204 may include any suitable shape, such as a U shape, an M shape, a W shape, a stepped shape, and so on. Thus, as Figure 4 shown, the damage detection structure 302 may be arranged in a zigzag shape in the edge region of the stacked first semiconductor element 102 and second semiconductor element 202.

[0064] The conductive pads 212 of the second conductive path 204 are electrically coupled to the conductive pads 112 of the first conductive path 104. According to some embodiments, the conductive pads 212 of the second conductive path 204 are in contact with the conductive pads 112 of the first conductive path 104.

[0065] The positions of the conductive pads 112 and 212 are described with reference to Figure 5 description. Figure 5 is a perspective view of a semiconductor device 300 according to some embodiments. As Figure 5 shown, the position of each conductive pad 112 may correspond to the position of each conductive pad 212.

[0066] According to some embodiments, the semiconductor device 300 includes a conductive path 304 located in the second semiconductor device 200 and a conductive terminal below the bottom surface of the second semiconductor device 200. The conductive terminal 306 may be electrically coupled to the first conductive path 104 and the second conductive path 204 through the conductive path 304. The conductive path 304 may be connected to any suitable part of the conductive pads 112 / 212 or the damage detection structure 302.

[0067] The conductive path 304 may include a conductive wire, a conductive pad, a conductive via, etc. The conductive path 304 may be made of metal, including copper, silver, gold, etc., their alloys or combinations thereof. The conductive terminal 306 may include a microbump, a controlled collapse chip connection (C4) bump, a solder ball, a ball grid array (BGA) ball, etc. or combinations thereof. The conductive terminal 306 may be made of metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., their alloys or combinations thereof.

[0068] Damage in the first semiconductor element 102 and the second semiconductor element 202 can be detected by physical failure analysis (PFA). According to some embodiments, during the monitoring of damage, a signal is generated and transmitted by the damage detection structure 302, and then a signal interruption caused by the damage is monitored. Therefore, the damage can be detected before it reaches the active region in the edge regions of the stacked first semiconductor element 102 and second semiconductor element 202. Therefore, chip damage problems and the RMA (Return Material Authorization) rate can be reduced.

[0069] In addition, since the first conductive path 104 is electrically coupled to the second conductive path 204, information about damage in the edge region 101b of the first semiconductor element 102 and the edge region 201b of the second semiconductor element 202 can be obtained at once, without the need for multiple monitoring.

[0070] The positions of the first conductive path 104 and the second conductive path 204 are described with reference to Figure 6 description. Figure 6 is a perspective view of the semiconductor device 300 according to some embodiments. For simplicity, only a part of the first conductive path 104 and the second conductive path 204 is shown. As Figure 6 shown, the first conductive path 104 and the second conductive path 204 are arranged in a staggered manner. The damage detection structure 302 has a zigzag shape, and the turning points of the zigzag shape may be adjacent to the top surface of the first semiconductor device 100 and the bottom surface of the second semiconductor device 200, respectively.

[0071] The positions of the conductive path 304 and the conductive terminal 306 can be adjusted. For example, as Figure 6 shown, the conductive terminal 306 can be disposed above the top surface of the first semiconductor device 100. Or, as Figure 5As shown, the conductive path 304 can be disposed in the second semiconductor device 200, and the conductive terminal 306 can be disposed below the bottom surface of the second semiconductor device 200. In addition, the number of the conductive path 304 and the conductive terminal 306 can be adjusted. For example, the semiconductor device 300 can include more than two conductive paths 304 and / or more than two conductive terminals 306, and the embodiments of the present invention are not limited thereto.

[0072] Figure 7 is a perspective view of a semiconductor device 400 according to some embodiments. It should be noted that the semiconductor device 400 can include components that are the same as or similar to those of the semiconductor device 300, and for simplicity, these components will not be discussed in detail. In the following embodiments, the area of the first semiconductor device 100 is different from the area of the second semiconductor device 200.

[0073] As Figure 7 shown, the area of the second semiconductor device 200 is larger than the area of the first semiconductor device 100. For example, the second semiconductor device 200 is an interposer, and the first semiconductor device 100 is a semiconductor chip. In particular, when viewed from a direction perpendicular to the top surface of the first semiconductor device 100, the edge region of the second semiconductor element 202 can surround the edge region of the first semiconductor element 102. The conductive pad 212 can be located (e.g., surround) outside the conductive pad 112.

[0074] The positions of the first conductive path 104 and the second conductive path 204 are described with reference to Figure 8 this. Figure 8 is a perspective view of a semiconductor device 400 according to some embodiments of the present disclosure. For simplicity, only a part of the first conductive path 104 and the second conductive path 204 is shown. As Figure 8 shown, the first conductive path 104 and the second conductive path 204 are arranged in an interleaved manner. The first conductive path 104 is spaced apart from the second conductive path 204.

[0075] According to some embodiments, the damage detection structure 302 includes a plurality of conductive lines 402 extending along the top surface of the second semiconductor device 200. The conductive lines 402 can electrically couple the second conductive path 204 to the first conductive path 104. The conductive lines 402 can be made of metal, including copper, silver, gold, etc., their alloys or combinations thereof. The conductive lines 402 can extend below the bottom surface of the first semiconductor device 100 and can be located below the sealing ring (e.g., Figure 3B the sealing ring 108 in

[0076] Figure 9A cross-sectional view of a semiconductor device 500 according to some embodiments of the present disclosure is shown. It should be noted that the semiconductor device 500 may include components that are the same as or similar to those of the semiconductor device 300, and for the sake of simplicity, these components will not be discussed in detail hereinafter. In the following embodiments, more than two semiconductor elements will be monitored.

[0077] As Figure 9 shown, according to some embodiments, a substrate 502 is provided. The substrate 502 may be a package substrate. The substrate 502 may be a printed circuit board (PCB). The substrate 502 may include bulk semiconductors, compound semiconductors, alloy semiconductors, etc. or combinations thereof, and may be made of silicon, germanium, or any suitable semiconductor material. The substrate 502 may include a wiring structure therein. The substrate 502 may be a coreless substrate or may include an insulating core, such as a fiberglass reinforced resin core, to prevent the substrate 502 from warping.

[0078] According to some embodiments, the semiconductor device 500 includes a first stacked structure 300a and a second stacked structure 300b located above the substrate 502. Each of the first stacked structure 300a and the second stacked structure 300b may include components that are the same as or similar to those of the Figure 6 semiconductor device 300 shown therein. In particular, each of the first stacked structure 300a and the second stacked structure 300b may include stacked semiconductor elements similar to the first semiconductor element 100 and the second semiconductor element 200 shown in Figure 6 therein.

[0079] The damage detection structure may include a first portion 302a and a second portion 302b. The first portion 302a is located in an edge region of the semiconductor elements of the first stacked structure 300a, and the second portion 302b is located in an edge region of the semiconductor elements of the second stacked structure 300b. Each of the first portion 302a and the second portion 302b of the damage detection structure may include a first conduction path 104 and a second conduction path 204 as Figure 6 shown, Figure 9 and the similar first conduction path and second conduction path are respectively labeled as 104a / b and 204a / 204b in

[0080] The damage detection structure may further include a plurality of third conduction paths 504 and 506 located in the substrate 502. The third conduction paths 504 and 506 may electrically couple the first portion 302a of the damage detection structure to the second portion 302b.

[0081] The semiconductor device 500 may include additional conductive paths and two or more conductive terminals (not shown). For example, the conductive paths may be disposed in the substrate 502, and the conductive terminals may be disposed below the bottom surface of the substrate 502. The conductive terminals may be electrically coupled to the damage detection structure through the conductive paths. Since the damage detection structure surrounds the four semiconductor elements, it is possible to monitor whether the edge regions of these 4 semiconductor elements are damaged at one time, without the need for multiple monitoring.

[0082] It should be noted that the two stacked structures 300a and 300b are only for illustrative purposes, and more stacked structures may be disposed above the substrate 502. In addition, the first stacked structure 300a and / or the second stacked structure 300b may include semiconductor devices having different areas, such as those described in the Figure 8 aforementioned embodiments. In addition, additional semiconductor elements (such as semiconductor chips, resistors, capacitors, or inductors) may also be disposed above the substrate 502.

[0083] The present disclosure can be applied to system on integrated chips (SoIC), integrated fan out (InFO), chip on wafer on substrate (CoWoS), 2.5-dimensional (2.5D) / three-dimensional (3D) integrated circuit (3D IC), or any suitable semiconductor packaging structure.

[0084] In summary, the semiconductor device according to the present disclosure includes a damage detection structure disposed in the edge region and surrounding the active region of the semiconductor element, so that damage in the edge region can be detected before the damage reaches the active region. Therefore, chip damage problems and the return merchandise authorization (RMA) rate can be reduced. In addition, by adjusting the arrangement of the damage detection structure, information about damage to the edge regions of these semiconductor elements can be obtained at one time, without the need for multiple monitoring.

[0085] Although the present invention has been described by way of examples and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar structures (as would be apparent to those skilled in the art), for example, combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A semiconductor device comprising: A first semiconductor element including a first edge region; a second semiconductor element stacked below the first semiconductor element, comprising a second edge region; as well as Damage detection structure, including: A plurality of first conductive paths disposed in the first edge region; and A plurality of second conductive paths are disposed in the second edge region, wherein the plurality of second conductive paths are electrically coupled to the plurality of first conductive paths.

2. The semiconductor device according to claim 1, wherein: The plurality of first conductive paths are spaced apart from one another, and the plurality of second conductive paths are spaced apart from one another.

3. The semiconductor device according to claim 1, wherein: The plurality of first conductive paths include a plurality of first conductive pads, the plurality of second conductive paths include a plurality of second conductive pads, and each of the plurality of first conductive pads is in direct contact with a corresponding one of the plurality of second conductive pads.

4. The semiconductor device according to claim 1, wherein: The first conductive path has an inverted V shape, an inverted U shape, an inverted M shape, an inverted W shape, an inverted step shape or a combination thereof, and the second conductive path has a V shape, a U shape, an M shape, a W shape, a step shape or a combination thereof.

5. The semiconductor device according to claim 1, wherein: The first semiconductor element and the second semiconductor element are semiconductor chips.

6. The semiconductor device according to claim 1, wherein: The first semiconductor element is a semiconductor chip, and the second semiconductor element is an interposer.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further includes: A conductive line extending along the top surface of the second semiconductor element is used to electrically couple the plurality of second conductive paths with the plurality of first conductive paths.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: a substrate stacked below the second semiconductor element, The damage detection structure further includes a plurality of third conductive paths disposed in the substrate for electrically coupling with the plurality of first conductive paths and / or the plurality of second conductive paths.

9. A semiconductor device comprising: A first semiconductor element vertically overlaps a second semiconductor element; as well as Damage detection structure, including: a plurality of first conductive paths extending along a first edge of the first semiconductor element; and a plurality of second conductive paths extending along a second edge of the second semiconductor element for electrically coupling with the plurality of first conductive paths, The plurality of first conductive paths and the plurality of second conductive paths are in a first staggered arrangement.

10. The semiconductor device according to claim 9, wherein: The first semiconductor element and the second semiconductor element are assembled face to face.

11. The semiconductor device according to claim 9, wherein: The semiconductor device further includes: A conductive terminal is disposed above the top surface of the first semiconductor element and / or below the bottom surface of the second semiconductor element, wherein the conductive terminal is electrically coupled to the plurality of first conductive paths and the plurality of second conductive paths.

12. The semiconductor device according to claim 9, wherein: The semiconductor device further includes: a plurality of first dielectric layers for separating adjacent first conductive paths; and a plurality of second dielectric layers, used to separate adjacent second conductive paths; The plurality of first dielectric layers and the plurality of second dielectric layers are arranged in a second staggered manner.

13. The semiconductor device according to claim 9, wherein: The semiconductor device further includes: An encapsulation ring surrounds the damage detection structure.

14. The semiconductor device according to claim 9, wherein: The first edge of the first semiconductor element vertically overlaps the second edge of the second semiconductor element.

15. The semiconductor device according to claim 9, wherein: In a top view, the second edge of the second semiconductor element surrounds the first edge of the first semiconductor element.

16. A semiconductor device comprising: A first stacked structure includes a first semiconductor element and a second semiconductor element; as well as a damage detection structure disposed in an edge region of the first stacked structure and comprising a first conductive path; The first conductive path continuously surrounds the first active region of the first semiconductor element and the second active region of the second semiconductor element in a zigzag shape.

17. The semiconductor device according to claim 16, wherein: The sawtooth shape includes a plurality of inverted V shapes adjacent to a first active region of the first semiconductor element and a plurality of V shapes adjacent to a second active region of the second semiconductor element.

18. The semiconductor device according to claim 17, wherein: In the top view, each of the plurality of inverted V shapes is located between two V shapes.

19. The semiconductor device according to claim 16, wherein: The semiconductor device further includes: a substrate located below the first stacked structure; and a second stacked structure located above the substrate and including a third semiconductor element and a fourth semiconductor element, Wherein, the damage detection structure further comprises: a second conductive path surrounding a third active region of the third semiconductor element and a fourth active region of the fourth semiconductor element; and A third conductive path is located in the substrate and is used to electrically couple the second conductive path with the first conductive path.

20. The semiconductor device according to claim 16, wherein The first conductive path includes a conductive via and a conductive pad.

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