Multilayer capacitor structure and manufacturing method thereof

Abstract

The invention provides a multilayer capacitor structure and a manufacturing method thereof. The multilayer capacitor structure comprises a substrate; the stacked body is formed by alternately arranging electrode material layers and dielectric material layers, and the plurality of electrode material layers comprise first electrodes and second electrodes which are alternately arranged in sequence; the first electrode hole at least partially penetrates through the stacked body, first conductors and first intervals are alternately arranged in the first electrode hole, each first conductor is connected with each first electrode and led out to the top of the first electrode hole, and each first interval isolates each second electrode; the second electrode hole at least partially penetrates through the stacked body, second conductors and second intervals are alternately arranged in the second electrode hole, each second conductor is connected with each second electrode and led out to the top of the second electrode hole, and each second interval isolates each first electrode; and the conductive caps are respectively positioned at the tops of the first electrode holes and the second electrode holes and are respectively connected with the first electrodes and the second electrodes. According to the invention, the manufacturing process can be optimized by reducing the photoetching times, and the capacitance density can be improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and particularly relates to a multi-layer capacitor structure and a manufacturing method thereof. Background Art

[0002] Capacitors are widely used in integrated circuits and are important components of integrated circuits. According to the different working characteristics of the circuits where the capacitive elements are located, there are various types of capacitor structures. Such as Metal-Oxide-Semiconductor (MOS) capacitors, Polysilicon-Insulator-Polysilicon (PIP) capacitors, PN junction capacitors, Metal-Oxide-Metal (MOM) capacitors, and Metal-Insulator-Metal (MIM) capacitors. Among them, MOM and MIM capacitors are commonly found in the back-end interconnect layer of CMOS. Since they use metal plates to reduce parasitic capacitance and dissipation resistance, they have better frequency and temperature characteristics than the front-end MOS, PIP, junction capacitors, etc. Moreover, they have the advantages of not occupying device area and having a lower integration difficulty with the CMOS back-end process. The difference between MOM capacitors and MIM capacitors is that the former forms a capacitor by using upper and lower layer metal interconnections and in-layer metal wires, while the latter constructs a capacitor through a separately formed plate stack structure. Therefore, MOM capacitors can be directly embedded into the back-end interconnect layer without additional photomasks. However, due to the limitations of the line width and thickness dimensions of the interconnect layer and the dielectric constant of the interlayer dielectric, the capacitance value density is small. Compared with MOM capacitors, MIM capacitors have a simple structure and can be regarded as a kind of parallel plate capacitor composed of two metal plates + dielectric layer. Their capacitance value is accurate, stability is good, and both parasitic capacitance and resistance are smaller than those of MOM capacitors. Therefore, in semiconductor devices, especially in high-frequency devices, MIM capacitors are usually selected.

[0003] Compared with single-layer capacitors, multi-layer capacitors can significantly increase the capacitance value per unit area. However, for existing multi-layer capacitor structures, each additional layer of electrodes requires an additional photolithography, resulting in relatively high material costs and process costs. Taking, for example, Figure 1a the multi-layer trench capacitor structure (3-layer electrode material layer 13' and two dielectric material layers) shown. The trench structure requires 1 photomask, 3 layers of electrodes require 3 photomasks, and an additional 1 photomask is required to achieve the interconnection of the upper and lower electrodes. A total of 5 photolithographies are required to form a complete MIM structure. At the same time, in order to reserve the RV hole area, a part of the effective area will be sacrificed. Although in the prior art, there is also a method of designing each layer of plates into exactly the same capacitor structure. Please refer to Figure 1bThe shown multi-layer capacitor structure (including 6 electrode material layers 13’ and 5 dielectric material layers) can reuse the photomasks of the same bottom electrode and the same top electrode, thus saving the number of photomasks. However, each electrode material layer still requires one lithography (at least 6 lithographies in total), making it overly dependent on lithography production capacity (lithography resources). Summary of the Invention

[0004] The object of the present invention is to provide a multi-layer capacitor structure and its manufacturing method to increase its capacitance density and optimize its manufacturing process to reduce the number of lithographies.

[0005] To solve the above technical problems, the multi-layer capacitor structure provided by the present invention includes:

[0006] A substrate;

[0007] A stack formed by alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers, disposed on the substrate, and the plurality of electrode material layers include a first electrode and a second electrode alternately arranged in sequence;

[0008] A first electrode hole at least partially penetrating the stack, in which a first conductor and a first spacer are alternately provided, each first conductor connects each first electrode and leads to the top of the first electrode hole, and each first spacer isolates each second electrode;

[0009] A second electrode hole at least partially penetrating the stack, in which a second conductor and a second spacer are alternately provided, each second conductor connects each second electrode and leads to the top of the second electrode hole, and each second spacer isolates each first electrode;

[0010] Two conductive caps respectively located at the tops of the first electrode hole and the second electrode hole, and respectively electrically connected to each first conductor and electrically connected to each second conductor.

[0011] Optionally, it further includes metal interconnect lines and redistribution lines. The metal interconnect lines are disposed in the substrate outside the stack, and the redistribution lines are respectively connected to the conductive caps and the corresponding metal interconnect lines along the outer wall of the stack.

[0012] Optionally, the first electrode hole does not completely penetrate the stack and its bottom wall is the surface of the lowermost first electrode. The first electrode hole includes a first part and a second part with sequentially decreasing pore diameters from top to bottom and alternately arranged. The first part penetrates the first electrode, and the second part penetrates the second electrode and its adjacent dielectric material layer. The first conductor is connected to the side wall of the first electrode exposed by the first part, and the first spacer covers the side walls of the second electrode and the dielectric material layer exposed by the second part.

[0013] Optionally, the second electrode hole does not completely penetrate the stack, and its bottom wall is the surface of the lowermost second electrode. The second electrode hole includes a third part and a fourth part with diameters decreasing successively from top to bottom and arranged alternately. The third part penetrates the first electrode and its adjacent dielectric material layer, and the fourth part penetrates the second electrode. The second conductor is connected to the side wall of the second electrode exposed by the fourth part, and the first spacer covers the first electrode and the dielectric material layer exposed by the third part.

[0014] Optionally, the redistribution line has the same material as the conductive cap, the first conductor connecting the lowermost electrode material layer, and the second conductor.

[0015] Alternatively, the redistribution line has the same material as the conductive cap, but the materials of the first conductor and the second conductor connecting the lowermost electrode material layer are different from the material of the redistribution line.

[0016] Optionally, it further includes metal interconnect lines and redistribution lines. The metal interconnect lines are disposed in the substrate below the stack. The first electrode hole and the second electrode hole both completely penetrate the stack and expose the surfaces of the corresponding metal interconnect lines respectively. The redistribution lines are located in the first electrode hole and the second electrode hole and connect the conductive cap and the corresponding metal interconnect lines respectively.

[0017] Optionally, the first electrode hole includes a first part and a second part with diameters decreasing successively from top to bottom and arranged alternately. The first part penetrates the first electrode, and the second part penetrates the second electrode and its adjacent dielectric material layer. And the first part or the second part corresponding to the lowermost electrode material layer extends downward to expose the surface of the corresponding metal interconnect line. The first conductor is connected to the side wall of the first electrode exposed by the first part, and the first spacer covers the side walls of the second electrode and the dielectric material layer exposed by the second part.

[0018] Optionally, the second electrode hole includes a third part and a fourth part with diameters decreasing successively from top to bottom and arranged alternately. The third part penetrates the first electrode and its adjacent dielectric material layer, and the fourth part penetrates the second electrode. And the third part or the fourth part corresponding to the lowermost electrode material layer extends downward to expose the surface of the corresponding metal interconnect line. The second conductor is connected to the side wall of the second electrode exposed by the fourth part, and the second spacer covers the side walls of the first electrode and the dielectric material layer exposed by the third part.

[0019] Optionally, the material of the redistribution line is the same as that of the conductive cap.

[0020] Alternatively, the material of the redistribution line is different from that of the conductive cap.

[0021] Optionally, the stacked body includes a plurality of planar capacitors and / or trench capacitors formed by the plurality of electrode material layers and the plurality of dielectric material layers.

[0022] Based on another aspect of the present invention, there is also provided a manufacturing method of a multi-layer capacitor structure, including:

[0023] Providing a substrate;

[0024] Alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stacked body, where the plurality of electrode material layers include a first electrode and a second electrode that are alternately arranged in sequence;

[0025] Forming a first electrode hole and a second electrode hole that at least partially penetrate the stacked body, and alternately forming a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately forming a second conductor and a second spacer on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole, each of the first spacers isolates each of the second electrodes, each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole, and each of the second spacers isolates each of the first electrodes;

[0026] Forming conductive caps on the tops of the first electrode hole and the second electrode hole respectively, and electrically connecting each of the first conductors and electrically connecting each of the second conductors respectively.

[0027] Optionally, the steps of forming the first conductor, the first spacer, the second conductor, and the second spacer include:

[0028] Forming a hard mask layer to cover the surface of the stacked body, and performing a first photolithography process and a corresponding etching process on the hard mask layer to form a first opening to expose the surface of the first electrode;

[0029] Forming a first spacer material layer to cover the surface of the hard mask layer and the inner wall of the first opening;

[0030] Performing a second photolithography process and a corresponding etching process to form a second opening that sequentially penetrates the first spacer material layer, the hard mask layer, and the first electrode, and exposes the surface of the dielectric material layer;

[0031] Removing the surface of the hard mask layer, the first spacer material layer at the bottom of the first opening, and the dielectric material layer at the bottom of the second opening, so that the bottom of the first opening exposes the surface of the first electrode, and the bottom of the second opening exposes the surface of the second electrode;

[0032] Forming a second spacer material layer to cover the surface of the hard mask layer, the inner walls of the first opening and the second opening;

[0033] Remove the second spacer material layer on the surface of the hard mask layer, at the bottom of the first opening, and at the bottom of the second opening, and use the remaining second spacer material layer on the sidewall of the second opening as the second spacer;

[0034] Remove the first electrode at the bottom of the first opening and the second electrode at the bottom of the second opening to form a first part exposing the sidewall of the first electrode in the first opening and a fourth part exposing the second electrode in the second opening;

[0035] Form a first conductive material layer covering the surface of the hard mask layer, the inner walls of the first opening, and the second opening;

[0036] Remove the first conductive material layer on the surface of the hard mask layer, at the bottom of the first opening, and at the bottom of the second opening, and use the remaining first conductive material layer on the sidewall of the second opening as the second conductor, and use the remaining first conductive material layer on the sidewall of the first opening as the first conductor.

[0037] Optionally, the substrate includes a capacitor region for forming a capacitor structure and metal interconnects provided outside the capacitor region. The step of electrically connecting the metal interconnects and the capacitor structure includes:

[0038] Perform a third lithography process and a corresponding etching process on the stack to remove the stack outside the capacitor region, with the bottom of the first electrode hole exposing the surface of the bottommost first electrode and the bottom of the second electrode hole exposing the surface of the bottommost second electrode;

[0039] Form sidewalls on the sidewalls of the stack, form the first spacer in the first electrode hole, and form the second spacer in the second electrode hole;

[0040] Form redistribution holes in the substrate to expose the metal interconnects;

[0041] Form a redistribution metal layer covering the surface of the substrate, the outer walls of the stack, filling the redistribution holes, the first electrode hole, and the second electrode hole, and perform a patterning process on the redistribution metal layer, and use the redistribution metal layer filling the first electrode hole as the first conductor, use the redistribution metal layer filling the second electrode hole as the second conductor, use the redistribution metal layer at the top of the first electrode hole and the top of the second electrode hole as the conductive cap, and use the redistribution metal layer connecting the metal interconnects and the corresponding conductive caps as the redistribution line.

[0042] Optionally, the substrate includes a capacitor region for forming a capacitor structure and metal interconnects provided outside the capacitor region. The step of electrically connecting the metal interconnects and the capacitor structure includes:

[0043] Perform a third lithography process and a corresponding etching process on the stack, removing the stack outside the capacitor region. The first conductor is formed in the first electrode hole to electrically lead out all of the first electrodes, and the second conductor is formed in the second electrode hole to electrically lead out all of the second electrodes;

[0044] Form sidewalls on the sidewalls of the stack;

[0045] Form redistribution holes in the substrate to expose the metal interconnect lines;

[0046] Form a redistribution metal layer to cover the surface of the substrate, the outer wall of the stack, fill the redistribution holes, and perform a patterning process on the redistribution metal layer. Use the redistribution metal layer at the top of the first electrode hole and the top of the second electrode hole as the conductive caps, and use the redistribution metal layer connecting the metal interconnect lines and the corresponding conductive caps as redistribution lines.

[0047] Optionally, the substrate includes a capacitor region for forming a capacitor structure and metal interconnect lines disposed in the capacitor region. The steps of electrically connecting the metal interconnect lines and the capacitor structure include:

[0048] Perform a third lithography process and a corresponding etching process on the stack, removing the stack outside the capacitor region. The first electrode hole and the second electrode hole both penetrate the stack and expose the substrate on the corresponding metal interconnect lines. The first conductor is formed in the first electrode hole to electrically lead out each of the first electrodes, and the second conductor is formed in the second electrode hole to electrically lead out each of the second electrodes;

[0049] Form sidewalls on the sidewalls of the stack, form the first spacer in the first electrode hole and the second spacer in the second electrode hole, and expose the surface of the corresponding metal interconnect lines;

[0050] Form a redistribution metal layer to cover the surface of the substrate, the outer wall of the stack, fill the first electrode hole and the second electrode hole, and perform a patterning process on the redistribution metal layer. Use the redistribution metal layer at the top of the first electrode hole and the top of the second electrode hole as the conductive caps, and use the redistribution metal layer in the first electrode hole and the second electrode hole as redistribution lines to respectively connect the conductive caps and the corresponding metal interconnect lines.

[0051] Optionally, the substrate includes a capacitor region for forming a capacitor structure and metal interconnect lines disposed in the capacitor region. The steps of electrically connecting the metal interconnect lines and the capacitor structure include:

[0052] Perform a third lithography process and a corresponding etching process on the stack, removing the stack outside the capacitor region. The first electrode hole and the second electrode hole both penetrate the stack. A first conductor is formed in the first electrode hole to electrically lead out each of the first electrodes, and a second conductor is formed in the second electrode hole to electrically lead out each of the second electrodes. Moreover, redistribution lines are formed in the first electrode hole and the second electrode hole to electrically lead out the metal interconnects below them upward.

[0053] Form sidewalls on the sidewalls of the stack.

[0054] Form a redistribution metal layer to cover the surface of the substrate and the outer wall of the stack, perform a patterning process on the redistribution metal layer, and use the redistribution metal layers at the tops of the first electrode hole and the second electrode hole as the conductive caps to electrically connect the first electrode to the corresponding redistribution line and electrically connect the second electrode to the corresponding redistribution line.

[0055] In summary, the multi-layer capacitor structure provided by the present invention includes a stack provided on a substrate and formed by alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers. The plurality of electrode material layers include a first electrode and a second electrode alternately arranged in sequence. The first electrode holes at least partially penetrate the stack, and a first conductor and a first spacer are alternately provided therein. Each first conductor connects each first electrode and leads out to the top of the first electrode hole. Each first spacer isolates each second electrode. The second electrode holes at least partially penetrate the stack, and a second conductor and a second spacer are alternately provided therein. Each second conductor connects each second electrode and leads out to the top of the second electrode hole. Each second spacer isolates each first electrode. Two conductive caps are respectively located at the tops of the first electrode hole and the second electrode hole, and respectively connect each first electrode and each second electrode. Compared with the multi-layer capacitor structure of the conventional solution, where an additional photomask and one additional lithography are required for each additional layer, the multi-layer capacitor structure of the present invention does not require an increase in the number of photomasks and lithography. It always only requires 3 photomasks and three lithographies, which can significantly reduce the photomask cost and save lithography resources. Compared with the multi-layer capacitor structure of the reused photomask solution, where an additional lithography is required for each additional layer, the multi-layer capacitor structure of the present invention does not require an increase in the number of lithographies. It always only requires three lithographies, which can significantly save lithography resources and reduce the dependence on lithography production capacity. Moreover, compared with the multi-layer capacitor structure of the conventional solution, where an additional electrode hole is required for each additional layer to lead out the corresponding electrode, the multi-layer capacitor structure of the present invention always only requires 2 electrode holes, which can significantly reduce the area occupied by the electrode holes on the electrode plate, so as to release a larger effective area to increase the capacitance value. Compared with the multi-layer capacitor structure of the reused photomask solution (two electrode holes), where the electrode holes of each layer have the same size, the electrode holes in the multi-layer capacitor structure of the present invention gradually decrease from top to bottom, which can release a larger effective area in the electrodes near the substrate to increase the capacitance value. Description of the Drawings

[0056] Those of ordinary skill in the art should understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention.

[0057] Figure 1a and Figure 1b are schematic diagrams of two multi-layer capacitor structures in the related art;

[0058] Figure 2 is a flowchart of a manufacturing method of a multi-layer capacitor structure provided in Embodiment 1;

[0059] Figures 3a to 3p is a schematic diagram of the structure corresponding to the corresponding steps of a manufacturing method of a multi-layer capacitor structure provided in Embodiment 1;

[0060] Figure 3r 、 Figures 3r_1 to 3r_4 is a schematic diagram of the structure corresponding to the corresponding steps of another manufacturing method of a multi-layer capacitor structure provided in Embodiment 1;

[0061] Figures 4a to 4f is a schematic diagram of the structure corresponding to the corresponding steps of a manufacturing method of a multi-layer capacitor structure provided in Embodiment 2;

[0062] Figure 4g is a schematic diagram of another multi-layer capacitor structure provided in Embodiment 2;

[0063] Figures 5a to 5k is a schematic diagram of the structure corresponding to the corresponding steps of a manufacturing method of a multi-layer capacitor structure provided in Embodiment 3;

[0064] Figure 5l is a schematic diagram of another multi-layer capacitor structure provided in Embodiment 3;

[0065] Figures 6a to 6h is a schematic diagram of the structure corresponding to the corresponding steps of a manufacturing method of a multi-layer capacitor structure provided in Embodiment 4;

[0066] Figure 6i is a schematic diagram of another multi-layer capacitor structure provided in Embodiment 4;

[0067] Figure 7 is a schematic diagram of the first electrode hole and the second electrode hole provided in Embodiment 5.

[0068] In the drawings:

[0069] 10 - Substrate; 11 - Metal interconnection; AA - Capacitor region; 21a, 21b, 21c, 21d, 21e - First electrode material layer; 22a, 22b, 22c, 22d, 22e - Second electrode material layer; 23 - Electrode material layer; 24 - Dielectric material layer; 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i - First to ninth dielectric material layers; 25 - Hard mask layer; 26 - First opening; 26a - First part; 26b - Second part; 27a, 27b, 27c, 27d - First to fourth spacer material layers; 28 - Second opening; 28a - Third part; 28b - Fourth part; 31a, 31b, 31c, 31d - Second spacer; 29a, 29b, 29c - First to third conductive material layers; 32a, 32b, 32c, 32d, 32e - Second conductor; 33a, 33b, 33c, 33d, 33e - First conductor; 34a, 34b, 34c - First spacer; 35 - Sidewall; 41 - Redistribution hole; 42 - Redistribution line; 43 - Conductive cap. Detailed implementation manners

[0070] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are not drawn to scale, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes different scales are used.

[0071] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, unless the content clearly indicates otherwise.

[0072] Embodiment 1

[0073] Embodiment 1 provides a manufacturing method for a multi-layer capacitor structure.

[0074] Figure 2 is a flowchart of the manufacturing method for the multi-layer capacitor structure provided in Embodiment 1.

[0075] AsFigure 2 As shown in Figure 2 , the manufacturing method of the multi-layer capacitor structure provided in this embodiment includes:

[0076] S01: Providing a substrate;

[0077] S02: Alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stack, where the plurality of electrode material layers include a first electrode and a second electrode that are alternately arranged in sequence;

[0078] S03: Forming a first electrode hole and a second electrode hole that at least partially penetrate the stack, alternately forming a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately forming a second conductor and a second spacer on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole. Each of the first spacers isolates each of the second electrodes. Each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole. Each of the second spacers isolates each of the first electrodes;

[0079] S04: Forming conductive caps at the tops of the first electrode hole and the second electrode hole respectively, and electrically connecting each of the first conductors and each of the second conductors respectively.

[0080] Figures 3a to 3p FIG. Figures 3a to 3p is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the multi-layer capacitor structure provided in this embodiment. Next, the manufacturing method of the multi-layer capacitor structure will be described in detail with reference to Figures 3a to 3p FIG. Figures 3a to 3p .

[0081] First, please refer to Figure 3a FIG. Figure 3a , and perform step S01 to provide a substrate 10.

[0082] The substrate 10 can be any suitable substrate material well-known to those skilled in the art. For example, it can be at least one of the materials mentioned below: silicon, silicon-on-insulator, stacked silicon-on-insulator, stacked silicon germanide-on-insulator, germanium silicide-on-insulator, and germanium-on-insulator. In this embodiment, the material of the substrate 10 is taken as silicon (silicon substrate) for illustration.

[0083] A device layer and an interconnect layer electrically connected to the device layer are formed in the substrate 10. The interconnect layer is located above the device layer and can be formed by a damascene process. Among them, a plurality of metal interconnect lines 11 are arranged at intervals in the Nth layer (N≥1) of the interconnect layer, and an insulating dielectric layer covers the surface of the metal interconnect lines 11. In this embodiment, the metal interconnect lines 11 can be the top (top layer) interconnect lines of the interconnect layer, which include a first interconnect line and a second interconnect line arranged at intervals. The material of the insulating dielectric layer can, for example, include silicon oxide, silicon nitride, or silicon oxynitride (for example, silicon nitride covers the metal interconnect lines as its etch stop layer, and silicon oxide covers this etch stop layer), etc. Particularly, in this embodiment, a capacitor region AA for forming a capacitor structure is provided in the substrate 10, and at least part of the first interconnect line and at least part of the second interconnect line are arranged outside the capacitor region AA of the substrate 10.

[0084] In addition, in other examples of this embodiment, according to needs, a plurality of (at least two) first interconnect lines and / or a plurality of second interconnect lines can also be provided, and a plurality of identical metal interconnect lines 11 are connected in parallel to the first electrode or the second electrode of the capacitor structure.

[0085] Next, please refer to Figure 3b , perform step S02, and stack a plurality of electrode material layers 23 and a plurality of dielectric material layers 24 alternately on the substrate 10 to form a stack. The plurality of electrode material layers 23 include a first electrode material layer (first electrode) and a second electrode material layer (second electrode) alternately arranged in sequence.

[0086] The electrode material layer 23 includes any suitable conductive material that can be etched, such as platinum, aluminum copper, titanium nitride, gold, titanium, tantalum nitride, tantalum, tungsten, or tungsten nitride, etc. The dielectric material layer 24 can be an insulating material and preferably has a high dielectric constant. It can be one or more of the following: aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, zinc oxide, tungsten oxide, nickel oxide, molybdenum oxide, or silicon dioxide, etc. In the stack of this embodiment, the materials and thicknesses of the plurality of electrode material layers 23 are the same, and the materials and thicknesses of the plurality of dielectric material layers 24 are the same to simplify the subsequent etching process. The number of layers of the electrode material layer 23 can be one more layer (or the same) than the number of layers of the dielectric material layer 24. The number of layers of the electrode material layer 23 can preferably be greater than or equal to 3, and the number of layers of the dielectric material layer 24 can preferably be greater than or equal to 2 to increase the capacitance value per unit area of the capacitor structure (i.e., the number of parallel capacitors). Among them, the odd-numbered layers or even-numbered layers of the plurality of electrode material layers 23 in the stack can be the first electrode (first electrode material layer) or the second electrode (second electrode material layer) respectively, and the number of layers of the first electrode and the second electrode can be the same or differ by one layer.

[0087] In this embodiment, a total of 4 electrode material layers 23 and 3 dielectric material layers 24 may be included. That is, the stack includes, from top to bottom, a first electrode material layer 21a, a first dielectric material layer 24a, a second electrode material layer 22a, a second dielectric material layer 24b, a first electrode material layer 21b, a third dielectric material layer 24c, and a second electrode material layer 22b.

[0088] Next, step S03 is performed to form a first electrode hole (first opening) and a second electrode hole (second opening) that at least partially penetrate the stack, and alternately form a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately form a second conductor and a second spacer on the inner wall of the second electrode hole. Each first conductor connects each first electrode material layer in the first electrode hole and leads to the top of the first electrode hole. Each first spacer isolates each second electrode material layer in the first electrode hole. Each second conductor connects each second electrode material layer in the second electrode hole and leads to the top of the second electrode hole. Each second spacer isolates each first electrode material layer in the second electrode hole.

[0089] Specifically, please refer to Figure 3c , to form a hard mask layer 25 covering the electrode material layer 23 on the topmost layer of the stack, that is, covering the first electrode material layer 21a. The material of the hard mask layer 25 may include a layer of hard material or a composite structure composed of at least two layers of materials.

[0090] Please refer to Figure 3d , perform a first lithography process and an etching process to form a first opening 26 in the hard mask layer 25 of the stack in the capacitor region AA, exposing the surface of the first electrode material layer 21a. Among them, the first opening 26 can be used to form a first electrode hole subsequently.

[0091] Please refer to Figure 3e , to form a first spacer material layer 27a conformally covering the surface of the hard mask layer 25 and the inner wall of the first opening 26 (including the exposed surface of the first electrode material layer 21a and the sidewall of the hard mask layer 25). The first spacer 27a material layer can be any suitable insulating material with a material different from that of the hard mask layer 25. In this embodiment, the material of the first spacer material layer 27a can be the same as that of the dielectric material layer 24 to simplify the deposition process and etching process in the manufacturing process, and the thickness of the first spacer material layer 27a can also preferably be the same as the thickness of the dielectric material layer 24.

[0092] Please refer to Figure 3f, perform a second lithography process and an etching process to form a second opening 28 in the first spacer material layer 27a and the hard mask layer 25 of the stack in the capacitor region AA, so as to expose the surface of the first electrode material layer 21a. The second opening 28 can be used to form a second electrode hole subsequently. In an example, the aperture of the second opening 28 can be close to the aperture of the first opening 26 covered with the first spacer material layer 27a, so that the first electrode hole and the second electrode hole formed subsequently have similar apertures. Taking the first opening 26 and the second opening 28 both being circular as an example, the diameter of the second opening 28 can be smaller than the diameter of the first opening 26 by twice the thickness of the first spacer material layer 27a. In other examples, the apertures of the first opening 26 and the second opening 28 can also be reasonably set according to the actual situation. Of course, the cross-sectional shapes of the first opening 26 and the second opening 28 can also be square, rectangular, etc.

[0093] Please refer to Figure 3g , utilize the second opening 28, perform an etching process to remove the first electrode material layer 21a exposed by the second opening 28, and stop the etching at the surface of the first dielectric material layer 24a, that is, expose the surface of the first dielectric material layer 24a.

[0094] Please refer to Figure 3h , perform an etching process to remove the first spacer material layer 27a at the bottom of the first opening 26 and the first dielectric material layer 24 at the bottom of the second opening 28, and stop the etching at the surface of the electrode material layer 23, that is, expose the surface of the first electrode material layer 21a at the bottom of the first opening 26, retain the first spacer material layer 27a on the sidewall of the first opening 26, which covers the sidewall of the hard mask layer 25, expose the sidewalls of the first electrode material layer 21a and the first dielectric material layer 24a on the sidewall of the second opening 28, expose the surface of the second electrode material layer 22a at the bottom of the second opening 28, and use the partial spatial structure passing through the first electrode material layer 21a and the first dielectric material layer 24a in the second opening 28 as the third part 28a of the second electrode hole. In practice, an etching process with a relatively low etching selectivity to the first dielectric material layer 24a and the first spacer material layer 27a can be preferably used, so as to etch the first dielectric material layer 24a and the first spacer material layer 27a simultaneously. Of course, the first spacer material layer 27a on the hard mask layer 25 can also be partially removed or completely removed in the above etching process.

[0095] Please refer to Figure 3i, a second spacer material layer 27b is formed to conformally cover the surface of the hard mask layer 25, the inner walls of the first opening 26, and the inner walls of the second opening 28, that is, it includes covering the surface of the exposed first electrode material layer 21a, the surface of the second electrode material layer 22a, and the sidewalls of the third part 28a. The second spacer material layer 27b can be any suitable insulating material with a material different from that of the hard mask layer 25. In this embodiment, the material of the second spacer material layer 27b can be the same as that of the first spacer material layer 27a, and an atomic layer deposition process can be used to form it to improve the film quality and step coverage.

[0096] Please refer to Figure 3j , perform an etching process to remove the second spacer material layer 27b at the bottom of the first opening 26 and the second spacer material layer 27b at the bottom of the second opening 28 (so that the bottom of the first opening 26 exposes the surface of the first electrode material layer 21a, and the bottom of the second opening 28 exposes the surface of the second electrode material layer 22a), and then continue to etch to remove the exposed first electrode material layer 21a in the first opening 26 and the exposed second electrode material layer 22a in the second opening 28, and the etching stops at the corresponding dielectric material layer, retaining the remaining second spacer material layer 27b on the sidewalls of the first opening 26, which covers the sidewalls of the remaining first spacer material layer 27a, and using the remaining second spacer material layer 27b on the sidewalls of the second opening 28 as the second spacer 31a. Among them, within the first opening 26, the remaining second spacer material layer 27b covers the previously remaining first spacer material layer 27a, exposes the sidewalls of the first electrode material layer 21a and the surface of the first dielectric material layer 24a, and uses the partial spatial structure passing through the first electrode material layer 21a in the first opening 26 as the first part 26a of the first electrode hole; within the second opening 28, the second spacer 31a sequentially covers the sidewalls of the hard mask layer 25, the first electrode material layer 21a, and the first dielectric material layer 24a, that is, it covers the sidewalls of the third part 28a, is used to electrically isolate the first electrode material layer 21a within the second opening 28, and exposes the sidewalls of the second electrode material layer 22a and the surface of the second dielectric material layer 24b, and uses the partial spatial structure passing through the second electrode material layer 22a in the second opening 28 as the fourth part 28b of the second electrode hole. Of course, the second spacer material layer 27b on the hard mask layer 25 can also be partially removed or completely removed during the above etching process.

[0097] Please refer to Figure 3k, a first conductive material layer 29a is formed to conformally cover the surface of the hard mask layer 25, the inner walls of the first opening 26, and the inner walls of the second opening 28. The material of the first conductive material layer 29a can be any suitable conductive material, and it is preferably formed by atomic layer deposition to improve the film quality and its step coverage. In this embodiment, the material of the first conductive material layer 29a can be the same as that of the electrode material layer 23 to facilitate synchronous etching and simplify the process. In the first opening 26, the first conductive material layer 29a covers the sidewalls of the remaining second spacer material layer 27b, the sidewalls of the first electrode material layer 21a (i.e., the sidewalls of the first part 26a), and the surface of the first dielectric material layer 24a; in the second opening 28, the first conductive material layer 29a covers the sidewalls of the second spacer 31a, the sidewalls of the second electrode material layer 22a (i.e., the sidewalls of the fourth part 28b), and the surface of the second dielectric material layer 24b.

[0098] Please refer to Figure 3l, the etching process is performed to remove the first conductive material layer 29a at the bottom of the first opening 26 and the bottom of the second opening 28 (so that the surface of the first dielectric material layer 24a is exposed at the bottom of the first opening 26, and the surface of the second dielectric material layer 24b is exposed at the bottom of the second opening 28). Then, the etching process is continued to etch downward through three material layers (including two dielectric material layers 24 and one electrode material layer 23 between the two dielectric material layers 24), and the etching stops on the electrode material layer 23 under the latter dielectric material layer 24. That is, in the first opening 26, the first dielectric material layer 24a, the second electrode material layer 22a, and the second dielectric material layer 24b are sequentially etched away to form a second part 26b that penetrates the first dielectric material layer 24a, the second electrode material layer 22a, and the second dielectric material layer 24b, and the etching stops on the surface of the first electrode material layer 21b. In the second opening 28, the second dielectric material layer 24b, the first electrode material layer 21b, and the third dielectric material layer 24c are sequentially etched away to form a third part 28a that penetrates the second dielectric material layer 24b, the first electrode material layer 21b, and the third dielectric material layer 24c, and the etching stops on the surface of the second electrode material layer 22b. After performing the above etching process, the first conductive material layer 29a remaining on the sidewall of the first opening 26 is used as the first conductor 33a, which covers the remaining sidewall of the second spacer material layer 27b and the first electrode material layer 21a (the first part 26a) for electrically leading out the first electrode material layer 21a to the top of the first opening 26. The first conductive material layer 29a remaining on the sidewall of the second opening 28 is used as the second conductor 32a, which covers the sidewall of the second spacer 31a and the fourth part 28b for electrically leading out the second electrode material layer 22a to the top of the second opening 28. Moreover, the bottom of the first opening 26 exposes the surface of the first electrode material layer 21b, the second part 26b in the first opening 26 exposes the sidewalls of the first dielectric material layer 24a, the second electrode material layer 22a, and the second dielectric material layer 24b, the bottom of the second opening 28 exposes the surface of the second electrode material layer 22b, and the third part 28a in the second opening 28 exposes the sidewalls of the second dielectric material layer 24b, the first electrode material layer 21b, and the third dielectric material layer 24c.

[0099] In this embodiment, an etching process with a low etching selectivity for the spacer material layer (including the first spacer material layer 27a and the second spacer material layer 27b), the dielectric material layer 24, the electrode material layer 23, and the first conductive material layer 29a can be selected, and the above materials are etched synchronously to achieve the above effects. Of course, the first conductive material layer 29a on the hard mask layer 25 may also be partially or completely removed in the above etching process. In addition, during the above etching process, due to the low selectivity of the etching process, the top of the hard mask layer 25 and other exposed material layers (including the spacer material layer and the conductive material layer) are also consumed by a partial thickness synchronously, so that the periphery of the first opening 26 and the second opening 28 can basically remain flat, that is, there is no or only a small step height difference between the hard mask layer 25 and the spacer material layer and the conductive material layer in the first opening 26 and the second opening 28.

[0100] Please refer to Figure 3m , perform a third lithography process and an etching process on the stack body to remove the hard mask layer 25, the electrode material layer 23, and the dielectric material layer 24 outside the capacitor region AA, and expose the surface of the substrate 10 outside the capacitor region AA.

[0101] Please refer to Figure 3n , form a third spacer material 27c to conformally cover the surface of the substrate 10, the outer wall of the stack body, the inner wall of the first opening 26, and the inner wall of the second opening 28, that is, including covering the surface of the exposed first electrode material layer 21b, the surface of the second electrode material layer 22b, and the side wall of the third part 28a. The third spacer material layer can be any suitable insulating material with a material different from that of the hard mask layer 25. In this embodiment, the material of the third spacer material layer 27c can be the same as that of the first spacer material layer 27a or the second spacer material layer 27b, and an atomic layer deposition process can be used to form it to improve the step coverage.

[0102] Please refer to Figure 3o , perform an etching process to remove the third spacer material layer 27c on the surface of the substrate 10, the surface of the hard mask layer 25, the bottom of the first opening 26, and the bottom of the second opening 28, and use the remaining third spacer material layer 27c covering the side wall of the first opening 26 (the side walls of the first conductor 33a and the second part 26b) as the first spacer 34a, and expose the surface of the first electrode material layer 21b, use the remaining third spacer material layer 27c covering the side wall of the second opening 28 (the side walls of the second conductor 32a and the third part 28a) as the second spacer 31b, and expose the surface of the second electrode material layer 22b, and use the remaining third spacer material layer 27c covering the side wall of the stack body as the sidewall 35 to isolate the side wall of the stack body.

[0103] Next, step S04 is performed to form conductive caps 43 respectively on the tops of the first electrode holes (the first openings 26) and the second electrode holes (the second openings 28), and connect the respective first electrode material layers or the respective second electrode material layers.

[0104] Specifically, please refer to Figure 3p , perform a patterning process on the insulating dielectric layer on the surface of the substrate 10 to form redistribution holes 41 exposing the metal interconnections 11 (including the metal interconnections corresponding to the capacitor structure and other metal interconnections), then form a redistribution metal layer covering the surface of the substrate 10 and the outer walls of the stacked body, and fill the redistribution holes 41, the first openings 26, and the second openings 28. Next, perform a patterning process on the redistribution metal layer to form redistribution lines 42 electrically connecting the metal interconnections 11 with the first electrode material layer and the second electrode material layer of the capacitor structure, and electrically leading out other metal interconnections. Among them, the redistribution metal layer in the first opening 26 can be the first conductor 33b for electrically leading out the lowermost first electrode material layer 22b, and the redistribution metal layer on the top of the first opening 26 can be used as the conductive cap 43 for connecting the first conductor 33a and the first conductor 33b in the first opening 26, that is, electrically connecting the first electrode material layer 21a and the first electrode material layer 21b. The redistribution metal layer in the second opening 28 can be the second conductor 32b for electrically leading out the lowermost second electrode material layer 22b, and the redistribution metal layer on the top of the second opening 28 can be used as the conductive cap 43 for connecting the second conductor 32a and the second conductor 32b in the second opening 28, that is, the second electrode material layer 22a and the second electrode material layer 22b. The material of the redistribution metal layer can include aluminum or copper-aluminum alloy, etc., and can be formed by PVD process.

[0105] Particularly, in the remaining examples of this embodiment, when the number of electrode layers of the formed capacitor structure is greater than 4 layers, a similar manufacturing method as above can also be adopted. Figure 3r The shown capacitor structure includes 10 electrode material layers 23 and 9 dielectric material layers 24, that is, it includes 5 first electrode material layers (21a, 21b, 21c, 21d, 21e) and 5 second electrode material layers (22a, 22b, 22c, 22d, 22e) and the first to ninth dielectric material layers (24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i). Please refer to Figure 3r , to form Figure 3r The process of forming the shown capacitor structure may include: First, refer to Figures 3c to 3l , to form Figure 3r_1In the structure shown, a first opening 26 is formed in the first to fourth electrode material layers (21a, 21b, 22a, 22b) in the stack to expose the surface of the third electrode material layer 21b and the side wall of the second part 26b, and a second opening 28 is formed to expose the surface of the fourth electrode material layer 22b and the side wall of the third part 28a. A first conductor 33a connecting the first electrode material layer 21a is formed on the side wall of the first opening 26, and a second spacer 31a isolating the first electrode material layer 21a and a second conductor 32a connecting the second electrode material layer 22a are formed on the side wall of the second opening 28. Then, please refer to Figures 3i to 3l , repeat Figures 3i to 3l the corresponding steps to form Figure 3r_2 the structure shown, and expand (etch) the first opening 26 and the second opening 28 downward to the fifth to sixth electrode material layers (21c, 22c) to form a first opening 26 to expose the surface of the fifth electrode material layer 21c and the side wall of the second part 26b, and a second opening 28 to expose the surface of the sixth electrode material layer 22c and the surface of the third part 28a. A first spacer 34a isolating the second electrode material layer 22a and a first conductor 33b connecting the third electrode material layer 21b are formed on the side wall of the first opening 26, and a second spacer 31b isolating the third electrode material layer 21b and a second conductor 32b connecting the fourth electrode material layer 22b are formed on the side wall of the second opening 28. Then, continue to refer to Figures 3i to 3l , repeat Figures 3i to 3l the corresponding steps to form Figure 3r_3 the structure shown, and expand the first opening 26 and the second opening 28 downward to the seventh to eighth electrode material layers (21d, 22d) to form a first opening 26 to expose the surface of the seventh electrode material layer 21d and the side wall of the second part 26b, and a second opening 28 to expose the surface of the eighth electrode material layer 22d. A first spacer 34b isolating the fourth electrode material layer 22b and a first conductor 33c connecting the fifth electrode material layer 21c are formed on the side wall of the first opening 26, and a second spacer 31c isolating the fifth electrode material layer 21c and a second conductor 32c connecting the sixth electrode material layer 22c are formed on the side wall of the second opening 28. Then, similarly repeat several groups of Figures 3i to 3l the corresponding steps (in this example, continue to repeat one group), until the first opening 26 and the second opening 28 are expanded downward to the ninth to tenth electrode material layers (21e, 22e) to form Figure 3r_4In the structure shown, the first opening 26 exposes the surface of the ninth electrode material layer 21e and the sidewalls of the second part 26b, and the second opening 28 is formed to expose the surface of the tenth electrode material layer 22e and the sidewalls of the third part 28a. A first spacer 34c for isolating the sixth electrode material layer 22c and a first conductor 33d connecting the seventh electrode material layer 21d are formed on the sidewalls of the first opening 26, and a second spacer 31d for isolating the seventh electrode material layer 21d and a second conductor 32d connecting the eighth electrode material layer 22d are formed on the sidewalls of the second opening 28. Then, please refer to Figures 3m to 3p , to implement the patterning of the stack (including the third lithography process), and complete the electrical connection between the first electrode material layer and the second electrode material layer of the capacitor structure and the corresponding metal interconnection line 11, thereby forming a capacitor structure including 10 electrode layers as shown in Figure 3r .

[0106] From the above two examples of this embodiment, it is not difficult to see that capacitor structures including 4 electrode layers and 10 electrode layers can both be prepared by only three photomasks and three lithography processes (excluding the patterning processes of the redistribution vias 41 and redistribution lines 42). The following table shows the number of photomasks and the number of lithography times required for forming multilayer capacitor structures with different numbers of electrode layers for the relative conventional scheme and the reused photomask scheme (both excluding the patterning processes of the redistribution vias 41 and redistribution lines 42):

[0107]

[0108]

[0109] For the multilayer capacitor structure of the conventional scheme, each additional layer requires an additional photomask and one additional lithography. The multilayer capacitor structure of this embodiment does not require an increase in the number of photomasks and lithography times, and always only requires 3 photomasks and three lithography processes, which can significantly reduce the photomask cost and save lithography resources. For the multilayer capacitor structure of the reused photomask scheme, each additional layer requires an additional lithography. The multilayer capacitor structure of this embodiment does not require an increase in the number of lithography times, and always only requires three lithography processes, which can significantly save lithography resources and reduce the dependence on lithography production capacity.

[0110] Taking the area of the bottommost electrode plate as 900 square micrometers as an example, and the area of one electrode via as 9 square micrometers, the following table shows the effective area of the topmost electrode plate when forming multilayer capacitor structures with different numbers of electrode layers for the relative conventional scheme and the reused photomask scheme:

[0111]

[0112] As can be seen from the above, for each additional layer in the multi-layer capacitor structure of the conventional solution, an additional electrode hole is required to lead out the corresponding electrode. In the multi-layer capacitor structure of this embodiment, only 2 electrode holes are always required, which can significantly reduce the area of the electrode holes occupying the electrode plate, so as to release a larger effective area to increase the capacitance value. Compared with the multi-layer capacitor structure of the multiplexed photomask solution (two electrode holes) where the electrode holes of each layer have the same size, the electrode holes in the multi-layer capacitor structure of this embodiment gradually decrease from top to bottom, and a larger effective area can be released in the electrodes close to the substrate to increase the capacitance value.

[0113] Embodiment 2

[0114] Embodiment 2 provides a manufacturing method for a multi-layer capacitor structure.

[0115] Figure 2 It is a flowchart of the manufacturing method for the multi-layer capacitor structure provided by Embodiment 2.

[0116] As Figure 2 shown, the manufacturing method for the multi-layer capacitor structure provided by this embodiment includes:

[0117] S01: Provide a substrate;

[0118] S02: Alternately stack a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stack, and the plurality of electrode material layers include first electrodes and second electrodes that are alternately arranged in sequence;

[0119] S03: Form a first electrode hole and a second electrode hole that at least partially penetrate the stack, and alternately form a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately form a second conductor and a second spacer on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole. Each of the first spacers isolates each of the second electrodes. Each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole. Each of the second spacers isolates each of the first electrodes;

[0120] S04: Form conductive caps on the tops of the first electrode hole and the second electrode hole respectively, and electrically connect each of the first conductors or electrically connect each of the second conductors respectively.

[0121] The manufacturing method for the multi-layer capacitor structure provided by Embodiment 2 is basically similar to the manufacturing method of Embodiment 1, and the difference lies only in the different preparation methods of the first conductor and the second conductor at the end (that is, the steps Figure 3l after Figure 4a in Embodiment 1 are different). Figures 3a to 3l The steps Figures 4a to 4f before can refer to the method of Figure 3lThe structural schematic diagram corresponding to the subsequent steps. Next, the manufacturing method of the multi-layer capacitor structure will be described in detail in conjunction with Figures 4a to 4f the manufacturing method of the multi-layer capacitor structure will be described in detail.

[0122] Please refer to Figure 4a , a third spacer material layer 27c is formed to conformally cover the surface of the stack, the inner walls of the first opening 26, and the inner walls of the second opening 28, that is, it includes covering the surface of the exposed first electrode material layer 21b, the surface of the second electrode material layer 22b, the side walls of the second part 26b, and the third part 28a. The third spacer material layer 27c can be any suitable insulating material with a material different from that of the hard mask layer. In this embodiment, the material of the third spacer material layer 27c can be the same as that of the first spacer material layer 27a or the second spacer material layer 27b, and can be formed by atomic layer deposition technology to improve the film quality and its step coverage.

[0123] Please refer to Figure 4b , an etching process is performed to remove the third spacer material layer 27c on the surface of the hard mask layer 25, the bottom of the first opening 26, and the bottom of the second opening 28, and the remaining third spacer material layer 27c covering the side wall of the first opening 26 (the side walls of the first conductor 33a and the second part 26b) is used as the first spacer 34a, and the surface of the first electrode material layer 21b is exposed. The remaining third spacer material layer 27c covering the side wall of the second opening 28 (the side walls of the second conductor 32a and the third part 28a) is used as the second spacer 31b, and the surface of the second electrode material layer 22b is exposed.

[0124] Please refer to Figure 4c , a second conductive material layer 29b is formed to cover the surface of the hard mask layer 25 and fill the first opening 26 and the second opening 28 above the hard mask layer 25 (that is, fill the first opening 26 and the second opening 28 completely). The material of the second conductive material layer 29b can refer to the material of the first conductive material layer 29a, for example, including titanium nitride, and is formed by processes such as PVD or CVD.

[0125] Please refer to Figure 4d, a third lithography process and an etching process are performed on the stack covered with the second conductive material layer 29b to remove the hard mask layer 25, the electrode material layer, the dielectric material layer (i.e., the stack outside the capacitor region AA), and the second conductive material layer 29b on the surface of the hard mask layer 25 outside the capacitor region AA, and the second conductive material layer 29b in the first opening 26 and the second opening 28 is retained, and the surface of the hard mask layer 25 and the surface of the substrate 10 outside the capacitor region AA are exposed. The second conductive material layer 29b in the first opening 26 is used as the first conductor 33b for electrically leading out the first electrode material layer 21b, and the second conductive material layer 29b in the second opening 28 is used as the second conductor 32b for electrically leading out the second electrode material layer 22b. Specifically, a patterned photoresist can be first formed to cover only the stack in the capacitor region AA, and then, the hard mask layer 25, the electrode material layer, and the dielectric material layer outside the capacitor region AA are etched away, and then the patterned photoresist layer is removed, and then, the second conductive material layer 29b on the surface of the hard mask layer 25 is etched away.

[0126] Please refer to Figure 4e , sidewalls 35 are formed to cover the sidewalls of the stack, and the sidewalls of the stack are isolated (insulated).

[0127] Please refer to Figure 4f , a patterning process is performed on the insulating dielectric layer on the surface of the substrate 10 to form redistribution holes 41 exposing the metal interconnections 11, and then a redistribution metal layer is formed to cover the surface of the substrate 10 and the outer walls of the stack and fill the redistribution holes 41, and a patterning process is performed on the redistribution metal layer to form redistribution lines 42 electrically connecting the metal interconnections 11 with the first electrode material layer and the second electrode material layer of the capacitor structure respectively. Among them, the redistribution metal layer at the top of the first opening 26 can be used as a conductive cap 43 for connecting the first conductor 33a and the first conductor 33b in the first opening 26, that is, electrically connecting the first electrode material layer 21a and the first electrode material layer 21b, and the redistribution metal layer at the top of the second opening 28 can be used as a conductive cap 43 for connecting the second conductor 32a and the second conductor 32b in the second opening 28, that is, electrically connecting the second electrode material layer 22a and the second electrode material layer 22b. The material of the redistribution metal layer can include aluminum or copper-aluminum alloy, etc. It can be understood that the thickness of the redistribution metal layer is relatively thick (large amount of use), and its material usually includes aluminum, while the material of the second conductive material layer is usually an electrode material (such as titanium nitride). Compared with filling the redistribution metal layer in the first opening or the second opening with a high aspect ratio, even the second conductive material layer formed by the PVD process has a better filling effect (step coverage), which is beneficial to solving the problem that it is difficult to fill aluminum.

[0128] In particular, in the remaining examples of this embodiment, when the number of electrode layers of the formed capacitor structure is greater than 4 layers, a similar manufacturing method as above can also be used.Figure 4g The capacitor structure shown includes 10 electrode material layers 23 and 9 dielectric material layers 24, that is, it includes 5 first electrode material layers (21a, 21b, 21c, 21d, 21e) and 5 second electrode material layers (22a, 22b, 22c, 22d, 22e) and the first to ninth dielectric material layers (24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i). The manufacturing method can refer to Figure 3r the manufacturing method of the capacitor structure with 10 electrodes in

[0129] Example 3

[0130] Example 3 provides a manufacturing method for a multi-layer capacitor structure.

[0131] Figure 2 is a flowchart of the manufacturing method for the multi-layer capacitor structure provided in Example 3.

[0132] As Figure 2 shown, the manufacturing method for the multi-layer capacitor structure provided in this embodiment includes:

[0133] S01: Provide a substrate;

[0134] S02: Alternately stack a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stack. The plurality of electrode material layers include a first electrode and a second electrode that are alternately arranged in sequence;

[0135] S03: Form a first electrode hole and a second electrode hole that at least partially penetrate the stack, and alternately form a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately form a second conductor and a second spacer on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole. Each of the first spacers isolates each of the second electrodes. Each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole. Each of the second spacers isolates each of the first electrodes;

[0136] S04: Form conductive caps at the tops of the first electrode hole and the second electrode hole respectively, and electrically connect each of the first conductors and electrically connect each of the second conductors respectively.

[0137] The manufacturing method for the multi-layer capacitor structure provided in Example 3 is basically similar to the manufacturing method in Example 1 (or Example 2), and the difference is only that the position and corresponding connection method of the metal interconnection line for connecting the capacitor structure relative to the capacitor structure are different. Figures 5a to 5k is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method for the multi-layer capacitor structure provided in this embodiment. Next, it will be combined with Figures 5a to 5kA method for manufacturing the multi-layer capacitor structure will be described in detail.

[0138] First, please refer to Figure 5a and perform step S01 to provide a substrate 10.

[0139] The substrate 10 can be any suitable substrate material well-known to those skilled in the art. For example, it can be at least one of the materials mentioned below: silicon, silicon-on-insulator, silicon-on-insulator stacked silicon, silicon-on-insulator stacked germanium silicide, germanium silicide-on-insulator, and germanium-on-insulator, etc. In this embodiment, the material of the substrate 10 is taken as silicon (silicon substrate) for illustration.

[0140] A device layer and an interconnect layer electrically connected to the device layer are formed in the substrate 10. The interconnect layer is located above the device layer and can be formed by a damascene process. Among them, a plurality of metal interconnect lines 11 are arranged at intervals in the Nth layer (N is greater than or equal to 1) of the interconnect layer. The surface of the metal interconnect line 11 is covered with an insulating dielectric layer. In this embodiment, the metal interconnect line 11 can be the top (top layer) interconnect line of the interconnect layer, which includes a first interconnect line and a second interconnect line arranged at intervals. The material of the insulating dielectric layer can, for example, include silicon oxide, silicon nitride, or silicon oxynitride (for example, silicon nitride covers the metal interconnect line as its etch stop layer, and silicon oxide covers this etch stop layer), etc. In particular, in this embodiment, a capacitor region AA for forming a capacitor structure is provided in the substrate 10, and at least part of the first interconnect line and at least part of the second interconnect line are arranged in the capacitor region AA of the substrate 10.

[0141] In addition, in other examples of this embodiment, according to needs, a plurality of (at least two) first interconnect lines 11 and / or a plurality of second interconnect lines can also be provided. A plurality of the same metal interconnect lines 11 can be connected in parallel to the first electrode or the second electrode of the capacitor structure.

[0142] Next, please refer to Figure 5b and perform step S02 to stack a plurality of electrode material layers 23 and a plurality of dielectric material layers 24 alternately on the substrate 10 to form a stacked body. The plurality of electrode material layers 23 include a first electrode material layer (first electrode) and a second electrode material layer (second electrode) alternately arranged in sequence.

[0143] The electrode material layer 23 includes any suitable conductive material that can be etched, such as platinum, aluminum copper, titanium nitride, gold, titanium, tantalum nitride, tantalum, tungsten, or tungsten nitride, etc. The dielectric material layer 24 can be an insulating material and preferably has a high dielectric constant, and it can be one or more of the following: alumina, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, zinc oxide, tungsten oxide, nickel oxide, molybdenum oxide, or silicon dioxide, etc. In the stack of this embodiment, the materials and thicknesses of the multiple electrode material layers 23 are the same, and the materials and thicknesses of the multiple dielectric material layers 24 are the same to simplify the subsequent etching process. The number of electrode material layers 23 can be one layer more (or the same) than the number of dielectric material layers 24. The number of electrode material layers 23 can preferably be greater than or equal to 3, and the number of dielectric material layers 24 can preferably be greater than or equal to 2 to increase the capacitance value per unit area of the capacitor structure (i.e., the number of parallel capacitor layers). Among them, the odd-numbered layers or even-numbered layers of the multiple electrode material layers 23 in the stack can be the first electrode (the first electrode material layer) or the second electrode (the second electrode material layer) respectively, and the number of layers of the first electrode and the second electrode can be the same or differ by one layer.

[0144] In this embodiment, a total of 4 electrode material layers 23 and 3 dielectric material layers 24 can be included, that is, the stack includes, from top to bottom, a first electrode material layer 21a, a first dielectric material layer 24a, a second electrode material layer 22a, a second dielectric material layer 24b, a first electrode material layer 21b, a third dielectric material layer 24c, and a second electrode material layer 22b.

[0145] Next, step S03 is performed to form a first electrode hole (the first opening 26) and a second electrode hole (the second opening 28) that at least partially penetrate the stack, and alternately form a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately form a second conductor and a second spacer on the inner wall of the second electrode hole. Each first conductor connects each first electrode material layer in the first electrode hole and leads to the top of the first electrode hole. Each first spacer isolates each second electrode material layer in the first electrode hole. Each second conductor connects each second electrode material layer in the second electrode hole and leads to the top of the second electrode hole. Each second spacer isolates each first electrode material layer in the second electrode hole.

[0146] Specifically, reference can be made to Figures 3c to 3l , in the stack to form as Figure 5cIn the structure shown, the remaining first conductive material layer 29a on the sidewall of the first opening 26 serves as the first conductor 33a, which covers the remaining second spacer material layer and the sidewalls of the first part 26a (the first electrode material layer 21a) for electrically leading out the first electrode material layer 21a. The remaining first conductive material layer 29a on the sidewall of the second opening 28 serves as the second conductor 32a, which covers the second spacer 31a and the sidewalls of the fourth part 28b (the second electrode material layer 22a) for electrically leading out the second electrode material layer 22a. Moreover, the bottom of the first opening 26 exposes the surface of the first electrode material layer 21b, and the second part 26b within the first opening 26 exposes the sidewalls of the first dielectric material layer 24a, the second electrode material layer 22a, and the second dielectric material layer 24b. The bottom of the second opening 28 exposes the surface of the second electrode material layer 22b, and the third part 28a within the second opening 28 exposes the sidewalls of the second dielectric material layer 24b, the first electrode material layer 21b, and the third dielectric material layer 24c. It should be particularly noted that the first opening 26 is located directly above at least one metal interconnect 11 for connecting the first electrode material layer, and the second opening 28 is located directly above at least one metal interconnect 11 for connecting the second electrode material layer.

[0147] Please refer to Figure 5d , form a third spacer material layer 27c conformally covering the surface of the stack (the hard mask layer 25), the inner wall of the first opening 26, and the inner wall of the second opening 28. Then perform an etching process to remove the third spacer material layer 27c on the surface of the hard mask layer 25 (the stack), the bottom of the first opening 26, and the bottom of the second opening 28. Use the remaining third spacer material layer 27c covering the sidewall of the first opening 26 (the sidewalls of the first conductor and the second part 26b) as the first spacer 34a, and expose the surface of the first electrode material layer 21b. Use the remaining third spacer material layer 27c covering the sidewall of the second opening 28 (the sidewalls of the second conductor 32a and the third part 28a) as the second spacer 31b, and expose the surface of the second electrode material layer 22b. Then continue etching to remove one layer of the electrode material layer 23 and stop, that is, remove the first electrode material layer 21b at the bottom of the first opening 26, expose the sidewall of the first electrode material layer 21b and the surface of the third dielectric material layer 24c, remove the second electrode material layer 22b at the bottom of the second opening 28, and expose the sidewall of the second electrode material layer 22b and the surface of the substrate 10. In this embodiment, the material of the third spacer material layer 27c can be the same as that of the first spacer material layer 27a or the second spacer material layer 27b, and can be formed by atomic layer deposition process to improve the step coverage.

[0148] Please refer to Figure 5e, a second conductive material layer 29b is formed to conformally cover the surface of the hard mask layer 25, the inner walls of the first opening 26, and the inner walls of the second opening 28. The material of the second conductive material layer 29b can be any suitable conductive material, and preferably, an atomic layer deposition process can be used to form it to improve the film quality and step coverage. In this embodiment, the material of the second conductive material layer 29b can be the same as that of the first conductive material layer 29a to simplify the process. In the first opening 26, the second conductive material layer 29b covers the first spacer 34a, the sidewalls of the first electrode material layer 21b (i.e., the first part 26a), and the surface of the third dielectric material layer 24c; in the second opening 28, the second conductive material layer 29b covers the second spacer 31b, the sidewalls of the second electrode material layer 22b (i.e., the fourth part 28b), and the surface of the substrate 10.

[0149] Please refer to Figure 5f , perform an etching process to remove the second conductive material layer 29b at the bottoms of the first opening 26 and the second opening 28 (exposing the surface of the third dielectric material layer 24c at the bottom of the first opening 26 and exposing the surface of the substrate 10 at the bottom of the second opening 28), and then continue to perform an etching process to etch two material layers downward (including one dielectric material layer 24 and one electrode material layer 23), and the etching stops at the surface of the insulating dielectric layer on the metal interconnection 11 in the substrate 10, that is, in the first opening 26, the third dielectric material layer 24c, the second electrode material layer 22b, and a part of the insulating dielectric layer in the substrate 10 are sequentially etched and removed, and in the second opening 28, a part of the insulating dielectric layer in the substrate 10 is etched and removed. After performing the above etching process, the remaining second conductive material layer 29b on the sidewalls of the first opening 26 is used as the first conductor 33b, which covers the first spacer 34a and the sidewalls of the first part 26a (the first electrode material layer 21b) and is used for electrically leading out the first electrode material layer 21b, and the remaining second conductive material layer 29b on the sidewalls of the second opening 28 is used as the second conductor 32b, which covers the second spacer 31b and the sidewalls of the fourth part 28b and is used for electrically leading out the second electrode material layer 22b. Moreover, the bottom of the first opening 26 extends into the substrate 10, and the second part 26b in the first opening 26 exposes the sidewalls of the third dielectric material layer 24c and the second electrode material layer 22b, and the bottom of the second opening 28 extends into the substrate 10. Among them, the bottoms of the first opening 26 and the second opening 28 can preferably stop etching on the etching stop layer on the metal interconnection 11 in the substrate 10 (the material of which can include, for example, silicon nitride).

[0150] In this embodiment, an etching process with a low etching selectivity to the spacer material layer, the dielectric material layer 24, the electrode material layer 23, and the conductive material layer can be selected, and the above effects can be achieved through synchronous etching. Of course, the second conductive material layer 29b on the hard mask layer 25 can also be completely removed in the above etching process. In addition, during the above etching process, due to the low etching selectivity, the top of the hard mask layer 25 and other exposed material layers (including the spacer material layer and the conductive material layer) are also consumed by a part of their thickness synchronously, so that the periphery of the first opening 26 and the second opening 28 can basically remain flat, that is, there is no or only a small step height difference between the hard mask layer 25 and the spacer material layer and the conductive material layer in the first opening 26 and the second opening 28.

[0151] Please refer to Figure 5g , perform a third lithography process and an etching process on the stacked body to remove the hard mask layer 25, the electrode material layer 23, and the dielectric material layer 24 outside the capacitor region AA, and expose the surface of the substrate 10 outside the capacitor region AA.

[0152] Please refer to Figure 5h , form a fourth spacer material layer 27d to conformally cover the surface of the substrate 10, the outer wall of the stacked body, the inner wall of the first opening 26, and the inner wall of the second opening 28. The fourth spacer material layer 27d can be any suitable insulating material different from the hard mask layer 25. In this embodiment, the material of the fourth spacer material layer 27d can be the same as that of the first spacer material layer 27a, and an atomic layer deposition process can be used to form it to improve the step coverage.

[0153] Please refer to Figure 5i , perform an etching process to remove the fourth spacer material layer 27d on the surface of the substrate 10, the surface of the hard mask layer 25, the bottom of the first opening 26, and the bottom of the second opening 28, and use the remaining fourth spacer material layer 27d covering the side wall of the first opening 26 (the side walls of the first conductor 33b, the second part 26b, and the part extending into the substrate 10) as the first spacer 34b, and expose the substrate 10. Use the remaining fourth spacer material layer 27d covering the side wall of the second opening 28 (the side walls of the second conductor 32b and the part extending into the substrate 10) as the second spacer 31c, and expose the substrate 10. Use the remaining fourth spacer material layer 27d covering the side wall of the stacked body as the sidewall 35 to isolate the side wall of the stacked body.

[0154] Please refer to Figure 5j, a patterning process is performed on the insulating material layer on the surface of the substrate 10 to form redistribution holes 41 that expose the metal interconnects 11. Among them, the exposed metal interconnects 11 include the metal interconnects 11 corresponding to the first opening 26 and the second opening 28 and other metal interconnects 11 outside the capacitor region AA. The specific process may include: forming a patterned photoresist layer covering the substrate 10 and the stack, and the opening of the patterned photoresist layer is projected onto the surface of the metal interconnects 11 outside the capacitor region AA; then, using the patterned photoresist layer to etch away the insulating dielectric layer above the metal interconnects 11, and the etching stops at the etch stop layer on the metal interconnects 11; then, in-situ removing the patterned photoresist layer, and performing an etching process to remove the etch stop layer on the metal interconnects 11 to expose the metal interconnects 11 outside the capacitor region AA, the metal interconnects 11 below the first opening 26 and the second opening 28.

[0155] Please refer to Figure 5k , a redistribution metal layer is formed to cover the surface of the substrate 10 and the outer wall of the stack, and fill the redistribution holes 41, the first opening 26 and the second opening 28, and a patterning process is performed on the redistribution metal layer to form redistribution lines 42 in the stack to electrically connect the metal interconnects 11 to the first electrode material layer and the second electrode material layer of the capacitor structure respectively, and form redistribution lines 42 on the surface of the substrate 10 to electrically lead out the metal interconnects 11. Among them, the redistribution metal layer at the top of the first opening 26 can be used as a conductive cap 43 to connect the first conductor 33a and the first conductor 33b in the first opening 26, and the electrical connection is the first electrode material layer 21a and the first electrode material layer 21b. The redistribution metal layer in the first opening 26 can be the redistribution line 42 for electrically connecting the conductive cap 43 (the first electrode) and the corresponding metal interconnect 11. The redistribution metal layer at the top of the second opening 28 can be used as a conductive cap 43 to connect the second conductor 32a and the second conductor 32b in the second opening 28, that is, electrically connect the second electrode material layer 22a and the second electrode material layer 22b. The redistribution metal layer in the second opening 28 can be the redistribution line 42 for electrically connecting the conductive cap 43 (the second electrode) and the corresponding metal interconnect 11. Among them, the material of the redistribution metal layer may include aluminum or copper-aluminum alloy, etc.

[0156] In particular, in the remaining examples of this embodiment, when the number of electrode layers of the formed capacitor structure is greater than 4 layers, a similar manufacturing method as above can also be adopted. Figure 5lThe capacitor structure shown includes 10 electrode material layers 23 and 9 dielectric material layers 24, that is, it includes 5 first electrode material layers (21a, 21b, 21c, 21d, 21e) and 5 second electrode material layers (22a, 22b, 22c, 22d, 22e) and the first to ninth dielectric material layers (24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i). Please refer to Figure 5l , to form Figure 5l The process of forming the capacitor structure shown may include: First, referring to Figures 3c to 3l , in the first to fourth electrode material layers (21a, 21b, 22a, 22b) in the stack, form a first opening 26 to expose the surface of the third electrode material layer 21b and the side wall of the second part 26b, and form a second opening 28 to expose the surface of the fourth electrode material layer 22b and the side wall of the third part 28a, and form a first conductor 33a connecting the first electrode material layer 21a on the side wall of the first opening 26, and form a second spacer 31a isolating the first electrode material layer 21a and a second conductor 32a connecting the second electrode material layer 22a on the side wall of the second opening 28; Next, referring to Figures 3i to 3l , repeat Figures 3i to 3l the corresponding steps, expand (etch) the first opening 26 and the second opening 28 downward to the fifth to sixth electrode material layers (21c, 22c), form a first opening 26 to expose the surface of the fifth electrode material layer 21c and the side wall of the second part 26b, and form a second opening 28 to expose the surface of the sixth electrode material layer 22c and the surface of the third part 28a, and form a first spacer 34a isolating the second electrode material layer 22a and a first conductor 33b connecting the third electrode material layer 21b on the side wall of the first opening 26, and form a second spacer 31b isolating the third electrode material layer 21b and a second conductor 32b connecting the fourth electrode material layer 22b on the side wall of the second opening 28; Next, continue to refer to Figures 3i to 3l , repeat Figures 3i to 3l the corresponding steps, expand the first opening 26 and the second opening 28 downward to the seventh to eighth electrode material layers (21d, 22d), form a first opening 26 to expose the surface of the seventh electrode material layer 21d and the side wall of the second part 26b, and form a second opening 28 to expose the surface of the eighth electrode material layer 22d, and form a first spacer 34b isolating the fourth electrode material layer 22b and a first conductor 33c connecting the fifth electrode material layer 21c on the side wall of the first opening 26, and form a second spacer 31c isolating the fifth electrode material layer 21c and a second conductor 32c connecting the sixth electrode material layer 22c on the side wall of the second opening 28; Next, similarly repeat several groups of Figures 3i to 3lThe corresponding steps (in this example, repeating a group is sufficient) until the first opening 26 and the second opening 28 are extended downward to the ninth to tenth electrode material layers (21e, 22e), the first opening 26 exposes the surface of the ninth electrode material layer 21e and the sidewall of the second part 26b, and the second opening 28 is formed to expose the surface of the tenth electrode material layer 22e and the sidewall of the third part 28a, and a first spacer 34c for isolating the sixth electrode material layer 22c and a first conductor 33d connecting the seventh electrode material layer 21d are formed on the sidewall of the first opening 26, and a second spacer 31d for isolating the seventh electrode material layer 21d and a second conductor 32d connecting the eighth electrode material layer 22d are formed on the sidewall of the second opening 28; then, please refer to Figures 5d to 5k , to pattern the stack (including the third lithography process), and complete the electrical connection between the first electrode and the second electrode of the capacitor structure and the corresponding metal interconnection line 11, thereby forming a capacitor structure including 10 electrode layers as shown in Figure 5l .

[0157] Thus, in this embodiment, a multi-layer capacitor structure can be fabricated by only three photomasks and three lithography processes (excluding the patterning processes of redistribution vias and redistribution lines), which is beneficial to saving lithography resources and reducing the cost of photomasks. Moreover, the sizes of the first opening (the first electrode via) and the second opening (the second electrode via) gradually decrease from top to bottom, which is also beneficial to releasing more effective area to increase the capacitance value. In particular, in this embodiment, the current input to the capacitor structure does not flow through the redistribution vias but is directly connected to the underlying metal interconnection line at the electrode vias, avoiding the resistance introduced by the additional redistribution lines and reducing the parasitic capacitance, resulting in better frequency characteristics.

[0158] Embodiment 4

[0159] Embodiment 4 provides a method for manufacturing a multi-layer capacitor structure.

[0160] Figure 2 is a flowchart of the method for manufacturing the multi-layer capacitor structure provided in Embodiment 4.

[0161] As shown in Figure 2 , the method for manufacturing the multi-layer capacitor structure provided in this embodiment includes:

[0162] S01: Provide a substrate;

[0163] S02: Alternately stack a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stack, and the plurality of electrode material layers include a first electrode and a second electrode that are alternately arranged in sequence;

[0164] S03: Form first and second electrode holes that at least partially penetrate the stack, alternately form first conductors and first spacings on the inner wall of the first electrode hole, and alternately form second conductors and second spacings on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole. Each of the first spacings isolates each of the second electrodes. Each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole. Each of the second spacings isolates each of the first electrodes;

[0165] S04: Form conductive caps at the tops of the first electrode hole and the second electrode hole respectively to electrically connect each of the first conductors and each of the second conductors respectively.

[0166] The manufacturing method of the multi-layer capacitor structure provided in the fourth embodiment is basically similar to that of the third embodiment, and the difference lies only in the different ways of electrically leading out the metal interconnections under the stack (that is, the steps after Figure 5f in the third embodiment are different). Figure 6a The steps of Figures 5a to 5f can refer to the Figures 6a to 6h method of the first embodiment. Figures 6a to 6h FIG.

[0167] First, referring to Figures 5a to 5f of the third embodiment, a structure as shown in Figure 6a is formed in the stack. A second conductive material layer 29b is conformally formed to cover the surface of the hard mask layer 25, the inner walls of the first opening 26, and the inner walls of the second opening 28. The material of the second conductive material layer 29b can be any suitable conductive material, and preferably, an atomic layer deposition process can be used to form it to improve the film quality and step coverage. In this embodiment, the material of the second conductive material layer 29b can be the same as that of the first conductive material layer 29a to simplify the process. In the first opening 26, the second conductive material layer 29b covers the first spacing 34a, the sidewalls of the first electrode material layer 21b (i.e., the first part 26a), and the surface of the third dielectric material layer 24c. In the second opening 28, the second conductive material layer 29b covers the second spacing 31b, the sidewalls of the second electrode material layer 22b (i.e., the fourth part 28b), and the surface of the substrate 10.

[0168] Please refer to Figure 6b, an etching process is performed to remove the second conductive material layer 29b at the bottom of the first opening 26 and the bottom of the second opening 28 (exposing the third dielectric material layer 24c at the bottom of the first opening 26 and the surface of the substrate 10 at the bottom of the second opening 28), and then the etching process is continued to etch downward until the surface of the metal interconnect 11 in the substrate 10 is exposed, that is, the third dielectric material layer 24c, the second electrode material layer 22b, and the insulating dielectric layer of the substrate 10 (including the etch stop layer on the surface of the metal interconnect 11) are sequentially etched away within the first opening 26, and the insulating dielectric layer of the substrate 10 (including the etch stop layer on the surface of the metal interconnect 11) is etched away within the second opening 28. After performing the above etching process, the remaining second conductive material layer 29b on the sidewall of the first opening 26 is used as the first conductor 33b, which covers the sidewalls of the first spacer 34a and the first portion 26a (the first electrode material layer 21b) for electrically leading out the first electrode material layer 21b, and the remaining second conductive material layer 29b on the sidewall of the second opening 28 is used as the second conductor 32b, which covers the sidewalls of the second spacer 31b and the fourth portion 28b (the second electrode material layer 22b) for electrically leading out the second electrode material layer 22b. Moreover, the bottom of the first opening 26 exposes the surface of the corresponding metal interconnect 11, the second portion 26b within the first opening 26 exposes the sidewalls of the third dielectric material layer 24c and the second electrode material layer 22b, and the bottom of the second opening 28 exposes the surface of the corresponding metal interconnect 11.

[0169] In this embodiment, an etching process with a relatively low etching selectivity to the spacer material layer, the dielectric material layer 24, the electrode material layer 23, and the conductive material layer can be selected, and the above effect can be achieved through synchronous etching. Of course, the second conductive material layer 29b on the hard mask layer 25 can also be completely removed in the above etching process. In addition, during the above etching process, due to the relatively low etching selectivity, the top of the hard mask layer 25 and other exposed material layers (including the spacer material layer and the conductive material layer) are also consumed by a part of their thickness synchronously, so that the periphery of the first opening 26 and the second opening 28 can be basically kept flat, that is, there is no or only a small step height difference between the hard mask layer 25 and the spacer material layer and the conductive material layer within the first opening 26 and the second opening 28.

[0170] Please refer to Figure 6c , a fourth spacer material layer 27d is formed to conformally cover the surface of the stack, the inner wall of the first opening 26, and the inner wall of the second opening 28. The fourth spacer material layer 27d can be any suitable insulating material with a different material from the hard mask layer 25. In this embodiment, the material of the fourth spacer material layer 27d can be the same as that of the first spacer material layer 27a, and an atomic layer deposition process can be used to form it to improve the step coverage.

[0171] Please refer to Figure 6d, Perform an etching process to remove the fourth spacer material layer 27d on the surface of the substrate 10, the surface of the hard mask layer 25, the bottom of the first opening 26, and the bottom of the second opening 28. Use the remaining fourth spacer material layer 27d covering the sidewalls of the first opening 26 (the sidewalls of the first conductor, the second part 26b, and the part extending into the substrate 10) as the first spacer 34b, and expose the surface of the corresponding metal interconnect 11. Use the remaining fourth spacer material layer 27d covering the sidewalls of the second opening 28 (the sidewalls of the second conductor 32b and the part extending into the substrate 10) as the second spacer 31c, and expose the surface of the corresponding metal interconnect 11.

[0172] Please refer to Figure 6e , Form a third conductive material layer 29c to cover the surface of the hard mask layer 25, and fill the first opening 26 and the second opening 28 above the hard mask layer 25 (i.e., fill the first opening 26 and the second opening 28 completely). The material of the third conductive material layer 29c can refer to the material of the first conductive material layer 29a, for example, including titanium nitride, and is formed by processes such as PVD, CVD, or atomic layer deposition.

[0173] Please refer to Figure 6f , Perform a third lithography process and an etching process on the stack covered with the third conductive material layer 29c to remove the hard mask layer 25, the electrode material layer 23, the dielectric material layer, the hard mask layer 25 (i.e., the stack outside the capacitor region AA), and the third conductive material layer 29c on the surface of the hard mask layer 25 outside the capacitor region AA. Retain the third conductive material layer 29c in the first opening 26 and the second opening 28. Use the third conductive material layer 29c in the first opening 26 as the redistribution line 42 of the first opening 26, and the third conductive material layer 29c in the second opening 28 as the redistribution line 42 of the second opening 28, and expose the surface of the hard mask layer 25 and the surface of the substrate 10 outside the capacitor region AA. Specifically, a patterned photoresist layer can be formed to only cover the stack in the capacitor region AA first, then, etch and remove the third conductive material layer 29c, the hard mask layer 25, the electrode material layer 23, and the dielectric material layer 24 outside the capacitor region AA, then remove the patterned photoresist layer, and then, etch and remove the third conductive material layer 29c on the surface of the hard mask layer 25.

[0174] Please refer to Figure 6g , Form sidewalls 35 to cover the sidewalls of the stack, and perform an isolation (insulation) treatment on the sidewalls of the stack.

[0175] Please refer to Figure 6h, a patterning process is performed on the insulating dielectric layer on the surface of the substrate 10 to form redistribution holes 41 exposing the metal interconnects 11, and then a redistribution metal layer is formed to cover the surface of the substrate 10 and the outer walls of the stack, and the redistribution holes 41 are filled, and a patterning process is performed on the redistribution metal layer to form redistribution lines 42 electrically connecting the metal interconnects 11 with the first electrode material layer and the second electrode material layer of the capacitor structure respectively. Among them, the redistribution metal layer at the top of the first opening 26 can be used as a conductive cap 43 to connect the first conductor 33a and the first conductor 33b in the first opening 26, that is, electrically connect the first electrode material layer 21a and the first electrode material layer 21a21b. The redistribution metal layer at the top of the second opening 28 can be used as a conductive cap 43 to connect the second conductor 32a and the second conductor 32b in the second opening 28, that is, electrically connect the second electrode material layer 22a and the second electrode material layer 22b. The redistribution lines 42 on the surface of the substrate 10 can electrically lead out the metal interconnects 11 under the substrate 10. The material of the redistribution metal layer may include aluminum or copper-aluminum alloy, etc. It can be understood that the thickness of the redistribution metal layer is relatively thick (large amount of usage), and its material usually includes metal aluminum, while the material of the third conductive material layer 29c is usually an electrode material (such as titanium nitride). Compared with filling the redistribution metal layer in the first opening 26 or the second opening 28 with a high aspect ratio, even the third conductive material layer 29c formed by the PVD process has a better filling effect (step coverage rate), which is beneficial to solving the problem that it is difficult to fill with metal aluminum.

[0176] Specifically, in the remaining examples of this embodiment, when the number of electrode layers of the formed capacitor structure is greater than 4 layers, a similar manufacturing method as described above can also be adopted. Figure 6i The shown capacitor structure includes 10 electrode material layers 23 and 9 dielectric material layers 24, that is, it includes 5 first electrode material layers (21a, 21b, 21c, 21d, 21e) and 5 second electrode material layers (22a, 22b, 22c, 22d, 22e) and the first to ninth dielectric material layers (24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i). The manufacturing method can refer to Figure 5l the manufacturing method of the capacitor structure with 10-layer electrodes.

[0177] Therefore, in this embodiment, the multilayer capacitor structure can be prepared by only three masks and three photolithography processes (excluding the patterning process of redistribution holes and redistribution lines), which is beneficial to saving photolithography resources and reducing mask costs, and the sizes of the first opening (first electrode hole) and the second opening (second electrode hole) are smaller layer by layer from top to bottom, which can also help release more effective area to increase the capacitance value. In particular, in this embodiment, the current of the input capacitor structure does not need to flow through the redistribution hole, but is directly connected to the metal interconnection line below at the electrode hole, avoiding the resistance introduced by the additional redistribution line, and reducing the parasitic capacitance, so that it has better frequency characteristics.

[0178] Embodiment 5

[0179] Embodiment 5 provides a multilayer capacitor structure.

[0180] Figure 3p , Figure 3r , Figure 4f , Figure 4g , Figure 5k , Figure 5l , Figure 6h and Figure 6i This is a schematic diagram of a multilayer capacitor structure provided in Example 5.

[0181] The multilayer capacitor structure provided in this embodiment includes a substrate, a stack, a first electrode hole (first opening), a second electrode hole (second opening), a first conductor, a first spacer, a second conductor, a second spacer and a conductive cap. The stack is provided on the substrate, and is formed by alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers, wherein the plurality of electrode material layers include first electrodes (first electrode material layers) and second electrodes (second electrode material layers) alternately arranged in sequence; the first electrode hole at least partially penetrates the stack, wherein first conductors and first spacers are alternately arranged, wherein each first conductor is connected to each first electrode and leads to the top of the first electrode hole, and each first spacer isolates each second electrode; the second electrode hole at least partially penetrates the stack, wherein second conductors and second spacers are alternately arranged, wherein each second conductor is connected to each second electrode and leads to the top of the second electrode hole, and each second spacer isolates each first electrode; two conductive caps are respectively located at the top of the first electrode hole and the second electrode hole, and are respectively connected to each first electrode or each second electrode.

[0182] Specifically, in Figure 3p and Figure 3rIn the multi-layer capacitor structure shown, the first electrode hole (the first opening 26) is used to electrically lead out the first electrode material layer (such as 21a, 21b, 21c, 21d, 21e) of the capacitor structure. The conductive cap 43 provided at the top of the first electrode hole is used to connect the first electrode material layer (such as 21a, 21b, 21c, 21d, 21e) used in the first electrode hole. The second electrode hole (the second opening 28) is used to electrically lead out the second electrode material layer (such as 22a, 22b, 22c, 22d, 22e) of the capacitor structure. The conductive cap 43 provided at the top of the second electrode hole is used to connect the second electrode material layer (such as 22a, 22b, 22c, 22d, 22e) used in the second electrode hole. The metal interconnect line 11 connected to the capacitor structure is located in the substrate 10 outside the stack (capacitor region AA). The redistribution line 42 passes through the redistribution hole 41 on the surface of the substrate 10 and is connected to the conductive caps 43 at the tops of the first electrode hole and the second electrode hole along the outer wall of the stack, that is, connected to the electrodes corresponding to the capacitor structure. Among them, neither the first electrode hole nor the second electrode hole completely penetrates the stack, specifically as Figure 7As shown, the first electrode hole includes a first part 26a and a second part 26b with diameters decreasing successively from top to bottom and arranged alternately. The first part 26a penetrates the first electrode material layer and exposes the sidewall of the first electrode material layer. The second part 26b penetrates the second electrode material layer and its adjacent dielectric material layer 24, and exposes the sidewalls of the second electrode material layer and the corresponding (adjacent) dielectric material layer. The bottom of the first electrode hole is the surface of the lowermost (bottommost) first electrode material layer in the stack. The first conductor (such as 33a, 33b, 33c, 33d, 33e) is connected to the sidewall of the first material layer exposed by the first part 26a and extends upward to the top of the first electrode hole. The first spacer covers the sidewalls of the second electrode material layer and the dielectric material layer exposed by the second part 26b and extends upward to the top of the first electrode hole and is connected to the lowermost first electrode material layer. The first conductor connected to the lowermost first electrode material layer fills the first electrode hole. The decreasing sizes of the adjacent first part 26a and second part 26b are twice the thickness of the corresponding first conductor or first spacer. The second electrode hole includes a third part 28a and a fourth part 28b with diameters decreasing successively from top to bottom and arranged alternately. The third part 28a penetrates the first electrode material layer (such as 21a, 21b, 21c, 21d, 21e) and its adjacent dielectric material layer, and exposes the sidewalls of the first electrode material layer and the adjacent dielectric material layer. The fourth part 28b penetrates the second electrode material layer (such as 22a, 22b, 22c, 22d, 22e) and exposes the sidewall of the second electrode material layer. The bottom of the second electrode hole is the surface of the lowermost second electrode material layer in the stack. The second spacer covers the sidewalls of the first electrode material layer and the corresponding dielectric material layer exposed by the third part 28a and extends upward to the top of the second electrode hole. The second conductor (such as 32a, 32b, 32c, 32d, 32d) is connected to the sidewall of the second electrode material layer exposed by the fourth part 28b and extends upward to the top of the second electrode hole. The second conductor connected to the lowermost second electrode material layer fills the second electrode hole. The decreasing sizes of the adjacent third part 28a and fourth part 28b are twice the thickness of the corresponding second conductor or second spacer. Particularly, in this example, the materials of the two conductive caps 43, the first conductor connected to the lowermost first electrode material layer, and the second conductor connected to the lowermost second electrode material layer are the same as the material of the redistribution line 42. Of course, the materials of the first conductor connected to the lowermost first electrode material layer and the second conductor connected to the lowermost second electrode material layer are different from the materials of the remaining first conductors or the remaining second conductors.

[0183] Figure 4f and Figure 4g The multi-layer capacitor structure and the overall structure shown in Figure 3p and Figure 3r The multi-layer capacitor structure shown in is basically similar, and the difference is only that: in Figure 4f and Figure 4gIn the multi-layer capacitor structure shown, the materials of the first conductor connected to the first electrode material layer of the lowermost layer and the second conductor connected to the second electrode material layer of the lowermost layer are different from those of the redistribution line 42 and the conductive cap 43, and are the same as those of the remaining first conductors or the remaining second conductors. The material can be an electrode material, such as titanium nitride.

[0184] In Figure 5k and Figure 5lIn the multi-layer capacitor structure shown, similar to the above, the first electrode hole (the first opening 26) is used to electrically lead out the first electrode material layer of the capacitor structure, and the second electrode hole (the second opening 28) is used to electrically lead out the second electrode material layer of the capacitor structure. The conductive cap 43 provided at the top of the second electrode hole is used to connect the second electrode material layer used in the second electrode hole. Different from the above, the metal interconnect line 11 connected to the capacitor structure is located in the substrate 10 below the stack (capacitor region AA). Both the first electrode hole and the second electrode hole completely penetrate the stack, and the bottoms of the first electrode hole and the second electrode hole respectively expose the surfaces of the corresponding metal interconnect lines 11. Among them, the first electrode hole includes a first part 26a and a second part 26b with diameters decreasing in sequence from top to bottom and arranged alternately. The first part 26a penetrates the first electrode material layer and exposes the sidewall of the first electrode. The second part 26b penetrates the second electrode material layer and its adjacent dielectric material layer, and exposes the sidewalls of the second electrode material layer and the corresponding (adjacent) dielectric material layer. The bottom of the first electrode hole is the surface of the corresponding metal interconnect line 11. The first conductor (such as 33a, 33b, 33c, 33d, 33e) is connected to the sidewall of the first electrode material layer exposed by the first part 26a and extends upward to the top of the first electrode hole. The first spacer covers the sidewalls of the second electrode material layer and the dielectric material layer exposed by the second part 26b and extends upward to the top of the first electrode hole. The redistribution line 42 fills the remaining part of the first electrode hole, connects to the metal interconnect line 11 and extends to the top of the first electrode hole. The conductive cap 43 provided at the top of the first electrode hole is used to connect all the first electrode material layers and the redistribution line 42 in the first electrode hole. The decreasing size of the adjacent first part 26a and second part 26b is twice the thickness of the corresponding first conductor or first spacer. The second electrode hole includes a third part 28a and a fourth part 28b with diameters decreasing in sequence from top to bottom and arranged alternately. The third part 28a penetrates the first electrode material layer and its adjacent dielectric material layer, and exposes the sidewalls of the first electrode material layer and the adjacent dielectric material layer. The fourth part 28b penetrates the second electrode material layer and exposes the sidewall of the second electrode material layer. The bottom of the second electrode hole is the surface of the corresponding metal interconnect line 11. The second spacer covers the sidewalls of the first electrode material layer and the corresponding dielectric material layer exposed by the third part 28a and extends upward to the top of the second electrode hole. The second conductor (such as 32a, 32b, 32c, 32d, 32d) is connected to the sidewall of the second electrode material layer exposed by the fourth part 28b and extends upward to the top of the second electrode hole. The redistribution line 42 fills the remaining part of the second electrode hole, connects to the metal interconnect line 11 and extends to the top of the second electrode hole. The conductive cap 43 provided at the top of the second electrode hole is used to connect all the second electrode material layers and the redistribution line 42 in the second electrode hole. The decreasing size of the adjacent third part 28a and fourth part 28b is twice the thickness of the corresponding second conductor or second spacer.Specifically, in this example, the two conductive caps 43 and the two redistribution lines 42 are made of the same material, for example, formed synchronously using a redistribution metal layer. Of course, the material of the two redistribution lines 42 is different from that of the first conductor or the second conductor.

[0185] Figure 6h and Figure 6i The multi-layer capacitor structure and the overall structure shown are Figure 5k and Figure 5l The multi-layer capacitor structure shown is basically similar, and the difference is only that: in Figure 6h and Figure 6i In the multi-layer capacitor structure shown, the material of the redistribution lines 42 in the two electrode holes is different from that of the conductive caps 43. The material of the redistribution lines 42 in the two electrode holes can be the same as that of the first conductor or the second conductor, and it is an electrode material, such as titanium nitride.

[0186] Embodiment Six

[0187] Embodiment Six provides a multi-layer capacitor structure.

[0188] The multi-layer capacitor structure provided in this embodiment is similar to the multi-layer capacitor structure provided in Embodiment Five, and both have electrode holes with the same settings and the structures inside. However, different from the flat capacitor formed by multiple electrode material layers and dielectric material layers in the stack of Embodiment Five, the stack of this embodiment includes a trench capacitor formed by multiple electrode material layers and dielectric material layers. Of course, the stack of this embodiment can also include a flat capacitor formed by electrode material layers and dielectric material layers.

[0189] In summary, the multi-layer capacitor structure provided by the present invention includes a stack disposed on a substrate and formed by alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers. The plurality of electrode material layers include a first electrode and a second electrode alternately arranged in sequence. There is a first electrode hole at least partially penetrating the stack, in which a first conductor and a first spacer are alternately provided. Each first conductor connects each first electrode and extends to the top of the first electrode hole. Each first spacer isolates each second electrode. There is a second electrode hole at least partially penetrating the stack, in which a second conductor and a second spacer are alternately provided. Each second conductor connects each second electrode and extends to the top of the second electrode hole. Each second spacer isolates each first electrode. There are two conductive caps respectively located at the tops of the first electrode hole and the second electrode hole, and each is connected to each first electrode and each second electrode. Compared with the conventional multi-layer capacitor structure where an additional mask and one additional lithography are required for each additional layer, the multi-layer capacitor structure of the present invention does not require an increase in the number of masks and lithography. It always only requires 3 masks and three lithographies, which can significantly reduce the mask cost and save lithography resources. Compared with the multi-layer capacitor structure of the multiplexing mask scheme where an additional lithography is required for each additional layer, the multi-layer capacitor structure of the present invention does not require an increase in the number of lithographies. It always only requires three lithographies, which can significantly save lithography resources and reduce the dependence on lithography production capacity. Moreover, compared with the conventional multi-layer capacitor structure where an additional electrode hole is required for each additional layer to lead out the corresponding electrode, the multi-layer capacitor structure of the present invention always only requires 2 electrode holes, which can significantly reduce the area occupied by the electrode holes on the electrode plate to release a larger effective area to increase the capacitance value. Compared with the multi-layer capacitor structure of the multiplexing mask scheme (two electrode holes) where the electrode holes of each layer have the same size, the electrode holes in the multi-layer capacitor structure of the present invention gradually decrease from top to bottom, which can release a larger effective area in the electrodes near the substrate to increase the capacitance value.

[0190] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A multi-layer capacitor structure, characterized in that, Comprising: A substrate; A stack formed by alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers, disposed on the substrate, and the plurality of electrode material layers include a first electrode and a second electrode alternately arranged in sequence; A first electrode hole at least partially penetrating the stack, in which a first conductor and a first spacer are alternately provided, each first conductor is connected to each first electrode and led out to the top of the first electrode hole, and each first spacer isolates each second electrode; A second electrode hole at least partially penetrating the stack, in which a second conductor and a second spacer are alternately provided, each second conductor is connected to each second electrode and led out to the top of the second electrode hole, and each second spacer isolates each first electrode; Two conductive caps respectively located at the tops of the first electrode hole and the second electrode hole, and electrically connected to each first conductor and each second conductor respectively.

2. The multi-layer capacitor structure according to claim 1, wherein Further comprising metal interconnect lines and redistribution lines, the metal interconnect lines are disposed in the substrate outside the stack, and the redistribution lines are respectively connected to the conductive caps and the corresponding metal interconnect lines along the outer wall of the stack.

3. The multilayer capacitor structure according to claim 2, characterized in that, The first electrode hole does not completely penetrate the stack and its bottom wall is the surface of the lowermost first electrode. The first electrode hole includes a first part and a second part with diameters decreasing in sequence from top to bottom and alternately arranged. The first part penetrates the first electrode, and the second part penetrates the second electrode and its adjacent dielectric material layer. The first conductor is connected to the side wall of the first electrode exposed by the first part, and the first spacer covers the side walls of the second electrode and the dielectric material layer exposed by the second part.

4. The multi-layer capacitor structure according to claim 2, wherein The second electrode hole does not completely penetrate the stack and its bottom wall is the surface of the lowermost second electrode. The second electrode hole includes a third part and a fourth part with diameters decreasing in sequence from top to bottom and alternately arranged. The third part penetrates the first electrode and its adjacent dielectric material layer, and the fourth part penetrates the second electrode. The second conductor is connected to the side wall of the second electrode exposed by the fourth part, and the first spacer covers the side walls of the first electrode and the dielectric material layer exposed by the third part.

5. The multilayer capacitor structure according to claim 3 or 4, characterized in that, The redistribution lines are made of the same material as the conductive caps, the first conductors, and the second conductors connecting the lowermost electrode material layer, Or, the redistribution lines are made of the same material as the conductive caps, but the materials of the first conductors and the second conductors connecting the lowermost electrode material layer are different from the materials of the redistribution lines.

6. The multi-layer capacitor structure according to claim 1, characterized in that, Further comprising metal interconnect lines and redistribution lines, the metal interconnect lines are disposed in the substrate below the stack, the first electrode hole and the second electrode hole both completely penetrate the stack and expose the surfaces of the corresponding metal interconnect lines respectively, and the redistribution lines are located in the first electrode hole and the second electrode hole and are respectively connected to the conductive caps and the corresponding metal interconnect lines.

7. The multilayer capacitor structure according to claim 6, wherein, The first electrode hole includes a first part and a second part which are alternately arranged and have gradually decreasing diameters from top to bottom. The first part penetrates through the first electrode, and the second part penetrates through the second electrode and its adjacent dielectric material layer, and the first part or the second part corresponding to the lowermost electrode material layer extends downward to expose the surface of the corresponding metal interconnect line. The first conductor is connected to the side wall of the first electrode exposed by the first part, and the first spacer covers the side walls of the second electrode and the dielectric material layer exposed by the second part.

8. The multilayer capacitor structure according to claim 6, characterized in that, The second electrode hole includes a third part and a fourth part which are alternately arranged and have gradually decreasing diameters from top to bottom. The third part penetrates through the first electrode and its adjacent dielectric material layer, and the fourth part penetrates through the second electrode, and the third part or the fourth part corresponding to the lowermost electrode material layer extends downward to expose the surface of the corresponding metal interconnect line. The second conductor is connected to the side wall of the second electrode exposed by the fourth part, and the second spacer covers the side walls of the first electrode and the dielectric material layer exposed by the third part.

9. The multilayer capacitor structure according to claim 7 or 8, characterized in that, The material of the redistribution line is the same as that of the conductive cap. Alternatively, the material of the redistribution line is different from that of the conductive cap.

10. The multilayer capacitor structure according to claim 1, characterized in that, The stack body includes a plurality of planar capacitors and / or trench capacitors formed by the plurality of electrode material layers and the plurality of dielectric material layers.

11. A manufacturing method of a multi-layer capacitor structure, characterized in that, Comprising: Providing a substrate; Alternately stacking a plurality of electrode material layers and a plurality of dielectric material layers on the substrate to form a stack body, and the plurality of electrode material layers include a first electrode and a second electrode which are alternately arranged in sequence; Forming a first electrode hole and a second electrode hole that at least partially penetrate the stack body, and alternately forming a first conductor and a first spacer on the inner wall of the first electrode hole, and alternately forming a second conductor and a second spacer on the inner wall of the second electrode hole. Each of the first conductors is connected to each of the first electrodes and led out to the top of the first electrode hole. Each of the first spacers isolates each of the second electrodes. Each of the second conductors is connected to each of the second electrodes and led out to the top of the second electrode hole. Each of the second spacers isolates each of the first electrodes; Forming conductive caps on the tops of the first electrode hole and the second electrode hole respectively, and electrically connecting each of the first conductors and electrically connecting each of the second conductors respectively.

12. The manufacturing method of the multilayer capacitor structure according to claim 11, characterized in that, The steps of forming the first conductor, the first spacer, the second conductor, and the second spacer include: Forming a hard mask layer to cover the surface of the stack body, and performing a first photolithography process and a corresponding etching process on the hard mask layer to form a first opening to expose the surface of the first electrode; Forming a first spacer material layer to cover the surface of the hard mask layer and the inner wall of the first opening; Performing a second photolithography process and a corresponding etching process to form a second opening that sequentially penetrates through the first spacer material layer, the hard mask layer, and the first electrode, and exposes the surface of the dielectric material layer; Removing the surface of the hard mask layer, the first spacer material layer at the bottom of the first opening, and the dielectric material layer at the bottom of the second opening, so that the bottom of the first opening exposes the surface of the first electrode, and the bottom of the second opening exposes the surface of the second electrode; Form a second spacer material layer to cover the surface of the hard mask layer, the inner walls of the first opening and the second opening; Remove the second spacer material layer on the surface of the hard mask layer, at the bottom of the first opening and at the bottom of the second opening, and use the remaining second spacer material layer located on the sidewall of the second opening as the second spacer; Remove the first electrode at the bottom of the first opening and the second electrode at the bottom of the second opening, so as to form a first part exposing the sidewall of the first electrode in the first opening, and a fourth part exposing the sidewall of the second electrode in the second opening; Form a first conductive material layer to cover the surface of the hard mask layer, the inner walls of the first opening and the second opening; Remove the first conductive material layer on the surface of the hard mask layer, at the bottom of the first opening and at the bottom of the second opening, and use the remaining first conductive material layer located on the sidewall of the second opening as the second conductor, and use the remaining first conductive material layer located on the sidewall of the first opening as the first conductor.

13. The manufacturing method of the multilayer capacitor structure according to claim 12, characterized in that, The substrate includes a capacitor region for forming a capacitor structure and metal interconnections provided outside the capacitor region. The step of electrically connecting the metal interconnections and the capacitor structure includes: Perform a third lithography process and a corresponding etching process on the stack, remove the stack outside the capacitor region, the bottom of the first electrode hole exposes the surface of the bottommost first electrode, and the bottom of the second electrode hole exposes the surface of the bottommost second electrode; Form sidewalls on the sidewalls of the stack, form the first spacer in the first electrode hole and form the second spacer in the second electrode hole; Form redistribution holes in the substrate to expose the metal interconnections; Form a redistribution metal layer to cover the surface of the substrate, the outer wall of the stack, fill the redistribution holes, the first electrode hole and the second electrode hole, and perform a patterning process on the redistribution metal layer, and use the redistribution metal layer filling the first electrode hole as the first conductor, use the redistribution metal layer filling the second electrode hole as the second conductor, use the redistribution metal layer at the top of the first electrode hole and the top of the second electrode hole as the conductive cap, and use the redistribution metal layer connecting the metal interconnection and the corresponding conductive cap as the redistribution line.

14. The manufacturing method of the multilayer capacitor structure according to claim 12, characterized in that, The substrate includes a capacitor region for forming a capacitor structure and metal interconnections provided outside the capacitor region. The step of electrically connecting the metal interconnections and the capacitor structure includes: Perform a third lithography process and a corresponding etching process on the stack, remove the stack outside the capacitor region, the first conductor is formed in the first electrode hole to electrically lead out all of the first electrodes, and the second conductor is formed in the second electrode hole to electrically lead out all of the second electrodes; Form sidewalls on the sidewalls of the stack; Form redistribution holes in the substrate to expose the metal interconnections; A redistribution metal layer is formed to cover the surface of the substrate, the outer walls of the stack, fill the redistribution holes, and a patterning process is performed on the redistribution metal layer. The redistribution metal layer at the tops of the first electrode hole and the second electrode hole serves as the conductive cap, and the redistribution metal layer connecting the metal interconnect line and the corresponding conductive cap serves as the redistribution line.

15. The manufacturing method of the multi-layer capacitor structure according to claim 12, characterized in that, The substrate includes a capacitor region for forming a capacitor structure and metal interconnect lines disposed within the capacitor region. The step of electrically connecting the metal interconnect lines and the capacitor structure includes: Performing a third lithography process and a corresponding etching process on the stack, removing the stack outside the capacitor region. The first electrode hole and the second electrode hole both penetrate the stack and expose the substrate on the corresponding metal interconnect line. A first conductor is formed in the first electrode hole to electrically lead out each of the first electrodes, and a second conductor is formed in the second electrode hole to electrically lead out each of the second electrodes. Forming sidewalls on the sidewalls of the stack, forming a first spacer in the first electrode hole and a second spacer in the second electrode hole, and exposing the surface of the corresponding metal interconnect line. Forming a redistribution metal layer to cover the surface of the substrate, the outer walls of the stack, filling the first electrode hole and the second electrode hole, and performing a patterning process on the redistribution metal layer. The redistribution metal layer at the tops of the first electrode hole and the second electrode hole serves as the conductive cap, and the redistribution metal layers in the first electrode hole and the second electrode hole serve as redistribution lines to respectively connect the conductive cap and the corresponding metal interconnect line.

16. The manufacturing method of the multilayer capacitor structure according to claim 12, characterized in that, The substrate includes a capacitor region for forming a capacitor structure and metal interconnect lines disposed within the capacitor region. The step of electrically connecting the metal interconnect lines and the capacitor structure includes: Performing a third lithography process and a corresponding etching process on the stack, removing the stack outside the capacitor region. The first electrode hole and the second electrode hole both penetrate the stack. A first conductor is formed in the first electrode hole to electrically lead out each of the first electrodes, and a second conductor is formed in the second electrode hole to electrically lead out each of the second electrodes. Also, redistribution lines are formed in the first electrode hole and the second electrode hole to electrically lead out the metal interconnect lines below them upward. Forming sidewalls on the sidewalls of the stack; Forming a redistribution metal layer to cover the surface of the substrate and the outer walls of the stack, and performing a patterning process on the redistribution metal layer. The redistribution metal layers at the tops of the first electrode hole and the second electrode hole serve as the conductive caps to electrically connect the first electrode and the corresponding redistribution line and to electrically connect the second electrode and the corresponding redistribution line.

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